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target/ppc: Use atomic min/max helpers
[qemu/ar7.git] / target / ppc / translate.c
blob79285b6698264d4c50af710bae74c11d9de1926d
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
35 #include "exec/log.h"
36
37
38 #define CPU_SINGLE_STEP 0x1
39 #define CPU_BRANCH_STEP 0x2
40 #define GDBSTUB_SINGLE_STEP 0x4
41
42 /* Include definitions for instructions classes and implementations flags */
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110
111 snprintf(p, cpu_reg_names_size, "fp%d", i);
112 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
113 offsetof(CPUPPCState, fpr[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "avr%dH", i);
118 #ifdef HOST_WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126 cpu_reg_names_size -= (i < 10) ? 6 : 7;
127
128 snprintf(p, cpu_reg_names_size, "avr%dL", i);
129 #ifdef HOST_WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
131 offsetof(CPUPPCState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 cpu_reg_names_size -= (i < 10) ? 6 : 7;
138 snprintf(p, cpu_reg_names_size, "vsr%d", i);
139 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, vsr[i]), p);
141 p += (i < 10) ? 5 : 6;
142 cpu_reg_names_size -= (i < 10) ? 5 : 6;
143 }
144
145 cpu_nip = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, lr), "lr");
156
157 #if defined(TARGET_PPC64)
158 cpu_cfar = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, cfar), "cfar");
160 #endif
161
162 cpu_xer = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, xer), "xer");
164 cpu_so = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, so), "SO");
166 cpu_ov = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, ov), "OV");
168 cpu_ca = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, ca), "CA");
170 cpu_ov32 = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov32), "OV32");
172 cpu_ca32 = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca32), "CA32");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178 cpu_reserve_val = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, reserve_val),
180 "reserve_val");
181
182 cpu_fpscr = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, fpscr), "fpscr");
184
185 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
186 offsetof(CPUPPCState, access_type), "access_type");
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 DisasContextBase base;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv, dr, le_mode;
196 bool lazy_tlb_flush;
197 bool need_access_type;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 bool gtse;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->base.pc_next - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->base.pc_next - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->base.pc_next);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->base.pc_next);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
381
382 typedef struct opcode_t {
383 unsigned char opc1, opc2, opc3, opc4;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad[4];
386 #endif
387 opc_handler_t handler;
388 const char *oname;
389 } opcode_t;
390
391 /* Helpers for priv. check */
392 #define GEN_PRIV \
393 do { \
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
395 } while (0)
396
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
401 #else
402 #define CHK_HV \
403 do { \
404 if (unlikely(ctx->pr || !ctx->hv)) { \
405 GEN_PRIV; \
406 } \
407 } while (0)
408 #define CHK_SV \
409 do { \
410 if (unlikely(ctx->pr)) { \
411 GEN_PRIV; \
412 } \
413 } while (0)
414 #define CHK_HVRM \
415 do { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
417 GEN_PRIV; \
418 } \
419 } while (0)
420 #endif
421
422 #define CHK_NONE
423
424 /*****************************************************************************/
425 /* PowerPC instructions table */
426
427 #if defined(DO_PPC_STATISTICS)
428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
429 { \
430 .opc1 = op1, \
431 .opc2 = op2, \
432 .opc3 = op3, \
433 .opc4 = 0xff, \
434 .handler = { \
435 .inval1 = invl, \
436 .type = _typ, \
437 .type2 = _typ2, \
438 .handler = &gen_##name, \
439 .oname = stringify(name), \
440 }, \
441 .oname = stringify(name), \
442 }
443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
444 { \
445 .opc1 = op1, \
446 .opc2 = op2, \
447 .opc3 = op3, \
448 .opc4 = 0xff, \
449 .handler = { \
450 .inval1 = invl1, \
451 .inval2 = invl2, \
452 .type = _typ, \
453 .type2 = _typ2, \
454 .handler = &gen_##name, \
455 .oname = stringify(name), \
456 }, \
457 .oname = stringify(name), \
458 }
459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
460 { \
461 .opc1 = op1, \
462 .opc2 = op2, \
463 .opc3 = op3, \
464 .opc4 = 0xff, \
465 .handler = { \
466 .inval1 = invl, \
467 .type = _typ, \
468 .type2 = _typ2, \
469 .handler = &gen_##name, \
470 .oname = onam, \
471 }, \
472 .oname = onam, \
473 }
474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
475 { \
476 .opc1 = op1, \
477 .opc2 = op2, \
478 .opc3 = op3, \
479 .opc4 = op4, \
480 .handler = { \
481 .inval1 = invl, \
482 .type = _typ, \
483 .type2 = _typ2, \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
486 }, \
487 .oname = stringify(name), \
488 }
489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
490 { \
491 .opc1 = op1, \
492 .opc2 = op2, \
493 .opc3 = op3, \
494 .opc4 = op4, \
495 .handler = { \
496 .inval1 = invl, \
497 .type = _typ, \
498 .type2 = _typ2, \
499 .handler = &gen_##name, \
500 .oname = onam, \
501 }, \
502 .oname = onam, \
503 }
504 #else
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
506 { \
507 .opc1 = op1, \
508 .opc2 = op2, \
509 .opc3 = op3, \
510 .opc4 = 0xff, \
511 .handler = { \
512 .inval1 = invl, \
513 .type = _typ, \
514 .type2 = _typ2, \
515 .handler = &gen_##name, \
516 }, \
517 .oname = stringify(name), \
518 }
519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .opc4 = 0xff, \
525 .handler = { \
526 .inval1 = invl1, \
527 .inval2 = invl2, \
528 .type = _typ, \
529 .type2 = _typ2, \
530 .handler = &gen_##name, \
531 }, \
532 .oname = stringify(name), \
533 }
534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
535 { \
536 .opc1 = op1, \
537 .opc2 = op2, \
538 .opc3 = op3, \
539 .opc4 = 0xff, \
540 .handler = { \
541 .inval1 = invl, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = onam, \
547 }
548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .opc4 = op4, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = stringify(name), \
561 }
562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
563 { \
564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .opc4 = op4, \
568 .handler = { \
569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = onam, \
575 }
576 #endif
577
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t, int reg)
580 {
581 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
582 }
583
584 static inline void gen_store_spr(int reg, TCGv t)
585 {
586 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
587 }
588
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext *ctx)
591 {
592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
593 }
594
595 static opc_handler_t invalid_handler = {
596 .inval1 = 0xFFFFFFFF,
597 .inval2 = 0xFFFFFFFF,
598 .type = PPC_NONE,
599 .type2 = PPC_NONE,
600 .handler = gen_invalid,
601 };
602
603 /*** Integer comparison ***/
604
605 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
606 {
607 TCGv t0 = tcg_temp_new();
608 TCGv t1 = tcg_temp_new();
609 TCGv_i32 t = tcg_temp_new_i32();
610
611 tcg_gen_movi_tl(t0, CRF_EQ);
612 tcg_gen_movi_tl(t1, CRF_LT);
613 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
614 tcg_gen_movi_tl(t1, CRF_GT);
615 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
616
617 tcg_gen_trunc_tl_i32(t, t0);
618 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
619 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
620
621 tcg_temp_free(t0);
622 tcg_temp_free(t1);
623 tcg_temp_free_i32(t);
624 }
625
626 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
627 {
628 TCGv t0 = tcg_const_tl(arg1);
629 gen_op_cmp(arg0, t0, s, crf);
630 tcg_temp_free(t0);
631 }
632
633 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
634 {
635 TCGv t0, t1;
636 t0 = tcg_temp_new();
637 t1 = tcg_temp_new();
638 if (s) {
639 tcg_gen_ext32s_tl(t0, arg0);
640 tcg_gen_ext32s_tl(t1, arg1);
641 } else {
642 tcg_gen_ext32u_tl(t0, arg0);
643 tcg_gen_ext32u_tl(t1, arg1);
644 }
645 gen_op_cmp(t0, t1, s, crf);
646 tcg_temp_free(t1);
647 tcg_temp_free(t0);
648 }
649
650 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
651 {
652 TCGv t0 = tcg_const_tl(arg1);
653 gen_op_cmp32(arg0, t0, s, crf);
654 tcg_temp_free(t0);
655 }
656
657 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
658 {
659 if (NARROW_MODE(ctx)) {
660 gen_op_cmpi32(reg, 0, 1, 0);
661 } else {
662 gen_op_cmpi(reg, 0, 1, 0);
663 }
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
670 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
671 1, crfD(ctx->opcode));
672 } else {
673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
674 1, crfD(ctx->opcode));
675 }
676 }
677
678 /* cmpi */
679 static void gen_cmpi(DisasContext *ctx)
680 {
681 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
682 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
683 1, crfD(ctx->opcode));
684 } else {
685 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
686 1, crfD(ctx->opcode));
687 }
688 }
689
690 /* cmpl */
691 static void gen_cmpl(DisasContext *ctx)
692 {
693 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
694 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
695 0, crfD(ctx->opcode));
696 } else {
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700 }
701
702 /* cmpli */
703 static void gen_cmpli(DisasContext *ctx)
704 {
705 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
706 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 } else {
709 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
710 0, crfD(ctx->opcode));
711 }
712 }
713
714 /* cmprb - range comparison: isupper, isaplha, islower*/
715 static void gen_cmprb(DisasContext *ctx)
716 {
717 TCGv_i32 src1 = tcg_temp_new_i32();
718 TCGv_i32 src2 = tcg_temp_new_i32();
719 TCGv_i32 src2lo = tcg_temp_new_i32();
720 TCGv_i32 src2hi = tcg_temp_new_i32();
721 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
722
723 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
724 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
725
726 tcg_gen_andi_i32(src1, src1, 0xFF);
727 tcg_gen_ext8u_i32(src2lo, src2);
728 tcg_gen_shri_i32(src2, src2, 8);
729 tcg_gen_ext8u_i32(src2hi, src2);
730
731 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
732 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
733 tcg_gen_and_i32(crf, src2lo, src2hi);
734
735 if (ctx->opcode & 0x00200000) {
736 tcg_gen_shri_i32(src2, src2, 8);
737 tcg_gen_ext8u_i32(src2lo, src2);
738 tcg_gen_shri_i32(src2, src2, 8);
739 tcg_gen_ext8u_i32(src2hi, src2);
740 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
741 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
742 tcg_gen_and_i32(src2lo, src2lo, src2hi);
743 tcg_gen_or_i32(crf, crf, src2lo);
744 }
745 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
746 tcg_temp_free_i32(src1);
747 tcg_temp_free_i32(src2);
748 tcg_temp_free_i32(src2lo);
749 tcg_temp_free_i32(src2hi);
750 }
751
752 #if defined(TARGET_PPC64)
753 /* cmpeqb */
754 static void gen_cmpeqb(DisasContext *ctx)
755 {
756 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
757 cpu_gpr[rB(ctx->opcode)]);
758 }
759 #endif
760
761 /* isel (PowerPC 2.03 specification) */
762 static void gen_isel(DisasContext *ctx)
763 {
764 uint32_t bi = rC(ctx->opcode);
765 uint32_t mask = 0x08 >> (bi & 0x03);
766 TCGv t0 = tcg_temp_new();
767 TCGv zr;
768
769 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
770 tcg_gen_andi_tl(t0, t0, mask);
771
772 zr = tcg_const_tl(0);
773 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
774 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
775 cpu_gpr[rB(ctx->opcode)]);
776 tcg_temp_free(zr);
777 tcg_temp_free(t0);
778 }
779
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext *ctx)
782 {
783 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
784 cpu_gpr[rB(ctx->opcode)]);
785 }
786
787 /*** Integer arithmetic ***/
788
789 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
790 TCGv arg1, TCGv arg2, int sub)
791 {
792 TCGv t0 = tcg_temp_new();
793
794 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
795 tcg_gen_xor_tl(t0, arg1, arg2);
796 if (sub) {
797 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
798 } else {
799 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
800 }
801 tcg_temp_free(t0);
802 if (NARROW_MODE(ctx)) {
803 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
804 if (is_isa300(ctx)) {
805 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
806 }
807 } else {
808 if (is_isa300(ctx)) {
809 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
810 }
811 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
812 }
813 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
814 }
815
816 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
817 TCGv res, TCGv arg0, TCGv arg1,
818 int sub)
819 {
820 TCGv t0;
821
822 if (!is_isa300(ctx)) {
823 return;
824 }
825
826 t0 = tcg_temp_new();
827 if (sub) {
828 tcg_gen_eqv_tl(t0, arg0, arg1);
829 } else {
830 tcg_gen_xor_tl(t0, arg0, arg1);
831 }
832 tcg_gen_xor_tl(t0, t0, res);
833 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
834 tcg_temp_free(t0);
835 }
836
837 /* Common add function */
838 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
839 TCGv arg2, bool add_ca, bool compute_ca,
840 bool compute_ov, bool compute_rc0)
841 {
842 TCGv t0 = ret;
843
844 if (compute_ca || compute_ov) {
845 t0 = tcg_temp_new();
846 }
847
848 if (compute_ca) {
849 if (NARROW_MODE(ctx)) {
850 /* Caution: a non-obvious corner case of the spec is that we
851 must produce the *entire* 64-bit addition, but produce the
852 carry into bit 32. */
853 TCGv t1 = tcg_temp_new();
854 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
855 tcg_gen_add_tl(t0, arg1, arg2);
856 if (add_ca) {
857 tcg_gen_add_tl(t0, t0, cpu_ca);
858 }
859 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
860 tcg_temp_free(t1);
861 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
862 if (is_isa300(ctx)) {
863 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
864 }
865 } else {
866 TCGv zero = tcg_const_tl(0);
867 if (add_ca) {
868 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
869 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
870 } else {
871 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
872 }
873 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
874 tcg_temp_free(zero);
875 }
876 } else {
877 tcg_gen_add_tl(t0, arg1, arg2);
878 if (add_ca) {
879 tcg_gen_add_tl(t0, t0, cpu_ca);
880 }
881 }
882
883 if (compute_ov) {
884 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
885 }
886 if (unlikely(compute_rc0)) {
887 gen_set_Rc0(ctx, t0);
888 }
889
890 if (t0 != ret) {
891 tcg_gen_mov_tl(ret, t0);
892 tcg_temp_free(t0);
893 }
894 }
895 /* Add functions with two operands */
896 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
901 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
902 }
903 /* Add functions with one operand and one immediate */
904 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
905 add_ca, compute_ca, compute_ov) \
906 static void glue(gen_, name)(DisasContext *ctx) \
907 { \
908 TCGv t0 = tcg_const_tl(const_val); \
909 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
910 cpu_gpr[rA(ctx->opcode)], t0, \
911 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
912 tcg_temp_free(t0); \
913 }
914
915 /* add add. addo addo. */
916 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
917 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
918 /* addc addc. addco addco. */
919 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
920 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
921 /* adde adde. addeo addeo. */
922 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
923 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
924 /* addme addme. addmeo addmeo. */
925 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
926 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
927 /* addze addze. addzeo addzeo.*/
928 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
930 /* addi */
931 static void gen_addi(DisasContext *ctx)
932 {
933 target_long simm = SIMM(ctx->opcode);
934
935 if (rA(ctx->opcode) == 0) {
936 /* li case */
937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
938 } else {
939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
940 cpu_gpr[rA(ctx->opcode)], simm);
941 }
942 }
943 /* addic addic.*/
944 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
945 {
946 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
947 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
948 c, 0, 1, 0, compute_rc0);
949 tcg_temp_free(c);
950 }
951
952 static void gen_addic(DisasContext *ctx)
953 {
954 gen_op_addic(ctx, 0);
955 }
956
957 static void gen_addic_(DisasContext *ctx)
958 {
959 gen_op_addic(ctx, 1);
960 }
961
962 /* addis */
963 static void gen_addis(DisasContext *ctx)
964 {
965 target_long simm = SIMM(ctx->opcode);
966
967 if (rA(ctx->opcode) == 0) {
968 /* lis case */
969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
970 } else {
971 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
972 cpu_gpr[rA(ctx->opcode)], simm << 16);
973 }
974 }
975
976 /* addpcis */
977 static void gen_addpcis(DisasContext *ctx)
978 {
979 target_long d = DX(ctx->opcode);
980
981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
982 }
983
984 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
985 TCGv arg2, int sign, int compute_ov)
986 {
987 TCGv_i32 t0 = tcg_temp_new_i32();
988 TCGv_i32 t1 = tcg_temp_new_i32();
989 TCGv_i32 t2 = tcg_temp_new_i32();
990 TCGv_i32 t3 = tcg_temp_new_i32();
991
992 tcg_gen_trunc_tl_i32(t0, arg1);
993 tcg_gen_trunc_tl_i32(t1, arg2);
994 if (sign) {
995 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
996 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
997 tcg_gen_and_i32(t2, t2, t3);
998 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
999 tcg_gen_or_i32(t2, t2, t3);
1000 tcg_gen_movi_i32(t3, 0);
1001 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1002 tcg_gen_div_i32(t3, t0, t1);
1003 tcg_gen_extu_i32_tl(ret, t3);
1004 } else {
1005 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1006 tcg_gen_movi_i32(t3, 0);
1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1008 tcg_gen_divu_i32(t3, t0, t1);
1009 tcg_gen_extu_i32_tl(ret, t3);
1010 }
1011 if (compute_ov) {
1012 tcg_gen_extu_i32_tl(cpu_ov, t2);
1013 if (is_isa300(ctx)) {
1014 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1015 }
1016 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1017 }
1018 tcg_temp_free_i32(t0);
1019 tcg_temp_free_i32(t1);
1020 tcg_temp_free_i32(t2);
1021 tcg_temp_free_i32(t3);
1022
1023 if (unlikely(Rc(ctx->opcode) != 0))
1024 gen_set_Rc0(ctx, ret);
1025 }
1026 /* Div functions */
1027 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1028 static void glue(gen_, name)(DisasContext *ctx) \
1029 { \
1030 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1032 sign, compute_ov); \
1033 }
1034 /* divwu divwu. divwuo divwuo. */
1035 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1036 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1037 /* divw divw. divwo divwo. */
1038 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1039 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1040
1041 /* div[wd]eu[o][.] */
1042 #define GEN_DIVE(name, hlpr, compute_ov) \
1043 static void gen_##name(DisasContext *ctx) \
1044 { \
1045 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1046 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1048 tcg_temp_free_i32(t0); \
1049 if (unlikely(Rc(ctx->opcode) != 0)) { \
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1051 } \
1052 }
1053
1054 GEN_DIVE(divweu, divweu, 0);
1055 GEN_DIVE(divweuo, divweu, 1);
1056 GEN_DIVE(divwe, divwe, 0);
1057 GEN_DIVE(divweo, divwe, 1);
1058
1059 #if defined(TARGET_PPC64)
1060 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1061 TCGv arg2, int sign, int compute_ov)
1062 {
1063 TCGv_i64 t0 = tcg_temp_new_i64();
1064 TCGv_i64 t1 = tcg_temp_new_i64();
1065 TCGv_i64 t2 = tcg_temp_new_i64();
1066 TCGv_i64 t3 = tcg_temp_new_i64();
1067
1068 tcg_gen_mov_i64(t0, arg1);
1069 tcg_gen_mov_i64(t1, arg2);
1070 if (sign) {
1071 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1072 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1073 tcg_gen_and_i64(t2, t2, t3);
1074 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1075 tcg_gen_or_i64(t2, t2, t3);
1076 tcg_gen_movi_i64(t3, 0);
1077 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1078 tcg_gen_div_i64(ret, t0, t1);
1079 } else {
1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1081 tcg_gen_movi_i64(t3, 0);
1082 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1083 tcg_gen_divu_i64(ret, t0, t1);
1084 }
1085 if (compute_ov) {
1086 tcg_gen_mov_tl(cpu_ov, t2);
1087 if (is_isa300(ctx)) {
1088 tcg_gen_mov_tl(cpu_ov32, t2);
1089 }
1090 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1091 }
1092 tcg_temp_free_i64(t0);
1093 tcg_temp_free_i64(t1);
1094 tcg_temp_free_i64(t2);
1095 tcg_temp_free_i64(t3);
1096
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, ret);
1099 }
1100
1101 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1102 static void glue(gen_, name)(DisasContext *ctx) \
1103 { \
1104 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1106 sign, compute_ov); \
1107 }
1108 /* divdu divdu. divduo divduo. */
1109 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1110 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1111 /* divd divd. divdo divdo. */
1112 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1113 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1114
1115 GEN_DIVE(divdeu, divdeu, 0);
1116 GEN_DIVE(divdeuo, divdeu, 1);
1117 GEN_DIVE(divde, divde, 0);
1118 GEN_DIVE(divdeo, divde, 1);
1119 #endif
1120
1121 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1122 TCGv arg2, int sign)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, arg1);
1128 tcg_gen_trunc_tl_i32(t1, arg2);
1129 if (sign) {
1130 TCGv_i32 t2 = tcg_temp_new_i32();
1131 TCGv_i32 t3 = tcg_temp_new_i32();
1132 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1133 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1134 tcg_gen_and_i32(t2, t2, t3);
1135 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1136 tcg_gen_or_i32(t2, t2, t3);
1137 tcg_gen_movi_i32(t3, 0);
1138 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1139 tcg_gen_rem_i32(t3, t0, t1);
1140 tcg_gen_ext_i32_tl(ret, t3);
1141 tcg_temp_free_i32(t2);
1142 tcg_temp_free_i32(t3);
1143 } else {
1144 TCGv_i32 t2 = tcg_const_i32(1);
1145 TCGv_i32 t3 = tcg_const_i32(0);
1146 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1147 tcg_gen_remu_i32(t3, t0, t1);
1148 tcg_gen_extu_i32_tl(ret, t3);
1149 tcg_temp_free_i32(t2);
1150 tcg_temp_free_i32(t3);
1151 }
1152 tcg_temp_free_i32(t0);
1153 tcg_temp_free_i32(t1);
1154 }
1155
1156 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1158 { \
1159 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign); \
1162 }
1163
1164 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1165 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1166
1167 #if defined(TARGET_PPC64)
1168 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1169 TCGv arg2, int sign)
1170 {
1171 TCGv_i64 t0 = tcg_temp_new_i64();
1172 TCGv_i64 t1 = tcg_temp_new_i64();
1173
1174 tcg_gen_mov_i64(t0, arg1);
1175 tcg_gen_mov_i64(t1, arg2);
1176 if (sign) {
1177 TCGv_i64 t2 = tcg_temp_new_i64();
1178 TCGv_i64 t3 = tcg_temp_new_i64();
1179 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1180 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1181 tcg_gen_and_i64(t2, t2, t3);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1183 tcg_gen_or_i64(t2, t2, t3);
1184 tcg_gen_movi_i64(t3, 0);
1185 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1186 tcg_gen_rem_i64(ret, t0, t1);
1187 tcg_temp_free_i64(t2);
1188 tcg_temp_free_i64(t3);
1189 } else {
1190 TCGv_i64 t2 = tcg_const_i64(1);
1191 TCGv_i64 t3 = tcg_const_i64(0);
1192 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1193 tcg_gen_remu_i64(ret, t0, t1);
1194 tcg_temp_free_i64(t2);
1195 tcg_temp_free_i64(t3);
1196 }
1197 tcg_temp_free_i64(t0);
1198 tcg_temp_free_i64(t1);
1199 }
1200
1201 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1202 static void glue(gen_, name)(DisasContext *ctx) \
1203 { \
1204 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1206 sign); \
1207 }
1208
1209 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1210 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1211 #endif
1212
1213 /* mulhw mulhw. */
1214 static void gen_mulhw(DisasContext *ctx)
1215 {
1216 TCGv_i32 t0 = tcg_temp_new_i32();
1217 TCGv_i32 t1 = tcg_temp_new_i32();
1218
1219 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1220 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1221 tcg_gen_muls2_i32(t0, t1, t0, t1);
1222 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1223 tcg_temp_free_i32(t0);
1224 tcg_temp_free_i32(t1);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1227 }
1228
1229 /* mulhwu mulhwu. */
1230 static void gen_mulhwu(DisasContext *ctx)
1231 {
1232 TCGv_i32 t0 = tcg_temp_new_i32();
1233 TCGv_i32 t1 = tcg_temp_new_i32();
1234
1235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1237 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1239 tcg_temp_free_i32(t0);
1240 tcg_temp_free_i32(t1);
1241 if (unlikely(Rc(ctx->opcode) != 0))
1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1243 }
1244
1245 /* mullw mullw. */
1246 static void gen_mullw(DisasContext *ctx)
1247 {
1248 #if defined(TARGET_PPC64)
1249 TCGv_i64 t0, t1;
1250 t0 = tcg_temp_new_i64();
1251 t1 = tcg_temp_new_i64();
1252 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1253 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1254 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1255 tcg_temp_free(t0);
1256 tcg_temp_free(t1);
1257 #else
1258 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1259 cpu_gpr[rB(ctx->opcode)]);
1260 #endif
1261 if (unlikely(Rc(ctx->opcode) != 0))
1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1263 }
1264
1265 /* mullwo mullwo. */
1266 static void gen_mullwo(DisasContext *ctx)
1267 {
1268 TCGv_i32 t0 = tcg_temp_new_i32();
1269 TCGv_i32 t1 = tcg_temp_new_i32();
1270
1271 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1272 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1273 tcg_gen_muls2_i32(t0, t1, t0, t1);
1274 #if defined(TARGET_PPC64)
1275 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1276 #else
1277 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1278 #endif
1279
1280 tcg_gen_sari_i32(t0, t0, 31);
1281 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1282 tcg_gen_extu_i32_tl(cpu_ov, t0);
1283 if (is_isa300(ctx)) {
1284 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1285 }
1286 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1287
1288 tcg_temp_free_i32(t0);
1289 tcg_temp_free_i32(t1);
1290 if (unlikely(Rc(ctx->opcode) != 0))
1291 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1292 }
1293
1294 /* mulli */
1295 static void gen_mulli(DisasContext *ctx)
1296 {
1297 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1298 SIMM(ctx->opcode));
1299 }
1300
1301 #if defined(TARGET_PPC64)
1302 /* mulhd mulhd. */
1303 static void gen_mulhd(DisasContext *ctx)
1304 {
1305 TCGv lo = tcg_temp_new();
1306 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1308 tcg_temp_free(lo);
1309 if (unlikely(Rc(ctx->opcode) != 0)) {
1310 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1311 }
1312 }
1313
1314 /* mulhdu mulhdu. */
1315 static void gen_mulhdu(DisasContext *ctx)
1316 {
1317 TCGv lo = tcg_temp_new();
1318 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1320 tcg_temp_free(lo);
1321 if (unlikely(Rc(ctx->opcode) != 0)) {
1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1323 }
1324 }
1325
1326 /* mulld mulld. */
1327 static void gen_mulld(DisasContext *ctx)
1328 {
1329 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1330 cpu_gpr[rB(ctx->opcode)]);
1331 if (unlikely(Rc(ctx->opcode) != 0))
1332 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1333 }
1334
1335 /* mulldo mulldo. */
1336 static void gen_mulldo(DisasContext *ctx)
1337 {
1338 TCGv_i64 t0 = tcg_temp_new_i64();
1339 TCGv_i64 t1 = tcg_temp_new_i64();
1340
1341 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1342 cpu_gpr[rB(ctx->opcode)]);
1343 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1344
1345 tcg_gen_sari_i64(t0, t0, 63);
1346 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1347 if (is_isa300(ctx)) {
1348 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1349 }
1350 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1351
1352 tcg_temp_free_i64(t0);
1353 tcg_temp_free_i64(t1);
1354
1355 if (unlikely(Rc(ctx->opcode) != 0)) {
1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1357 }
1358 }
1359 #endif
1360
1361 /* Common subf function */
1362 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1363 TCGv arg2, bool add_ca, bool compute_ca,
1364 bool compute_ov, bool compute_rc0)
1365 {
1366 TCGv t0 = ret;
1367
1368 if (compute_ca || compute_ov) {
1369 t0 = tcg_temp_new();
1370 }
1371
1372 if (compute_ca) {
1373 /* dest = ~arg1 + arg2 [+ ca]. */
1374 if (NARROW_MODE(ctx)) {
1375 /* Caution: a non-obvious corner case of the spec is that we
1376 must produce the *entire* 64-bit addition, but produce the
1377 carry into bit 32. */
1378 TCGv inv1 = tcg_temp_new();
1379 TCGv t1 = tcg_temp_new();
1380 tcg_gen_not_tl(inv1, arg1);
1381 if (add_ca) {
1382 tcg_gen_add_tl(t0, arg2, cpu_ca);
1383 } else {
1384 tcg_gen_addi_tl(t0, arg2, 1);
1385 }
1386 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1387 tcg_gen_add_tl(t0, t0, inv1);
1388 tcg_temp_free(inv1);
1389 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1390 tcg_temp_free(t1);
1391 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1392 if (is_isa300(ctx)) {
1393 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1394 }
1395 } else if (add_ca) {
1396 TCGv zero, inv1 = tcg_temp_new();
1397 tcg_gen_not_tl(inv1, arg1);
1398 zero = tcg_const_tl(0);
1399 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1400 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1401 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1402 tcg_temp_free(zero);
1403 tcg_temp_free(inv1);
1404 } else {
1405 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1406 tcg_gen_sub_tl(t0, arg2, arg1);
1407 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1408 }
1409 } else if (add_ca) {
1410 /* Since we're ignoring carry-out, we can simplify the
1411 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1412 tcg_gen_sub_tl(t0, arg2, arg1);
1413 tcg_gen_add_tl(t0, t0, cpu_ca);
1414 tcg_gen_subi_tl(t0, t0, 1);
1415 } else {
1416 tcg_gen_sub_tl(t0, arg2, arg1);
1417 }
1418
1419 if (compute_ov) {
1420 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1421 }
1422 if (unlikely(compute_rc0)) {
1423 gen_set_Rc0(ctx, t0);
1424 }
1425
1426 if (t0 != ret) {
1427 tcg_gen_mov_tl(ret, t0);
1428 tcg_temp_free(t0);
1429 }
1430 }
1431 /* Sub functions with Two operands functions */
1432 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1433 static void glue(gen_, name)(DisasContext *ctx) \
1434 { \
1435 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1437 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1438 }
1439 /* Sub functions with one operand and one immediate */
1440 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1441 add_ca, compute_ca, compute_ov) \
1442 static void glue(gen_, name)(DisasContext *ctx) \
1443 { \
1444 TCGv t0 = tcg_const_tl(const_val); \
1445 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1446 cpu_gpr[rA(ctx->opcode)], t0, \
1447 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1448 tcg_temp_free(t0); \
1449 }
1450 /* subf subf. subfo subfo. */
1451 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1452 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1453 /* subfc subfc. subfco subfco. */
1454 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1455 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1456 /* subfe subfe. subfeo subfo. */
1457 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1458 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1459 /* subfme subfme. subfmeo subfmeo. */
1460 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1461 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1462 /* subfze subfze. subfzeo subfzeo.*/
1463 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1464 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1465
1466 /* subfic */
1467 static void gen_subfic(DisasContext *ctx)
1468 {
1469 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1470 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1471 c, 0, 1, 0, 0);
1472 tcg_temp_free(c);
1473 }
1474
1475 /* neg neg. nego nego. */
1476 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1477 {
1478 TCGv zero = tcg_const_tl(0);
1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1480 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1481 tcg_temp_free(zero);
1482 }
1483
1484 static void gen_neg(DisasContext *ctx)
1485 {
1486 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1487 if (unlikely(Rc(ctx->opcode))) {
1488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1489 }
1490 }
1491
1492 static void gen_nego(DisasContext *ctx)
1493 {
1494 gen_op_arith_neg(ctx, 1);
1495 }
1496
1497 /*** Integer logical ***/
1498 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1499 static void glue(gen_, name)(DisasContext *ctx) \
1500 { \
1501 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1502 cpu_gpr[rB(ctx->opcode)]); \
1503 if (unlikely(Rc(ctx->opcode) != 0)) \
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1505 }
1506
1507 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1508 static void glue(gen_, name)(DisasContext *ctx) \
1509 { \
1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1511 if (unlikely(Rc(ctx->opcode) != 0)) \
1512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1513 }
1514
1515 /* and & and. */
1516 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1517 /* andc & andc. */
1518 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1519
1520 /* andi. */
1521 static void gen_andi_(DisasContext *ctx)
1522 {
1523 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1524 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1525 }
1526
1527 /* andis. */
1528 static void gen_andis_(DisasContext *ctx)
1529 {
1530 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533
1534 /* cntlzw */
1535 static void gen_cntlzw(DisasContext *ctx)
1536 {
1537 TCGv_i32 t = tcg_temp_new_i32();
1538
1539 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1540 tcg_gen_clzi_i32(t, t, 32);
1541 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1542 tcg_temp_free_i32(t);
1543
1544 if (unlikely(Rc(ctx->opcode) != 0))
1545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1546 }
1547
1548 /* cnttzw */
1549 static void gen_cnttzw(DisasContext *ctx)
1550 {
1551 TCGv_i32 t = tcg_temp_new_i32();
1552
1553 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1554 tcg_gen_ctzi_i32(t, t, 32);
1555 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1556 tcg_temp_free_i32(t);
1557
1558 if (unlikely(Rc(ctx->opcode) != 0)) {
1559 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1560 }
1561 }
1562
1563 /* eqv & eqv. */
1564 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1565 /* extsb & extsb. */
1566 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1567 /* extsh & extsh. */
1568 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1569 /* nand & nand. */
1570 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1571 /* nor & nor. */
1572 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1573
1574 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1575 static void gen_pause(DisasContext *ctx)
1576 {
1577 TCGv_i32 t0 = tcg_const_i32(0);
1578 tcg_gen_st_i32(t0, cpu_env,
1579 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1580 tcg_temp_free_i32(t0);
1581
1582 /* Stop translation, this gives other CPUs a chance to run */
1583 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1584 }
1585 #endif /* defined(TARGET_PPC64) */
1586
1587 /* or & or. */
1588 static void gen_or(DisasContext *ctx)
1589 {
1590 int rs, ra, rb;
1591
1592 rs = rS(ctx->opcode);
1593 ra = rA(ctx->opcode);
1594 rb = rB(ctx->opcode);
1595 /* Optimisation for mr. ri case */
1596 if (rs != ra || rs != rb) {
1597 if (rs != rb)
1598 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1599 else
1600 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1601 if (unlikely(Rc(ctx->opcode) != 0))
1602 gen_set_Rc0(ctx, cpu_gpr[ra]);
1603 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1604 gen_set_Rc0(ctx, cpu_gpr[rs]);
1605 #if defined(TARGET_PPC64)
1606 } else if (rs != 0) { /* 0 is nop */
1607 int prio = 0;
1608
1609 switch (rs) {
1610 case 1:
1611 /* Set process priority to low */
1612 prio = 2;
1613 break;
1614 case 6:
1615 /* Set process priority to medium-low */
1616 prio = 3;
1617 break;
1618 case 2:
1619 /* Set process priority to normal */
1620 prio = 4;
1621 break;
1622 #if !defined(CONFIG_USER_ONLY)
1623 case 31:
1624 if (!ctx->pr) {
1625 /* Set process priority to very low */
1626 prio = 1;
1627 }
1628 break;
1629 case 5:
1630 if (!ctx->pr) {
1631 /* Set process priority to medium-hight */
1632 prio = 5;
1633 }
1634 break;
1635 case 3:
1636 if (!ctx->pr) {
1637 /* Set process priority to high */
1638 prio = 6;
1639 }
1640 break;
1641 case 7:
1642 if (ctx->hv && !ctx->pr) {
1643 /* Set process priority to very high */
1644 prio = 7;
1645 }
1646 break;
1647 #endif
1648 default:
1649 break;
1650 }
1651 if (prio) {
1652 TCGv t0 = tcg_temp_new();
1653 gen_load_spr(t0, SPR_PPR);
1654 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1655 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1656 gen_store_spr(SPR_PPR, t0);
1657 tcg_temp_free(t0);
1658 }
1659 #if !defined(CONFIG_USER_ONLY)
1660 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1661 * CPU and the kernel hangs. This applies to all encodings other
1662 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1663 * and all currently undefined.
1664 */
1665 gen_pause(ctx);
1666 #endif
1667 #endif
1668 }
1669 }
1670 /* orc & orc. */
1671 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1672
1673 /* xor & xor. */
1674 static void gen_xor(DisasContext *ctx)
1675 {
1676 /* Optimisation for "set to zero" case */
1677 if (rS(ctx->opcode) != rB(ctx->opcode))
1678 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1679 else
1680 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1683 }
1684
1685 /* ori */
1686 static void gen_ori(DisasContext *ctx)
1687 {
1688 target_ulong uimm = UIMM(ctx->opcode);
1689
1690 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1691 return;
1692 }
1693 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1694 }
1695
1696 /* oris */
1697 static void gen_oris(DisasContext *ctx)
1698 {
1699 target_ulong uimm = UIMM(ctx->opcode);
1700
1701 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1702 /* NOP */
1703 return;
1704 }
1705 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1706 }
1707
1708 /* xori */
1709 static void gen_xori(DisasContext *ctx)
1710 {
1711 target_ulong uimm = UIMM(ctx->opcode);
1712
1713 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1714 /* NOP */
1715 return;
1716 }
1717 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1718 }
1719
1720 /* xoris */
1721 static void gen_xoris(DisasContext *ctx)
1722 {
1723 target_ulong uimm = UIMM(ctx->opcode);
1724
1725 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1726 /* NOP */
1727 return;
1728 }
1729 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1730 }
1731
1732 /* popcntb : PowerPC 2.03 specification */
1733 static void gen_popcntb(DisasContext *ctx)
1734 {
1735 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1736 }
1737
1738 static void gen_popcntw(DisasContext *ctx)
1739 {
1740 #if defined(TARGET_PPC64)
1741 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1742 #else
1743 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1744 #endif
1745 }
1746
1747 #if defined(TARGET_PPC64)
1748 /* popcntd: PowerPC 2.06 specification */
1749 static void gen_popcntd(DisasContext *ctx)
1750 {
1751 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1752 }
1753 #endif
1754
1755 /* prtyw: PowerPC 2.05 specification */
1756 static void gen_prtyw(DisasContext *ctx)
1757 {
1758 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1759 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1760 TCGv t0 = tcg_temp_new();
1761 tcg_gen_shri_tl(t0, rs, 16);
1762 tcg_gen_xor_tl(ra, rs, t0);
1763 tcg_gen_shri_tl(t0, ra, 8);
1764 tcg_gen_xor_tl(ra, ra, t0);
1765 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1766 tcg_temp_free(t0);
1767 }
1768
1769 #if defined(TARGET_PPC64)
1770 /* prtyd: PowerPC 2.05 specification */
1771 static void gen_prtyd(DisasContext *ctx)
1772 {
1773 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1774 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1775 TCGv t0 = tcg_temp_new();
1776 tcg_gen_shri_tl(t0, rs, 32);
1777 tcg_gen_xor_tl(ra, rs, t0);
1778 tcg_gen_shri_tl(t0, ra, 16);
1779 tcg_gen_xor_tl(ra, ra, t0);
1780 tcg_gen_shri_tl(t0, ra, 8);
1781 tcg_gen_xor_tl(ra, ra, t0);
1782 tcg_gen_andi_tl(ra, ra, 1);
1783 tcg_temp_free(t0);
1784 }
1785 #endif
1786
1787 #if defined(TARGET_PPC64)
1788 /* bpermd */
1789 static void gen_bpermd(DisasContext *ctx)
1790 {
1791 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1792 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1793 }
1794 #endif
1795
1796 #if defined(TARGET_PPC64)
1797 /* extsw & extsw. */
1798 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1799
1800 /* cntlzd */
1801 static void gen_cntlzd(DisasContext *ctx)
1802 {
1803 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1804 if (unlikely(Rc(ctx->opcode) != 0))
1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1806 }
1807
1808 /* cnttzd */
1809 static void gen_cnttzd(DisasContext *ctx)
1810 {
1811 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1812 if (unlikely(Rc(ctx->opcode) != 0)) {
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815 }
1816
1817 /* darn */
1818 static void gen_darn(DisasContext *ctx)
1819 {
1820 int l = L(ctx->opcode);
1821
1822 if (l == 0) {
1823 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1824 } else if (l <= 2) {
1825 /* Return 64-bit random for both CRN and RRN */
1826 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1827 } else {
1828 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1829 }
1830 }
1831 #endif
1832
1833 /*** Integer rotate ***/
1834
1835 /* rlwimi & rlwimi. */
1836 static void gen_rlwimi(DisasContext *ctx)
1837 {
1838 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1839 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1840 uint32_t sh = SH(ctx->opcode);
1841 uint32_t mb = MB(ctx->opcode);
1842 uint32_t me = ME(ctx->opcode);
1843
1844 if (sh == (31-me) && mb <= me) {
1845 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1846 } else {
1847 target_ulong mask;
1848 TCGv t1;
1849
1850 #if defined(TARGET_PPC64)
1851 mb += 32;
1852 me += 32;
1853 #endif
1854 mask = MASK(mb, me);
1855
1856 t1 = tcg_temp_new();
1857 if (mask <= 0xffffffffu) {
1858 TCGv_i32 t0 = tcg_temp_new_i32();
1859 tcg_gen_trunc_tl_i32(t0, t_rs);
1860 tcg_gen_rotli_i32(t0, t0, sh);
1861 tcg_gen_extu_i32_tl(t1, t0);
1862 tcg_temp_free_i32(t0);
1863 } else {
1864 #if defined(TARGET_PPC64)
1865 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1866 tcg_gen_rotli_i64(t1, t1, sh);
1867 #else
1868 g_assert_not_reached();
1869 #endif
1870 }
1871
1872 tcg_gen_andi_tl(t1, t1, mask);
1873 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1874 tcg_gen_or_tl(t_ra, t_ra, t1);
1875 tcg_temp_free(t1);
1876 }
1877 if (unlikely(Rc(ctx->opcode) != 0)) {
1878 gen_set_Rc0(ctx, t_ra);
1879 }
1880 }
1881
1882 /* rlwinm & rlwinm. */
1883 static void gen_rlwinm(DisasContext *ctx)
1884 {
1885 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1886 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1887 int sh = SH(ctx->opcode);
1888 int mb = MB(ctx->opcode);
1889 int me = ME(ctx->opcode);
1890 int len = me - mb + 1;
1891 int rsh = (32 - sh) & 31;
1892
1893 if (sh != 0 && len > 0 && me == (31 - sh)) {
1894 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1895 } else if (me == 31 && rsh + len <= 32) {
1896 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1897 } else {
1898 target_ulong mask;
1899 #if defined(TARGET_PPC64)
1900 mb += 32;
1901 me += 32;
1902 #endif
1903 mask = MASK(mb, me);
1904 if (sh == 0) {
1905 tcg_gen_andi_tl(t_ra, t_rs, mask);
1906 } else if (mask <= 0xffffffffu) {
1907 TCGv_i32 t0 = tcg_temp_new_i32();
1908 tcg_gen_trunc_tl_i32(t0, t_rs);
1909 tcg_gen_rotli_i32(t0, t0, sh);
1910 tcg_gen_andi_i32(t0, t0, mask);
1911 tcg_gen_extu_i32_tl(t_ra, t0);
1912 tcg_temp_free_i32(t0);
1913 } else {
1914 #if defined(TARGET_PPC64)
1915 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1916 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1917 tcg_gen_andi_i64(t_ra, t_ra, mask);
1918 #else
1919 g_assert_not_reached();
1920 #endif
1921 }
1922 }
1923 if (unlikely(Rc(ctx->opcode) != 0)) {
1924 gen_set_Rc0(ctx, t_ra);
1925 }
1926 }
1927
1928 /* rlwnm & rlwnm. */
1929 static void gen_rlwnm(DisasContext *ctx)
1930 {
1931 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1932 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1933 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1934 uint32_t mb = MB(ctx->opcode);
1935 uint32_t me = ME(ctx->opcode);
1936 target_ulong mask;
1937
1938 #if defined(TARGET_PPC64)
1939 mb += 32;
1940 me += 32;
1941 #endif
1942 mask = MASK(mb, me);
1943
1944 if (mask <= 0xffffffffu) {
1945 TCGv_i32 t0 = tcg_temp_new_i32();
1946 TCGv_i32 t1 = tcg_temp_new_i32();
1947 tcg_gen_trunc_tl_i32(t0, t_rb);
1948 tcg_gen_trunc_tl_i32(t1, t_rs);
1949 tcg_gen_andi_i32(t0, t0, 0x1f);
1950 tcg_gen_rotl_i32(t1, t1, t0);
1951 tcg_gen_extu_i32_tl(t_ra, t1);
1952 tcg_temp_free_i32(t0);
1953 tcg_temp_free_i32(t1);
1954 } else {
1955 #if defined(TARGET_PPC64)
1956 TCGv_i64 t0 = tcg_temp_new_i64();
1957 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1958 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1959 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1960 tcg_temp_free_i64(t0);
1961 #else
1962 g_assert_not_reached();
1963 #endif
1964 }
1965
1966 tcg_gen_andi_tl(t_ra, t_ra, mask);
1967
1968 if (unlikely(Rc(ctx->opcode) != 0)) {
1969 gen_set_Rc0(ctx, t_ra);
1970 }
1971 }
1972
1973 #if defined(TARGET_PPC64)
1974 #define GEN_PPC64_R2(name, opc1, opc2) \
1975 static void glue(gen_, name##0)(DisasContext *ctx) \
1976 { \
1977 gen_##name(ctx, 0); \
1978 } \
1979 \
1980 static void glue(gen_, name##1)(DisasContext *ctx) \
1981 { \
1982 gen_##name(ctx, 1); \
1983 }
1984 #define GEN_PPC64_R4(name, opc1, opc2) \
1985 static void glue(gen_, name##0)(DisasContext *ctx) \
1986 { \
1987 gen_##name(ctx, 0, 0); \
1988 } \
1989 \
1990 static void glue(gen_, name##1)(DisasContext *ctx) \
1991 { \
1992 gen_##name(ctx, 0, 1); \
1993 } \
1994 \
1995 static void glue(gen_, name##2)(DisasContext *ctx) \
1996 { \
1997 gen_##name(ctx, 1, 0); \
1998 } \
1999 \
2000 static void glue(gen_, name##3)(DisasContext *ctx) \
2001 { \
2002 gen_##name(ctx, 1, 1); \
2003 }
2004
2005 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2006 {
2007 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2008 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2009 int len = me - mb + 1;
2010 int rsh = (64 - sh) & 63;
2011
2012 if (sh != 0 && len > 0 && me == (63 - sh)) {
2013 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2014 } else if (me == 63 && rsh + len <= 64) {
2015 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2016 } else {
2017 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2018 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2019 }
2020 if (unlikely(Rc(ctx->opcode) != 0)) {
2021 gen_set_Rc0(ctx, t_ra);
2022 }
2023 }
2024
2025 /* rldicl - rldicl. */
2026 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2027 {
2028 uint32_t sh, mb;
2029
2030 sh = SH(ctx->opcode) | (shn << 5);
2031 mb = MB(ctx->opcode) | (mbn << 5);
2032 gen_rldinm(ctx, mb, 63, sh);
2033 }
2034 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2035
2036 /* rldicr - rldicr. */
2037 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2038 {
2039 uint32_t sh, me;
2040
2041 sh = SH(ctx->opcode) | (shn << 5);
2042 me = MB(ctx->opcode) | (men << 5);
2043 gen_rldinm(ctx, 0, me, sh);
2044 }
2045 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2046
2047 /* rldic - rldic. */
2048 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2049 {
2050 uint32_t sh, mb;
2051
2052 sh = SH(ctx->opcode) | (shn << 5);
2053 mb = MB(ctx->opcode) | (mbn << 5);
2054 gen_rldinm(ctx, mb, 63 - sh, sh);
2055 }
2056 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2057
2058 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2059 {
2060 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2061 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2062 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2063 TCGv t0;
2064
2065 t0 = tcg_temp_new();
2066 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2067 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2068 tcg_temp_free(t0);
2069
2070 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2071 if (unlikely(Rc(ctx->opcode) != 0)) {
2072 gen_set_Rc0(ctx, t_ra);
2073 }
2074 }
2075
2076 /* rldcl - rldcl. */
2077 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2078 {
2079 uint32_t mb;
2080
2081 mb = MB(ctx->opcode) | (mbn << 5);
2082 gen_rldnm(ctx, mb, 63);
2083 }
2084 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2085
2086 /* rldcr - rldcr. */
2087 static inline void gen_rldcr(DisasContext *ctx, int men)
2088 {
2089 uint32_t me;
2090
2091 me = MB(ctx->opcode) | (men << 5);
2092 gen_rldnm(ctx, 0, me);
2093 }
2094 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2095
2096 /* rldimi - rldimi. */
2097 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2098 {
2099 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2100 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2101 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2102 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2103 uint32_t me = 63 - sh;
2104
2105 if (mb <= me) {
2106 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2107 } else {
2108 target_ulong mask = MASK(mb, me);
2109 TCGv t1 = tcg_temp_new();
2110
2111 tcg_gen_rotli_tl(t1, t_rs, sh);
2112 tcg_gen_andi_tl(t1, t1, mask);
2113 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2114 tcg_gen_or_tl(t_ra, t_ra, t1);
2115 tcg_temp_free(t1);
2116 }
2117 if (unlikely(Rc(ctx->opcode) != 0)) {
2118 gen_set_Rc0(ctx, t_ra);
2119 }
2120 }
2121 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2122 #endif
2123
2124 /*** Integer shift ***/
2125
2126 /* slw & slw. */
2127 static void gen_slw(DisasContext *ctx)
2128 {
2129 TCGv t0, t1;
2130
2131 t0 = tcg_temp_new();
2132 /* AND rS with a mask that is 0 when rB >= 0x20 */
2133 #if defined(TARGET_PPC64)
2134 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2135 tcg_gen_sari_tl(t0, t0, 0x3f);
2136 #else
2137 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2138 tcg_gen_sari_tl(t0, t0, 0x1f);
2139 #endif
2140 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2141 t1 = tcg_temp_new();
2142 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2143 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2144 tcg_temp_free(t1);
2145 tcg_temp_free(t0);
2146 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2147 if (unlikely(Rc(ctx->opcode) != 0))
2148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2149 }
2150
2151 /* sraw & sraw. */
2152 static void gen_sraw(DisasContext *ctx)
2153 {
2154 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2155 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2156 if (unlikely(Rc(ctx->opcode) != 0))
2157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2158 }
2159
2160 /* srawi & srawi. */
2161 static void gen_srawi(DisasContext *ctx)
2162 {
2163 int sh = SH(ctx->opcode);
2164 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2165 TCGv src = cpu_gpr[rS(ctx->opcode)];
2166 if (sh == 0) {
2167 tcg_gen_ext32s_tl(dst, src);
2168 tcg_gen_movi_tl(cpu_ca, 0);
2169 if (is_isa300(ctx)) {
2170 tcg_gen_movi_tl(cpu_ca32, 0);
2171 }
2172 } else {
2173 TCGv t0;
2174 tcg_gen_ext32s_tl(dst, src);
2175 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2176 t0 = tcg_temp_new();
2177 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2178 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2179 tcg_temp_free(t0);
2180 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2181 if (is_isa300(ctx)) {
2182 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2183 }
2184 tcg_gen_sari_tl(dst, dst, sh);
2185 }
2186 if (unlikely(Rc(ctx->opcode) != 0)) {
2187 gen_set_Rc0(ctx, dst);
2188 }
2189 }
2190
2191 /* srw & srw. */
2192 static void gen_srw(DisasContext *ctx)
2193 {
2194 TCGv t0, t1;
2195
2196 t0 = tcg_temp_new();
2197 /* AND rS with a mask that is 0 when rB >= 0x20 */
2198 #if defined(TARGET_PPC64)
2199 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2200 tcg_gen_sari_tl(t0, t0, 0x3f);
2201 #else
2202 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2203 tcg_gen_sari_tl(t0, t0, 0x1f);
2204 #endif
2205 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2206 tcg_gen_ext32u_tl(t0, t0);
2207 t1 = tcg_temp_new();
2208 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2209 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2210 tcg_temp_free(t1);
2211 tcg_temp_free(t0);
2212 if (unlikely(Rc(ctx->opcode) != 0))
2213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2214 }
2215
2216 #if defined(TARGET_PPC64)
2217 /* sld & sld. */
2218 static void gen_sld(DisasContext *ctx)
2219 {
2220 TCGv t0, t1;
2221
2222 t0 = tcg_temp_new();
2223 /* AND rS with a mask that is 0 when rB >= 0x40 */
2224 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2225 tcg_gen_sari_tl(t0, t0, 0x3f);
2226 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2227 t1 = tcg_temp_new();
2228 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2229 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2230 tcg_temp_free(t1);
2231 tcg_temp_free(t0);
2232 if (unlikely(Rc(ctx->opcode) != 0))
2233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2234 }
2235
2236 /* srad & srad. */
2237 static void gen_srad(DisasContext *ctx)
2238 {
2239 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2240 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2241 if (unlikely(Rc(ctx->opcode) != 0))
2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2243 }
2244 /* sradi & sradi. */
2245 static inline void gen_sradi(DisasContext *ctx, int n)
2246 {
2247 int sh = SH(ctx->opcode) + (n << 5);
2248 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2249 TCGv src = cpu_gpr[rS(ctx->opcode)];
2250 if (sh == 0) {
2251 tcg_gen_mov_tl(dst, src);
2252 tcg_gen_movi_tl(cpu_ca, 0);
2253 if (is_isa300(ctx)) {
2254 tcg_gen_movi_tl(cpu_ca32, 0);
2255 }
2256 } else {
2257 TCGv t0;
2258 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2259 t0 = tcg_temp_new();
2260 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2261 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2262 tcg_temp_free(t0);
2263 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2264 if (is_isa300(ctx)) {
2265 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2266 }
2267 tcg_gen_sari_tl(dst, src, sh);
2268 }
2269 if (unlikely(Rc(ctx->opcode) != 0)) {
2270 gen_set_Rc0(ctx, dst);
2271 }
2272 }
2273
2274 static void gen_sradi0(DisasContext *ctx)
2275 {
2276 gen_sradi(ctx, 0);
2277 }
2278
2279 static void gen_sradi1(DisasContext *ctx)
2280 {
2281 gen_sradi(ctx, 1);
2282 }
2283
2284 /* extswsli & extswsli. */
2285 static inline void gen_extswsli(DisasContext *ctx, int n)
2286 {
2287 int sh = SH(ctx->opcode) + (n << 5);
2288 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2289 TCGv src = cpu_gpr[rS(ctx->opcode)];
2290
2291 tcg_gen_ext32s_tl(dst, src);
2292 tcg_gen_shli_tl(dst, dst, sh);
2293 if (unlikely(Rc(ctx->opcode) != 0)) {
2294 gen_set_Rc0(ctx, dst);
2295 }
2296 }
2297
2298 static void gen_extswsli0(DisasContext *ctx)
2299 {
2300 gen_extswsli(ctx, 0);
2301 }
2302
2303 static void gen_extswsli1(DisasContext *ctx)
2304 {
2305 gen_extswsli(ctx, 1);
2306 }
2307
2308 /* srd & srd. */
2309 static void gen_srd(DisasContext *ctx)
2310 {
2311 TCGv t0, t1;
2312
2313 t0 = tcg_temp_new();
2314 /* AND rS with a mask that is 0 when rB >= 0x40 */
2315 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2316 tcg_gen_sari_tl(t0, t0, 0x3f);
2317 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2318 t1 = tcg_temp_new();
2319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2320 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2321 tcg_temp_free(t1);
2322 tcg_temp_free(t0);
2323 if (unlikely(Rc(ctx->opcode) != 0))
2324 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2325 }
2326 #endif
2327
2328 /*** Addressing modes ***/
2329 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2330 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2331 target_long maskl)
2332 {
2333 target_long simm = SIMM(ctx->opcode);
2334
2335 simm &= ~maskl;
2336 if (rA(ctx->opcode) == 0) {
2337 if (NARROW_MODE(ctx)) {
2338 simm = (uint32_t)simm;
2339 }
2340 tcg_gen_movi_tl(EA, simm);
2341 } else if (likely(simm != 0)) {
2342 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2343 if (NARROW_MODE(ctx)) {
2344 tcg_gen_ext32u_tl(EA, EA);
2345 }
2346 } else {
2347 if (NARROW_MODE(ctx)) {
2348 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2349 } else {
2350 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2351 }
2352 }
2353 }
2354
2355 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2356 {
2357 if (rA(ctx->opcode) == 0) {
2358 if (NARROW_MODE(ctx)) {
2359 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2360 } else {
2361 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2362 }
2363 } else {
2364 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 }
2369 }
2370
2371 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2372 {
2373 if (rA(ctx->opcode) == 0) {
2374 tcg_gen_movi_tl(EA, 0);
2375 } else if (NARROW_MODE(ctx)) {
2376 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 } else {
2378 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2379 }
2380 }
2381
2382 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2383 target_long val)
2384 {
2385 tcg_gen_addi_tl(ret, arg1, val);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(ret, ret);
2388 }
2389 }
2390
2391 static inline void gen_align_no_le(DisasContext *ctx)
2392 {
2393 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2394 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2395 }
2396
2397 /*** Integer load ***/
2398 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2399 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2400
2401 #define GEN_QEMU_LOAD_TL(ldop, op) \
2402 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2403 TCGv val, \
2404 TCGv addr) \
2405 { \
2406 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2407 }
2408
2409 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2410 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2411 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2412 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2413 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2414
2415 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2416 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2417
2418 #define GEN_QEMU_LOAD_64(ldop, op) \
2419 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2420 TCGv_i64 val, \
2421 TCGv addr) \
2422 { \
2423 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2424 }
2425
2426 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2427 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2428 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2429 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2430 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2431
2432 #if defined(TARGET_PPC64)
2433 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2434 #endif
2435
2436 #define GEN_QEMU_STORE_TL(stop, op) \
2437 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2438 TCGv val, \
2439 TCGv addr) \
2440 { \
2441 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2442 }
2443
2444 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2445 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2446 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2447
2448 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2449 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2450
2451 #define GEN_QEMU_STORE_64(stop, op) \
2452 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2453 TCGv_i64 val, \
2454 TCGv addr) \
2455 { \
2456 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2457 }
2458
2459 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2460 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2461 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2462 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2463
2464 #if defined(TARGET_PPC64)
2465 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2466 #endif
2467
2468 #define GEN_LD(name, ldop, opc, type) \
2469 static void glue(gen_, name)(DisasContext *ctx) \
2470 { \
2471 TCGv EA; \
2472 gen_set_access_type(ctx, ACCESS_INT); \
2473 EA = tcg_temp_new(); \
2474 gen_addr_imm_index(ctx, EA, 0); \
2475 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2476 tcg_temp_free(EA); \
2477 }
2478
2479 #define GEN_LDU(name, ldop, opc, type) \
2480 static void glue(gen_, name##u)(DisasContext *ctx) \
2481 { \
2482 TCGv EA; \
2483 if (unlikely(rA(ctx->opcode) == 0 || \
2484 rA(ctx->opcode) == rD(ctx->opcode))) { \
2485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2486 return; \
2487 } \
2488 gen_set_access_type(ctx, ACCESS_INT); \
2489 EA = tcg_temp_new(); \
2490 if (type == PPC_64B) \
2491 gen_addr_imm_index(ctx, EA, 0x03); \
2492 else \
2493 gen_addr_imm_index(ctx, EA, 0); \
2494 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2495 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2496 tcg_temp_free(EA); \
2497 }
2498
2499 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2500 static void glue(gen_, name##ux)(DisasContext *ctx) \
2501 { \
2502 TCGv EA; \
2503 if (unlikely(rA(ctx->opcode) == 0 || \
2504 rA(ctx->opcode) == rD(ctx->opcode))) { \
2505 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2506 return; \
2507 } \
2508 gen_set_access_type(ctx, ACCESS_INT); \
2509 EA = tcg_temp_new(); \
2510 gen_addr_reg_index(ctx, EA); \
2511 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2513 tcg_temp_free(EA); \
2514 }
2515
2516 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2517 static void glue(gen_, name##x)(DisasContext *ctx) \
2518 { \
2519 TCGv EA; \
2520 chk; \
2521 gen_set_access_type(ctx, ACCESS_INT); \
2522 EA = tcg_temp_new(); \
2523 gen_addr_reg_index(ctx, EA); \
2524 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2525 tcg_temp_free(EA); \
2526 }
2527
2528 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2529 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2530
2531 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2532 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2533
2534 #define GEN_LDS(name, ldop, op, type) \
2535 GEN_LD(name, ldop, op | 0x20, type); \
2536 GEN_LDU(name, ldop, op | 0x21, type); \
2537 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2538 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2539
2540 /* lbz lbzu lbzux lbzx */
2541 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2542 /* lha lhau lhaux lhax */
2543 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2544 /* lhz lhzu lhzux lhzx */
2545 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2546 /* lwz lwzu lwzux lwzx */
2547 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2548 #if defined(TARGET_PPC64)
2549 /* lwaux */
2550 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2551 /* lwax */
2552 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2553 /* ldux */
2554 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2555 /* ldx */
2556 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2557
2558 /* CI load/store variants */
2559 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2560 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2561 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2562 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2563
2564 static void gen_ld(DisasContext *ctx)
2565 {
2566 TCGv EA;
2567 if (Rc(ctx->opcode)) {
2568 if (unlikely(rA(ctx->opcode) == 0 ||
2569 rA(ctx->opcode) == rD(ctx->opcode))) {
2570 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2571 return;
2572 }
2573 }
2574 gen_set_access_type(ctx, ACCESS_INT);
2575 EA = tcg_temp_new();
2576 gen_addr_imm_index(ctx, EA, 0x03);
2577 if (ctx->opcode & 0x02) {
2578 /* lwa (lwau is undefined) */
2579 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2580 } else {
2581 /* ld - ldu */
2582 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2583 }
2584 if (Rc(ctx->opcode))
2585 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2586 tcg_temp_free(EA);
2587 }
2588
2589 /* lq */
2590 static void gen_lq(DisasContext *ctx)
2591 {
2592 int ra, rd;
2593 TCGv EA, hi, lo;
2594
2595 /* lq is a legal user mode instruction starting in ISA 2.07 */
2596 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2597 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2598
2599 if (!legal_in_user_mode && ctx->pr) {
2600 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2601 return;
2602 }
2603
2604 if (!le_is_supported && ctx->le_mode) {
2605 gen_align_no_le(ctx);
2606 return;
2607 }
2608 ra = rA(ctx->opcode);
2609 rd = rD(ctx->opcode);
2610 if (unlikely((rd & 1) || rd == ra)) {
2611 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2612 return;
2613 }
2614
2615 gen_set_access_type(ctx, ACCESS_INT);
2616 EA = tcg_temp_new();
2617 gen_addr_imm_index(ctx, EA, 0x0F);
2618
2619 /* Note that the low part is always in RD+1, even in LE mode. */
2620 lo = cpu_gpr[rd + 1];
2621 hi = cpu_gpr[rd];
2622
2623 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2624 #ifdef CONFIG_ATOMIC128
2625 TCGv_i32 oi = tcg_temp_new_i32();
2626 if (ctx->le_mode) {
2627 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2628 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2629 } else {
2630 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2631 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2632 }
2633 tcg_temp_free_i32(oi);
2634 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2635 #else
2636 /* Restart with exclusive lock. */
2637 gen_helper_exit_atomic(cpu_env);
2638 ctx->base.is_jmp = DISAS_NORETURN;
2639 #endif
2640 } else if (ctx->le_mode) {
2641 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2642 gen_addr_add(ctx, EA, EA, 8);
2643 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2644 } else {
2645 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2646 gen_addr_add(ctx, EA, EA, 8);
2647 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2648 }
2649 tcg_temp_free(EA);
2650 }
2651 #endif
2652
2653 /*** Integer store ***/
2654 #define GEN_ST(name, stop, opc, type) \
2655 static void glue(gen_, name)(DisasContext *ctx) \
2656 { \
2657 TCGv EA; \
2658 gen_set_access_type(ctx, ACCESS_INT); \
2659 EA = tcg_temp_new(); \
2660 gen_addr_imm_index(ctx, EA, 0); \
2661 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2662 tcg_temp_free(EA); \
2663 }
2664
2665 #define GEN_STU(name, stop, opc, type) \
2666 static void glue(gen_, stop##u)(DisasContext *ctx) \
2667 { \
2668 TCGv EA; \
2669 if (unlikely(rA(ctx->opcode) == 0)) { \
2670 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2671 return; \
2672 } \
2673 gen_set_access_type(ctx, ACCESS_INT); \
2674 EA = tcg_temp_new(); \
2675 if (type == PPC_64B) \
2676 gen_addr_imm_index(ctx, EA, 0x03); \
2677 else \
2678 gen_addr_imm_index(ctx, EA, 0); \
2679 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2680 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2681 tcg_temp_free(EA); \
2682 }
2683
2684 #define GEN_STUX(name, stop, opc2, opc3, type) \
2685 static void glue(gen_, name##ux)(DisasContext *ctx) \
2686 { \
2687 TCGv EA; \
2688 if (unlikely(rA(ctx->opcode) == 0)) { \
2689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2690 return; \
2691 } \
2692 gen_set_access_type(ctx, ACCESS_INT); \
2693 EA = tcg_temp_new(); \
2694 gen_addr_reg_index(ctx, EA); \
2695 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2697 tcg_temp_free(EA); \
2698 }
2699
2700 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2701 static void glue(gen_, name##x)(DisasContext *ctx) \
2702 { \
2703 TCGv EA; \
2704 chk; \
2705 gen_set_access_type(ctx, ACCESS_INT); \
2706 EA = tcg_temp_new(); \
2707 gen_addr_reg_index(ctx, EA); \
2708 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2709 tcg_temp_free(EA); \
2710 }
2711 #define GEN_STX(name, stop, opc2, opc3, type) \
2712 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2713
2714 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2715 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2716
2717 #define GEN_STS(name, stop, op, type) \
2718 GEN_ST(name, stop, op | 0x20, type); \
2719 GEN_STU(name, stop, op | 0x21, type); \
2720 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2721 GEN_STX(name, stop, 0x17, op | 0x00, type)
2722
2723 /* stb stbu stbux stbx */
2724 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2725 /* sth sthu sthux sthx */
2726 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2727 /* stw stwu stwux stwx */
2728 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2729 #if defined(TARGET_PPC64)
2730 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2731 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2732 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2733 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2734 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2735 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2736
2737 static void gen_std(DisasContext *ctx)
2738 {
2739 int rs;
2740 TCGv EA;
2741
2742 rs = rS(ctx->opcode);
2743 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2744 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2745 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2746 TCGv hi, lo;
2747
2748 if (!(ctx->insns_flags & PPC_64BX)) {
2749 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2750 }
2751
2752 if (!legal_in_user_mode && ctx->pr) {
2753 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2754 return;
2755 }
2756
2757 if (!le_is_supported && ctx->le_mode) {
2758 gen_align_no_le(ctx);
2759 return;
2760 }
2761
2762 if (unlikely(rs & 1)) {
2763 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2764 return;
2765 }
2766 gen_set_access_type(ctx, ACCESS_INT);
2767 EA = tcg_temp_new();
2768 gen_addr_imm_index(ctx, EA, 0x03);
2769
2770 /* Note that the low part is always in RS+1, even in LE mode. */
2771 lo = cpu_gpr[rs + 1];
2772 hi = cpu_gpr[rs];
2773
2774 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2775 #ifdef CONFIG_ATOMIC128
2776 TCGv_i32 oi = tcg_temp_new_i32();
2777 if (ctx->le_mode) {
2778 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2779 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2780 } else {
2781 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2782 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2783 }
2784 tcg_temp_free_i32(oi);
2785 #else
2786 /* Restart with exclusive lock. */
2787 gen_helper_exit_atomic(cpu_env);
2788 ctx->base.is_jmp = DISAS_NORETURN;
2789 #endif
2790 } else if (ctx->le_mode) {
2791 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2792 gen_addr_add(ctx, EA, EA, 8);
2793 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2794 } else {
2795 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2796 gen_addr_add(ctx, EA, EA, 8);
2797 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2798 }
2799 tcg_temp_free(EA);
2800 } else {
2801 /* std / stdu */
2802 if (Rc(ctx->opcode)) {
2803 if (unlikely(rA(ctx->opcode) == 0)) {
2804 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2805 return;
2806 }
2807 }
2808 gen_set_access_type(ctx, ACCESS_INT);
2809 EA = tcg_temp_new();
2810 gen_addr_imm_index(ctx, EA, 0x03);
2811 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2812 if (Rc(ctx->opcode))
2813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2814 tcg_temp_free(EA);
2815 }
2816 }
2817 #endif
2818 /*** Integer load and store with byte reverse ***/
2819
2820 /* lhbrx */
2821 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2822
2823 /* lwbrx */
2824 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2825
2826 #if defined(TARGET_PPC64)
2827 /* ldbrx */
2828 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2829 /* stdbrx */
2830 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2831 #endif /* TARGET_PPC64 */
2832
2833 /* sthbrx */
2834 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2835 /* stwbrx */
2836 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2837
2838 /*** Integer load and store multiple ***/
2839
2840 /* lmw */
2841 static void gen_lmw(DisasContext *ctx)
2842 {
2843 TCGv t0;
2844 TCGv_i32 t1;
2845
2846 if (ctx->le_mode) {
2847 gen_align_no_le(ctx);
2848 return;
2849 }
2850 gen_set_access_type(ctx, ACCESS_INT);
2851 t0 = tcg_temp_new();
2852 t1 = tcg_const_i32(rD(ctx->opcode));
2853 gen_addr_imm_index(ctx, t0, 0);
2854 gen_helper_lmw(cpu_env, t0, t1);
2855 tcg_temp_free(t0);
2856 tcg_temp_free_i32(t1);
2857 }
2858
2859 /* stmw */
2860 static void gen_stmw(DisasContext *ctx)
2861 {
2862 TCGv t0;
2863 TCGv_i32 t1;
2864
2865 if (ctx->le_mode) {
2866 gen_align_no_le(ctx);
2867 return;
2868 }
2869 gen_set_access_type(ctx, ACCESS_INT);
2870 t0 = tcg_temp_new();
2871 t1 = tcg_const_i32(rS(ctx->opcode));
2872 gen_addr_imm_index(ctx, t0, 0);
2873 gen_helper_stmw(cpu_env, t0, t1);
2874 tcg_temp_free(t0);
2875 tcg_temp_free_i32(t1);
2876 }
2877
2878 /*** Integer load and store strings ***/
2879
2880 /* lswi */
2881 /* PowerPC32 specification says we must generate an exception if
2882 * rA is in the range of registers to be loaded.
2883 * In an other hand, IBM says this is valid, but rA won't be loaded.
2884 * For now, I'll follow the spec...
2885 */
2886 static void gen_lswi(DisasContext *ctx)
2887 {
2888 TCGv t0;
2889 TCGv_i32 t1, t2;
2890 int nb = NB(ctx->opcode);
2891 int start = rD(ctx->opcode);
2892 int ra = rA(ctx->opcode);
2893 int nr;
2894
2895 if (ctx->le_mode) {
2896 gen_align_no_le(ctx);
2897 return;
2898 }
2899 if (nb == 0)
2900 nb = 32;
2901 nr = DIV_ROUND_UP(nb, 4);
2902 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2904 return;
2905 }
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 t0 = tcg_temp_new();
2908 gen_addr_register(ctx, t0);
2909 t1 = tcg_const_i32(nb);
2910 t2 = tcg_const_i32(start);
2911 gen_helper_lsw(cpu_env, t0, t1, t2);
2912 tcg_temp_free(t0);
2913 tcg_temp_free_i32(t1);
2914 tcg_temp_free_i32(t2);
2915 }
2916
2917 /* lswx */
2918 static void gen_lswx(DisasContext *ctx)
2919 {
2920 TCGv t0;
2921 TCGv_i32 t1, t2, t3;
2922
2923 if (ctx->le_mode) {
2924 gen_align_no_le(ctx);
2925 return;
2926 }
2927 gen_set_access_type(ctx, ACCESS_INT);
2928 t0 = tcg_temp_new();
2929 gen_addr_reg_index(ctx, t0);
2930 t1 = tcg_const_i32(rD(ctx->opcode));
2931 t2 = tcg_const_i32(rA(ctx->opcode));
2932 t3 = tcg_const_i32(rB(ctx->opcode));
2933 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2934 tcg_temp_free(t0);
2935 tcg_temp_free_i32(t1);
2936 tcg_temp_free_i32(t2);
2937 tcg_temp_free_i32(t3);
2938 }
2939
2940 /* stswi */
2941 static void gen_stswi(DisasContext *ctx)
2942 {
2943 TCGv t0;
2944 TCGv_i32 t1, t2;
2945 int nb = NB(ctx->opcode);
2946
2947 if (ctx->le_mode) {
2948 gen_align_no_le(ctx);
2949 return;
2950 }
2951 gen_set_access_type(ctx, ACCESS_INT);
2952 t0 = tcg_temp_new();
2953 gen_addr_register(ctx, t0);
2954 if (nb == 0)
2955 nb = 32;
2956 t1 = tcg_const_i32(nb);
2957 t2 = tcg_const_i32(rS(ctx->opcode));
2958 gen_helper_stsw(cpu_env, t0, t1, t2);
2959 tcg_temp_free(t0);
2960 tcg_temp_free_i32(t1);
2961 tcg_temp_free_i32(t2);
2962 }
2963
2964 /* stswx */
2965 static void gen_stswx(DisasContext *ctx)
2966 {
2967 TCGv t0;
2968 TCGv_i32 t1, t2;
2969
2970 if (ctx->le_mode) {
2971 gen_align_no_le(ctx);
2972 return;
2973 }
2974 gen_set_access_type(ctx, ACCESS_INT);
2975 t0 = tcg_temp_new();
2976 gen_addr_reg_index(ctx, t0);
2977 t1 = tcg_temp_new_i32();
2978 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2979 tcg_gen_andi_i32(t1, t1, 0x7F);
2980 t2 = tcg_const_i32(rS(ctx->opcode));
2981 gen_helper_stsw(cpu_env, t0, t1, t2);
2982 tcg_temp_free(t0);
2983 tcg_temp_free_i32(t1);
2984 tcg_temp_free_i32(t2);
2985 }
2986
2987 /*** Memory synchronisation ***/
2988 /* eieio */
2989 static void gen_eieio(DisasContext *ctx)
2990 {
2991 TCGBar bar = TCG_MO_LD_ST;
2992
2993 /*
2994 * POWER9 has a eieio instruction variant using bit 6 as a hint to
2995 * tell the CPU it is a store-forwarding barrier.
2996 */
2997 if (ctx->opcode & 0x2000000) {
2998 /*
2999 * ISA says that "Reserved fields in instructions are ignored
3000 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3001 * as this is not an instruction software should be using,
3002 * complain to the user.
3003 */
3004 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3005 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3006 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3007 } else {
3008 bar = TCG_MO_ST_LD;
3009 }
3010 }
3011
3012 tcg_gen_mb(bar | TCG_BAR_SC);
3013 }
3014
3015 #if !defined(CONFIG_USER_ONLY)
3016 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3017 {
3018 TCGv_i32 t;
3019 TCGLabel *l;
3020
3021 if (!ctx->lazy_tlb_flush) {
3022 return;
3023 }
3024 l = gen_new_label();
3025 t = tcg_temp_new_i32();
3026 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3027 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3028 if (global) {
3029 gen_helper_check_tlb_flush_global(cpu_env);
3030 } else {
3031 gen_helper_check_tlb_flush_local(cpu_env);
3032 }
3033 gen_set_label(l);
3034 tcg_temp_free_i32(t);
3035 }
3036 #else
3037 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3038 #endif
3039
3040 /* isync */
3041 static void gen_isync(DisasContext *ctx)
3042 {
3043 /*
3044 * We need to check for a pending TLB flush. This can only happen in
3045 * kernel mode however so check MSR_PR
3046 */
3047 if (!ctx->pr) {
3048 gen_check_tlb_flush(ctx, false);
3049 }
3050 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3051 gen_stop_exception(ctx);
3052 }
3053
3054 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3055
3056 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3057 {
3058 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3059 TCGv t0 = tcg_temp_new();
3060
3061 gen_set_access_type(ctx, ACCESS_RES);
3062 gen_addr_reg_index(ctx, t0);
3063 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3064 tcg_gen_mov_tl(cpu_reserve, t0);
3065 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3066 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3067 tcg_temp_free(t0);
3068 }
3069
3070 #define LARX(name, memop) \
3071 static void gen_##name(DisasContext *ctx) \
3072 { \
3073 gen_load_locked(ctx, memop); \
3074 }
3075
3076 /* lwarx */
3077 LARX(lbarx, DEF_MEMOP(MO_UB))
3078 LARX(lharx, DEF_MEMOP(MO_UW))
3079 LARX(lwarx, DEF_MEMOP(MO_UL))
3080
3081 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3082 {
3083 uint32_t gpr_FC = FC(ctx->opcode);
3084 TCGv EA = tcg_temp_new();
3085 TCGv src, dst;
3086
3087 gen_addr_register(ctx, EA);
3088 dst = cpu_gpr[rD(ctx->opcode)];
3089 src = cpu_gpr[rD(ctx->opcode) + 1];
3090
3091 memop |= MO_ALIGN;
3092 switch (gpr_FC) {
3093 case 0: /* Fetch and add */
3094 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3095 break;
3096 case 1: /* Fetch and xor */
3097 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3098 break;
3099 case 2: /* Fetch and or */
3100 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3101 break;
3102 case 3: /* Fetch and 'and' */
3103 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3104 break;
3105 case 4: /* Fetch and max unsigned */
3106 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3107 break;
3108 case 5: /* Fetch and max signed */
3109 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3110 break;
3111 case 6: /* Fetch and min unsigned */
3112 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3113 break;
3114 case 7: /* Fetch and min signed */
3115 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3116 break;
3117 case 8: /* Swap */
3118 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3119 break;
3120 case 16: /* compare and swap not equal */
3121 case 24: /* Fetch and increment bounded */
3122 case 25: /* Fetch and increment equal */
3123 case 28: /* Fetch and decrement bounded */
3124 gen_invalid(ctx);
3125 break;
3126 default:
3127 /* invoke data storage error handler */
3128 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3129 }
3130 tcg_temp_free(EA);
3131 }
3132
3133 static void gen_lwat(DisasContext *ctx)
3134 {
3135 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3136 }
3137
3138 #ifdef TARGET_PPC64
3139 static void gen_ldat(DisasContext *ctx)
3140 {
3141 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3142 }
3143 #endif
3144
3145 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3146 {
3147 uint32_t gpr_FC = FC(ctx->opcode);
3148 TCGv EA = tcg_temp_new();
3149 TCGv src, discard;
3150
3151 gen_addr_register(ctx, EA);
3152 src = cpu_gpr[rD(ctx->opcode)];
3153 discard = tcg_temp_new();
3154
3155 memop |= MO_ALIGN;
3156 switch (gpr_FC) {
3157 case 0: /* add and Store */
3158 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3159 break;
3160 case 1: /* xor and Store */
3161 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3162 break;
3163 case 2: /* Or and Store */
3164 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3165 break;
3166 case 3: /* 'and' and Store */
3167 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3168 break;
3169 case 4: /* Store max unsigned */
3170 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3171 break;
3172 case 5: /* Store max signed */
3173 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3174 break;
3175 case 6: /* Store min unsigned */
3176 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3177 break;
3178 case 7: /* Store min signed */
3179 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3180 break;
3181 case 24: /* Store twin */
3182 gen_invalid(ctx);
3183 break;
3184 default:
3185 /* invoke data storage error handler */
3186 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3187 }
3188 tcg_temp_free(discard);
3189 tcg_temp_free(EA);
3190 }
3191
3192 static void gen_stwat(DisasContext *ctx)
3193 {
3194 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3195 }
3196
3197 #ifdef TARGET_PPC64
3198 static void gen_stdat(DisasContext *ctx)
3199 {
3200 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3201 }
3202 #endif
3203
3204 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3205 {
3206 TCGLabel *l1 = gen_new_label();
3207 TCGLabel *l2 = gen_new_label();
3208 TCGv t0 = tcg_temp_new();
3209 int reg = rS(ctx->opcode);
3210
3211 gen_set_access_type(ctx, ACCESS_RES);
3212 gen_addr_reg_index(ctx, t0);
3213 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3214 tcg_temp_free(t0);
3215
3216 t0 = tcg_temp_new();
3217 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3218 cpu_gpr[reg], ctx->mem_idx,
3219 DEF_MEMOP(memop) | MO_ALIGN);
3220 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3221 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3222 tcg_gen_or_tl(t0, t0, cpu_so);
3223 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3224 tcg_temp_free(t0);
3225 tcg_gen_br(l2);
3226
3227 gen_set_label(l1);
3228
3229 /* Address mismatch implies failure. But we still need to provide the
3230 memory barrier semantics of the instruction. */
3231 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3232 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3233
3234 gen_set_label(l2);
3235 tcg_gen_movi_tl(cpu_reserve, -1);
3236 }
3237
3238 #define STCX(name, memop) \
3239 static void gen_##name(DisasContext *ctx) \
3240 { \
3241 gen_conditional_store(ctx, memop); \
3242 }
3243
3244 STCX(stbcx_, DEF_MEMOP(MO_UB))
3245 STCX(sthcx_, DEF_MEMOP(MO_UW))
3246 STCX(stwcx_, DEF_MEMOP(MO_UL))
3247
3248 #if defined(TARGET_PPC64)
3249 /* ldarx */
3250 LARX(ldarx, DEF_MEMOP(MO_Q))
3251 /* stdcx. */
3252 STCX(stdcx_, DEF_MEMOP(MO_Q))
3253
3254 /* lqarx */
3255 static void gen_lqarx(DisasContext *ctx)
3256 {
3257 int rd = rD(ctx->opcode);
3258 TCGv EA, hi, lo;
3259
3260 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3261 (rd == rB(ctx->opcode)))) {
3262 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3263 return;
3264 }
3265
3266 gen_set_access_type(ctx, ACCESS_RES);
3267 EA = tcg_temp_new();
3268 gen_addr_reg_index(ctx, EA);
3269
3270 /* Note that the low part is always in RD+1, even in LE mode. */
3271 lo = cpu_gpr[rd + 1];
3272 hi = cpu_gpr[rd];
3273
3274 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3275 #ifdef CONFIG_ATOMIC128
3276 TCGv_i32 oi = tcg_temp_new_i32();
3277 if (ctx->le_mode) {
3278 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3279 ctx->mem_idx));
3280 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3281 } else {
3282 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3283 ctx->mem_idx));
3284 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3285 }
3286 tcg_temp_free_i32(oi);
3287 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3288 #else
3289 /* Restart with exclusive lock. */
3290 gen_helper_exit_atomic(cpu_env);
3291 ctx->base.is_jmp = DISAS_NORETURN;
3292 tcg_temp_free(EA);
3293 return;
3294 #endif
3295 } else if (ctx->le_mode) {
3296 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3297 tcg_gen_mov_tl(cpu_reserve, EA);
3298 gen_addr_add(ctx, EA, EA, 8);
3299 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3300 } else {
3301 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3302 tcg_gen_mov_tl(cpu_reserve, EA);
3303 gen_addr_add(ctx, EA, EA, 8);
3304 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3305 }
3306 tcg_temp_free(EA);
3307
3308 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3309 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3310 }
3311
3312 /* stqcx. */
3313 static void gen_stqcx_(DisasContext *ctx)
3314 {
3315 int rs = rS(ctx->opcode);
3316 TCGv EA, hi, lo;
3317
3318 if (unlikely(rs & 1)) {
3319 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3320 return;
3321 }
3322
3323 gen_set_access_type(ctx, ACCESS_RES);
3324 EA = tcg_temp_new();
3325 gen_addr_reg_index(ctx, EA);
3326
3327 /* Note that the low part is always in RS+1, even in LE mode. */
3328 lo = cpu_gpr[rs + 1];
3329 hi = cpu_gpr[rs];
3330
3331 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3332 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3333 #ifdef CONFIG_ATOMIC128
3334 if (ctx->le_mode) {
3335 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3336 } else {
3337 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);
3338 }
3339 #else
3340 /* Restart with exclusive lock. */
3341 gen_helper_exit_atomic(cpu_env);
3342 ctx->base.is_jmp = DISAS_NORETURN;
3343 #endif
3344 tcg_temp_free(EA);
3345 tcg_temp_free_i32(oi);
3346 } else {
3347 TCGLabel *lab_fail = gen_new_label();
3348 TCGLabel *lab_over = gen_new_label();
3349 TCGv_i64 t0 = tcg_temp_new_i64();
3350 TCGv_i64 t1 = tcg_temp_new_i64();
3351
3352 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3353 tcg_temp_free(EA);
3354
3355 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3356 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3357 ? offsetof(CPUPPCState, reserve_val2)
3358 : offsetof(CPUPPCState, reserve_val)));
3359 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3360
3361 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3362 gen_qemu_ld64_i64(ctx, t0, t0);
3363 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3364 ? offsetof(CPUPPCState, reserve_val)
3365 : offsetof(CPUPPCState, reserve_val2)));
3366 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3367
3368 /* Success */
3369 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3370 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3371 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3372
3373 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3374 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3375 tcg_gen_br(lab_over);
3376
3377 gen_set_label(lab_fail);
3378 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3379
3380 gen_set_label(lab_over);
3381 tcg_gen_movi_tl(cpu_reserve, -1);
3382 tcg_temp_free_i64(t0);
3383 tcg_temp_free_i64(t1);
3384 }
3385 }
3386 #endif /* defined(TARGET_PPC64) */
3387
3388 /* sync */
3389 static void gen_sync(DisasContext *ctx)
3390 {
3391 uint32_t l = (ctx->opcode >> 21) & 3;
3392
3393 /*
3394 * We may need to check for a pending TLB flush.
3395 *
3396 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3397 *
3398 * Additionally, this can only happen in kernel mode however so
3399 * check MSR_PR as well.
3400 */
3401 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3402 gen_check_tlb_flush(ctx, true);
3403 }
3404 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3405 }
3406
3407 /* wait */
3408 static void gen_wait(DisasContext *ctx)
3409 {
3410 TCGv_i32 t0 = tcg_const_i32(1);
3411 tcg_gen_st_i32(t0, cpu_env,
3412 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3413 tcg_temp_free_i32(t0);
3414 /* Stop translation, as the CPU is supposed to sleep from now */
3415 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3416 }
3417
3418 #if defined(TARGET_PPC64)
3419 static void gen_doze(DisasContext *ctx)
3420 {
3421 #if defined(CONFIG_USER_ONLY)
3422 GEN_PRIV;
3423 #else
3424 TCGv_i32 t;
3425
3426 CHK_HV;
3427 t = tcg_const_i32(PPC_PM_DOZE);
3428 gen_helper_pminsn(cpu_env, t);
3429 tcg_temp_free_i32(t);
3430 gen_stop_exception(ctx);
3431 #endif /* defined(CONFIG_USER_ONLY) */
3432 }
3433
3434 static void gen_nap(DisasContext *ctx)
3435 {
3436 #if defined(CONFIG_USER_ONLY)
3437 GEN_PRIV;
3438 #else
3439 TCGv_i32 t;
3440
3441 CHK_HV;
3442 t = tcg_const_i32(PPC_PM_NAP);
3443 gen_helper_pminsn(cpu_env, t);
3444 tcg_temp_free_i32(t);
3445 gen_stop_exception(ctx);
3446 #endif /* defined(CONFIG_USER_ONLY) */
3447 }
3448
3449 static void gen_stop(DisasContext *ctx)
3450 {
3451 gen_nap(ctx);
3452 }
3453
3454 static void gen_sleep(DisasContext *ctx)
3455 {
3456 #if defined(CONFIG_USER_ONLY)
3457 GEN_PRIV;
3458 #else
3459 TCGv_i32 t;
3460
3461 CHK_HV;
3462 t = tcg_const_i32(PPC_PM_SLEEP);
3463 gen_helper_pminsn(cpu_env, t);
3464 tcg_temp_free_i32(t);
3465 gen_stop_exception(ctx);
3466 #endif /* defined(CONFIG_USER_ONLY) */
3467 }
3468
3469 static void gen_rvwinkle(DisasContext *ctx)
3470 {
3471 #if defined(CONFIG_USER_ONLY)
3472 GEN_PRIV;
3473 #else
3474 TCGv_i32 t;
3475
3476 CHK_HV;
3477 t = tcg_const_i32(PPC_PM_RVWINKLE);
3478 gen_helper_pminsn(cpu_env, t);
3479 tcg_temp_free_i32(t);
3480 gen_stop_exception(ctx);
3481 #endif /* defined(CONFIG_USER_ONLY) */
3482 }
3483 #endif /* #if defined(TARGET_PPC64) */
3484
3485 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3486 {
3487 #if defined(TARGET_PPC64)
3488 if (ctx->has_cfar)
3489 tcg_gen_movi_tl(cpu_cfar, nip);
3490 #endif
3491 }
3492
3493 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3494 {
3495 if (unlikely(ctx->singlestep_enabled)) {
3496 return false;
3497 }
3498
3499 #ifndef CONFIG_USER_ONLY
3500 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3501 #else
3502 return true;
3503 #endif
3504 }
3505
3506 /*** Branch ***/
3507 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3508 {
3509 if (NARROW_MODE(ctx)) {
3510 dest = (uint32_t) dest;
3511 }
3512 if (use_goto_tb(ctx, dest)) {
3513 tcg_gen_goto_tb(n);
3514 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3515 tcg_gen_exit_tb(ctx->base.tb, n);
3516 } else {
3517 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3518 if (unlikely(ctx->singlestep_enabled)) {
3519 if ((ctx->singlestep_enabled &
3520 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3521 (ctx->exception == POWERPC_EXCP_BRANCH ||
3522 ctx->exception == POWERPC_EXCP_TRACE)) {
3523 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3524 }
3525 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3526 gen_debug_exception(ctx);
3527 }
3528 }
3529 tcg_gen_lookup_and_goto_ptr();
3530 }
3531 }
3532
3533 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3534 {
3535 if (NARROW_MODE(ctx)) {
3536 nip = (uint32_t)nip;
3537 }
3538 tcg_gen_movi_tl(cpu_lr, nip);
3539 }
3540
3541 /* b ba bl bla */
3542 static void gen_b(DisasContext *ctx)
3543 {
3544 target_ulong li, target;
3545
3546 ctx->exception = POWERPC_EXCP_BRANCH;
3547 /* sign extend LI */
3548 li = LI(ctx->opcode);
3549 li = (li ^ 0x02000000) - 0x02000000;
3550 if (likely(AA(ctx->opcode) == 0)) {
3551 target = ctx->base.pc_next + li - 4;
3552 } else {
3553 target = li;
3554 }
3555 if (LK(ctx->opcode)) {
3556 gen_setlr(ctx, ctx->base.pc_next);
3557 }
3558 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3559 gen_goto_tb(ctx, 0, target);
3560 }
3561
3562 #define BCOND_IM 0
3563 #define BCOND_LR 1
3564 #define BCOND_CTR 2
3565 #define BCOND_TAR 3
3566
3567 static void gen_bcond(DisasContext *ctx, int type)
3568 {
3569 uint32_t bo = BO(ctx->opcode);
3570 TCGLabel *l1;
3571 TCGv target;
3572
3573 ctx->exception = POWERPC_EXCP_BRANCH;
3574 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3575 target = tcg_temp_local_new();
3576 if (type == BCOND_CTR)
3577 tcg_gen_mov_tl(target, cpu_ctr);
3578 else if (type == BCOND_TAR)
3579 gen_load_spr(target, SPR_TAR);
3580 else
3581 tcg_gen_mov_tl(target, cpu_lr);
3582 } else {
3583 target = NULL;
3584 }
3585 if (LK(ctx->opcode))
3586 gen_setlr(ctx, ctx->base.pc_next);
3587 l1 = gen_new_label();
3588 if ((bo & 0x4) == 0) {
3589 /* Decrement and test CTR */
3590 TCGv temp = tcg_temp_new();
3591 if (unlikely(type == BCOND_CTR)) {
3592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3593 return;
3594 }
3595 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3596 if (NARROW_MODE(ctx)) {
3597 tcg_gen_ext32u_tl(temp, cpu_ctr);
3598 } else {
3599 tcg_gen_mov_tl(temp, cpu_ctr);
3600 }
3601 if (bo & 0x2) {
3602 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3603 } else {
3604 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3605 }
3606 tcg_temp_free(temp);
3607 }
3608 if ((bo & 0x10) == 0) {
3609 /* Test CR */
3610 uint32_t bi = BI(ctx->opcode);
3611 uint32_t mask = 0x08 >> (bi & 0x03);
3612 TCGv_i32 temp = tcg_temp_new_i32();
3613
3614 if (bo & 0x8) {
3615 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3616 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3617 } else {
3618 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3619 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3620 }
3621 tcg_temp_free_i32(temp);
3622 }
3623 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3624 if (type == BCOND_IM) {
3625 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3626 if (likely(AA(ctx->opcode) == 0)) {
3627 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3628 } else {
3629 gen_goto_tb(ctx, 0, li);
3630 }
3631 } else {
3632 if (NARROW_MODE(ctx)) {
3633 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3634 } else {
3635 tcg_gen_andi_tl(cpu_nip, target, ~3);
3636 }
3637 tcg_gen_lookup_and_goto_ptr();
3638 tcg_temp_free(target);
3639 }
3640 if ((bo & 0x14) != 0x14) {
3641 gen_set_label(l1);
3642 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3643 }
3644 }
3645
3646 static void gen_bc(DisasContext *ctx)
3647 {
3648 gen_bcond(ctx, BCOND_IM);
3649 }
3650
3651 static void gen_bcctr(DisasContext *ctx)
3652 {
3653 gen_bcond(ctx, BCOND_CTR);
3654 }
3655
3656 static void gen_bclr(DisasContext *ctx)
3657 {
3658 gen_bcond(ctx, BCOND_LR);
3659 }
3660
3661 static void gen_bctar(DisasContext *ctx)
3662 {
3663 gen_bcond(ctx, BCOND_TAR);
3664 }
3665
3666 /*** Condition register logical ***/
3667 #define GEN_CRLOGIC(name, tcg_op, opc) \
3668 static void glue(gen_, name)(DisasContext *ctx) \
3669 { \
3670 uint8_t bitmask; \
3671 int sh; \
3672 TCGv_i32 t0, t1; \
3673 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3674 t0 = tcg_temp_new_i32(); \
3675 if (sh > 0) \
3676 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3677 else if (sh < 0) \
3678 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3679 else \
3680 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3681 t1 = tcg_temp_new_i32(); \
3682 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3683 if (sh > 0) \
3684 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3685 else if (sh < 0) \
3686 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3687 else \
3688 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3689 tcg_op(t0, t0, t1); \
3690 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3691 tcg_gen_andi_i32(t0, t0, bitmask); \
3692 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3693 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3694 tcg_temp_free_i32(t0); \
3695 tcg_temp_free_i32(t1); \
3696 }
3697
3698 /* crand */
3699 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3700 /* crandc */
3701 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3702 /* creqv */
3703 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3704 /* crnand */
3705 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3706 /* crnor */
3707 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3708 /* cror */
3709 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3710 /* crorc */
3711 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3712 /* crxor */
3713 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3714
3715 /* mcrf */
3716 static void gen_mcrf(DisasContext *ctx)
3717 {
3718 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3719 }
3720
3721 /*** System linkage ***/
3722
3723 /* rfi (supervisor only) */
3724 static void gen_rfi(DisasContext *ctx)
3725 {
3726 #if defined(CONFIG_USER_ONLY)
3727 GEN_PRIV;
3728 #else
3729 /* This instruction doesn't exist anymore on 64-bit server
3730 * processors compliant with arch 2.x
3731 */
3732 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3734 return;
3735 }
3736 /* Restore CPU state */
3737 CHK_SV;
3738 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3739 gen_helper_rfi(cpu_env);
3740 gen_sync_exception(ctx);
3741 #endif
3742 }
3743
3744 #if defined(TARGET_PPC64)
3745 static void gen_rfid(DisasContext *ctx)
3746 {
3747 #if defined(CONFIG_USER_ONLY)
3748 GEN_PRIV;
3749 #else
3750 /* Restore CPU state */
3751 CHK_SV;
3752 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3753 gen_helper_rfid(cpu_env);
3754 gen_sync_exception(ctx);
3755 #endif
3756 }
3757
3758 static void gen_hrfid(DisasContext *ctx)
3759 {
3760 #if defined(CONFIG_USER_ONLY)
3761 GEN_PRIV;
3762 #else
3763 /* Restore CPU state */
3764 CHK_HV;
3765 gen_helper_hrfid(cpu_env);
3766 gen_sync_exception(ctx);
3767 #endif
3768 }
3769 #endif
3770
3771 /* sc */
3772 #if defined(CONFIG_USER_ONLY)
3773 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3774 #else
3775 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3776 #endif
3777 static void gen_sc(DisasContext *ctx)
3778 {
3779 uint32_t lev;
3780
3781 lev = (ctx->opcode >> 5) & 0x7F;
3782 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3783 }
3784
3785 /*** Trap ***/
3786
3787 /* Check for unconditional traps (always or never) */
3788 static bool check_unconditional_trap(DisasContext *ctx)
3789 {
3790 /* Trap never */
3791 if (TO(ctx->opcode) == 0) {
3792 return true;
3793 }
3794 /* Trap always */
3795 if (TO(ctx->opcode) == 31) {
3796 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3797 return true;
3798 }
3799 return false;
3800 }
3801
3802 /* tw */
3803 static void gen_tw(DisasContext *ctx)
3804 {
3805 TCGv_i32 t0;
3806
3807 if (check_unconditional_trap(ctx)) {
3808 return;
3809 }
3810 t0 = tcg_const_i32(TO(ctx->opcode));
3811 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3812 t0);
3813 tcg_temp_free_i32(t0);
3814 }
3815
3816 /* twi */
3817 static void gen_twi(DisasContext *ctx)
3818 {
3819 TCGv t0;
3820 TCGv_i32 t1;
3821
3822 if (check_unconditional_trap(ctx)) {
3823 return;
3824 }
3825 t0 = tcg_const_tl(SIMM(ctx->opcode));
3826 t1 = tcg_const_i32(TO(ctx->opcode));
3827 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3828 tcg_temp_free(t0);
3829 tcg_temp_free_i32(t1);
3830 }
3831
3832 #if defined(TARGET_PPC64)
3833 /* td */
3834 static void gen_td(DisasContext *ctx)
3835 {
3836 TCGv_i32 t0;
3837
3838 if (check_unconditional_trap(ctx)) {
3839 return;
3840 }
3841 t0 = tcg_const_i32(TO(ctx->opcode));
3842 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3843 t0);
3844 tcg_temp_free_i32(t0);
3845 }
3846
3847 /* tdi */
3848 static void gen_tdi(DisasContext *ctx)
3849 {
3850 TCGv t0;
3851 TCGv_i32 t1;
3852
3853 if (check_unconditional_trap(ctx)) {
3854 return;
3855 }
3856 t0 = tcg_const_tl(SIMM(ctx->opcode));
3857 t1 = tcg_const_i32(TO(ctx->opcode));
3858 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3859 tcg_temp_free(t0);
3860 tcg_temp_free_i32(t1);
3861 }
3862 #endif
3863
3864 /*** Processor control ***/
3865
3866 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3867 {
3868 TCGv t0 = tcg_temp_new();
3869 TCGv t1 = tcg_temp_new();
3870 TCGv t2 = tcg_temp_new();
3871 tcg_gen_mov_tl(dst, cpu_xer);
3872 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3873 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3874 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3875 tcg_gen_or_tl(t0, t0, t1);
3876 tcg_gen_or_tl(dst, dst, t2);
3877 tcg_gen_or_tl(dst, dst, t0);
3878 if (is_isa300(ctx)) {
3879 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3880 tcg_gen_or_tl(dst, dst, t0);
3881 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3882 tcg_gen_or_tl(dst, dst, t0);
3883 }
3884 tcg_temp_free(t0);
3885 tcg_temp_free(t1);
3886 tcg_temp_free(t2);
3887 }
3888
3889 static void gen_write_xer(TCGv src)
3890 {
3891 /* Write all flags, while reading back check for isa300 */
3892 tcg_gen_andi_tl(cpu_xer, src,
3893 ~((1u << XER_SO) |
3894 (1u << XER_OV) | (1u << XER_OV32) |
3895 (1u << XER_CA) | (1u << XER_CA32)));
3896 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3897 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3898 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3899 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3900 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3901 }
3902
3903 /* mcrxr */
3904 static void gen_mcrxr(DisasContext *ctx)
3905 {
3906 TCGv_i32 t0 = tcg_temp_new_i32();
3907 TCGv_i32 t1 = tcg_temp_new_i32();
3908 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3909
3910 tcg_gen_trunc_tl_i32(t0, cpu_so);
3911 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3912 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3913 tcg_gen_shli_i32(t0, t0, 3);
3914 tcg_gen_shli_i32(t1, t1, 2);
3915 tcg_gen_shli_i32(dst, dst, 1);
3916 tcg_gen_or_i32(dst, dst, t0);
3917 tcg_gen_or_i32(dst, dst, t1);
3918 tcg_temp_free_i32(t0);
3919 tcg_temp_free_i32(t1);
3920
3921 tcg_gen_movi_tl(cpu_so, 0);
3922 tcg_gen_movi_tl(cpu_ov, 0);
3923 tcg_gen_movi_tl(cpu_ca, 0);
3924 }
3925
3926 #ifdef TARGET_PPC64
3927 /* mcrxrx */
3928 static void gen_mcrxrx(DisasContext *ctx)
3929 {
3930 TCGv t0 = tcg_temp_new();
3931 TCGv t1 = tcg_temp_new();
3932 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3933
3934 /* copy OV and OV32 */
3935 tcg_gen_shli_tl(t0, cpu_ov, 1);
3936 tcg_gen_or_tl(t0, t0, cpu_ov32);
3937 tcg_gen_shli_tl(t0, t0, 2);
3938 /* copy CA and CA32 */
3939 tcg_gen_shli_tl(t1, cpu_ca, 1);
3940 tcg_gen_or_tl(t1, t1, cpu_ca32);
3941 tcg_gen_or_tl(t0, t0, t1);
3942 tcg_gen_trunc_tl_i32(dst, t0);
3943 tcg_temp_free(t0);
3944 tcg_temp_free(t1);
3945 }
3946 #endif
3947
3948 /* mfcr mfocrf */
3949 static void gen_mfcr(DisasContext *ctx)
3950 {
3951 uint32_t crm, crn;
3952
3953 if (likely(ctx->opcode & 0x00100000)) {
3954 crm = CRM(ctx->opcode);
3955 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3956 crn = ctz32 (crm);
3957 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3958 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3959 cpu_gpr[rD(ctx->opcode)], crn * 4);
3960 }
3961 } else {
3962 TCGv_i32 t0 = tcg_temp_new_i32();
3963 tcg_gen_mov_i32(t0, cpu_crf[0]);
3964 tcg_gen_shli_i32(t0, t0, 4);
3965 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3966 tcg_gen_shli_i32(t0, t0, 4);
3967 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3968 tcg_gen_shli_i32(t0, t0, 4);
3969 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3970 tcg_gen_shli_i32(t0, t0, 4);
3971 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3972 tcg_gen_shli_i32(t0, t0, 4);
3973 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3974 tcg_gen_shli_i32(t0, t0, 4);
3975 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3976 tcg_gen_shli_i32(t0, t0, 4);
3977 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3978 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3979 tcg_temp_free_i32(t0);
3980 }
3981 }
3982
3983 /* mfmsr */
3984 static void gen_mfmsr(DisasContext *ctx)
3985 {
3986 CHK_SV;
3987 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3988 }
3989
3990 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3991 {
3992 #if 0
3993 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3994 printf("ERROR: try to access SPR %d !\n", sprn);
3995 #endif
3996 }
3997 #define SPR_NOACCESS (&spr_noaccess)
3998
3999 /* mfspr */
4000 static inline void gen_op_mfspr(DisasContext *ctx)
4001 {
4002 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4003 uint32_t sprn = SPR(ctx->opcode);
4004
4005 #if defined(CONFIG_USER_ONLY)
4006 read_cb = ctx->spr_cb[sprn].uea_read;
4007 #else
4008 if (ctx->pr) {
4009 read_cb = ctx->spr_cb[sprn].uea_read;
4010 } else if (ctx->hv) {
4011 read_cb = ctx->spr_cb[sprn].hea_read;
4012 } else {
4013 read_cb = ctx->spr_cb[sprn].oea_read;
4014 }
4015 #endif
4016 if (likely(read_cb != NULL)) {
4017 if (likely(read_cb != SPR_NOACCESS)) {
4018 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4019 } else {
4020 /* Privilege exception */
4021 /* This is a hack to avoid warnings when running Linux:
4022 * this OS breaks the PowerPC virtualisation model,
4023 * allowing userland application to read the PVR
4024 */
4025 if (sprn != SPR_PVR) {
4026 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4027 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4028 ctx->base.pc_next - 4);
4029 }
4030 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4031 }
4032 } else {
4033 /* ISA 2.07 defines these as no-ops */
4034 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4035 (sprn >= 808 && sprn <= 811)) {
4036 /* This is a nop */
4037 return;
4038 }
4039 /* Not defined */
4040 qemu_log_mask(LOG_GUEST_ERROR,
4041 "Trying to read invalid spr %d (0x%03x) at "
4042 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4043
4044 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4045 * it can generate a priv, a hv emu or a no-op
4046 */
4047 if (sprn & 0x10) {
4048 if (ctx->pr) {
4049 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4050 }
4051 } else {
4052 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4053 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4054 }
4055 }
4056 }
4057 }
4058
4059 static void gen_mfspr(DisasContext *ctx)
4060 {
4061 gen_op_mfspr(ctx);
4062 }
4063
4064 /* mftb */
4065 static void gen_mftb(DisasContext *ctx)
4066 {
4067 gen_op_mfspr(ctx);
4068 }
4069
4070 /* mtcrf mtocrf*/
4071 static void gen_mtcrf(DisasContext *ctx)
4072 {
4073 uint32_t crm, crn;
4074
4075 crm = CRM(ctx->opcode);
4076 if (likely((ctx->opcode & 0x00100000))) {
4077 if (crm && ((crm & (crm - 1)) == 0)) {
4078 TCGv_i32 temp = tcg_temp_new_i32();
4079 crn = ctz32 (crm);
4080 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4081 tcg_gen_shri_i32(temp, temp, crn * 4);
4082 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4083 tcg_temp_free_i32(temp);
4084 }
4085 } else {
4086 TCGv_i32 temp = tcg_temp_new_i32();
4087 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4088 for (crn = 0 ; crn < 8 ; crn++) {
4089 if (crm & (1 << crn)) {
4090 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4091 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4092 }
4093 }
4094 tcg_temp_free_i32(temp);
4095 }
4096 }
4097
4098 /* mtmsr */
4099 #if defined(TARGET_PPC64)
4100 static void gen_mtmsrd(DisasContext *ctx)
4101 {
4102 CHK_SV;
4103
4104 #if !defined(CONFIG_USER_ONLY)
4105 if (ctx->opcode & 0x00010000) {
4106 /* Special form that does not need any synchronisation */
4107 TCGv t0 = tcg_temp_new();
4108 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4109 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4110 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4111 tcg_temp_free(t0);
4112 } else {
4113 /* XXX: we need to update nip before the store
4114 * if we enter power saving mode, we will exit the loop
4115 * directly from ppc_store_msr
4116 */
4117 gen_update_nip(ctx, ctx->base.pc_next);
4118 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4119 /* Must stop the translation as machine state (may have) changed */
4120 /* Note that mtmsr is not always defined as context-synchronizing */
4121 gen_stop_exception(ctx);
4122 }
4123 #endif /* !defined(CONFIG_USER_ONLY) */
4124 }
4125 #endif /* defined(TARGET_PPC64) */
4126
4127 static void gen_mtmsr(DisasContext *ctx)
4128 {
4129 CHK_SV;
4130
4131 #if !defined(CONFIG_USER_ONLY)
4132 if (ctx->opcode & 0x00010000) {
4133 /* Special form that does not need any synchronisation */
4134 TCGv t0 = tcg_temp_new();
4135 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4136 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4137 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4138 tcg_temp_free(t0);
4139 } else {
4140 TCGv msr = tcg_temp_new();
4141
4142 /* XXX: we need to update nip before the store
4143 * if we enter power saving mode, we will exit the loop
4144 * directly from ppc_store_msr
4145 */
4146 gen_update_nip(ctx, ctx->base.pc_next);
4147 #if defined(TARGET_PPC64)
4148 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4149 #else
4150 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4151 #endif
4152 gen_helper_store_msr(cpu_env, msr);
4153 tcg_temp_free(msr);
4154 /* Must stop the translation as machine state (may have) changed */
4155 /* Note that mtmsr is not always defined as context-synchronizing */
4156 gen_stop_exception(ctx);
4157 }
4158 #endif
4159 }
4160
4161 /* mtspr */
4162 static void gen_mtspr(DisasContext *ctx)
4163 {
4164 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4165 uint32_t sprn = SPR(ctx->opcode);
4166
4167 #if defined(CONFIG_USER_ONLY)
4168 write_cb = ctx->spr_cb[sprn].uea_write;
4169 #else
4170 if (ctx->pr) {
4171 write_cb = ctx->spr_cb[sprn].uea_write;
4172 } else if (ctx->hv) {
4173 write_cb = ctx->spr_cb[sprn].hea_write;
4174 } else {
4175 write_cb = ctx->spr_cb[sprn].oea_write;
4176 }
4177 #endif
4178 if (likely(write_cb != NULL)) {
4179 if (likely(write_cb != SPR_NOACCESS)) {
4180 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4181 } else {
4182 /* Privilege exception */
4183 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4184 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4185 ctx->base.pc_next - 4);
4186 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4187 }
4188 } else {
4189 /* ISA 2.07 defines these as no-ops */
4190 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4191 (sprn >= 808 && sprn <= 811)) {
4192 /* This is a nop */
4193 return;
4194 }
4195
4196 /* Not defined */
4197 qemu_log_mask(LOG_GUEST_ERROR,
4198 "Trying to write invalid spr %d (0x%03x) at "
4199 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4200
4201
4202 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4203 * it can generate a priv, a hv emu or a no-op
4204 */
4205 if (sprn & 0x10) {
4206 if (ctx->pr) {
4207 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4208 }
4209 } else {
4210 if (ctx->pr || sprn == 0) {
4211 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4212 }
4213 }
4214 }
4215 }
4216
4217 #if defined(TARGET_PPC64)
4218 /* setb */
4219 static void gen_setb(DisasContext *ctx)
4220 {
4221 TCGv_i32 t0 = tcg_temp_new_i32();
4222 TCGv_i32 t8 = tcg_temp_new_i32();
4223 TCGv_i32 tm1 = tcg_temp_new_i32();
4224 int crf = crfS(ctx->opcode);
4225
4226 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4227 tcg_gen_movi_i32(t8, 8);
4228 tcg_gen_movi_i32(tm1, -1);
4229 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4230 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4231
4232 tcg_temp_free_i32(t0);
4233 tcg_temp_free_i32(t8);
4234 tcg_temp_free_i32(tm1);
4235 }
4236 #endif
4237
4238 /*** Cache management ***/
4239
4240 /* dcbf */
4241 static void gen_dcbf(DisasContext *ctx)
4242 {
4243 /* XXX: specification says this is treated as a load by the MMU */
4244 TCGv t0;
4245 gen_set_access_type(ctx, ACCESS_CACHE);
4246 t0 = tcg_temp_new();
4247 gen_addr_reg_index(ctx, t0);
4248 gen_qemu_ld8u(ctx, t0, t0);
4249 tcg_temp_free(t0);
4250 }
4251
4252 /* dcbi (Supervisor only) */
4253 static void gen_dcbi(DisasContext *ctx)
4254 {
4255 #if defined(CONFIG_USER_ONLY)
4256 GEN_PRIV;
4257 #else
4258 TCGv EA, val;
4259
4260 CHK_SV;
4261 EA = tcg_temp_new();
4262 gen_set_access_type(ctx, ACCESS_CACHE);
4263 gen_addr_reg_index(ctx, EA);
4264 val = tcg_temp_new();
4265 /* XXX: specification says this should be treated as a store by the MMU */
4266 gen_qemu_ld8u(ctx, val, EA);
4267 gen_qemu_st8(ctx, val, EA);
4268 tcg_temp_free(val);
4269 tcg_temp_free(EA);
4270 #endif /* defined(CONFIG_USER_ONLY) */
4271 }
4272
4273 /* dcdst */
4274 static void gen_dcbst(DisasContext *ctx)
4275 {
4276 /* XXX: specification say this is treated as a load by the MMU */
4277 TCGv t0;
4278 gen_set_access_type(ctx, ACCESS_CACHE);
4279 t0 = tcg_temp_new();
4280 gen_addr_reg_index(ctx, t0);
4281 gen_qemu_ld8u(ctx, t0, t0);
4282 tcg_temp_free(t0);
4283 }
4284
4285 /* dcbt */
4286 static void gen_dcbt(DisasContext *ctx)
4287 {
4288 /* interpreted as no-op */
4289 /* XXX: specification say this is treated as a load by the MMU
4290 * but does not generate any exception
4291 */
4292 }
4293
4294 /* dcbtst */
4295 static void gen_dcbtst(DisasContext *ctx)
4296 {
4297 /* interpreted as no-op */
4298 /* XXX: specification say this is treated as a load by the MMU
4299 * but does not generate any exception
4300 */
4301 }
4302
4303 /* dcbtls */
4304 static void gen_dcbtls(DisasContext *ctx)
4305 {
4306 /* Always fails locking the cache */
4307 TCGv t0 = tcg_temp_new();
4308 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4309 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4310 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4311 tcg_temp_free(t0);
4312 }
4313
4314 /* dcbz */
4315 static void gen_dcbz(DisasContext *ctx)
4316 {
4317 TCGv tcgv_addr;
4318 TCGv_i32 tcgv_op;
4319
4320 gen_set_access_type(ctx, ACCESS_CACHE);
4321 tcgv_addr = tcg_temp_new();
4322 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4323 gen_addr_reg_index(ctx, tcgv_addr);
4324 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4325 tcg_temp_free(tcgv_addr);
4326 tcg_temp_free_i32(tcgv_op);
4327 }
4328
4329 /* dst / dstt */
4330 static void gen_dst(DisasContext *ctx)
4331 {
4332 if (rA(ctx->opcode) == 0) {
4333 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4334 } else {
4335 /* interpreted as no-op */
4336 }
4337 }
4338
4339 /* dstst /dststt */
4340 static void gen_dstst(DisasContext *ctx)
4341 {
4342 if (rA(ctx->opcode) == 0) {
4343 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4344 } else {
4345 /* interpreted as no-op */
4346 }
4347
4348 }
4349
4350 /* dss / dssall */
4351 static void gen_dss(DisasContext *ctx)
4352 {
4353 /* interpreted as no-op */
4354 }
4355
4356 /* icbi */
4357 static void gen_icbi(DisasContext *ctx)
4358 {
4359 TCGv t0;
4360 gen_set_access_type(ctx, ACCESS_CACHE);
4361 t0 = tcg_temp_new();
4362 gen_addr_reg_index(ctx, t0);
4363 gen_helper_icbi(cpu_env, t0);
4364 tcg_temp_free(t0);
4365 }
4366
4367 /* Optional: */
4368 /* dcba */
4369 static void gen_dcba(DisasContext *ctx)
4370 {
4371 /* interpreted as no-op */
4372 /* XXX: specification say this is treated as a store by the MMU
4373 * but does not generate any exception
4374 */
4375 }
4376
4377 /*** Segment register manipulation ***/
4378 /* Supervisor only: */
4379
4380 /* mfsr */
4381 static void gen_mfsr(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_PRIV;
4385 #else
4386 TCGv t0;
4387
4388 CHK_SV;
4389 t0 = tcg_const_tl(SR(ctx->opcode));
4390 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4391 tcg_temp_free(t0);
4392 #endif /* defined(CONFIG_USER_ONLY) */
4393 }
4394
4395 /* mfsrin */
4396 static void gen_mfsrin(DisasContext *ctx)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 GEN_PRIV;
4400 #else
4401 TCGv t0;
4402
4403 CHK_SV;
4404 t0 = tcg_temp_new();
4405 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4406 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4407 tcg_temp_free(t0);
4408 #endif /* defined(CONFIG_USER_ONLY) */
4409 }
4410
4411 /* mtsr */
4412 static void gen_mtsr(DisasContext *ctx)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 GEN_PRIV;
4416 #else
4417 TCGv t0;
4418
4419 CHK_SV;
4420 t0 = tcg_const_tl(SR(ctx->opcode));
4421 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4422 tcg_temp_free(t0);
4423 #endif /* defined(CONFIG_USER_ONLY) */
4424 }
4425
4426 /* mtsrin */
4427 static void gen_mtsrin(DisasContext *ctx)
4428 {
4429 #if defined(CONFIG_USER_ONLY)
4430 GEN_PRIV;
4431 #else
4432 TCGv t0;
4433 CHK_SV;
4434
4435 t0 = tcg_temp_new();
4436 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4437 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4438 tcg_temp_free(t0);
4439 #endif /* defined(CONFIG_USER_ONLY) */
4440 }
4441
4442 #if defined(TARGET_PPC64)
4443 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4444
4445 /* mfsr */
4446 static void gen_mfsr_64b(DisasContext *ctx)
4447 {
4448 #if defined(CONFIG_USER_ONLY)
4449 GEN_PRIV;
4450 #else
4451 TCGv t0;
4452
4453 CHK_SV;
4454 t0 = tcg_const_tl(SR(ctx->opcode));
4455 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4456 tcg_temp_free(t0);
4457 #endif /* defined(CONFIG_USER_ONLY) */
4458 }
4459
4460 /* mfsrin */
4461 static void gen_mfsrin_64b(DisasContext *ctx)
4462 {
4463 #if defined(CONFIG_USER_ONLY)
4464 GEN_PRIV;
4465 #else
4466 TCGv t0;
4467
4468 CHK_SV;
4469 t0 = tcg_temp_new();
4470 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4471 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4472 tcg_temp_free(t0);
4473 #endif /* defined(CONFIG_USER_ONLY) */
4474 }
4475
4476 /* mtsr */
4477 static void gen_mtsr_64b(DisasContext *ctx)
4478 {
4479 #if defined(CONFIG_USER_ONLY)
4480 GEN_PRIV;
4481 #else
4482 TCGv t0;
4483
4484 CHK_SV;
4485 t0 = tcg_const_tl(SR(ctx->opcode));
4486 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4487 tcg_temp_free(t0);
4488 #endif /* defined(CONFIG_USER_ONLY) */
4489 }
4490
4491 /* mtsrin */
4492 static void gen_mtsrin_64b(DisasContext *ctx)
4493 {
4494 #if defined(CONFIG_USER_ONLY)
4495 GEN_PRIV;
4496 #else
4497 TCGv t0;
4498
4499 CHK_SV;
4500 t0 = tcg_temp_new();
4501 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4502 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4503 tcg_temp_free(t0);
4504 #endif /* defined(CONFIG_USER_ONLY) */
4505 }
4506
4507 /* slbmte */
4508 static void gen_slbmte(DisasContext *ctx)
4509 {
4510 #if defined(CONFIG_USER_ONLY)
4511 GEN_PRIV;
4512 #else
4513 CHK_SV;
4514
4515 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4516 cpu_gpr[rS(ctx->opcode)]);
4517 #endif /* defined(CONFIG_USER_ONLY) */
4518 }
4519
4520 static void gen_slbmfee(DisasContext *ctx)
4521 {
4522 #if defined(CONFIG_USER_ONLY)
4523 GEN_PRIV;
4524 #else
4525 CHK_SV;
4526
4527 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4528 cpu_gpr[rB(ctx->opcode)]);
4529 #endif /* defined(CONFIG_USER_ONLY) */
4530 }
4531
4532 static void gen_slbmfev(DisasContext *ctx)
4533 {
4534 #if defined(CONFIG_USER_ONLY)
4535 GEN_PRIV;
4536 #else
4537 CHK_SV;
4538
4539 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4540 cpu_gpr[rB(ctx->opcode)]);
4541 #endif /* defined(CONFIG_USER_ONLY) */
4542 }
4543
4544 static void gen_slbfee_(DisasContext *ctx)
4545 {
4546 #if defined(CONFIG_USER_ONLY)
4547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4548 #else
4549 TCGLabel *l1, *l2;
4550
4551 if (unlikely(ctx->pr)) {
4552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4553 return;
4554 }
4555 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4556 cpu_gpr[rB(ctx->opcode)]);
4557 l1 = gen_new_label();
4558 l2 = gen_new_label();
4559 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4560 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4561 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4562 tcg_gen_br(l2);
4563 gen_set_label(l1);
4564 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4565 gen_set_label(l2);
4566 #endif
4567 }
4568 #endif /* defined(TARGET_PPC64) */
4569
4570 /*** Lookaside buffer management ***/
4571 /* Optional & supervisor only: */
4572
4573 /* tlbia */
4574 static void gen_tlbia(DisasContext *ctx)
4575 {
4576 #if defined(CONFIG_USER_ONLY)
4577 GEN_PRIV;
4578 #else
4579 CHK_HV;
4580
4581 gen_helper_tlbia(cpu_env);
4582 #endif /* defined(CONFIG_USER_ONLY) */
4583 }
4584
4585 /* tlbiel */
4586 static void gen_tlbiel(DisasContext *ctx)
4587 {
4588 #if defined(CONFIG_USER_ONLY)
4589 GEN_PRIV;
4590 #else
4591 CHK_SV;
4592
4593 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4594 #endif /* defined(CONFIG_USER_ONLY) */
4595 }
4596
4597 /* tlbie */
4598 static void gen_tlbie(DisasContext *ctx)
4599 {
4600 #if defined(CONFIG_USER_ONLY)
4601 GEN_PRIV;
4602 #else
4603 TCGv_i32 t1;
4604
4605 if (ctx->gtse) {
4606 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4607 } else {
4608 CHK_HV; /* Else hypervisor privileged */
4609 }
4610
4611 if (NARROW_MODE(ctx)) {
4612 TCGv t0 = tcg_temp_new();
4613 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4614 gen_helper_tlbie(cpu_env, t0);
4615 tcg_temp_free(t0);
4616 } else {
4617 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4618 }
4619 t1 = tcg_temp_new_i32();
4620 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4621 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4622 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4623 tcg_temp_free_i32(t1);
4624 #endif /* defined(CONFIG_USER_ONLY) */
4625 }
4626
4627 /* tlbsync */
4628 static void gen_tlbsync(DisasContext *ctx)
4629 {
4630 #if defined(CONFIG_USER_ONLY)
4631 GEN_PRIV;
4632 #else
4633
4634 if (ctx->gtse) {
4635 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4636 } else {
4637 CHK_HV; /* Else hypervisor privileged */
4638 }
4639
4640 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4641 if (ctx->insns_flags & PPC_BOOKE) {
4642 gen_check_tlb_flush(ctx, true);
4643 }
4644 #endif /* defined(CONFIG_USER_ONLY) */
4645 }
4646
4647 #if defined(TARGET_PPC64)
4648 /* slbia */
4649 static void gen_slbia(DisasContext *ctx)
4650 {
4651 #if defined(CONFIG_USER_ONLY)
4652 GEN_PRIV;
4653 #else
4654 CHK_SV;
4655
4656 gen_helper_slbia(cpu_env);
4657 #endif /* defined(CONFIG_USER_ONLY) */
4658 }
4659
4660 /* slbie */
4661 static void gen_slbie(DisasContext *ctx)
4662 {
4663 #if defined(CONFIG_USER_ONLY)
4664 GEN_PRIV;
4665 #else
4666 CHK_SV;
4667
4668 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4669 #endif /* defined(CONFIG_USER_ONLY) */
4670 }
4671
4672 /* slbieg */
4673 static void gen_slbieg(DisasContext *ctx)
4674 {
4675 #if defined(CONFIG_USER_ONLY)
4676 GEN_PRIV;
4677 #else
4678 CHK_SV;
4679
4680 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4681 #endif /* defined(CONFIG_USER_ONLY) */
4682 }
4683
4684 /* slbsync */
4685 static void gen_slbsync(DisasContext *ctx)
4686 {
4687 #if defined(CONFIG_USER_ONLY)
4688 GEN_PRIV;
4689 #else
4690 CHK_SV;
4691 gen_check_tlb_flush(ctx, true);
4692 #endif /* defined(CONFIG_USER_ONLY) */
4693 }
4694
4695 #endif /* defined(TARGET_PPC64) */
4696
4697 /*** External control ***/
4698 /* Optional: */
4699
4700 /* eciwx */
4701 static void gen_eciwx(DisasContext *ctx)
4702 {
4703 TCGv t0;
4704 /* Should check EAR[E] ! */
4705 gen_set_access_type(ctx, ACCESS_EXT);
4706 t0 = tcg_temp_new();
4707 gen_addr_reg_index(ctx, t0);
4708 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4709 DEF_MEMOP(MO_UL | MO_ALIGN));
4710 tcg_temp_free(t0);
4711 }
4712
4713 /* ecowx */
4714 static void gen_ecowx(DisasContext *ctx)
4715 {
4716 TCGv t0;
4717 /* Should check EAR[E] ! */
4718 gen_set_access_type(ctx, ACCESS_EXT);
4719 t0 = tcg_temp_new();
4720 gen_addr_reg_index(ctx, t0);
4721 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4722 DEF_MEMOP(MO_UL | MO_ALIGN));
4723 tcg_temp_free(t0);
4724 }
4725
4726 /* PowerPC 601 specific instructions */
4727
4728 /* abs - abs. */
4729 static void gen_abs(DisasContext *ctx)
4730 {
4731 TCGLabel *l1 = gen_new_label();
4732 TCGLabel *l2 = gen_new_label();
4733 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4734 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4735 tcg_gen_br(l2);
4736 gen_set_label(l1);
4737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4738 gen_set_label(l2);
4739 if (unlikely(Rc(ctx->opcode) != 0))
4740 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4741 }
4742
4743 /* abso - abso. */
4744 static void gen_abso(DisasContext *ctx)
4745 {
4746 TCGLabel *l1 = gen_new_label();
4747 TCGLabel *l2 = gen_new_label();
4748 TCGLabel *l3 = gen_new_label();
4749 /* Start with XER OV disabled, the most likely case */
4750 tcg_gen_movi_tl(cpu_ov, 0);
4751 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4752 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4753 tcg_gen_movi_tl(cpu_ov, 1);
4754 tcg_gen_movi_tl(cpu_so, 1);
4755 tcg_gen_br(l2);
4756 gen_set_label(l1);
4757 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4758 tcg_gen_br(l3);
4759 gen_set_label(l2);
4760 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4761 gen_set_label(l3);
4762 if (unlikely(Rc(ctx->opcode) != 0))
4763 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4764 }
4765
4766 /* clcs */
4767 static void gen_clcs(DisasContext *ctx)
4768 {
4769 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4770 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4771 tcg_temp_free_i32(t0);
4772 /* Rc=1 sets CR0 to an undefined state */
4773 }
4774
4775 /* div - div. */
4776 static void gen_div(DisasContext *ctx)
4777 {
4778 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4779 cpu_gpr[rB(ctx->opcode)]);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4782 }
4783
4784 /* divo - divo. */
4785 static void gen_divo(DisasContext *ctx)
4786 {
4787 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4788 cpu_gpr[rB(ctx->opcode)]);
4789 if (unlikely(Rc(ctx->opcode) != 0))
4790 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4791 }
4792
4793 /* divs - divs. */
4794 static void gen_divs(DisasContext *ctx)
4795 {
4796 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4797 cpu_gpr[rB(ctx->opcode)]);
4798 if (unlikely(Rc(ctx->opcode) != 0))
4799 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4800 }
4801
4802 /* divso - divso. */
4803 static void gen_divso(DisasContext *ctx)
4804 {
4805 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4806 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4807 if (unlikely(Rc(ctx->opcode) != 0))
4808 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4809 }
4810
4811 /* doz - doz. */
4812 static void gen_doz(DisasContext *ctx)
4813 {
4814 TCGLabel *l1 = gen_new_label();
4815 TCGLabel *l2 = gen_new_label();
4816 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4817 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4818 tcg_gen_br(l2);
4819 gen_set_label(l1);
4820 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4821 gen_set_label(l2);
4822 if (unlikely(Rc(ctx->opcode) != 0))
4823 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4824 }
4825
4826 /* dozo - dozo. */
4827 static void gen_dozo(DisasContext *ctx)
4828 {
4829 TCGLabel *l1 = gen_new_label();
4830 TCGLabel *l2 = gen_new_label();
4831 TCGv t0 = tcg_temp_new();
4832 TCGv t1 = tcg_temp_new();
4833 TCGv t2 = tcg_temp_new();
4834 /* Start with XER OV disabled, the most likely case */
4835 tcg_gen_movi_tl(cpu_ov, 0);
4836 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4837 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4838 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4839 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4840 tcg_gen_andc_tl(t1, t1, t2);
4841 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4842 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4843 tcg_gen_movi_tl(cpu_ov, 1);
4844 tcg_gen_movi_tl(cpu_so, 1);
4845 tcg_gen_br(l2);
4846 gen_set_label(l1);
4847 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4848 gen_set_label(l2);
4849 tcg_temp_free(t0);
4850 tcg_temp_free(t1);
4851 tcg_temp_free(t2);
4852 if (unlikely(Rc(ctx->opcode) != 0))
4853 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4854 }
4855
4856 /* dozi */
4857 static void gen_dozi(DisasContext *ctx)
4858 {
4859 target_long simm = SIMM(ctx->opcode);
4860 TCGLabel *l1 = gen_new_label();
4861 TCGLabel *l2 = gen_new_label();
4862 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4863 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4864 tcg_gen_br(l2);
4865 gen_set_label(l1);
4866 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4867 gen_set_label(l2);
4868 if (unlikely(Rc(ctx->opcode) != 0))
4869 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4870 }
4871
4872 /* lscbx - lscbx. */
4873 static void gen_lscbx(DisasContext *ctx)
4874 {
4875 TCGv t0 = tcg_temp_new();
4876 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4877 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4878 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4879
4880 gen_addr_reg_index(ctx, t0);
4881 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4882 tcg_temp_free_i32(t1);
4883 tcg_temp_free_i32(t2);
4884 tcg_temp_free_i32(t3);
4885 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4886 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4887 if (unlikely(Rc(ctx->opcode) != 0))
4888 gen_set_Rc0(ctx, t0);
4889 tcg_temp_free(t0);
4890 }
4891
4892 /* maskg - maskg. */
4893 static void gen_maskg(DisasContext *ctx)
4894 {
4895 TCGLabel *l1 = gen_new_label();
4896 TCGv t0 = tcg_temp_new();
4897 TCGv t1 = tcg_temp_new();
4898 TCGv t2 = tcg_temp_new();
4899 TCGv t3 = tcg_temp_new();
4900 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4901 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4902 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4903 tcg_gen_addi_tl(t2, t0, 1);
4904 tcg_gen_shr_tl(t2, t3, t2);
4905 tcg_gen_shr_tl(t3, t3, t1);
4906 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4907 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4908 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4909 gen_set_label(l1);
4910 tcg_temp_free(t0);
4911 tcg_temp_free(t1);
4912 tcg_temp_free(t2);
4913 tcg_temp_free(t3);
4914 if (unlikely(Rc(ctx->opcode) != 0))
4915 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4916 }
4917
4918 /* maskir - maskir. */
4919 static void gen_maskir(DisasContext *ctx)
4920 {
4921 TCGv t0 = tcg_temp_new();
4922 TCGv t1 = tcg_temp_new();
4923 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4924 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4925 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4926 tcg_temp_free(t0);
4927 tcg_temp_free(t1);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4930 }
4931
4932 /* mul - mul. */
4933 static void gen_mul(DisasContext *ctx)
4934 {
4935 TCGv_i64 t0 = tcg_temp_new_i64();
4936 TCGv_i64 t1 = tcg_temp_new_i64();
4937 TCGv t2 = tcg_temp_new();
4938 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4939 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4940 tcg_gen_mul_i64(t0, t0, t1);
4941 tcg_gen_trunc_i64_tl(t2, t0);
4942 gen_store_spr(SPR_MQ, t2);
4943 tcg_gen_shri_i64(t1, t0, 32);
4944 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4945 tcg_temp_free_i64(t0);
4946 tcg_temp_free_i64(t1);
4947 tcg_temp_free(t2);
4948 if (unlikely(Rc(ctx->opcode) != 0))
4949 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4950 }
4951
4952 /* mulo - mulo. */
4953 static void gen_mulo(DisasContext *ctx)
4954 {
4955 TCGLabel *l1 = gen_new_label();
4956 TCGv_i64 t0 = tcg_temp_new_i64();
4957 TCGv_i64 t1 = tcg_temp_new_i64();
4958 TCGv t2 = tcg_temp_new();
4959 /* Start with XER OV disabled, the most likely case */
4960 tcg_gen_movi_tl(cpu_ov, 0);
4961 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4962 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4963 tcg_gen_mul_i64(t0, t0, t1);
4964 tcg_gen_trunc_i64_tl(t2, t0);
4965 gen_store_spr(SPR_MQ, t2);
4966 tcg_gen_shri_i64(t1, t0, 32);
4967 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4968 tcg_gen_ext32s_i64(t1, t0);
4969 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4970 tcg_gen_movi_tl(cpu_ov, 1);
4971 tcg_gen_movi_tl(cpu_so, 1);
4972 gen_set_label(l1);
4973 tcg_temp_free_i64(t0);
4974 tcg_temp_free_i64(t1);
4975 tcg_temp_free(t2);
4976 if (unlikely(Rc(ctx->opcode) != 0))
4977 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4978 }
4979
4980 /* nabs - nabs. */
4981 static void gen_nabs(DisasContext *ctx)
4982 {
4983 TCGLabel *l1 = gen_new_label();
4984 TCGLabel *l2 = gen_new_label();
4985 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4986 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4987 tcg_gen_br(l2);
4988 gen_set_label(l1);
4989 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4990 gen_set_label(l2);
4991 if (unlikely(Rc(ctx->opcode) != 0))
4992 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4993 }
4994
4995 /* nabso - nabso. */
4996 static void gen_nabso(DisasContext *ctx)
4997 {
4998 TCGLabel *l1 = gen_new_label();
4999 TCGLabel *l2 = gen_new_label();
5000 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5001 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5002 tcg_gen_br(l2);
5003 gen_set_label(l1);
5004 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5005 gen_set_label(l2);
5006 /* nabs never overflows */
5007 tcg_gen_movi_tl(cpu_ov, 0);
5008 if (unlikely(Rc(ctx->opcode) != 0))
5009 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5010 }
5011
5012 /* rlmi - rlmi. */
5013 static void gen_rlmi(DisasContext *ctx)
5014 {
5015 uint32_t mb = MB(ctx->opcode);
5016 uint32_t me = ME(ctx->opcode);
5017 TCGv t0 = tcg_temp_new();
5018 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5019 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5020 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5021 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5022 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5023 tcg_temp_free(t0);
5024 if (unlikely(Rc(ctx->opcode) != 0))
5025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5026 }
5027
5028 /* rrib - rrib. */
5029 static void gen_rrib(DisasContext *ctx)
5030 {
5031 TCGv t0 = tcg_temp_new();
5032 TCGv t1 = tcg_temp_new();
5033 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5034 tcg_gen_movi_tl(t1, 0x80000000);
5035 tcg_gen_shr_tl(t1, t1, t0);
5036 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5037 tcg_gen_and_tl(t0, t0, t1);
5038 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5039 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5040 tcg_temp_free(t0);
5041 tcg_temp_free(t1);
5042 if (unlikely(Rc(ctx->opcode) != 0))
5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5044 }
5045
5046 /* sle - sle. */
5047 static void gen_sle(DisasContext *ctx)
5048 {
5049 TCGv t0 = tcg_temp_new();
5050 TCGv t1 = tcg_temp_new();
5051 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5052 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5053 tcg_gen_subfi_tl(t1, 32, t1);
5054 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5055 tcg_gen_or_tl(t1, t0, t1);
5056 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5057 gen_store_spr(SPR_MQ, t1);
5058 tcg_temp_free(t0);
5059 tcg_temp_free(t1);
5060 if (unlikely(Rc(ctx->opcode) != 0))
5061 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5062 }
5063
5064 /* sleq - sleq. */
5065 static void gen_sleq(DisasContext *ctx)
5066 {
5067 TCGv t0 = tcg_temp_new();
5068 TCGv t1 = tcg_temp_new();
5069 TCGv t2 = tcg_temp_new();
5070 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5071 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5072 tcg_gen_shl_tl(t2, t2, t0);
5073 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5074 gen_load_spr(t1, SPR_MQ);
5075 gen_store_spr(SPR_MQ, t0);
5076 tcg_gen_and_tl(t0, t0, t2);
5077 tcg_gen_andc_tl(t1, t1, t2);
5078 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5079 tcg_temp_free(t0);
5080 tcg_temp_free(t1);
5081 tcg_temp_free(t2);
5082 if (unlikely(Rc(ctx->opcode) != 0))
5083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5084 }
5085
5086 /* sliq - sliq. */
5087 static void gen_sliq(DisasContext *ctx)
5088 {
5089 int sh = SH(ctx->opcode);
5090 TCGv t0 = tcg_temp_new();
5091 TCGv t1 = tcg_temp_new();
5092 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5093 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5094 tcg_gen_or_tl(t1, t0, t1);
5095 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5096 gen_store_spr(SPR_MQ, t1);
5097 tcg_temp_free(t0);
5098 tcg_temp_free(t1);
5099 if (unlikely(Rc(ctx->opcode) != 0))
5100 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5101 }
5102
5103 /* slliq - slliq. */
5104 static void gen_slliq(DisasContext *ctx)
5105 {
5106 int sh = SH(ctx->opcode);
5107 TCGv t0 = tcg_temp_new();
5108 TCGv t1 = tcg_temp_new();
5109 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5110 gen_load_spr(t1, SPR_MQ);
5111 gen_store_spr(SPR_MQ, t0);
5112 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5113 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5114 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5115 tcg_temp_free(t0);
5116 tcg_temp_free(t1);
5117 if (unlikely(Rc(ctx->opcode) != 0))
5118 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5119 }
5120
5121 /* sllq - sllq. */
5122 static void gen_sllq(DisasContext *ctx)
5123 {
5124 TCGLabel *l1 = gen_new_label();
5125 TCGLabel *l2 = gen_new_label();
5126 TCGv t0 = tcg_temp_local_new();
5127 TCGv t1 = tcg_temp_local_new();
5128 TCGv t2 = tcg_temp_local_new();
5129 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5130 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5131 tcg_gen_shl_tl(t1, t1, t2);
5132 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5133 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5134 gen_load_spr(t0, SPR_MQ);
5135 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5136 tcg_gen_br(l2);
5137 gen_set_label(l1);
5138 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5139 gen_load_spr(t2, SPR_MQ);
5140 tcg_gen_andc_tl(t1, t2, t1);
5141 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5142 gen_set_label(l2);
5143 tcg_temp_free(t0);
5144 tcg_temp_free(t1);
5145 tcg_temp_free(t2);
5146 if (unlikely(Rc(ctx->opcode) != 0))
5147 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5148 }
5149
5150 /* slq - slq. */
5151 static void gen_slq(DisasContext *ctx)
5152 {
5153 TCGLabel *l1 = gen_new_label();
5154 TCGv t0 = tcg_temp_new();
5155 TCGv t1 = tcg_temp_new();
5156 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5157 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5158 tcg_gen_subfi_tl(t1, 32, t1);
5159 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5160 tcg_gen_or_tl(t1, t0, t1);
5161 gen_store_spr(SPR_MQ, t1);
5162 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5163 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5164 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5165 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5166 gen_set_label(l1);
5167 tcg_temp_free(t0);
5168 tcg_temp_free(t1);
5169 if (unlikely(Rc(ctx->opcode) != 0))
5170 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5171 }
5172
5173 /* sraiq - sraiq. */
5174 static void gen_sraiq(DisasContext *ctx)
5175 {
5176 int sh = SH(ctx->opcode);
5177 TCGLabel *l1 = gen_new_label();
5178 TCGv t0 = tcg_temp_new();
5179 TCGv t1 = tcg_temp_new();
5180 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5181 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5182 tcg_gen_or_tl(t0, t0, t1);
5183 gen_store_spr(SPR_MQ, t0);
5184 tcg_gen_movi_tl(cpu_ca, 0);
5185 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5186 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5187 tcg_gen_movi_tl(cpu_ca, 1);
5188 gen_set_label(l1);
5189 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5190 tcg_temp_free(t0);
5191 tcg_temp_free(t1);
5192 if (unlikely(Rc(ctx->opcode) != 0))
5193 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5194 }
5195
5196 /* sraq - sraq. */
5197 static void gen_sraq(DisasContext *ctx)
5198 {
5199 TCGLabel *l1 = gen_new_label();
5200 TCGLabel *l2 = gen_new_label();
5201 TCGv t0 = tcg_temp_new();
5202 TCGv t1 = tcg_temp_local_new();
5203 TCGv t2 = tcg_temp_local_new();
5204 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5205 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5206 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5207 tcg_gen_subfi_tl(t2, 32, t2);
5208 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5209 tcg_gen_or_tl(t0, t0, t2);
5210 gen_store_spr(SPR_MQ, t0);
5211 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5212 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5213 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5214 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5215 gen_set_label(l1);
5216 tcg_temp_free(t0);
5217 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5218 tcg_gen_movi_tl(cpu_ca, 0);
5219 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5220 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5221 tcg_gen_movi_tl(cpu_ca, 1);
5222 gen_set_label(l2);
5223 tcg_temp_free(t1);
5224 tcg_temp_free(t2);
5225 if (unlikely(Rc(ctx->opcode) != 0))
5226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5227 }
5228
5229 /* sre - sre. */
5230 static void gen_sre(DisasContext *ctx)
5231 {
5232 TCGv t0 = tcg_temp_new();
5233 TCGv t1 = tcg_temp_new();
5234 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5235 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5236 tcg_gen_subfi_tl(t1, 32, t1);
5237 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5238 tcg_gen_or_tl(t1, t0, t1);
5239 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5240 gen_store_spr(SPR_MQ, t1);
5241 tcg_temp_free(t0);
5242 tcg_temp_free(t1);
5243 if (unlikely(Rc(ctx->opcode) != 0))
5244 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5245 }
5246
5247 /* srea - srea. */
5248 static void gen_srea(DisasContext *ctx)
5249 {
5250 TCGv t0 = tcg_temp_new();
5251 TCGv t1 = tcg_temp_new();
5252 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5253 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5254 gen_store_spr(SPR_MQ, t0);
5255 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5256 tcg_temp_free(t0);
5257 tcg_temp_free(t1);
5258 if (unlikely(Rc(ctx->opcode) != 0))
5259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5260 }
5261
5262 /* sreq */
5263 static void gen_sreq(DisasContext *ctx)
5264 {
5265 TCGv t0 = tcg_temp_new();
5266 TCGv t1 = tcg_temp_new();
5267 TCGv t2 = tcg_temp_new();
5268 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5269 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5270 tcg_gen_shr_tl(t1, t1, t0);
5271 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5272 gen_load_spr(t2, SPR_MQ);
5273 gen_store_spr(SPR_MQ, t0);
5274 tcg_gen_and_tl(t0, t0, t1);
5275 tcg_gen_andc_tl(t2, t2, t1);
5276 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5277 tcg_temp_free(t0);
5278 tcg_temp_free(t1);
5279 tcg_temp_free(t2);
5280 if (unlikely(Rc(ctx->opcode) != 0))
5281 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5282 }
5283
5284 /* sriq */
5285 static void gen_sriq(DisasContext *ctx)
5286 {
5287 int sh = SH(ctx->opcode);
5288 TCGv t0 = tcg_temp_new();
5289 TCGv t1 = tcg_temp_new();
5290 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5291 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5292 tcg_gen_or_tl(t1, t0, t1);
5293 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5294 gen_store_spr(SPR_MQ, t1);
5295 tcg_temp_free(t0);
5296 tcg_temp_free(t1);
5297 if (unlikely(Rc(ctx->opcode) != 0))
5298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5299 }
5300
5301 /* srliq */
5302 static void gen_srliq(DisasContext *ctx)
5303 {
5304 int sh = SH(ctx->opcode);
5305 TCGv t0 = tcg_temp_new();
5306 TCGv t1 = tcg_temp_new();
5307 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5308 gen_load_spr(t1, SPR_MQ);
5309 gen_store_spr(SPR_MQ, t0);
5310 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5311 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5312 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5313 tcg_temp_free(t0);
5314 tcg_temp_free(t1);
5315 if (unlikely(Rc(ctx->opcode) != 0))
5316 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5317 }
5318
5319 /* srlq */
5320 static void gen_srlq(DisasContext *ctx)
5321 {
5322 TCGLabel *l1 = gen_new_label();
5323 TCGLabel *l2 = gen_new_label();
5324 TCGv t0 = tcg_temp_local_new();
5325 TCGv t1 = tcg_temp_local_new();
5326 TCGv t2 = tcg_temp_local_new();
5327 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5328 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5329 tcg_gen_shr_tl(t2, t1, t2);
5330 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5331 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5332 gen_load_spr(t0, SPR_MQ);
5333 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5334 tcg_gen_br(l2);
5335 gen_set_label(l1);
5336 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5337 tcg_gen_and_tl(t0, t0, t2);
5338 gen_load_spr(t1, SPR_MQ);
5339 tcg_gen_andc_tl(t1, t1, t2);
5340 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5341 gen_set_label(l2);
5342 tcg_temp_free(t0);
5343 tcg_temp_free(t1);
5344 tcg_temp_free(t2);
5345 if (unlikely(Rc(ctx->opcode) != 0))
5346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5347 }
5348
5349 /* srq */
5350 static void gen_srq(DisasContext *ctx)
5351 {
5352 TCGLabel *l1 = gen_new_label();
5353 TCGv t0 = tcg_temp_new();
5354 TCGv t1 = tcg_temp_new();
5355 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5356 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5357 tcg_gen_subfi_tl(t1, 32, t1);
5358 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5359 tcg_gen_or_tl(t1, t0, t1);
5360 gen_store_spr(SPR_MQ, t1);
5361 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5362 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5363 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5364 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5365 gen_set_label(l1);
5366 tcg_temp_free(t0);
5367 tcg_temp_free(t1);
5368 if (unlikely(Rc(ctx->opcode) != 0))
5369 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5370 }
5371
5372 /* PowerPC 602 specific instructions */
5373
5374 /* dsa */
5375 static void gen_dsa(DisasContext *ctx)
5376 {
5377 /* XXX: TODO */
5378 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5379 }
5380
5381 /* esa */
5382 static void gen_esa(DisasContext *ctx)
5383 {
5384 /* XXX: TODO */
5385 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5386 }
5387
5388 /* mfrom */
5389 static void gen_mfrom(DisasContext *ctx)
5390 {
5391 #if defined(CONFIG_USER_ONLY)
5392 GEN_PRIV;
5393 #else
5394 CHK_SV;
5395 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5396 #endif /* defined(CONFIG_USER_ONLY) */
5397 }
5398
5399 /* 602 - 603 - G2 TLB management */
5400
5401 /* tlbld */
5402 static void gen_tlbld_6xx(DisasContext *ctx)
5403 {
5404 #if defined(CONFIG_USER_ONLY)
5405 GEN_PRIV;
5406 #else
5407 CHK_SV;
5408 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5409 #endif /* defined(CONFIG_USER_ONLY) */
5410 }
5411
5412 /* tlbli */
5413 static void gen_tlbli_6xx(DisasContext *ctx)
5414 {
5415 #if defined(CONFIG_USER_ONLY)
5416 GEN_PRIV;
5417 #else
5418 CHK_SV;
5419 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5420 #endif /* defined(CONFIG_USER_ONLY) */
5421 }
5422
5423 /* 74xx TLB management */
5424
5425 /* tlbld */
5426 static void gen_tlbld_74xx(DisasContext *ctx)
5427 {
5428 #if defined(CONFIG_USER_ONLY)
5429 GEN_PRIV;
5430 #else
5431 CHK_SV;
5432 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5433 #endif /* defined(CONFIG_USER_ONLY) */
5434 }
5435
5436 /* tlbli */
5437 static void gen_tlbli_74xx(DisasContext *ctx)
5438 {
5439 #if defined(CONFIG_USER_ONLY)
5440 GEN_PRIV;
5441 #else
5442 CHK_SV;
5443 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5444 #endif /* defined(CONFIG_USER_ONLY) */
5445 }
5446
5447 /* POWER instructions not in PowerPC 601 */
5448
5449 /* clf */
5450 static void gen_clf(DisasContext *ctx)
5451 {
5452 /* Cache line flush: implemented as no-op */
5453 }
5454
5455 /* cli */
5456 static void gen_cli(DisasContext *ctx)
5457 {
5458 #if defined(CONFIG_USER_ONLY)
5459 GEN_PRIV;
5460 #else
5461 /* Cache line invalidate: privileged and treated as no-op */
5462 CHK_SV;
5463 #endif /* defined(CONFIG_USER_ONLY) */
5464 }
5465
5466 /* dclst */
5467 static void gen_dclst(DisasContext *ctx)
5468 {
5469 /* Data cache line store: treated as no-op */
5470 }
5471
5472 static void gen_mfsri(DisasContext *ctx)
5473 {
5474 #if defined(CONFIG_USER_ONLY)
5475 GEN_PRIV;
5476 #else
5477 int ra = rA(ctx->opcode);
5478 int rd = rD(ctx->opcode);
5479 TCGv t0;
5480
5481 CHK_SV;
5482 t0 = tcg_temp_new();
5483 gen_addr_reg_index(ctx, t0);
5484 tcg_gen_extract_tl(t0, t0, 28, 4);
5485 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5486 tcg_temp_free(t0);
5487 if (ra != 0 && ra != rd)
5488 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5489 #endif /* defined(CONFIG_USER_ONLY) */
5490 }
5491
5492 static void gen_rac(DisasContext *ctx)
5493 {
5494 #if defined(CONFIG_USER_ONLY)
5495 GEN_PRIV;
5496 #else
5497 TCGv t0;
5498
5499 CHK_SV;
5500 t0 = tcg_temp_new();
5501 gen_addr_reg_index(ctx, t0);
5502 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5503 tcg_temp_free(t0);
5504 #endif /* defined(CONFIG_USER_ONLY) */
5505 }
5506
5507 static void gen_rfsvc(DisasContext *ctx)
5508 {
5509 #if defined(CONFIG_USER_ONLY)
5510 GEN_PRIV;
5511 #else
5512 CHK_SV;
5513
5514 gen_helper_rfsvc(cpu_env);
5515 gen_sync_exception(ctx);
5516 #endif /* defined(CONFIG_USER_ONLY) */
5517 }
5518
5519 /* svc is not implemented for now */
5520
5521 /* BookE specific instructions */
5522
5523 /* XXX: not implemented on 440 ? */
5524 static void gen_mfapidi(DisasContext *ctx)
5525 {
5526 /* XXX: TODO */
5527 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5528 }
5529
5530 /* XXX: not implemented on 440 ? */
5531 static void gen_tlbiva(DisasContext *ctx)
5532 {
5533 #if defined(CONFIG_USER_ONLY)
5534 GEN_PRIV;
5535 #else
5536 TCGv t0;
5537
5538 CHK_SV;
5539 t0 = tcg_temp_new();
5540 gen_addr_reg_index(ctx, t0);
5541 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5542 tcg_temp_free(t0);
5543 #endif /* defined(CONFIG_USER_ONLY) */
5544 }
5545
5546 /* All 405 MAC instructions are translated here */
5547 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5548 int ra, int rb, int rt, int Rc)
5549 {
5550 TCGv t0, t1;
5551
5552 t0 = tcg_temp_local_new();
5553 t1 = tcg_temp_local_new();
5554
5555 switch (opc3 & 0x0D) {
5556 case 0x05:
5557 /* macchw - macchw. - macchwo - macchwo. */
5558 /* macchws - macchws. - macchwso - macchwso. */
5559 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5560 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5561 /* mulchw - mulchw. */
5562 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5563 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5564 tcg_gen_ext16s_tl(t1, t1);
5565 break;
5566 case 0x04:
5567 /* macchwu - macchwu. - macchwuo - macchwuo. */
5568 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5569 /* mulchwu - mulchwu. */
5570 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5571 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5572 tcg_gen_ext16u_tl(t1, t1);
5573 break;
5574 case 0x01:
5575 /* machhw - machhw. - machhwo - machhwo. */
5576 /* machhws - machhws. - machhwso - machhwso. */
5577 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5578 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5579 /* mulhhw - mulhhw. */
5580 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5581 tcg_gen_ext16s_tl(t0, t0);
5582 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5583 tcg_gen_ext16s_tl(t1, t1);
5584 break;
5585 case 0x00:
5586 /* machhwu - machhwu. - machhwuo - machhwuo. */
5587 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5588 /* mulhhwu - mulhhwu. */
5589 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5590 tcg_gen_ext16u_tl(t0, t0);
5591 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5592 tcg_gen_ext16u_tl(t1, t1);
5593 break;
5594 case 0x0D:
5595 /* maclhw - maclhw. - maclhwo - maclhwo. */
5596 /* maclhws - maclhws. - maclhwso - maclhwso. */
5597 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5598 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5599 /* mullhw - mullhw. */
5600 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5601 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5602 break;
5603 case 0x0C:
5604 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5605 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5606 /* mullhwu - mullhwu. */
5607 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5608 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5609 break;
5610 }
5611 if (opc2 & 0x04) {
5612 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5613 tcg_gen_mul_tl(t1, t0, t1);
5614 if (opc2 & 0x02) {
5615 /* nmultiply-and-accumulate (0x0E) */
5616 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5617 } else {
5618 /* multiply-and-accumulate (0x0C) */
5619 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5620 }
5621
5622 if (opc3 & 0x12) {
5623 /* Check overflow and/or saturate */
5624 TCGLabel *l1 = gen_new_label();
5625
5626 if (opc3 & 0x10) {
5627 /* Start with XER OV disabled, the most likely case */
5628 tcg_gen_movi_tl(cpu_ov, 0);
5629 }
5630 if (opc3 & 0x01) {
5631 /* Signed */
5632 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5633 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5634 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5635 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5636 if (opc3 & 0x02) {
5637 /* Saturate */
5638 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5639 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5640 }
5641 } else {
5642 /* Unsigned */
5643 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5644 if (opc3 & 0x02) {
5645 /* Saturate */
5646 tcg_gen_movi_tl(t0, UINT32_MAX);
5647 }
5648 }
5649 if (opc3 & 0x10) {
5650 /* Check overflow */
5651 tcg_gen_movi_tl(cpu_ov, 1);
5652 tcg_gen_movi_tl(cpu_so, 1);
5653 }
5654 gen_set_label(l1);
5655 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5656 }
5657 } else {
5658 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5659 }
5660 tcg_temp_free(t0);
5661 tcg_temp_free(t1);
5662 if (unlikely(Rc) != 0) {
5663 /* Update Rc0 */
5664 gen_set_Rc0(ctx, cpu_gpr[rt]);
5665 }
5666 }
5667
5668 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5669 static void glue(gen_, name)(DisasContext *ctx) \
5670 { \
5671 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5672 rD(ctx->opcode), Rc(ctx->opcode)); \
5673 }
5674
5675 /* macchw - macchw. */
5676 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5677 /* macchwo - macchwo. */
5678 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5679 /* macchws - macchws. */
5680 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5681 /* macchwso - macchwso. */
5682 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5683 /* macchwsu - macchwsu. */
5684 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5685 /* macchwsuo - macchwsuo. */
5686 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5687 /* macchwu - macchwu. */
5688 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5689 /* macchwuo - macchwuo. */
5690 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5691 /* machhw - machhw. */
5692 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5693 /* machhwo - machhwo. */
5694 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5695 /* machhws - machhws. */
5696 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5697 /* machhwso - machhwso. */
5698 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5699 /* machhwsu - machhwsu. */
5700 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5701 /* machhwsuo - machhwsuo. */
5702 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5703 /* machhwu - machhwu. */
5704 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5705 /* machhwuo - machhwuo. */
5706 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5707 /* maclhw - maclhw. */
5708 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5709 /* maclhwo - maclhwo. */
5710 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5711 /* maclhws - maclhws. */
5712 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5713 /* maclhwso - maclhwso. */
5714 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5715 /* maclhwu - maclhwu. */
5716 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5717 /* maclhwuo - maclhwuo. */
5718 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5719 /* maclhwsu - maclhwsu. */
5720 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5721 /* maclhwsuo - maclhwsuo. */
5722 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5723 /* nmacchw - nmacchw. */
5724 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5725 /* nmacchwo - nmacchwo. */
5726 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5727 /* nmacchws - nmacchws. */
5728 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5729 /* nmacchwso - nmacchwso. */
5730 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5731 /* nmachhw - nmachhw. */
5732 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5733 /* nmachhwo - nmachhwo. */
5734 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5735 /* nmachhws - nmachhws. */
5736 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5737 /* nmachhwso - nmachhwso. */
5738 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5739 /* nmaclhw - nmaclhw. */
5740 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5741 /* nmaclhwo - nmaclhwo. */
5742 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5743 /* nmaclhws - nmaclhws. */
5744 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5745 /* nmaclhwso - nmaclhwso. */
5746 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5747
5748 /* mulchw - mulchw. */
5749 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5750 /* mulchwu - mulchwu. */
5751 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5752 /* mulhhw - mulhhw. */
5753 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5754 /* mulhhwu - mulhhwu. */
5755 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5756 /* mullhw - mullhw. */
5757 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5758 /* mullhwu - mullhwu. */
5759 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5760
5761 /* mfdcr */
5762 static void gen_mfdcr(DisasContext *ctx)
5763 {
5764 #if defined(CONFIG_USER_ONLY)
5765 GEN_PRIV;
5766 #else
5767 TCGv dcrn;
5768
5769 CHK_SV;
5770 dcrn = tcg_const_tl(SPR(ctx->opcode));
5771 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5772 tcg_temp_free(dcrn);
5773 #endif /* defined(CONFIG_USER_ONLY) */
5774 }
5775
5776 /* mtdcr */
5777 static void gen_mtdcr(DisasContext *ctx)
5778 {
5779 #if defined(CONFIG_USER_ONLY)
5780 GEN_PRIV;
5781 #else
5782 TCGv dcrn;
5783
5784 CHK_SV;
5785 dcrn = tcg_const_tl(SPR(ctx->opcode));
5786 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5787 tcg_temp_free(dcrn);
5788 #endif /* defined(CONFIG_USER_ONLY) */
5789 }
5790
5791 /* mfdcrx */
5792 /* XXX: not implemented on 440 ? */
5793 static void gen_mfdcrx(DisasContext *ctx)
5794 {
5795 #if defined(CONFIG_USER_ONLY)
5796 GEN_PRIV;
5797 #else
5798 CHK_SV;
5799 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5800 cpu_gpr[rA(ctx->opcode)]);
5801 /* Note: Rc update flag set leads to undefined state of Rc0 */
5802 #endif /* defined(CONFIG_USER_ONLY) */
5803 }
5804
5805 /* mtdcrx */
5806 /* XXX: not implemented on 440 ? */
5807 static void gen_mtdcrx(DisasContext *ctx)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 GEN_PRIV;
5811 #else
5812 CHK_SV;
5813 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5814 cpu_gpr[rS(ctx->opcode)]);
5815 /* Note: Rc update flag set leads to undefined state of Rc0 */
5816 #endif /* defined(CONFIG_USER_ONLY) */
5817 }
5818
5819 /* mfdcrux (PPC 460) : user-mode access to DCR */
5820 static void gen_mfdcrux(DisasContext *ctx)
5821 {
5822 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5823 cpu_gpr[rA(ctx->opcode)]);
5824 /* Note: Rc update flag set leads to undefined state of Rc0 */
5825 }
5826
5827 /* mtdcrux (PPC 460) : user-mode access to DCR */
5828 static void gen_mtdcrux(DisasContext *ctx)
5829 {
5830 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5831 cpu_gpr[rS(ctx->opcode)]);
5832 /* Note: Rc update flag set leads to undefined state of Rc0 */
5833 }
5834
5835 /* dccci */
5836 static void gen_dccci(DisasContext *ctx)
5837 {
5838 CHK_SV;
5839 /* interpreted as no-op */
5840 }
5841
5842 /* dcread */
5843 static void gen_dcread(DisasContext *ctx)
5844 {
5845 #if defined(CONFIG_USER_ONLY)
5846 GEN_PRIV;
5847 #else
5848 TCGv EA, val;
5849
5850 CHK_SV;
5851 gen_set_access_type(ctx, ACCESS_CACHE);
5852 EA = tcg_temp_new();
5853 gen_addr_reg_index(ctx, EA);
5854 val = tcg_temp_new();
5855 gen_qemu_ld32u(ctx, val, EA);
5856 tcg_temp_free(val);
5857 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5858 tcg_temp_free(EA);
5859 #endif /* defined(CONFIG_USER_ONLY) */
5860 }
5861
5862 /* icbt */
5863 static void gen_icbt_40x(DisasContext *ctx)
5864 {
5865 /* interpreted as no-op */
5866 /* XXX: specification say this is treated as a load by the MMU
5867 * but does not generate any exception
5868 */
5869 }
5870
5871 /* iccci */
5872 static void gen_iccci(DisasContext *ctx)
5873 {
5874 CHK_SV;
5875 /* interpreted as no-op */
5876 }
5877
5878 /* icread */
5879 static void gen_icread(DisasContext *ctx)
5880 {
5881 CHK_SV;
5882 /* interpreted as no-op */
5883 }
5884
5885 /* rfci (supervisor only) */
5886 static void gen_rfci_40x(DisasContext *ctx)
5887 {
5888 #if defined(CONFIG_USER_ONLY)
5889 GEN_PRIV;
5890 #else
5891 CHK_SV;
5892 /* Restore CPU state */
5893 gen_helper_40x_rfci(cpu_env);
5894 gen_sync_exception(ctx);
5895 #endif /* defined(CONFIG_USER_ONLY) */
5896 }
5897
5898 static void gen_rfci(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 GEN_PRIV;
5902 #else
5903 CHK_SV;
5904 /* Restore CPU state */
5905 gen_helper_rfci(cpu_env);
5906 gen_sync_exception(ctx);
5907 #endif /* defined(CONFIG_USER_ONLY) */
5908 }
5909
5910 /* BookE specific */
5911
5912 /* XXX: not implemented on 440 ? */
5913 static void gen_rfdi(DisasContext *ctx)
5914 {
5915 #if defined(CONFIG_USER_ONLY)
5916 GEN_PRIV;
5917 #else
5918 CHK_SV;
5919 /* Restore CPU state */
5920 gen_helper_rfdi(cpu_env);
5921 gen_sync_exception(ctx);
5922 #endif /* defined(CONFIG_USER_ONLY) */
5923 }
5924
5925 /* XXX: not implemented on 440 ? */
5926 static void gen_rfmci(DisasContext *ctx)
5927 {
5928 #if defined(CONFIG_USER_ONLY)
5929 GEN_PRIV;
5930 #else
5931 CHK_SV;
5932 /* Restore CPU state */
5933 gen_helper_rfmci(cpu_env);
5934 gen_sync_exception(ctx);
5935 #endif /* defined(CONFIG_USER_ONLY) */
5936 }
5937
5938 /* TLB management - PowerPC 405 implementation */
5939
5940 /* tlbre */
5941 static void gen_tlbre_40x(DisasContext *ctx)
5942 {
5943 #if defined(CONFIG_USER_ONLY)
5944 GEN_PRIV;
5945 #else
5946 CHK_SV;
5947 switch (rB(ctx->opcode)) {
5948 case 0:
5949 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5950 cpu_gpr[rA(ctx->opcode)]);
5951 break;
5952 case 1:
5953 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5954 cpu_gpr[rA(ctx->opcode)]);
5955 break;
5956 default:
5957 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5958 break;
5959 }
5960 #endif /* defined(CONFIG_USER_ONLY) */
5961 }
5962
5963 /* tlbsx - tlbsx. */
5964 static void gen_tlbsx_40x(DisasContext *ctx)
5965 {
5966 #if defined(CONFIG_USER_ONLY)
5967 GEN_PRIV;
5968 #else
5969 TCGv t0;
5970
5971 CHK_SV;
5972 t0 = tcg_temp_new();
5973 gen_addr_reg_index(ctx, t0);
5974 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5975 tcg_temp_free(t0);
5976 if (Rc(ctx->opcode)) {
5977 TCGLabel *l1 = gen_new_label();
5978 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5979 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5980 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5981 gen_set_label(l1);
5982 }
5983 #endif /* defined(CONFIG_USER_ONLY) */
5984 }
5985
5986 /* tlbwe */
5987 static void gen_tlbwe_40x(DisasContext *ctx)
5988 {
5989 #if defined(CONFIG_USER_ONLY)
5990 GEN_PRIV;
5991 #else
5992 CHK_SV;
5993
5994 switch (rB(ctx->opcode)) {
5995 case 0:
5996 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5997 cpu_gpr[rS(ctx->opcode)]);
5998 break;
5999 case 1:
6000 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6001 cpu_gpr[rS(ctx->opcode)]);
6002 break;
6003 default:
6004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6005 break;
6006 }
6007 #endif /* defined(CONFIG_USER_ONLY) */
6008 }
6009
6010 /* TLB management - PowerPC 440 implementation */
6011
6012 /* tlbre */
6013 static void gen_tlbre_440(DisasContext *ctx)
6014 {
6015 #if defined(CONFIG_USER_ONLY)
6016 GEN_PRIV;
6017 #else
6018 CHK_SV;
6019
6020 switch (rB(ctx->opcode)) {
6021 case 0:
6022 case 1:
6023 case 2:
6024 {
6025 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6026 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6027 t0, cpu_gpr[rA(ctx->opcode)]);
6028 tcg_temp_free_i32(t0);
6029 }
6030 break;
6031 default:
6032 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6033 break;
6034 }
6035 #endif /* defined(CONFIG_USER_ONLY) */
6036 }
6037
6038 /* tlbsx - tlbsx. */
6039 static void gen_tlbsx_440(DisasContext *ctx)
6040 {
6041 #if defined(CONFIG_USER_ONLY)
6042 GEN_PRIV;
6043 #else
6044 TCGv t0;
6045
6046 CHK_SV;
6047 t0 = tcg_temp_new();
6048 gen_addr_reg_index(ctx, t0);
6049 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6050 tcg_temp_free(t0);
6051 if (Rc(ctx->opcode)) {
6052 TCGLabel *l1 = gen_new_label();
6053 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6054 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6055 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6056 gen_set_label(l1);
6057 }
6058 #endif /* defined(CONFIG_USER_ONLY) */
6059 }
6060
6061 /* tlbwe */
6062 static void gen_tlbwe_440(DisasContext *ctx)
6063 {
6064 #if defined(CONFIG_USER_ONLY)
6065 GEN_PRIV;
6066 #else
6067 CHK_SV;
6068 switch (rB(ctx->opcode)) {
6069 case 0:
6070 case 1:
6071 case 2:
6072 {
6073 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6074 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6075 cpu_gpr[rS(ctx->opcode)]);
6076 tcg_temp_free_i32(t0);
6077 }
6078 break;
6079 default:
6080 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6081 break;
6082 }
6083 #endif /* defined(CONFIG_USER_ONLY) */
6084 }
6085
6086 /* TLB management - PowerPC BookE 2.06 implementation */
6087
6088 /* tlbre */
6089 static void gen_tlbre_booke206(DisasContext *ctx)
6090 {
6091 #if defined(CONFIG_USER_ONLY)
6092 GEN_PRIV;
6093 #else
6094 CHK_SV;
6095 gen_helper_booke206_tlbre(cpu_env);
6096 #endif /* defined(CONFIG_USER_ONLY) */
6097 }
6098
6099 /* tlbsx - tlbsx. */
6100 static void gen_tlbsx_booke206(DisasContext *ctx)
6101 {
6102 #if defined(CONFIG_USER_ONLY)
6103 GEN_PRIV;
6104 #else
6105 TCGv t0;
6106
6107 CHK_SV;
6108 if (rA(ctx->opcode)) {
6109 t0 = tcg_temp_new();
6110 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6111 } else {
6112 t0 = tcg_const_tl(0);
6113 }
6114
6115 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6116 gen_helper_booke206_tlbsx(cpu_env, t0);
6117 tcg_temp_free(t0);
6118 #endif /* defined(CONFIG_USER_ONLY) */
6119 }
6120
6121 /* tlbwe */
6122 static void gen_tlbwe_booke206(DisasContext *ctx)
6123 {
6124 #if defined(CONFIG_USER_ONLY)
6125 GEN_PRIV;
6126 #else
6127 CHK_SV;
6128 gen_helper_booke206_tlbwe(cpu_env);
6129 #endif /* defined(CONFIG_USER_ONLY) */
6130 }
6131
6132 static void gen_tlbivax_booke206(DisasContext *ctx)
6133 {
6134 #if defined(CONFIG_USER_ONLY)
6135 GEN_PRIV;
6136 #else
6137 TCGv t0;
6138
6139 CHK_SV;
6140 t0 = tcg_temp_new();
6141 gen_addr_reg_index(ctx, t0);
6142 gen_helper_booke206_tlbivax(cpu_env, t0);
6143 tcg_temp_free(t0);
6144 #endif /* defined(CONFIG_USER_ONLY) */
6145 }
6146
6147 static void gen_tlbilx_booke206(DisasContext *ctx)
6148 {
6149 #if defined(CONFIG_USER_ONLY)
6150 GEN_PRIV;
6151 #else
6152 TCGv t0;
6153
6154 CHK_SV;
6155 t0 = tcg_temp_new();
6156 gen_addr_reg_index(ctx, t0);
6157
6158 switch((ctx->opcode >> 21) & 0x3) {
6159 case 0:
6160 gen_helper_booke206_tlbilx0(cpu_env, t0);
6161 break;
6162 case 1:
6163 gen_helper_booke206_tlbilx1(cpu_env, t0);
6164 break;
6165 case 3:
6166 gen_helper_booke206_tlbilx3(cpu_env, t0);
6167 break;
6168 default:
6169 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6170 break;
6171 }
6172
6173 tcg_temp_free(t0);
6174 #endif /* defined(CONFIG_USER_ONLY) */
6175 }
6176
6177
6178 /* wrtee */
6179 static void gen_wrtee(DisasContext *ctx)
6180 {
6181 #if defined(CONFIG_USER_ONLY)
6182 GEN_PRIV;
6183 #else
6184 TCGv t0;
6185
6186 CHK_SV;
6187 t0 = tcg_temp_new();
6188 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6189 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6190 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6191 tcg_temp_free(t0);
6192 /* Stop translation to have a chance to raise an exception
6193 * if we just set msr_ee to 1
6194 */
6195 gen_stop_exception(ctx);
6196 #endif /* defined(CONFIG_USER_ONLY) */
6197 }
6198
6199 /* wrteei */
6200 static void gen_wrteei(DisasContext *ctx)
6201 {
6202 #if defined(CONFIG_USER_ONLY)
6203 GEN_PRIV;
6204 #else
6205 CHK_SV;
6206 if (ctx->opcode & 0x00008000) {
6207 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6208 /* Stop translation to have a chance to raise an exception */
6209 gen_stop_exception(ctx);
6210 } else {
6211 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6212 }
6213 #endif /* defined(CONFIG_USER_ONLY) */
6214 }
6215
6216 /* PowerPC 440 specific instructions */
6217
6218 /* dlmzb */
6219 static void gen_dlmzb(DisasContext *ctx)
6220 {
6221 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6222 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6223 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6224 tcg_temp_free_i32(t0);
6225 }
6226
6227 /* mbar replaces eieio on 440 */
6228 static void gen_mbar(DisasContext *ctx)
6229 {
6230 /* interpreted as no-op */
6231 }
6232
6233 /* msync replaces sync on 440 */
6234 static void gen_msync_4xx(DisasContext *ctx)
6235 {
6236 /* interpreted as no-op */
6237 }
6238
6239 /* icbt */
6240 static void gen_icbt_440(DisasContext *ctx)
6241 {
6242 /* interpreted as no-op */
6243 /* XXX: specification say this is treated as a load by the MMU
6244 * but does not generate any exception
6245 */
6246 }
6247
6248 /* Embedded.Processor Control */
6249
6250 static void gen_msgclr(DisasContext *ctx)
6251 {
6252 #if defined(CONFIG_USER_ONLY)
6253 GEN_PRIV;
6254 #else
6255 CHK_HV;
6256 /* 64-bit server processors compliant with arch 2.x */
6257 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6258 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6259 } else {
6260 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6261 }
6262 #endif /* defined(CONFIG_USER_ONLY) */
6263 }
6264
6265 static void gen_msgsnd(DisasContext *ctx)
6266 {
6267 #if defined(CONFIG_USER_ONLY)
6268 GEN_PRIV;
6269 #else
6270 CHK_HV;
6271 /* 64-bit server processors compliant with arch 2.x */
6272 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6273 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6274 } else {
6275 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6276 }
6277 #endif /* defined(CONFIG_USER_ONLY) */
6278 }
6279
6280 static void gen_msgsync(DisasContext *ctx)
6281 {
6282 #if defined(CONFIG_USER_ONLY)
6283 GEN_PRIV;
6284 #else
6285 CHK_HV;
6286 #endif /* defined(CONFIG_USER_ONLY) */
6287 /* interpreted as no-op */
6288 }
6289
6290 #if defined(TARGET_PPC64)
6291 static void gen_maddld(DisasContext *ctx)
6292 {
6293 TCGv_i64 t1 = tcg_temp_new_i64();
6294
6295 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6296 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6297 tcg_temp_free_i64(t1);
6298 }
6299
6300 /* maddhd maddhdu */
6301 static void gen_maddhd_maddhdu(DisasContext *ctx)
6302 {
6303 TCGv_i64 lo = tcg_temp_new_i64();
6304 TCGv_i64 hi = tcg_temp_new_i64();
6305 TCGv_i64 t1 = tcg_temp_new_i64();
6306
6307 if (Rc(ctx->opcode)) {
6308 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6309 cpu_gpr[rB(ctx->opcode)]);
6310 tcg_gen_movi_i64(t1, 0);
6311 } else {
6312 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6313 cpu_gpr[rB(ctx->opcode)]);
6314 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6315 }
6316 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6317 cpu_gpr[rC(ctx->opcode)], t1);
6318 tcg_temp_free_i64(lo);
6319 tcg_temp_free_i64(hi);
6320 tcg_temp_free_i64(t1);
6321 }
6322 #endif /* defined(TARGET_PPC64) */
6323
6324 static void gen_tbegin(DisasContext *ctx)
6325 {
6326 if (unlikely(!ctx->tm_enabled)) {
6327 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6328 return;
6329 }
6330 gen_helper_tbegin(cpu_env);
6331 }
6332
6333 #define GEN_TM_NOOP(name) \
6334 static inline void gen_##name(DisasContext *ctx) \
6335 { \
6336 if (unlikely(!ctx->tm_enabled)) { \
6337 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6338 return; \
6339 } \
6340 /* Because tbegin always fails in QEMU, these user \
6341 * space instructions all have a simple implementation: \
6342 * \
6343 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6344 * = 0b0 || 0b00 || 0b0 \
6345 */ \
6346 tcg_gen_movi_i32(cpu_crf[0], 0); \
6347 }
6348
6349 GEN_TM_NOOP(tend);
6350 GEN_TM_NOOP(tabort);
6351 GEN_TM_NOOP(tabortwc);
6352 GEN_TM_NOOP(tabortwci);
6353 GEN_TM_NOOP(tabortdc);
6354 GEN_TM_NOOP(tabortdci);
6355 GEN_TM_NOOP(tsr);
6356 static inline void gen_cp_abort(DisasContext *ctx)
6357 {
6358 // Do Nothing
6359 }
6360
6361 #define GEN_CP_PASTE_NOOP(name) \
6362 static inline void gen_##name(DisasContext *ctx) \
6363 { \
6364 /* Generate invalid exception until \
6365 * we have an implementation of the copy \
6366 * paste facility \
6367 */ \
6368 gen_invalid(ctx); \
6369 }
6370
6371 GEN_CP_PASTE_NOOP(copy)
6372 GEN_CP_PASTE_NOOP(paste)
6373
6374 static void gen_tcheck(DisasContext *ctx)
6375 {
6376 if (unlikely(!ctx->tm_enabled)) {
6377 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6378 return;
6379 }
6380 /* Because tbegin always fails, the tcheck implementation
6381 * is simple:
6382 *
6383 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6384 * = 0b1 || 0b00 || 0b0
6385 */
6386 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6387 }
6388
6389 #if defined(CONFIG_USER_ONLY)
6390 #define GEN_TM_PRIV_NOOP(name) \
6391 static inline void gen_##name(DisasContext *ctx) \
6392 { \
6393 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6394 }
6395
6396 #else
6397
6398 #define GEN_TM_PRIV_NOOP(name) \
6399 static inline void gen_##name(DisasContext *ctx) \
6400 { \
6401 CHK_SV; \
6402 if (unlikely(!ctx->tm_enabled)) { \
6403 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6404 return; \
6405 } \
6406 /* Because tbegin always fails, the implementation is \
6407 * simple: \
6408 * \
6409 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6410 * = 0b0 || 0b00 | 0b0 \
6411 */ \
6412 tcg_gen_movi_i32(cpu_crf[0], 0); \
6413 }
6414
6415 #endif
6416
6417 GEN_TM_PRIV_NOOP(treclaim);
6418 GEN_TM_PRIV_NOOP(trechkpt);
6419
6420 #include "translate/fp-impl.inc.c"
6421
6422 #include "translate/vmx-impl.inc.c"
6423
6424 #include "translate/vsx-impl.inc.c"
6425
6426 #include "translate/dfp-impl.inc.c"
6427
6428 #include "translate/spe-impl.inc.c"
6429
6430 /* Handles lfdp, lxsd, lxssp */
6431 static void gen_dform39(DisasContext *ctx)
6432 {
6433 switch (ctx->opcode & 0x3) {
6434 case 0: /* lfdp */
6435 if (ctx->insns_flags2 & PPC2_ISA205) {
6436 return gen_lfdp(ctx);
6437 }
6438 break;
6439 case 2: /* lxsd */
6440 if (ctx->insns_flags2 & PPC2_ISA300) {
6441 return gen_lxsd(ctx);
6442 }
6443 break;
6444 case 3: /* lxssp */
6445 if (ctx->insns_flags2 & PPC2_ISA300) {
6446 return gen_lxssp(ctx);
6447 }
6448 break;
6449 }
6450 return gen_invalid(ctx);
6451 }
6452
6453 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6454 static void gen_dform3D(DisasContext *ctx)
6455 {
6456 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6457 switch (ctx->opcode & 0x7) {
6458 case 1: /* lxv */
6459 if (ctx->insns_flags2 & PPC2_ISA300) {
6460 return gen_lxv(ctx);
6461 }
6462 break;
6463 case 5: /* stxv */
6464 if (ctx->insns_flags2 & PPC2_ISA300) {
6465 return gen_stxv(ctx);
6466 }
6467 break;
6468 }
6469 } else { /* DS-FORM */
6470 switch (ctx->opcode & 0x3) {
6471 case 0: /* stfdp */
6472 if (ctx->insns_flags2 & PPC2_ISA205) {
6473 return gen_stfdp(ctx);
6474 }
6475 break;
6476 case 2: /* stxsd */
6477 if (ctx->insns_flags2 & PPC2_ISA300) {
6478 return gen_stxsd(ctx);
6479 }
6480 break;
6481 case 3: /* stxssp */
6482 if (ctx->insns_flags2 & PPC2_ISA300) {
6483 return gen_stxssp(ctx);
6484 }
6485 break;
6486 }
6487 }
6488 return gen_invalid(ctx);
6489 }
6490
6491 static opcode_t opcodes[] = {
6492 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6493 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6494 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6495 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6496 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6497 #if defined(TARGET_PPC64)
6498 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6499 #endif
6500 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6501 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6502 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6503 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6504 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6505 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6506 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6507 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6508 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6509 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6510 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6511 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6512 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6513 #if defined(TARGET_PPC64)
6514 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6515 #endif
6516 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6517 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6518 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6519 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6520 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6521 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6522 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6523 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6524 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6525 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6526 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6527 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6528 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6529 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6530 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6531 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6532 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6533 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6534 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6535 #if defined(TARGET_PPC64)
6536 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6537 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6538 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6539 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6540 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6541 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6542 #endif
6543 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6544 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6545 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6546 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6547 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6548 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6549 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6550 #if defined(TARGET_PPC64)
6551 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6552 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6553 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6554 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6555 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6556 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6557 PPC_NONE, PPC2_ISA300),
6558 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6559 PPC_NONE, PPC2_ISA300),
6560 #endif
6561 #if defined(TARGET_PPC64)
6562 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6563 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6564 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6565 #endif
6566 /* handles lfdp, lxsd, lxssp */
6567 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6568 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6569 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6570 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6571 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6572 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6573 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6574 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6575 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6576 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6577 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6578 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6579 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6580 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6581 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6582 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6583 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6584 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6585 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6586 #if defined(TARGET_PPC64)
6587 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6588 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6589 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6590 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6591 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6592 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6593 #endif
6594 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6595 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6596 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6597 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6598 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6599 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6600 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6601 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6602 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6603 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6604 #if defined(TARGET_PPC64)
6605 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6606 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6607 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6608 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6609 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6610 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6611 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6612 #endif
6613 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6614 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6615 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6616 #if defined(TARGET_PPC64)
6617 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6618 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6619 #endif
6620 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6621 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6622 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6623 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6624 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6625 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6626 #if defined(TARGET_PPC64)
6627 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6628 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6629 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6630 #endif
6631 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6632 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6633 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6634 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6635 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6636 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6637 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6638 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6639 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6640 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6641 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6642 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6643 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6644 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6645 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6646 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6647 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6648 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6649 #if defined(TARGET_PPC64)
6650 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6651 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6652 PPC_SEGMENT_64B),
6653 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6654 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6655 PPC_SEGMENT_64B),
6656 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6657 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6658 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6659 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6660 #endif
6661 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6662 /* XXX Those instructions will need to be handled differently for
6663 * different ISA versions */
6664 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6665 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6666 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6667 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6668 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6669 #if defined(TARGET_PPC64)
6670 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6671 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6672 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6673 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6674 #endif
6675 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6676 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6677 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6678 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6679 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6680 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6681 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6682 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6683 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6684 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6685 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6686 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6687 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6688 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6689 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6690 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6691 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6692 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6693 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6694 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6695 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6696 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6697 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6698 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6699 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6700 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6701 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6702 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6703 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6704 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6705 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6706 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6707 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6708 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6709 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6710 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6711 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6712 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6713 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6714 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6715 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6716 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6717 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6718 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6719 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6720 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6721 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6722 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6723 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6724 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6725 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6726 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6727 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6728 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6729 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6730 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6731 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6732 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6733 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6734 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6735 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6736 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6737 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6738 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6739 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6740 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6741 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6742 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6743 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6744 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6745 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6746 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6747 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6748 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6749 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6750 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6751 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6752 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6753 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6754 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6755 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6756 PPC_NONE, PPC2_BOOKE206),
6757 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6758 PPC_NONE, PPC2_BOOKE206),
6759 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6760 PPC_NONE, PPC2_BOOKE206),
6761 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6762 PPC_NONE, PPC2_BOOKE206),
6763 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6764 PPC_NONE, PPC2_BOOKE206),
6765 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6766 PPC_NONE, PPC2_PRCNTL),
6767 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6768 PPC_NONE, PPC2_PRCNTL),
6769 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
6770 PPC_NONE, PPC2_PRCNTL),
6771 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6772 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6773 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6774 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6775 PPC_BOOKE, PPC2_BOOKE206),
6776 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6777 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6778 PPC_BOOKE, PPC2_BOOKE206),
6779 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
6780 PPC_440_SPEC),
6781 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6782 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6783 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6784 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6785 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6786 #if defined(TARGET_PPC64)
6787 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6788 PPC2_ISA300),
6789 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6790 #endif
6791
6792 #undef GEN_INT_ARITH_ADD
6793 #undef GEN_INT_ARITH_ADD_CONST
6794 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6795 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6796 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6797 add_ca, compute_ca, compute_ov) \
6798 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6799 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6800 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6801 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6802 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6803 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6804 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6805 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6806 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6807 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6808 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6809
6810 #undef GEN_INT_ARITH_DIVW
6811 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6812 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6813 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6814 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6815 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6816 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6817 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6818 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6819 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6820 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6821 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6822 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6823
6824 #if defined(TARGET_PPC64)
6825 #undef GEN_INT_ARITH_DIVD
6826 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6827 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6828 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6829 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6830 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6831 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6832
6833 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6834 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6835 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6836 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6837 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6838 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6839
6840 #undef GEN_INT_ARITH_MUL_HELPER
6841 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6842 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6843 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6844 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6845 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6846 #endif
6847
6848 #undef GEN_INT_ARITH_SUBF
6849 #undef GEN_INT_ARITH_SUBF_CONST
6850 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6851 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6852 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6853 add_ca, compute_ca, compute_ov) \
6854 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6855 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6856 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6857 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6858 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6859 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6860 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6861 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6862 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6863 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6864 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6865
6866 #undef GEN_LOGICAL1
6867 #undef GEN_LOGICAL2
6868 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6869 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6870 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6871 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6872 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6873 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6874 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6875 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6876 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6877 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6878 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6879 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6880 #if defined(TARGET_PPC64)
6881 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6882 #endif
6883
6884 #if defined(TARGET_PPC64)
6885 #undef GEN_PPC64_R2
6886 #undef GEN_PPC64_R4
6887 #define GEN_PPC64_R2(name, opc1, opc2) \
6888 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6889 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6890 PPC_64B)
6891 #define GEN_PPC64_R4(name, opc1, opc2) \
6892 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6893 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6894 PPC_64B), \
6895 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6896 PPC_64B), \
6897 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6898 PPC_64B)
6899 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6900 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6901 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6902 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6903 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6904 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6905 #endif
6906
6907 #undef GEN_LD
6908 #undef GEN_LDU
6909 #undef GEN_LDUX
6910 #undef GEN_LDX_E
6911 #undef GEN_LDS
6912 #define GEN_LD(name, ldop, opc, type) \
6913 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6914 #define GEN_LDU(name, ldop, opc, type) \
6915 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6916 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6917 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6918 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6919 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6920 #define GEN_LDS(name, ldop, op, type) \
6921 GEN_LD(name, ldop, op | 0x20, type) \
6922 GEN_LDU(name, ldop, op | 0x21, type) \
6923 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6924 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6925
6926 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6927 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6928 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6929 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6930 #if defined(TARGET_PPC64)
6931 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6932 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6933 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6934 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6935 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6936
6937 /* HV/P7 and later only */
6938 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6939 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6940 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6941 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6942 #endif
6943 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6944 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6945
6946 #undef GEN_ST
6947 #undef GEN_STU
6948 #undef GEN_STUX
6949 #undef GEN_STX_E
6950 #undef GEN_STS
6951 #define GEN_ST(name, stop, opc, type) \
6952 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6953 #define GEN_STU(name, stop, opc, type) \
6954 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6955 #define GEN_STUX(name, stop, opc2, opc3, type) \
6956 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6957 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6958 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6959 #define GEN_STS(name, stop, op, type) \
6960 GEN_ST(name, stop, op | 0x20, type) \
6961 GEN_STU(name, stop, op | 0x21, type) \
6962 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6963 GEN_STX(name, stop, 0x17, op | 0x00, type)
6964
6965 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6966 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6967 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6968 #if defined(TARGET_PPC64)
6969 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6970 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6971 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6972 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6973 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6974 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6975 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6976 #endif
6977 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6978 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6979
6980 #undef GEN_CRLOGIC
6981 #define GEN_CRLOGIC(name, tcg_op, opc) \
6982 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6983 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6984 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6985 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6986 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6987 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6988 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6989 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6990 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6991
6992 #undef GEN_MAC_HANDLER
6993 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6994 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6995 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6996 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6997 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6998 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6999 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7000 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7001 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7002 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7003 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7004 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7005 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7006 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7007 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7008 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7009 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7010 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7011 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7012 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7013 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7014 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7015 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7016 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7017 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7018 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7019 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7020 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7021 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7022 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7023 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7024 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7025 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7026 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7027 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7028 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7029 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7030 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7031 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7032 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7033 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7034 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7035 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7036 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7037
7038 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7039 PPC_NONE, PPC2_TM),
7040 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7041 PPC_NONE, PPC2_TM),
7042 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7043 PPC_NONE, PPC2_TM),
7044 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7045 PPC_NONE, PPC2_TM),
7046 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7047 PPC_NONE, PPC2_TM),
7048 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7049 PPC_NONE, PPC2_TM),
7050 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7051 PPC_NONE, PPC2_TM),
7052 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7053 PPC_NONE, PPC2_TM),
7054 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7055 PPC_NONE, PPC2_TM),
7056 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7057 PPC_NONE, PPC2_TM),
7058 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7059 PPC_NONE, PPC2_TM),
7060
7061 #include "translate/fp-ops.inc.c"
7062
7063 #include "translate/vmx-ops.inc.c"
7064
7065 #include "translate/vsx-ops.inc.c"
7066
7067 #include "translate/dfp-ops.inc.c"
7068
7069 #include "translate/spe-ops.inc.c"
7070 };
7071
7072 #include "helper_regs.h"
7073 #include "translate_init.inc.c"
7074
7075 /*****************************************************************************/
7076 /* Misc PowerPC helpers */
7077 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
7078 int flags)
7079 {
7080 #define RGPL 4
7081 #define RFPL 4
7082
7083 PowerPCCPU *cpu = POWERPC_CPU(cs);
7084 CPUPPCState *env = &cpu->env;
7085 int i;
7086
7087 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7088 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7089 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7090 cs->cpu_index);
7091 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7092 TARGET_FMT_lx " iidx %d didx %d\n",
7093 env->msr, env->spr[SPR_HID0],
7094 env->hflags, env->immu_idx, env->dmmu_idx);
7095 #if !defined(NO_TIMER_DUMP)
7096 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7097 #if !defined(CONFIG_USER_ONLY)
7098 " DECR %08" PRIu32
7099 #endif
7100 "\n",
7101 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7102 #if !defined(CONFIG_USER_ONLY)
7103 , cpu_ppc_load_decr(env)
7104 #endif
7105 );
7106 #endif
7107 for (i = 0; i < 32; i++) {
7108 if ((i & (RGPL - 1)) == 0)
7109 cpu_fprintf(f, "GPR%02d", i);
7110 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7111 if ((i & (RGPL - 1)) == (RGPL - 1))
7112 cpu_fprintf(f, "\n");
7113 }
7114 cpu_fprintf(f, "CR ");
7115 for (i = 0; i < 8; i++)
7116 cpu_fprintf(f, "%01x", env->crf[i]);
7117 cpu_fprintf(f, " [");
7118 for (i = 0; i < 8; i++) {
7119 char a = '-';
7120 if (env->crf[i] & 0x08)
7121 a = 'L';
7122 else if (env->crf[i] & 0x04)
7123 a = 'G';
7124 else if (env->crf[i] & 0x02)
7125 a = 'E';
7126 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7127 }
7128 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7129 env->reserve_addr);
7130
7131 if (flags & CPU_DUMP_FPU) {
7132 for (i = 0; i < 32; i++) {
7133 if ((i & (RFPL - 1)) == 0) {
7134 cpu_fprintf(f, "FPR%02d", i);
7135 }
7136 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7137 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7138 cpu_fprintf(f, "\n");
7139 }
7140 }
7141 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7142 }
7143
7144 #if !defined(CONFIG_USER_ONLY)
7145 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7146 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7147 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7148 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7149
7150 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7151 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7152 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7153 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7154
7155 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7156 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7157 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7158 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7159
7160 #if defined(TARGET_PPC64)
7161 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7162 env->excp_model == POWERPC_EXCP_POWER8) {
7163 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7164 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7165 }
7166 #endif
7167 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7168 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7169 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7170 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7171 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7172
7173 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7174 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7175 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7176 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7177
7178 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7179 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7180 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7181 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7182
7183 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7184 " EPR " TARGET_FMT_lx "\n",
7185 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7186 env->spr[SPR_BOOKE_EPR]);
7187
7188 /* FSL-specific */
7189 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7190 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7191 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7192 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7193
7194 /*
7195 * IVORs are left out as they are large and do not change often --
7196 * they can be read with "p $ivor0", "p $ivor1", etc.
7197 */
7198 }
7199
7200 #if defined(TARGET_PPC64)
7201 if (env->flags & POWERPC_FLAG_CFAR) {
7202 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7203 }
7204 #endif
7205
7206 if (env->spr_cb[SPR_LPCR].name)
7207 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7208
7209 switch (env->mmu_model) {
7210 case POWERPC_MMU_32B:
7211 case POWERPC_MMU_601:
7212 case POWERPC_MMU_SOFT_6xx:
7213 case POWERPC_MMU_SOFT_74xx:
7214 #if defined(TARGET_PPC64)
7215 case POWERPC_MMU_64B:
7216 case POWERPC_MMU_2_03:
7217 case POWERPC_MMU_2_06:
7218 case POWERPC_MMU_2_07:
7219 case POWERPC_MMU_3_00:
7220 #endif
7221 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7222 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7223 }
7224 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7225 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7226 }
7227 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7228 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7229 break;
7230 case POWERPC_MMU_BOOKE206:
7231 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7232 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7233 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7234 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7235
7236 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7237 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7238 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7239 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7240
7241 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7242 " TLB1CFG " TARGET_FMT_lx "\n",
7243 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7244 env->spr[SPR_BOOKE_TLB1CFG]);
7245 break;
7246 default:
7247 break;
7248 }
7249 #endif
7250
7251 #undef RGPL
7252 #undef RFPL
7253 }
7254
7255 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7256 fprintf_function cpu_fprintf, int flags)
7257 {
7258 #if defined(DO_PPC_STATISTICS)
7259 PowerPCCPU *cpu = POWERPC_CPU(cs);
7260 opc_handler_t **t1, **t2, **t3, *handler;
7261 int op1, op2, op3;
7262
7263 t1 = cpu->env.opcodes;
7264 for (op1 = 0; op1 < 64; op1++) {
7265 handler = t1[op1];
7266 if (is_indirect_opcode(handler)) {
7267 t2 = ind_table(handler);
7268 for (op2 = 0; op2 < 32; op2++) {
7269 handler = t2[op2];
7270 if (is_indirect_opcode(handler)) {
7271 t3 = ind_table(handler);
7272 for (op3 = 0; op3 < 32; op3++) {
7273 handler = t3[op3];
7274 if (handler->count == 0)
7275 continue;
7276 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7277 "%016" PRIx64 " %" PRId64 "\n",
7278 op1, op2, op3, op1, (op3 << 5) | op2,
7279 handler->oname,
7280 handler->count, handler->count);
7281 }
7282 } else {
7283 if (handler->count == 0)
7284 continue;
7285 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7286 "%016" PRIx64 " %" PRId64 "\n",
7287 op1, op2, op1, op2, handler->oname,
7288 handler->count, handler->count);
7289 }
7290 }
7291 } else {
7292 if (handler->count == 0)
7293 continue;
7294 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7295 " %" PRId64 "\n",
7296 op1, op1, handler->oname,
7297 handler->count, handler->count);
7298 }
7299 }
7300 #endif
7301 }
7302
7303 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7304 {
7305 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7306 CPUPPCState *env = cs->env_ptr;
7307 int bound;
7308
7309 ctx->exception = POWERPC_EXCP_NONE;
7310 ctx->spr_cb = env->spr_cb;
7311 ctx->pr = msr_pr;
7312 ctx->mem_idx = env->dmmu_idx;
7313 ctx->dr = msr_dr;
7314 #if !defined(CONFIG_USER_ONLY)
7315 ctx->hv = msr_hv || !env->has_hv_mode;
7316 #endif
7317 ctx->insns_flags = env->insns_flags;
7318 ctx->insns_flags2 = env->insns_flags2;
7319 ctx->access_type = -1;
7320 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7321 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7322 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7323 #if defined(TARGET_PPC64)
7324 ctx->sf_mode = msr_is_64bit(env, env->msr);
7325 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7326 #endif
7327 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7328 || env->mmu_model == POWERPC_MMU_601
7329 || (env->mmu_model & POWERPC_MMU_64B);
7330
7331 ctx->fpu_enabled = !!msr_fp;
7332 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7333 ctx->spe_enabled = !!msr_spe;
7334 else
7335 ctx->spe_enabled = false;
7336 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7337 ctx->altivec_enabled = !!msr_vr;
7338 else
7339 ctx->altivec_enabled = false;
7340 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7341 ctx->vsx_enabled = !!msr_vsx;
7342 } else {
7343 ctx->vsx_enabled = false;
7344 }
7345 #if defined(TARGET_PPC64)
7346 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7347 ctx->tm_enabled = !!msr_tm;
7348 } else {
7349 ctx->tm_enabled = false;
7350 }
7351 #endif
7352 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7353 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7354 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7355 else
7356 ctx->singlestep_enabled = 0;
7357 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7358 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7359 if (unlikely(ctx->base.singlestep_enabled)) {
7360 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7361 }
7362 #if defined (DO_SINGLE_STEP) && 0
7363 /* Single step trace mode */
7364 msr_se = 1;
7365 #endif
7366
7367 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7368 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7369 }
7370
7371 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7372 {
7373 }
7374
7375 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7376 {
7377 tcg_gen_insn_start(dcbase->pc_next);
7378 }
7379
7380 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7381 const CPUBreakpoint *bp)
7382 {
7383 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7384
7385 gen_debug_exception(ctx);
7386 /* The address covered by the breakpoint must be included in
7387 [tb->pc, tb->pc + tb->size) in order to for it to be
7388 properly cleared -- thus we increment the PC here so that
7389 the logic setting tb->size below does the right thing. */
7390 ctx->base.pc_next += 4;
7391 return true;
7392 }
7393
7394 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7395 {
7396 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7397 CPUPPCState *env = cs->env_ptr;
7398 opc_handler_t **table, *handler;
7399
7400 LOG_DISAS("----------------\n");
7401 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7402 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7403
7404 if (unlikely(need_byteswap(ctx))) {
7405 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7406 } else {
7407 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7408 }
7409 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7410 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7411 opc3(ctx->opcode), opc4(ctx->opcode),
7412 ctx->le_mode ? "little" : "big");
7413 ctx->base.pc_next += 4;
7414 table = env->opcodes;
7415 handler = table[opc1(ctx->opcode)];
7416 if (is_indirect_opcode(handler)) {
7417 table = ind_table(handler);
7418 handler = table[opc2(ctx->opcode)];
7419 if (is_indirect_opcode(handler)) {
7420 table = ind_table(handler);
7421 handler = table[opc3(ctx->opcode)];
7422 if (is_indirect_opcode(handler)) {
7423 table = ind_table(handler);
7424 handler = table[opc4(ctx->opcode)];
7425 }
7426 }
7427 }
7428 /* Is opcode *REALLY* valid ? */
7429 if (unlikely(handler->handler == &gen_invalid)) {
7430 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7431 "%02x - %02x - %02x - %02x (%08x) "
7432 TARGET_FMT_lx " %d\n",
7433 opc1(ctx->opcode), opc2(ctx->opcode),
7434 opc3(ctx->opcode), opc4(ctx->opcode),
7435 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7436 } else {
7437 uint32_t inval;
7438
7439 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7440 && Rc(ctx->opcode))) {
7441 inval = handler->inval2;
7442 } else {
7443 inval = handler->inval1;
7444 }
7445
7446 if (unlikely((ctx->opcode & inval) != 0)) {
7447 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7448 "%02x - %02x - %02x - %02x (%08x) "
7449 TARGET_FMT_lx "\n", ctx->opcode & inval,
7450 opc1(ctx->opcode), opc2(ctx->opcode),
7451 opc3(ctx->opcode), opc4(ctx->opcode),
7452 ctx->opcode, ctx->base.pc_next - 4);
7453 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7454 ctx->base.is_jmp = DISAS_NORETURN;
7455 return;
7456 }
7457 }
7458 (*(handler->handler))(ctx);
7459 #if defined(DO_PPC_STATISTICS)
7460 handler->count++;
7461 #endif
7462 /* Check trace mode exceptions */
7463 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7464 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7465 ctx->exception != POWERPC_SYSCALL &&
7466 ctx->exception != POWERPC_EXCP_TRAP &&
7467 ctx->exception != POWERPC_EXCP_BRANCH)) {
7468 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next);
7469 }
7470
7471 if (tcg_check_temp_count()) {
7472 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7473 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7474 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7475 }
7476
7477 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7478 DISAS_NEXT : DISAS_NORETURN;
7479 }
7480
7481 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7482 {
7483 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7484
7485 if (ctx->exception == POWERPC_EXCP_NONE) {
7486 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7487 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7488 if (unlikely(ctx->base.singlestep_enabled)) {
7489 gen_debug_exception(ctx);
7490 }
7491 /* Generate the return instruction */
7492 tcg_gen_exit_tb(NULL, 0);
7493 }
7494 }
7495
7496 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7497 {
7498 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7499 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7500 }
7501
7502 static const TranslatorOps ppc_tr_ops = {
7503 .init_disas_context = ppc_tr_init_disas_context,
7504 .tb_start = ppc_tr_tb_start,
7505 .insn_start = ppc_tr_insn_start,
7506 .breakpoint_check = ppc_tr_breakpoint_check,
7507 .translate_insn = ppc_tr_translate_insn,
7508 .tb_stop = ppc_tr_tb_stop,
7509 .disas_log = ppc_tr_disas_log,
7510 };
7511
7512 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7513 {
7514 DisasContext ctx;
7515
7516 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
7517 }
7518
7519 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7520 target_ulong *data)
7521 {
7522 env->nip = data[0];
7523 }
AR7 emulation for QEMU