hw/exynos4210_combiner.c

   1 /*
   2  * Samsung exynos4210 Interrupt Combiner
   3  *
   4  * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Evgeny Voevodin <e.voevodin@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17  * See the GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 /*
  24  * Exynos4210 Combiner represents an OR gate for SOC's IRQ lines. It combines
  25  * IRQ sources into groups and provides signal output to GIC from each group. It
  26  * is driven by common mask and enable/disable logic. Take a note that not all
  27  * IRQs are passed to GIC through Combiner.
  28  */
  29
  30 #include "sysbus.h"
  31
  32 #include "exynos4210.h"
  33
  34 //#define DEBUG_COMBINER
  35
  36 #ifdef DEBUG_COMBINER
  37 #define DPRINTF(fmt, ...) \
  38         do { fprintf(stdout, "COMBINER: [%s:%d] " fmt, __func__ , __LINE__, \
  39                 ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...) do {} while (0)
  42 #endif
  43
  44 #define    IIC_NGRP        64            /* Internal Interrupt Combiner
  45                                             Groups number */
  46 #define    IIC_NIRQ        (IIC_NGRP * 8)/* Internal Interrupt Combiner
  47                                             Interrupts number */
  48 #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
  49 #define IIC_REGSET_SIZE    0x41
  50
  51 /*
  52  * State for each output signal of internal combiner
  53  */
  54 typedef struct CombinerGroupState {
  55     uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
  56     uint8_t src_pending;        /* Pending source interrupts before masking */
  57 } CombinerGroupState;
  58
  59 typedef struct Exynos4210CombinerState {
  60     SysBusDevice busdev;
  61     MemoryRegion iomem;
  62
  63     struct CombinerGroupState group[IIC_NGRP];
  64     uint32_t reg_set[IIC_REGSET_SIZE];
  65     uint32_t icipsr[2];
  66     uint32_t external;          /* 1 means that this combiner is external */
  67
  68     qemu_irq output_irq[IIC_NGRP];
  69 } Exynos4210CombinerState;
  70
  71 static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
  72     .name = "exynos4210.combiner.groupstate",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .minimum_version_id_old = 1,
  76     .fields = (VMStateField[]) {
  77         VMSTATE_UINT8(src_mask, CombinerGroupState),
  78         VMSTATE_UINT8(src_pending, CombinerGroupState),
  79         VMSTATE_END_OF_LIST()
  80     }
  81 };
  82
  83 static const VMStateDescription vmstate_exynos4210_combiner = {
  84     .name = "exynos4210.combiner",
  85     .version_id = 1,
  86     .minimum_version_id = 1,
  87     .minimum_version_id_old = 1,
  88     .fields = (VMStateField[]) {
  89         VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
  90                 vmstate_exynos4210_combiner_group_state, CombinerGroupState),
  91         VMSTATE_UINT32_ARRAY(reg_set, Exynos4210CombinerState,
  92                 IIC_REGSET_SIZE),
  93         VMSTATE_UINT32_ARRAY(icipsr, Exynos4210CombinerState, 2),
  94         VMSTATE_UINT32(external, Exynos4210CombinerState),
  95         VMSTATE_END_OF_LIST()
  96     }
  97 };
  98
  99 /*
 100  * Get Combiner input GPIO into irqs structure
 101  */
 102 void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
 103         int ext)
 104 {
 105     int n;
 106     int bit;
 107     int max;
 108     qemu_irq *irq;
 109
 110     max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
 111         EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
 112     irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
 113
 114     /*
 115      * Some IRQs of Int/External Combiner are going to two Combiners groups,
 116      * so let split them.
 117      */
 118     for (n = 0; n < max; n++) {
 119
 120         bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
 121
 122         switch (n) {
 123         /* MDNIE_LCD1 INTG1 */
 124         case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
 125              EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
 126             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 127                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
 128             continue;
 129
 130         /* TMU INTG3 */
 131         case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
 132             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 133                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
 134             continue;
 135
 136         /* LCD1 INTG12 */
 137         case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
 138              EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
 139             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 140                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
 141             continue;
 142
 143         /* Multi-Core Timer INTG12 */
 144         case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
 145              EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
 146                irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 147                        irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 148             continue;
 149
 150         /* Multi-Core Timer INTG35 */
 151         case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
 152              EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
 153             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 154                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 155             continue;
 156
 157         /* Multi-Core Timer INTG51 */
 158         case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
 159              EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
 160             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 161                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 162             continue;
 163
 164         /* Multi-Core Timer INTG53 */
 165         case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
 166              EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
 167             irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 168                     irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 169             continue;
 170         }
 171
 172         irq[n] = qdev_get_gpio_in(dev, n);
 173     }
 174 }
 175
 176 static uint64_t
 177 exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
 178 {
 179     struct Exynos4210CombinerState *s =
 180             (struct Exynos4210CombinerState *)opaque;
 181     uint32_t req_quad_base_n;    /* Base of registers quad. Multiply it by 4 and
 182                                    get a start of corresponding group quad */
 183     uint32_t grp_quad_base_n;    /* Base of group quad */
 184     uint32_t reg_n;              /* Register number inside the quad */
 185     uint32_t val;
 186
 187     if (s->external && (offset > 0x3c && offset != 0x100)) {
 188         hw_error("exynos4210.combiner: unallowed read access at offset 0x"
 189                 TARGET_FMT_plx "\n", offset);
 190     }
 191
 192     req_quad_base_n = offset >> 4;
 193     grp_quad_base_n = req_quad_base_n << 2;
 194     reg_n = (offset - (req_quad_base_n << 4)) >> 2;
 195
 196     if (req_quad_base_n >= IIC_NGRP) {
 197         /* Read of ICIPSR register */
 198         return s->icipsr[reg_n];
 199     }
 200
 201     val = 0;
 202
 203     switch (reg_n) {
 204     /* IISTR */
 205     case 2:
 206         val |= s->group[grp_quad_base_n].src_pending;
 207         val |= s->group[grp_quad_base_n + 1].src_pending << 8;
 208         val |= s->group[grp_quad_base_n + 2].src_pending << 16;
 209         val |= s->group[grp_quad_base_n + 3].src_pending << 24;
 210         break;
 211     /* IIMSR */
 212     case 3:
 213         val |= s->group[grp_quad_base_n].src_mask &
 214         s->group[grp_quad_base_n].src_pending;
 215         val |= (s->group[grp_quad_base_n + 1].src_mask &
 216                 s->group[grp_quad_base_n + 1].src_pending) << 8;
 217         val |= (s->group[grp_quad_base_n + 2].src_mask &
 218                 s->group[grp_quad_base_n + 2].src_pending) << 16;
 219         val |= (s->group[grp_quad_base_n + 3].src_mask &
 220                 s->group[grp_quad_base_n + 3].src_pending) << 24;
 221         break;
 222     default:
 223         if (offset >> 2 >= IIC_REGSET_SIZE) {
 224             hw_error("exynos4210.combiner: overflow of reg_set by 0x"
 225                     TARGET_FMT_plx "offset\n", offset);
 226         }
 227         val = s->reg_set[offset >> 2];
 228         return 0;
 229     }
 230     return val;
 231 }
 232
 233 static void exynos4210_combiner_update(void *opaque, uint8_t group_n)
 234 {
 235     struct Exynos4210CombinerState *s =
 236             (struct Exynos4210CombinerState *)opaque;
 237
 238     /* Send interrupt if needed */
 239     if (s->group[group_n].src_mask & s->group[group_n].src_pending) {
 240 #ifdef DEBUG_COMBINER
 241         if (group_n != 26) {
 242             /* skip uart */
 243             DPRINTF("%s raise IRQ[%d]\n", s->external ? "EXT" : "INT", group_n);
 244         }
 245 #endif
 246
 247         /* Set Combiner interrupt pending status after masking */
 248         if (group_n >= 32) {
 249             s->icipsr[1] |= 1 << (group_n - 32);
 250         } else {
 251             s->icipsr[0] |= 1 << group_n;
 252         }
 253
 254         qemu_irq_raise(s->output_irq[group_n]);
 255     } else {
 256 #ifdef DEBUG_COMBINER
 257         if (group_n != 26) {
 258             /* skip uart */
 259             DPRINTF("%s lower IRQ[%d]\n", s->external ? "EXT" : "INT", group_n);
 260         }
 261 #endif
 262
 263         /* Set Combiner interrupt pending status after masking */
 264         if (group_n >= 32) {
 265             s->icipsr[1] &= ~(1 << (group_n - 32));
 266         } else {
 267             s->icipsr[0] &= ~(1 << group_n);
 268         }
 269
 270         qemu_irq_lower(s->output_irq[group_n]);
 271     }
 272 }
 273
 274 static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
 275         uint64_t val, unsigned size)
 276 {
 277     struct Exynos4210CombinerState *s =
 278             (struct Exynos4210CombinerState *)opaque;
 279     uint32_t req_quad_base_n;    /* Base of registers quad. Multiply it by 4 and
 280                                    get a start of corresponding group quad */
 281     uint32_t grp_quad_base_n;    /* Base of group quad */
 282     uint32_t reg_n;              /* Register number inside the quad */
 283
 284     if (s->external && (offset > 0x3c && offset != 0x100)) {
 285         hw_error("exynos4210.combiner: unallowed write access at offset 0x"
 286                 TARGET_FMT_plx "\n", offset);
 287     }
 288
 289     req_quad_base_n = offset >> 4;
 290     grp_quad_base_n = req_quad_base_n << 2;
 291     reg_n = (offset - (req_quad_base_n << 4)) >> 2;
 292
 293     if (req_quad_base_n >= IIC_NGRP) {
 294         hw_error("exynos4210.combiner: unallowed write access at offset 0x"
 295                 TARGET_FMT_plx "\n", offset);
 296         return;
 297     }
 298
 299     if (reg_n > 1) {
 300         hw_error("exynos4210.combiner: unallowed write access at offset 0x"
 301                 TARGET_FMT_plx "\n", offset);
 302         return;
 303     }
 304
 305     if (offset >> 2 >= IIC_REGSET_SIZE) {
 306         hw_error("exynos4210.combiner: overflow of reg_set by 0x"
 307                 TARGET_FMT_plx "offset\n", offset);
 308     }
 309     s->reg_set[offset >> 2] = val;
 310
 311     switch (reg_n) {
 312     /* IIESR */
 313     case 0:
 314         /* FIXME: what if irq is pending, allowed by mask, and we allow it
 315          * again. Interrupt will rise again! */
 316
 317         DPRINTF("%s enable IRQ for groups %d, %d, %d, %d\n",
 318                 s->external ? "EXT" : "INT",
 319                 grp_quad_base_n,
 320                 grp_quad_base_n + 1,
 321                 grp_quad_base_n + 2,
 322                 grp_quad_base_n + 3);
 323
 324         /* Enable interrupt sources */
 325         s->group[grp_quad_base_n].src_mask |= val & 0xFF;
 326         s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8;
 327         s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16;
 328         s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24;
 329
 330         exynos4210_combiner_update(s, grp_quad_base_n);
 331         exynos4210_combiner_update(s, grp_quad_base_n + 1);
 332         exynos4210_combiner_update(s, grp_quad_base_n + 2);
 333         exynos4210_combiner_update(s, grp_quad_base_n + 3);
 334         break;
 335         /* IIECR */
 336     case 1:
 337         DPRINTF("%s disable IRQ for groups %d, %d, %d, %d\n",
 338                 s->external ? "EXT" : "INT",
 339                 grp_quad_base_n,
 340                 grp_quad_base_n + 1,
 341                 grp_quad_base_n + 2,
 342                 grp_quad_base_n + 3);
 343
 344         /* Disable interrupt sources */
 345         s->group[grp_quad_base_n].src_mask &= ~(val & 0xFF);
 346         s->group[grp_quad_base_n + 1].src_mask &= ~((val & 0xFF00) >> 8);
 347         s->group[grp_quad_base_n + 2].src_mask &= ~((val & 0xFF0000) >> 16);
 348         s->group[grp_quad_base_n + 3].src_mask &= ~((val & 0xFF000000) >> 24);
 349
 350         exynos4210_combiner_update(s, grp_quad_base_n);
 351         exynos4210_combiner_update(s, grp_quad_base_n + 1);
 352         exynos4210_combiner_update(s, grp_quad_base_n + 2);
 353         exynos4210_combiner_update(s, grp_quad_base_n + 3);
 354         break;
 355     default:
 356         hw_error("exynos4210.combiner: unallowed write access at offset 0x"
 357                 TARGET_FMT_plx "\n", offset);
 358         break;
 359     }
 360
 361     return;
 362 }
 363
 364 /* Get combiner group and bit from irq number */
 365 static uint8_t get_combiner_group_and_bit(int irq, uint8_t *bit)
 366 {
 367     *bit = irq - ((irq >> 3) << 3);
 368     return irq >> 3;
 369 }
 370
 371 /* Process a change in an external IRQ input.  */
 372 static void exynos4210_combiner_handler(void *opaque, int irq, int level)
 373 {
 374     struct Exynos4210CombinerState *s =
 375             (struct Exynos4210CombinerState *)opaque;
 376     uint8_t bit_n, group_n;
 377
 378     group_n = get_combiner_group_and_bit(irq, &bit_n);
 379
 380     if (s->external && group_n >= EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ) {
 381         DPRINTF("%s unallowed IRQ group 0x%x\n", s->external ? "EXT" : "INT"
 382                 , group_n);
 383         return;
 384     }
 385
 386     if (level) {
 387         s->group[group_n].src_pending |= 1 << bit_n;
 388     } else {
 389         s->group[group_n].src_pending &= ~(1 << bit_n);
 390     }
 391
 392     exynos4210_combiner_update(s, group_n);
 393
 394     return;
 395 }
 396
 397 static void exynos4210_combiner_reset(DeviceState *d)
 398 {
 399     struct Exynos4210CombinerState *s = (struct Exynos4210CombinerState *)d;
 400
 401     memset(&s->group, 0, sizeof(s->group));
 402     memset(&s->reg_set, 0, sizeof(s->reg_set));
 403
 404     s->reg_set[0xC0 >> 2] = 0x01010101;
 405     s->reg_set[0xC4 >> 2] = 0x01010101;
 406     s->reg_set[0xD0 >> 2] = 0x01010101;
 407     s->reg_set[0xD4 >> 2] = 0x01010101;
 408 }
 409
 410 static const MemoryRegionOps exynos4210_combiner_ops = {
 411     .read = exynos4210_combiner_read,
 412     .write = exynos4210_combiner_write,
 413     .endianness = DEVICE_NATIVE_ENDIAN,
 414 };
 415
 416 /*
 417  * Internal Combiner initialization.
 418  */
 419 static int exynos4210_combiner_init(SysBusDevice *dev)
 420 {
 421     unsigned int i;
 422     struct Exynos4210CombinerState *s =
 423             FROM_SYSBUS(struct Exynos4210CombinerState, dev);
 424
 425     /* Allocate general purpose input signals and connect a handler to each of
 426      * them */
 427     qdev_init_gpio_in(&s->busdev.qdev, exynos4210_combiner_handler, IIC_NIRQ);
 428
 429     /* Connect SysBusDev irqs to device specific irqs */
 430     for (i = 0; i < IIC_NIRQ; i++) {
 431         sysbus_init_irq(dev, &s->output_irq[i]);
 432     }
 433
 434     memory_region_init_io(&s->iomem, &exynos4210_combiner_ops, s,
 435             "exynos4210-combiner", IIC_REGION_SIZE);
 436     sysbus_init_mmio(dev, &s->iomem);
 437
 438     return 0;
 439 }
 440
 441 static Property exynos4210_combiner_properties[] = {
 442     DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0),
 443     DEFINE_PROP_END_OF_LIST(),
 444 };
 445
 446 static void exynos4210_combiner_class_init(ObjectClass *klass, void *data)
 447 {
 448     DeviceClass *dc = DEVICE_CLASS(klass);
 449     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 450
 451     k->init = exynos4210_combiner_init;
 452     dc->reset = exynos4210_combiner_reset;
 453     dc->props = exynos4210_combiner_properties;
 454     dc->vmsd = &vmstate_exynos4210_combiner;
 455 }
 456
 457 static TypeInfo exynos4210_combiner_info = {
 458     .name          = "exynos4210.combiner",
 459     .parent        = TYPE_SYS_BUS_DEVICE,
 460     .instance_size = sizeof(Exynos4210CombinerState),
 461     .class_init    = exynos4210_combiner_class_init,
 462 };
 463
 464 static void exynos4210_combiner_register_types(void)
 465 {
 466     type_register_static(&exynos4210_combiner_info);
 467 }
 468
 469 type_init(exynos4210_combiner_register_types)