hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/arm/arm.h"
  26 #include "hw/arm/primecell.h"
  27 #include "hw/devices.h"
  28 #include "net/net.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "hw/loader.h"
  32 #include "exec/address-spaces.h"
  33 #include "sysemu/block-backend.h"
  34 #include "hw/block/flash.h"
  35 #include "sysemu/device_tree.h"
  36 #include "qemu/error-report.h"
  37 #include <libfdt.h>
  38
  39 #define VEXPRESS_BOARD_ID 0x8e0
  40 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  41 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  42
  43 /* Number of virtio transports to create (0..8; limited by
  44  * number of available IRQ lines).
  45  */
  46 #define NUM_VIRTIO_TRANSPORTS 4
  47
  48 /* Address maps for peripherals:
  49  * the Versatile Express motherboard has two possible maps,
  50  * the "legacy" one (used for A9) and the "Cortex-A Series"
  51  * map (used for newer cores).
  52  * Individual daughterboards can also have different maps for
  53  * their peripherals.
  54  */
  55
  56 enum {
  57     VE_SYSREGS,
  58     VE_SP810,
  59     VE_SERIALPCI,
  60     VE_PL041,
  61     VE_MMCI,
  62     VE_KMI0,
  63     VE_KMI1,
  64     VE_UART0,
  65     VE_UART1,
  66     VE_UART2,
  67     VE_UART3,
  68     VE_WDT,
  69     VE_TIMER01,
  70     VE_TIMER23,
  71     VE_SERIALDVI,
  72     VE_RTC,
  73     VE_COMPACTFLASH,
  74     VE_CLCD,
  75     VE_NORFLASH0,
  76     VE_NORFLASH1,
  77     VE_NORFLASHALIAS,
  78     VE_SRAM,
  79     VE_VIDEORAM,
  80     VE_ETHERNET,
  81     VE_USB,
  82     VE_DAPROM,
  83     VE_VIRTIO,
  84 };
  85
  86 static hwaddr motherboard_legacy_map[] = {
  87     [VE_NORFLASHALIAS] = 0,
  88     /* CS7: 0x10000000 .. 0x10020000 */
  89     [VE_SYSREGS] = 0x10000000,
  90     [VE_SP810] = 0x10001000,
  91     [VE_SERIALPCI] = 0x10002000,
  92     [VE_PL041] = 0x10004000,
  93     [VE_MMCI] = 0x10005000,
  94     [VE_KMI0] = 0x10006000,
  95     [VE_KMI1] = 0x10007000,
  96     [VE_UART0] = 0x10009000,
  97     [VE_UART1] = 0x1000a000,
  98     [VE_UART2] = 0x1000b000,
  99     [VE_UART3] = 0x1000c000,
 100     [VE_WDT] = 0x1000f000,
 101     [VE_TIMER01] = 0x10011000,
 102     [VE_TIMER23] = 0x10012000,
 103     [VE_VIRTIO] = 0x10013000,
 104     [VE_SERIALDVI] = 0x10016000,
 105     [VE_RTC] = 0x10017000,
 106     [VE_COMPACTFLASH] = 0x1001a000,
 107     [VE_CLCD] = 0x1001f000,
 108     /* CS0: 0x40000000 .. 0x44000000 */
 109     [VE_NORFLASH0] = 0x40000000,
 110     /* CS1: 0x44000000 .. 0x48000000 */
 111     [VE_NORFLASH1] = 0x44000000,
 112     /* CS2: 0x48000000 .. 0x4a000000 */
 113     [VE_SRAM] = 0x48000000,
 114     /* CS3: 0x4c000000 .. 0x50000000 */
 115     [VE_VIDEORAM] = 0x4c000000,
 116     [VE_ETHERNET] = 0x4e000000,
 117     [VE_USB] = 0x4f000000,
 118 };
 119
 120 static hwaddr motherboard_aseries_map[] = {
 121     [VE_NORFLASHALIAS] = 0,
 122     /* CS0: 0x08000000 .. 0x0c000000 */
 123     [VE_NORFLASH0] = 0x08000000,
 124     /* CS4: 0x0c000000 .. 0x10000000 */
 125     [VE_NORFLASH1] = 0x0c000000,
 126     /* CS5: 0x10000000 .. 0x14000000 */
 127     /* CS1: 0x14000000 .. 0x18000000 */
 128     [VE_SRAM] = 0x14000000,
 129     /* CS2: 0x18000000 .. 0x1c000000 */
 130     [VE_VIDEORAM] = 0x18000000,
 131     [VE_ETHERNET] = 0x1a000000,
 132     [VE_USB] = 0x1b000000,
 133     /* CS3: 0x1c000000 .. 0x20000000 */
 134     [VE_DAPROM] = 0x1c000000,
 135     [VE_SYSREGS] = 0x1c010000,
 136     [VE_SP810] = 0x1c020000,
 137     [VE_SERIALPCI] = 0x1c030000,
 138     [VE_PL041] = 0x1c040000,
 139     [VE_MMCI] = 0x1c050000,
 140     [VE_KMI0] = 0x1c060000,
 141     [VE_KMI1] = 0x1c070000,
 142     [VE_UART0] = 0x1c090000,
 143     [VE_UART1] = 0x1c0a0000,
 144     [VE_UART2] = 0x1c0b0000,
 145     [VE_UART3] = 0x1c0c0000,
 146     [VE_WDT] = 0x1c0f0000,
 147     [VE_TIMER01] = 0x1c110000,
 148     [VE_TIMER23] = 0x1c120000,
 149     [VE_VIRTIO] = 0x1c130000,
 150     [VE_SERIALDVI] = 0x1c160000,
 151     [VE_RTC] = 0x1c170000,
 152     [VE_COMPACTFLASH] = 0x1c1a0000,
 153     [VE_CLCD] = 0x1c1f0000,
 154 };
 155
 156 /* Structure defining the peculiarities of a specific daughterboard */
 157
 158 typedef struct VEDBoardInfo VEDBoardInfo;
 159
 160 typedef struct {
 161     MachineClass parent;
 162     VEDBoardInfo *daughterboard;
 163 } VexpressMachineClass;
 164
 165 typedef struct {
 166     MachineState parent;
 167     bool secure;
 168 } VexpressMachineState;
 169
 170 #define TYPE_VEXPRESS_MACHINE   "vexpress"
 171 #define TYPE_VEXPRESS_A9_MACHINE   "vexpress-a9"
 172 #define TYPE_VEXPRESS_A15_MACHINE   "vexpress-a15"
 173 #define VEXPRESS_MACHINE(obj) \
 174     OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
 175 #define VEXPRESS_MACHINE_GET_CLASS(obj) \
 176     OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
 177 #define VEXPRESS_MACHINE_CLASS(klass) \
 178     OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
 179
 180 typedef void DBoardInitFn(const VexpressMachineState *machine,
 181                           ram_addr_t ram_size,
 182                           const char *cpu_model,
 183                           qemu_irq *pic);
 184
 185 struct VEDBoardInfo {
 186     struct arm_boot_info bootinfo;
 187     const hwaddr *motherboard_map;
 188     hwaddr loader_start;
 189     const hwaddr gic_cpu_if_addr;
 190     uint32_t proc_id;
 191     uint32_t num_voltage_sensors;
 192     const uint32_t *voltages;
 193     uint32_t num_clocks;
 194     const uint32_t *clocks;
 195     DBoardInitFn *init;
 196 };
 197
 198 static void init_cpus(const char *cpu_model, const char *privdev,
 199                       hwaddr periphbase, qemu_irq *pic, bool secure)
 200 {
 201     ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 202     DeviceState *dev;
 203     SysBusDevice *busdev;
 204     int n;
 205
 206     if (!cpu_oc) {
 207         fprintf(stderr, "Unable to find CPU definition\n");
 208         exit(1);
 209     }
 210
 211     /* Create the actual CPUs */
 212     for (n = 0; n < smp_cpus; n++) {
 213         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 214         Error *err = NULL;
 215
 216         if (!secure) {
 217             object_property_set_bool(cpuobj, false, "has_el3", NULL);
 218         }
 219
 220         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 221             object_property_set_int(cpuobj, periphbase,
 222                                     "reset-cbar", &error_abort);
 223         }
 224         object_property_set_bool(cpuobj, true, "realized", &err);
 225         if (err) {
 226             error_report_err(err);
 227             exit(1);
 228         }
 229     }
 230
 231     /* Create the private peripheral devices (including the GIC);
 232      * this must happen after the CPUs are created because a15mpcore_priv
 233      * wires itself up to the CPU's generic_timer gpio out lines.
 234      */
 235     dev = qdev_create(NULL, privdev);
 236     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 237     qdev_init_nofail(dev);
 238     busdev = SYS_BUS_DEVICE(dev);
 239     sysbus_mmio_map(busdev, 0, periphbase);
 240
 241     /* Interrupts [42:0] are from the motherboard;
 242      * [47:43] are reserved; [63:48] are daughterboard
 243      * peripherals. Note that some documentation numbers
 244      * external interrupts starting from 32 (because there
 245      * are internal interrupts 0..31).
 246      */
 247     for (n = 0; n < 64; n++) {
 248         pic[n] = qdev_get_gpio_in(dev, n);
 249     }
 250
 251     /* Connect the CPUs to the GIC */
 252     for (n = 0; n < smp_cpus; n++) {
 253         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 254
 255         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 256     }
 257 }
 258
 259 static void a9_daughterboard_init(const VexpressMachineState *vms,
 260                                   ram_addr_t ram_size,
 261                                   const char *cpu_model,
 262                                   qemu_irq *pic)
 263 {
 264     MemoryRegion *sysmem = get_system_memory();
 265     MemoryRegion *ram = g_new(MemoryRegion, 1);
 266     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 267     ram_addr_t low_ram_size;
 268
 269     if (!cpu_model) {
 270         cpu_model = "cortex-a9";
 271     }
 272
 273     if (ram_size > 0x40000000) {
 274         /* 1GB is the maximum the address space permits */
 275         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 276         exit(1);
 277     }
 278
 279     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size,
 280                            &error_abort);
 281     vmstate_register_ram_global(ram);
 282     low_ram_size = ram_size;
 283     if (low_ram_size > 0x4000000) {
 284         low_ram_size = 0x4000000;
 285     }
 286     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 287      * address space should in theory be remappable to various
 288      * things including ROM or RAM; we always map the RAM there.
 289      */
 290     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 291     memory_region_add_subregion(sysmem, 0x0, lowram);
 292     memory_region_add_subregion(sysmem, 0x60000000, ram);
 293
 294     /* 0x1e000000 A9MPCore (SCU) private memory region */
 295     init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure);
 296
 297     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 298
 299     /* 0x10020000 PL111 CLCD (daughterboard) */
 300     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 301
 302     /* 0x10060000 AXI RAM */
 303     /* 0x100e0000 PL341 Dynamic Memory Controller */
 304     /* 0x100e1000 PL354 Static Memory Controller */
 305     /* 0x100e2000 System Configuration Controller */
 306
 307     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 308     /* 0x100e5000 SP805 Watchdog module */
 309     /* 0x100e6000 BP147 TrustZone Protection Controller */
 310     /* 0x100e9000 PL301 'Fast' AXI matrix */
 311     /* 0x100ea000 PL301 'Slow' AXI matrix */
 312     /* 0x100ec000 TrustZone Address Space Controller */
 313     /* 0x10200000 CoreSight debug APB */
 314     /* 0x1e00a000 PL310 L2 Cache Controller */
 315     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 316 }
 317
 318 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 319  * values are in microvolts.
 320  */
 321 static const uint32_t a9_voltages[] = {
 322     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 323     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 324     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 325     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 326     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 327     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 328 };
 329
 330 /* Reset values for daughterboard oscillators (in Hz) */
 331 static const uint32_t a9_clocks[] = {
 332     45000000, /* AMBA AXI ACLK: 45MHz */
 333     23750000, /* daughterboard CLCD clock: 23.75MHz */
 334     66670000, /* Test chip reference clock: 66.67MHz */
 335 };
 336
 337 static VEDBoardInfo a9_daughterboard = {
 338     .motherboard_map = motherboard_legacy_map,
 339     .loader_start = 0x60000000,
 340     .gic_cpu_if_addr = 0x1e000100,
 341     .proc_id = 0x0c000191,
 342     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 343     .voltages = a9_voltages,
 344     .num_clocks = ARRAY_SIZE(a9_clocks),
 345     .clocks = a9_clocks,
 346     .init = a9_daughterboard_init,
 347 };
 348
 349 static void a15_daughterboard_init(const VexpressMachineState *vms,
 350                                    ram_addr_t ram_size,
 351                                    const char *cpu_model,
 352                                    qemu_irq *pic)
 353 {
 354     MemoryRegion *sysmem = get_system_memory();
 355     MemoryRegion *ram = g_new(MemoryRegion, 1);
 356     MemoryRegion *sram = g_new(MemoryRegion, 1);
 357
 358     if (!cpu_model) {
 359         cpu_model = "cortex-a15";
 360     }
 361
 362     {
 363         /* We have to use a separate 64 bit variable here to avoid the gcc
 364          * "comparison is always false due to limited range of data type"
 365          * warning if we are on a host where ram_addr_t is 32 bits.
 366          */
 367         uint64_t rsz = ram_size;
 368         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 369             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 370             exit(1);
 371         }
 372     }
 373
 374     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size,
 375                            &error_abort);
 376     vmstate_register_ram_global(ram);
 377     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 378     memory_region_add_subregion(sysmem, 0x80000000, ram);
 379
 380     /* 0x2c000000 A15MPCore private memory region (GIC) */
 381     init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure);
 382
 383     /* A15 daughterboard peripherals: */
 384
 385     /* 0x20000000: CoreSight interfaces: not modelled */
 386     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 387     /* 0x2a420000: SCC: not modelled */
 388     /* 0x2a430000: system counter: not modelled */
 389     /* 0x2b000000: HDLCD controller: not modelled */
 390     /* 0x2b060000: SP805 watchdog: not modelled */
 391     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 392     /* 0x2e000000: system SRAM */
 393     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
 394                            &error_abort);
 395     vmstate_register_ram_global(sram);
 396     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 397
 398     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 399     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 400 }
 401
 402 static const uint32_t a15_voltages[] = {
 403     900000, /* Vcore: 0.9V : CPU core voltage */
 404 };
 405
 406 static const uint32_t a15_clocks[] = {
 407     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 408     0, /* OSCCLK1: reserved */
 409     0, /* OSCCLK2: reserved */
 410     0, /* OSCCLK3: reserved */
 411     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 412     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 413     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 414     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 415     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 416 };
 417
 418 static VEDBoardInfo a15_daughterboard = {
 419     .motherboard_map = motherboard_aseries_map,
 420     .loader_start = 0x80000000,
 421     .gic_cpu_if_addr = 0x2c002000,
 422     .proc_id = 0x14000237,
 423     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 424     .voltages = a15_voltages,
 425     .num_clocks = ARRAY_SIZE(a15_clocks),
 426     .clocks = a15_clocks,
 427     .init = a15_daughterboard_init,
 428 };
 429
 430 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 431                                 hwaddr addr, hwaddr size, uint32_t intc,
 432                                 int irq)
 433 {
 434     /* Add a virtio_mmio node to the device tree blob:
 435      *   virtio_mmio@ADDRESS {
 436      *       compatible = "virtio,mmio";
 437      *       reg = <ADDRESS, SIZE>;
 438      *       interrupt-parent = <&intc>;
 439      *       interrupts = <0, irq, 1>;
 440      *   }
 441      * (Note that the format of the interrupts property is dependent on the
 442      * interrupt controller that interrupt-parent points to; these are for
 443      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 444      */
 445     int rc;
 446     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 447
 448     rc = qemu_fdt_add_subnode(fdt, nodename);
 449     rc |= qemu_fdt_setprop_string(fdt, nodename,
 450                                   "compatible", "virtio,mmio");
 451     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 452                                        acells, addr, scells, size);
 453     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 454     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 455     g_free(nodename);
 456     if (rc) {
 457         return -1;
 458     }
 459     return 0;
 460 }
 461
 462 static uint32_t find_int_controller(void *fdt)
 463 {
 464     /* Find the FDT node corresponding to the interrupt controller
 465      * for virtio-mmio devices. We do this by scanning the fdt for
 466      * a node with the right compatibility, since we know there is
 467      * only one GIC on a vexpress board.
 468      * We return the phandle of the node, or 0 if none was found.
 469      */
 470     const char *compat = "arm,cortex-a9-gic";
 471     int offset;
 472
 473     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 474     if (offset >= 0) {
 475         return fdt_get_phandle(fdt, offset);
 476     }
 477     return 0;
 478 }
 479
 480 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 481 {
 482     uint32_t acells, scells, intc;
 483     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 484
 485     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells");
 486     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells");
 487     intc = find_int_controller(fdt);
 488     if (!intc) {
 489         /* Not fatal, we just won't provide virtio. This will
 490          * happen with older device tree blobs.
 491          */
 492         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 493                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 494     } else {
 495         int i;
 496         const hwaddr *map = daughterboard->motherboard_map;
 497
 498         /* We iterate backwards here because adding nodes
 499          * to the dtb puts them in last-first.
 500          */
 501         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 502             add_virtio_mmio_node(fdt, acells, scells,
 503                                  map[VE_VIRTIO] + 0x200 * i,
 504                                  0x200, intc, 40 + i);
 505         }
 506     }
 507 }
 508
 509
 510 /* Open code a private version of pflash registration since we
 511  * need to set non-default device width for VExpress platform.
 512  */
 513 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 514                                           DriveInfo *di)
 515 {
 516     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 517
 518     if (di && qdev_prop_set_drive(dev, "drive",
 519                                   blk_by_legacy_dinfo(di))) {
 520         abort();
 521     }
 522
 523     qdev_prop_set_uint32(dev, "num-blocks",
 524                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 525     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 526     qdev_prop_set_uint8(dev, "width", 4);
 527     qdev_prop_set_uint8(dev, "device-width", 2);
 528     qdev_prop_set_uint8(dev, "big-endian", 0);
 529     qdev_prop_set_uint16(dev, "id0", 0x89);
 530     qdev_prop_set_uint16(dev, "id1", 0x18);
 531     qdev_prop_set_uint16(dev, "id2", 0x00);
 532     qdev_prop_set_uint16(dev, "id3", 0x00);
 533     qdev_prop_set_string(dev, "name", name);
 534     qdev_init_nofail(dev);
 535
 536     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 537     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 538 }
 539
 540 static void vexpress_common_init(MachineState *machine)
 541 {
 542     VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
 543     VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
 544     VEDBoardInfo *daughterboard = vmc->daughterboard;;
 545     DeviceState *dev, *sysctl, *pl041;
 546     qemu_irq pic[64];
 547     uint32_t sys_id;
 548     DriveInfo *dinfo;
 549     pflash_t *pflash0;
 550     ram_addr_t vram_size, sram_size;
 551     MemoryRegion *sysmem = get_system_memory();
 552     MemoryRegion *vram = g_new(MemoryRegion, 1);
 553     MemoryRegion *sram = g_new(MemoryRegion, 1);
 554     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 555     MemoryRegion *flash0mem;
 556     const hwaddr *map = daughterboard->motherboard_map;
 557     int i;
 558
 559     daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
 560
 561     /*
 562      * If a bios file was provided, attempt to map it into memory
 563      */
 564     if (bios_name) {
 565         const char *fn;
 566
 567         if (drive_get(IF_PFLASH, 0, 0)) {
 568             error_report("The contents of the first flash device may be "
 569                          "specified with -bios or with -drive if=pflash... "
 570                          "but you cannot use both options at once");
 571             exit(1);
 572         }
 573         fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 574         if (!fn || load_image_targphys(fn, map[VE_NORFLASH0],
 575                                        VEXPRESS_FLASH_SIZE) < 0) {
 576             error_report("Could not load ROM image '%s'", bios_name);
 577             exit(1);
 578         }
 579     }
 580
 581     /* Motherboard peripherals: the wiring is the same but the
 582      * addresses vary between the legacy and A-Series memory maps.
 583      */
 584
 585     sys_id = 0x1190f500;
 586
 587     sysctl = qdev_create(NULL, "realview_sysctl");
 588     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 589     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 590     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 591                          daughterboard->num_voltage_sensors);
 592     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 593         char *propname = g_strdup_printf("db-voltage[%d]", i);
 594         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 595         g_free(propname);
 596     }
 597     qdev_prop_set_uint32(sysctl, "len-db-clock",
 598                          daughterboard->num_clocks);
 599     for (i = 0; i < daughterboard->num_clocks; i++) {
 600         char *propname = g_strdup_printf("db-clock[%d]", i);
 601         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 602         g_free(propname);
 603     }
 604     qdev_init_nofail(sysctl);
 605     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 606
 607     /* VE_SP810: not modelled */
 608     /* VE_SERIALPCI: not modelled */
 609
 610     pl041 = qdev_create(NULL, "pl041");
 611     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 612     qdev_init_nofail(pl041);
 613     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 614     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 615
 616     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 617     /* Wire up MMC card detect and read-only signals */
 618     qdev_connect_gpio_out(dev, 0,
 619                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 620     qdev_connect_gpio_out(dev, 1,
 621                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 622
 623     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 624     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 625
 626     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 627     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 628     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 629     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 630
 631     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 632     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 633
 634     /* VE_SERIALDVI: not modelled */
 635
 636     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 637
 638     /* VE_COMPACTFLASH: not modelled */
 639
 640     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 641
 642     dinfo = drive_get_next(IF_PFLASH);
 643     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 644                                        dinfo);
 645     if (!pflash0) {
 646         fprintf(stderr, "vexpress: error registering flash 0.\n");
 647         exit(1);
 648     }
 649
 650     if (map[VE_NORFLASHALIAS] != -1) {
 651         /* Map flash 0 as an alias into low memory */
 652         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 653         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 654                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 655         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 656     }
 657
 658     dinfo = drive_get_next(IF_PFLASH);
 659     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 660                                   dinfo)) {
 661         fprintf(stderr, "vexpress: error registering flash 1.\n");
 662         exit(1);
 663     }
 664
 665     sram_size = 0x2000000;
 666     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
 667                            &error_abort);
 668     vmstate_register_ram_global(sram);
 669     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 670
 671     vram_size = 0x800000;
 672     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
 673                            &error_abort);
 674     vmstate_register_ram_global(vram);
 675     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 676
 677     /* 0x4e000000 LAN9118 Ethernet */
 678     if (nd_table[0].used) {
 679         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 680     }
 681
 682     /* VE_USB: not modelled */
 683
 684     /* VE_DAPROM: not modelled */
 685
 686     /* Create mmio transports, so the user can create virtio backends
 687      * (which will be automatically plugged in to the transports). If
 688      * no backend is created the transport will just sit harmlessly idle.
 689      */
 690     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 691         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 692                              pic[40 + i]);
 693     }
 694
 695     daughterboard->bootinfo.ram_size = machine->ram_size;
 696     daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
 697     daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
 698     daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
 699     daughterboard->bootinfo.nb_cpus = smp_cpus;
 700     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 701     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 702     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 703     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 704     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 705     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 706     /* Indicate that when booting Linux we should be in secure state */
 707     daughterboard->bootinfo.secure_boot = true;
 708     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 709 }
 710
 711 static bool vexpress_get_secure(Object *obj, Error **errp)
 712 {
 713     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 714
 715     return vms->secure;
 716 }
 717
 718 static void vexpress_set_secure(Object *obj, bool value, Error **errp)
 719 {
 720     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 721
 722     vms->secure = value;
 723 }
 724
 725 static void vexpress_instance_init(Object *obj)
 726 {
 727     VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
 728
 729     /* EL3 is enabled by default on vexpress */
 730     vms->secure = true;
 731     object_property_add_bool(obj, "secure", vexpress_get_secure,
 732                              vexpress_set_secure, NULL);
 733     object_property_set_description(obj, "secure",
 734                                     "Set on/off to enable/disable the ARM "
 735                                     "Security Extensions (TrustZone)",
 736                                     NULL);
 737 }
 738
 739 static void vexpress_class_init(ObjectClass *oc, void *data)
 740 {
 741     MachineClass *mc = MACHINE_CLASS(oc);
 742
 743     mc->name = TYPE_VEXPRESS_MACHINE;
 744     mc->desc = "ARM Versatile Express";
 745     mc->init = vexpress_common_init;
 746     mc->block_default_type = IF_SCSI;
 747     mc->max_cpus = 4;
 748 }
 749
 750 static void vexpress_a9_class_init(ObjectClass *oc, void *data)
 751 {
 752     MachineClass *mc = MACHINE_CLASS(oc);
 753     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 754
 755     mc->name = TYPE_VEXPRESS_A9_MACHINE;
 756     mc->desc = "ARM Versatile Express for Cortex-A9";
 757
 758     vmc->daughterboard = &a9_daughterboard;;
 759 }
 760
 761 static void vexpress_a15_class_init(ObjectClass *oc, void *data)
 762 {
 763     MachineClass *mc = MACHINE_CLASS(oc);
 764     VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
 765
 766     mc->name = TYPE_VEXPRESS_A15_MACHINE;
 767     mc->desc = "ARM Versatile Express for Cortex-A15";
 768
 769     vmc->daughterboard = &a15_daughterboard;
 770 }
 771
 772 static const TypeInfo vexpress_info = {
 773     .name = TYPE_VEXPRESS_MACHINE,
 774     .parent = TYPE_MACHINE,
 775     .abstract = true,
 776     .instance_size = sizeof(VexpressMachineState),
 777     .instance_init = vexpress_instance_init,
 778     .class_size = sizeof(VexpressMachineClass),
 779     .class_init = vexpress_class_init,
 780 };
 781
 782 static const TypeInfo vexpress_a9_info = {
 783     .name = TYPE_VEXPRESS_A9_MACHINE,
 784     .parent = TYPE_VEXPRESS_MACHINE,
 785     .class_init = vexpress_a9_class_init,
 786 };
 787
 788 static const TypeInfo vexpress_a15_info = {
 789     .name = TYPE_VEXPRESS_A15_MACHINE,
 790     .parent = TYPE_VEXPRESS_MACHINE,
 791     .class_init = vexpress_a15_class_init,
 792 };
 793
 794 static void vexpress_machine_init(void)
 795 {
 796     type_register_static(&vexpress_info);
 797     type_register_static(&vexpress_a9_info);
 798     type_register_static(&vexpress_a15_info);
 799 }
 800
 801 machine_init(vexpress_machine_init);