hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/ssi.h"
  12 #include "hw/arm/arm.h"
  13 #include "hw/devices.h"
  14 #include "qemu/timer.h"
  15 #include "hw/i2c/i2c.h"
  16 #include "net/net.h"
  17 #include "hw/boards.h"
  18 #include "exec/address-spaces.h"
  19
  20 #define GPIO_A 0
  21 #define GPIO_B 1
  22 #define GPIO_C 2
  23 #define GPIO_D 3
  24 #define GPIO_E 4
  25 #define GPIO_F 5
  26 #define GPIO_G 6
  27
  28 #define BP_OLED_I2C  0x01
  29 #define BP_OLED_SSI  0x02
  30 #define BP_GAMEPAD   0x04
  31
  32 #define NUM_IRQ_LINES 64
  33
  34 typedef const struct {
  35     const char *name;
  36     uint32_t did0;
  37     uint32_t did1;
  38     uint32_t dc0;
  39     uint32_t dc1;
  40     uint32_t dc2;
  41     uint32_t dc3;
  42     uint32_t dc4;
  43     uint32_t peripherals;
  44 } stellaris_board_info;
  45
  46 /* General purpose timer module.  */
  47
  48 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  49 #define STELLARIS_GPTM(obj) \
  50     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  51
  52 typedef struct gptm_state {
  53     SysBusDevice parent_obj;
  54
  55     MemoryRegion iomem;
  56     uint32_t config;
  57     uint32_t mode[2];
  58     uint32_t control;
  59     uint32_t state;
  60     uint32_t mask;
  61     uint32_t load[2];
  62     uint32_t match[2];
  63     uint32_t prescale[2];
  64     uint32_t match_prescale[2];
  65     uint32_t rtc;
  66     int64_t tick[2];
  67     struct gptm_state *opaque[2];
  68     QEMUTimer *timer[2];
  69     /* The timers have an alternate output used to trigger the ADC.  */
  70     qemu_irq trigger;
  71     qemu_irq irq;
  72 } gptm_state;
  73
  74 static void gptm_update_irq(gptm_state *s)
  75 {
  76     int level;
  77     level = (s->state & s->mask) != 0;
  78     qemu_set_irq(s->irq, level);
  79 }
  80
  81 static void gptm_stop(gptm_state *s, int n)
  82 {
  83     timer_del(s->timer[n]);
  84 }
  85
  86 static void gptm_reload(gptm_state *s, int n, int reset)
  87 {
  88     int64_t tick;
  89     if (reset)
  90         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  91     else
  92         tick = s->tick[n];
  93
  94     if (s->config == 0) {
  95         /* 32-bit CountDown.  */
  96         uint32_t count;
  97         count = s->load[0] | (s->load[1] << 16);
  98         tick += (int64_t)count * system_clock_scale;
  99     } else if (s->config == 1) {
 100         /* 32-bit RTC.  1Hz tick.  */
 101         tick += get_ticks_per_sec();
 102     } else if (s->mode[n] == 0xa) {
 103         /* PWM mode.  Not implemented.  */
 104     } else {
 105         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 106     }
 107     s->tick[n] = tick;
 108     timer_mod(s->timer[n], tick);
 109 }
 110
 111 static void gptm_tick(void *opaque)
 112 {
 113     gptm_state **p = (gptm_state **)opaque;
 114     gptm_state *s;
 115     int n;
 116
 117     s = *p;
 118     n = p - s->opaque;
 119     if (s->config == 0) {
 120         s->state |= 1;
 121         if ((s->control & 0x20)) {
 122             /* Output trigger.  */
 123             qemu_irq_pulse(s->trigger);
 124         }
 125         if (s->mode[0] & 1) {
 126             /* One-shot.  */
 127             s->control &= ~1;
 128         } else {
 129             /* Periodic.  */
 130             gptm_reload(s, 0, 0);
 131         }
 132     } else if (s->config == 1) {
 133         /* RTC.  */
 134         uint32_t match;
 135         s->rtc++;
 136         match = s->match[0] | (s->match[1] << 16);
 137         if (s->rtc > match)
 138             s->rtc = 0;
 139         if (s->rtc == 0) {
 140             s->state |= 8;
 141         }
 142         gptm_reload(s, 0, 0);
 143     } else if (s->mode[n] == 0xa) {
 144         /* PWM mode.  Not implemented.  */
 145     } else {
 146         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 147     }
 148     gptm_update_irq(s);
 149 }
 150
 151 static uint64_t gptm_read(void *opaque, hwaddr offset,
 152                           unsigned size)
 153 {
 154     gptm_state *s = (gptm_state *)opaque;
 155
 156     switch (offset) {
 157     case 0x00: /* CFG */
 158         return s->config;
 159     case 0x04: /* TAMR */
 160         return s->mode[0];
 161     case 0x08: /* TBMR */
 162         return s->mode[1];
 163     case 0x0c: /* CTL */
 164         return s->control;
 165     case 0x18: /* IMR */
 166         return s->mask;
 167     case 0x1c: /* RIS */
 168         return s->state;
 169     case 0x20: /* MIS */
 170         return s->state & s->mask;
 171     case 0x24: /* CR */
 172         return 0;
 173     case 0x28: /* TAILR */
 174         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 175     case 0x2c: /* TBILR */
 176         return s->load[1];
 177     case 0x30: /* TAMARCHR */
 178         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 179     case 0x34: /* TBMATCHR */
 180         return s->match[1];
 181     case 0x38: /* TAPR */
 182         return s->prescale[0];
 183     case 0x3c: /* TBPR */
 184         return s->prescale[1];
 185     case 0x40: /* TAPMR */
 186         return s->match_prescale[0];
 187     case 0x44: /* TBPMR */
 188         return s->match_prescale[1];
 189     case 0x48: /* TAR */
 190         if (s->config == 1) {
 191             return s->rtc;
 192         }
 193         qemu_log_mask(LOG_UNIMP,
 194                       "GPTM: read of TAR but timer read not supported");
 195         return 0;
 196     case 0x4c: /* TBR */
 197         qemu_log_mask(LOG_UNIMP,
 198                       "GPTM: read of TBR but timer read not supported");
 199         return 0;
 200     default:
 201         qemu_log_mask(LOG_GUEST_ERROR,
 202                       "GPTM: read at bad offset 0x%x\n", (int)offset);
 203         return 0;
 204     }
 205 }
 206
 207 static void gptm_write(void *opaque, hwaddr offset,
 208                        uint64_t value, unsigned size)
 209 {
 210     gptm_state *s = (gptm_state *)opaque;
 211     uint32_t oldval;
 212
 213     /* The timers should be disabled before changing the configuration.
 214        We take advantage of this and defer everything until the timer
 215        is enabled.  */
 216     switch (offset) {
 217     case 0x00: /* CFG */
 218         s->config = value;
 219         break;
 220     case 0x04: /* TAMR */
 221         s->mode[0] = value;
 222         break;
 223     case 0x08: /* TBMR */
 224         s->mode[1] = value;
 225         break;
 226     case 0x0c: /* CTL */
 227         oldval = s->control;
 228         s->control = value;
 229         /* TODO: Implement pause.  */
 230         if ((oldval ^ value) & 1) {
 231             if (value & 1) {
 232                 gptm_reload(s, 0, 1);
 233             } else {
 234                 gptm_stop(s, 0);
 235             }
 236         }
 237         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 238             if (value & 0x100) {
 239                 gptm_reload(s, 1, 1);
 240             } else {
 241                 gptm_stop(s, 1);
 242             }
 243         }
 244         break;
 245     case 0x18: /* IMR */
 246         s->mask = value & 0x77;
 247         gptm_update_irq(s);
 248         break;
 249     case 0x24: /* CR */
 250         s->state &= ~value;
 251         break;
 252     case 0x28: /* TAILR */
 253         s->load[0] = value & 0xffff;
 254         if (s->config < 4) {
 255             s->load[1] = value >> 16;
 256         }
 257         break;
 258     case 0x2c: /* TBILR */
 259         s->load[1] = value & 0xffff;
 260         break;
 261     case 0x30: /* TAMARCHR */
 262         s->match[0] = value & 0xffff;
 263         if (s->config < 4) {
 264             s->match[1] = value >> 16;
 265         }
 266         break;
 267     case 0x34: /* TBMATCHR */
 268         s->match[1] = value >> 16;
 269         break;
 270     case 0x38: /* TAPR */
 271         s->prescale[0] = value;
 272         break;
 273     case 0x3c: /* TBPR */
 274         s->prescale[1] = value;
 275         break;
 276     case 0x40: /* TAPMR */
 277         s->match_prescale[0] = value;
 278         break;
 279     case 0x44: /* TBPMR */
 280         s->match_prescale[0] = value;
 281         break;
 282     default:
 283         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 284     }
 285     gptm_update_irq(s);
 286 }
 287
 288 static const MemoryRegionOps gptm_ops = {
 289     .read = gptm_read,
 290     .write = gptm_write,
 291     .endianness = DEVICE_NATIVE_ENDIAN,
 292 };
 293
 294 static const VMStateDescription vmstate_stellaris_gptm = {
 295     .name = "stellaris_gptm",
 296     .version_id = 1,
 297     .minimum_version_id = 1,
 298     .fields = (VMStateField[]) {
 299         VMSTATE_UINT32(config, gptm_state),
 300         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 301         VMSTATE_UINT32(control, gptm_state),
 302         VMSTATE_UINT32(state, gptm_state),
 303         VMSTATE_UINT32(mask, gptm_state),
 304         VMSTATE_UNUSED(8),
 305         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 306         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 307         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 308         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 309         VMSTATE_UINT32(rtc, gptm_state),
 310         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 311         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 312         VMSTATE_END_OF_LIST()
 313     }
 314 };
 315
 316 static int stellaris_gptm_init(SysBusDevice *sbd)
 317 {
 318     DeviceState *dev = DEVICE(sbd);
 319     gptm_state *s = STELLARIS_GPTM(dev);
 320
 321     sysbus_init_irq(sbd, &s->irq);
 322     qdev_init_gpio_out(dev, &s->trigger, 1);
 323
 324     memory_region_init_io(&s->iomem, OBJECT(s), &gptm_ops, s,
 325                           "gptm", 0x1000);
 326     sysbus_init_mmio(sbd, &s->iomem);
 327
 328     s->opaque[0] = s->opaque[1] = s;
 329     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 330     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 331     vmstate_register(dev, -1, &vmstate_stellaris_gptm, s);
 332     return 0;
 333 }
 334
 335
 336 /* System controller.  */
 337
 338 typedef struct {
 339     MemoryRegion iomem;
 340     uint32_t pborctl;
 341     uint32_t ldopctl;
 342     uint32_t int_status;
 343     uint32_t int_mask;
 344     uint32_t resc;
 345     uint32_t rcc;
 346     uint32_t rcc2;
 347     uint32_t rcgc[3];
 348     uint32_t scgc[3];
 349     uint32_t dcgc[3];
 350     uint32_t clkvclr;
 351     uint32_t ldoarst;
 352     uint32_t user0;
 353     uint32_t user1;
 354     qemu_irq irq;
 355     stellaris_board_info *board;
 356 } ssys_state;
 357
 358 static void ssys_update(ssys_state *s)
 359 {
 360   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 361 }
 362
 363 static uint32_t pllcfg_sandstorm[16] = {
 364     0x31c0, /* 1 Mhz */
 365     0x1ae0, /* 1.8432 Mhz */
 366     0x18c0, /* 2 Mhz */
 367     0xd573, /* 2.4576 Mhz */
 368     0x37a6, /* 3.57954 Mhz */
 369     0x1ae2, /* 3.6864 Mhz */
 370     0x0c40, /* 4 Mhz */
 371     0x98bc, /* 4.906 Mhz */
 372     0x935b, /* 4.9152 Mhz */
 373     0x09c0, /* 5 Mhz */
 374     0x4dee, /* 5.12 Mhz */
 375     0x0c41, /* 6 Mhz */
 376     0x75db, /* 6.144 Mhz */
 377     0x1ae6, /* 7.3728 Mhz */
 378     0x0600, /* 8 Mhz */
 379     0x585b /* 8.192 Mhz */
 380 };
 381
 382 static uint32_t pllcfg_fury[16] = {
 383     0x3200, /* 1 Mhz */
 384     0x1b20, /* 1.8432 Mhz */
 385     0x1900, /* 2 Mhz */
 386     0xf42b, /* 2.4576 Mhz */
 387     0x37e3, /* 3.57954 Mhz */
 388     0x1b21, /* 3.6864 Mhz */
 389     0x0c80, /* 4 Mhz */
 390     0x98ee, /* 4.906 Mhz */
 391     0xd5b4, /* 4.9152 Mhz */
 392     0x0a00, /* 5 Mhz */
 393     0x4e27, /* 5.12 Mhz */
 394     0x1902, /* 6 Mhz */
 395     0xec1c, /* 6.144 Mhz */
 396     0x1b23, /* 7.3728 Mhz */
 397     0x0640, /* 8 Mhz */
 398     0xb11c /* 8.192 Mhz */
 399 };
 400
 401 #define DID0_VER_MASK        0x70000000
 402 #define DID0_VER_0           0x00000000
 403 #define DID0_VER_1           0x10000000
 404
 405 #define DID0_CLASS_MASK      0x00FF0000
 406 #define DID0_CLASS_SANDSTORM 0x00000000
 407 #define DID0_CLASS_FURY      0x00010000
 408
 409 static int ssys_board_class(const ssys_state *s)
 410 {
 411     uint32_t did0 = s->board->did0;
 412     switch (did0 & DID0_VER_MASK) {
 413     case DID0_VER_0:
 414         return DID0_CLASS_SANDSTORM;
 415     case DID0_VER_1:
 416         switch (did0 & DID0_CLASS_MASK) {
 417         case DID0_CLASS_SANDSTORM:
 418         case DID0_CLASS_FURY:
 419             return did0 & DID0_CLASS_MASK;
 420         }
 421         /* for unknown classes, fall through */
 422     default:
 423         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 424     }
 425 }
 426
 427 static uint64_t ssys_read(void *opaque, hwaddr offset,
 428                           unsigned size)
 429 {
 430     ssys_state *s = (ssys_state *)opaque;
 431
 432     switch (offset) {
 433     case 0x000: /* DID0 */
 434         return s->board->did0;
 435     case 0x004: /* DID1 */
 436         return s->board->did1;
 437     case 0x008: /* DC0 */
 438         return s->board->dc0;
 439     case 0x010: /* DC1 */
 440         return s->board->dc1;
 441     case 0x014: /* DC2 */
 442         return s->board->dc2;
 443     case 0x018: /* DC3 */
 444         return s->board->dc3;
 445     case 0x01c: /* DC4 */
 446         return s->board->dc4;
 447     case 0x030: /* PBORCTL */
 448         return s->pborctl;
 449     case 0x034: /* LDOPCTL */
 450         return s->ldopctl;
 451     case 0x040: /* SRCR0 */
 452         return 0;
 453     case 0x044: /* SRCR1 */
 454         return 0;
 455     case 0x048: /* SRCR2 */
 456         return 0;
 457     case 0x050: /* RIS */
 458         return s->int_status;
 459     case 0x054: /* IMC */
 460         return s->int_mask;
 461     case 0x058: /* MISC */
 462         return s->int_status & s->int_mask;
 463     case 0x05c: /* RESC */
 464         return s->resc;
 465     case 0x060: /* RCC */
 466         return s->rcc;
 467     case 0x064: /* PLLCFG */
 468         {
 469             int xtal;
 470             xtal = (s->rcc >> 6) & 0xf;
 471             switch (ssys_board_class(s)) {
 472             case DID0_CLASS_FURY:
 473                 return pllcfg_fury[xtal];
 474             case DID0_CLASS_SANDSTORM:
 475                 return pllcfg_sandstorm[xtal];
 476             default:
 477                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 478                 return 0;
 479             }
 480         }
 481     case 0x070: /* RCC2 */
 482         return s->rcc2;
 483     case 0x100: /* RCGC0 */
 484         return s->rcgc[0];
 485     case 0x104: /* RCGC1 */
 486         return s->rcgc[1];
 487     case 0x108: /* RCGC2 */
 488         return s->rcgc[2];
 489     case 0x110: /* SCGC0 */
 490         return s->scgc[0];
 491     case 0x114: /* SCGC1 */
 492         return s->scgc[1];
 493     case 0x118: /* SCGC2 */
 494         return s->scgc[2];
 495     case 0x120: /* DCGC0 */
 496         return s->dcgc[0];
 497     case 0x124: /* DCGC1 */
 498         return s->dcgc[1];
 499     case 0x128: /* DCGC2 */
 500         return s->dcgc[2];
 501     case 0x150: /* CLKVCLR */
 502         return s->clkvclr;
 503     case 0x160: /* LDOARST */
 504         return s->ldoarst;
 505     case 0x1e0: /* USER0 */
 506         return s->user0;
 507     case 0x1e4: /* USER1 */
 508         return s->user1;
 509     default:
 510         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 511         return 0;
 512     }
 513 }
 514
 515 static bool ssys_use_rcc2(ssys_state *s)
 516 {
 517     return (s->rcc2 >> 31) & 0x1;
 518 }
 519
 520 /*
 521  * Caculate the sys. clock period in ms.
 522  */
 523 static void ssys_calculate_system_clock(ssys_state *s)
 524 {
 525     if (ssys_use_rcc2(s)) {
 526         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 527     } else {
 528         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 529     }
 530 }
 531
 532 static void ssys_write(void *opaque, hwaddr offset,
 533                        uint64_t value, unsigned size)
 534 {
 535     ssys_state *s = (ssys_state *)opaque;
 536
 537     switch (offset) {
 538     case 0x030: /* PBORCTL */
 539         s->pborctl = value & 0xffff;
 540         break;
 541     case 0x034: /* LDOPCTL */
 542         s->ldopctl = value & 0x1f;
 543         break;
 544     case 0x040: /* SRCR0 */
 545     case 0x044: /* SRCR1 */
 546     case 0x048: /* SRCR2 */
 547         fprintf(stderr, "Peripheral reset not implemented\n");
 548         break;
 549     case 0x054: /* IMC */
 550         s->int_mask = value & 0x7f;
 551         break;
 552     case 0x058: /* MISC */
 553         s->int_status &= ~value;
 554         break;
 555     case 0x05c: /* RESC */
 556         s->resc = value & 0x3f;
 557         break;
 558     case 0x060: /* RCC */
 559         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 560             /* PLL enable.  */
 561             s->int_status |= (1 << 6);
 562         }
 563         s->rcc = value;
 564         ssys_calculate_system_clock(s);
 565         break;
 566     case 0x070: /* RCC2 */
 567         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 568             break;
 569         }
 570
 571         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 572             /* PLL enable.  */
 573             s->int_status |= (1 << 6);
 574         }
 575         s->rcc2 = value;
 576         ssys_calculate_system_clock(s);
 577         break;
 578     case 0x100: /* RCGC0 */
 579         s->rcgc[0] = value;
 580         break;
 581     case 0x104: /* RCGC1 */
 582         s->rcgc[1] = value;
 583         break;
 584     case 0x108: /* RCGC2 */
 585         s->rcgc[2] = value;
 586         break;
 587     case 0x110: /* SCGC0 */
 588         s->scgc[0] = value;
 589         break;
 590     case 0x114: /* SCGC1 */
 591         s->scgc[1] = value;
 592         break;
 593     case 0x118: /* SCGC2 */
 594         s->scgc[2] = value;
 595         break;
 596     case 0x120: /* DCGC0 */
 597         s->dcgc[0] = value;
 598         break;
 599     case 0x124: /* DCGC1 */
 600         s->dcgc[1] = value;
 601         break;
 602     case 0x128: /* DCGC2 */
 603         s->dcgc[2] = value;
 604         break;
 605     case 0x150: /* CLKVCLR */
 606         s->clkvclr = value;
 607         break;
 608     case 0x160: /* LDOARST */
 609         s->ldoarst = value;
 610         break;
 611     default:
 612         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 613     }
 614     ssys_update(s);
 615 }
 616
 617 static const MemoryRegionOps ssys_ops = {
 618     .read = ssys_read,
 619     .write = ssys_write,
 620     .endianness = DEVICE_NATIVE_ENDIAN,
 621 };
 622
 623 static void ssys_reset(void *opaque)
 624 {
 625     ssys_state *s = (ssys_state *)opaque;
 626
 627     s->pborctl = 0x7ffd;
 628     s->rcc = 0x078e3ac0;
 629
 630     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 631         s->rcc2 = 0;
 632     } else {
 633         s->rcc2 = 0x07802810;
 634     }
 635     s->rcgc[0] = 1;
 636     s->scgc[0] = 1;
 637     s->dcgc[0] = 1;
 638     ssys_calculate_system_clock(s);
 639 }
 640
 641 static int stellaris_sys_post_load(void *opaque, int version_id)
 642 {
 643     ssys_state *s = opaque;
 644
 645     ssys_calculate_system_clock(s);
 646
 647     return 0;
 648 }
 649
 650 static const VMStateDescription vmstate_stellaris_sys = {
 651     .name = "stellaris_sys",
 652     .version_id = 2,
 653     .minimum_version_id = 1,
 654     .post_load = stellaris_sys_post_load,
 655     .fields = (VMStateField[]) {
 656         VMSTATE_UINT32(pborctl, ssys_state),
 657         VMSTATE_UINT32(ldopctl, ssys_state),
 658         VMSTATE_UINT32(int_mask, ssys_state),
 659         VMSTATE_UINT32(int_status, ssys_state),
 660         VMSTATE_UINT32(resc, ssys_state),
 661         VMSTATE_UINT32(rcc, ssys_state),
 662         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 663         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 664         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 665         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 666         VMSTATE_UINT32(clkvclr, ssys_state),
 667         VMSTATE_UINT32(ldoarst, ssys_state),
 668         VMSTATE_END_OF_LIST()
 669     }
 670 };
 671
 672 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 673                               stellaris_board_info * board,
 674                               uint8_t *macaddr)
 675 {
 676     ssys_state *s;
 677
 678     s = (ssys_state *)g_malloc0(sizeof(ssys_state));
 679     s->irq = irq;
 680     s->board = board;
 681     /* Most devices come preprogrammed with a MAC address in the user data. */
 682     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 683     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 684
 685     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 686     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 687     ssys_reset(s);
 688     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 689     return 0;
 690 }
 691
 692
 693 /* I2C controller.  */
 694
 695 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 696 #define STELLARIS_I2C(obj) \
 697     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 698
 699 typedef struct {
 700     SysBusDevice parent_obj;
 701
 702     I2CBus *bus;
 703     qemu_irq irq;
 704     MemoryRegion iomem;
 705     uint32_t msa;
 706     uint32_t mcs;
 707     uint32_t mdr;
 708     uint32_t mtpr;
 709     uint32_t mimr;
 710     uint32_t mris;
 711     uint32_t mcr;
 712 } stellaris_i2c_state;
 713
 714 #define STELLARIS_I2C_MCS_BUSY    0x01
 715 #define STELLARIS_I2C_MCS_ERROR   0x02
 716 #define STELLARIS_I2C_MCS_ADRACK  0x04
 717 #define STELLARIS_I2C_MCS_DATACK  0x08
 718 #define STELLARIS_I2C_MCS_ARBLST  0x10
 719 #define STELLARIS_I2C_MCS_IDLE    0x20
 720 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 721
 722 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 723                                    unsigned size)
 724 {
 725     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 726
 727     switch (offset) {
 728     case 0x00: /* MSA */
 729         return s->msa;
 730     case 0x04: /* MCS */
 731         /* We don't emulate timing, so the controller is never busy.  */
 732         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 733     case 0x08: /* MDR */
 734         return s->mdr;
 735     case 0x0c: /* MTPR */
 736         return s->mtpr;
 737     case 0x10: /* MIMR */
 738         return s->mimr;
 739     case 0x14: /* MRIS */
 740         return s->mris;
 741     case 0x18: /* MMIS */
 742         return s->mris & s->mimr;
 743     case 0x20: /* MCR */
 744         return s->mcr;
 745     default:
 746         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 747         return 0;
 748     }
 749 }
 750
 751 static void stellaris_i2c_update(stellaris_i2c_state *s)
 752 {
 753     int level;
 754
 755     level = (s->mris & s->mimr) != 0;
 756     qemu_set_irq(s->irq, level);
 757 }
 758
 759 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 760                                 uint64_t value, unsigned size)
 761 {
 762     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 763
 764     switch (offset) {
 765     case 0x00: /* MSA */
 766         s->msa = value & 0xff;
 767         break;
 768     case 0x04: /* MCS */
 769         if ((s->mcr & 0x10) == 0) {
 770             /* Disabled.  Do nothing.  */
 771             break;
 772         }
 773         /* Grab the bus if this is starting a transfer.  */
 774         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 775             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 776                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 777             } else {
 778                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 779                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 780             }
 781         }
 782         /* If we don't have the bus then indicate an error.  */
 783         if (!i2c_bus_busy(s->bus)
 784                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 785             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 786             break;
 787         }
 788         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 789         if (value & 1) {
 790             /* Transfer a byte.  */
 791             /* TODO: Handle errors.  */
 792             if (s->msa & 1) {
 793                 /* Recv */
 794                 s->mdr = i2c_recv(s->bus) & 0xff;
 795             } else {
 796                 /* Send */
 797                 i2c_send(s->bus, s->mdr);
 798             }
 799             /* Raise an interrupt.  */
 800             s->mris |= 1;
 801         }
 802         if (value & 4) {
 803             /* Finish transfer.  */
 804             i2c_end_transfer(s->bus);
 805             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 806         }
 807         break;
 808     case 0x08: /* MDR */
 809         s->mdr = value & 0xff;
 810         break;
 811     case 0x0c: /* MTPR */
 812         s->mtpr = value & 0xff;
 813         break;
 814     case 0x10: /* MIMR */
 815         s->mimr = 1;
 816         break;
 817     case 0x1c: /* MICR */
 818         s->mris &= ~value;
 819         break;
 820     case 0x20: /* MCR */
 821         if (value & 1)
 822             hw_error(
 823                       "stellaris_i2c_write: Loopback not implemented\n");
 824         if (value & 0x20)
 825             hw_error(
 826                       "stellaris_i2c_write: Slave mode not implemented\n");
 827         s->mcr = value & 0x31;
 828         break;
 829     default:
 830         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 831                   (int)offset);
 832     }
 833     stellaris_i2c_update(s);
 834 }
 835
 836 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 837 {
 838     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 839         i2c_end_transfer(s->bus);
 840
 841     s->msa = 0;
 842     s->mcs = 0;
 843     s->mdr = 0;
 844     s->mtpr = 1;
 845     s->mimr = 0;
 846     s->mris = 0;
 847     s->mcr = 0;
 848     stellaris_i2c_update(s);
 849 }
 850
 851 static const MemoryRegionOps stellaris_i2c_ops = {
 852     .read = stellaris_i2c_read,
 853     .write = stellaris_i2c_write,
 854     .endianness = DEVICE_NATIVE_ENDIAN,
 855 };
 856
 857 static const VMStateDescription vmstate_stellaris_i2c = {
 858     .name = "stellaris_i2c",
 859     .version_id = 1,
 860     .minimum_version_id = 1,
 861     .fields = (VMStateField[]) {
 862         VMSTATE_UINT32(msa, stellaris_i2c_state),
 863         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 864         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 865         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 866         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 867         VMSTATE_UINT32(mris, stellaris_i2c_state),
 868         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 869         VMSTATE_END_OF_LIST()
 870     }
 871 };
 872
 873 static int stellaris_i2c_init(SysBusDevice *sbd)
 874 {
 875     DeviceState *dev = DEVICE(sbd);
 876     stellaris_i2c_state *s = STELLARIS_I2C(dev);
 877     I2CBus *bus;
 878
 879     sysbus_init_irq(sbd, &s->irq);
 880     bus = i2c_init_bus(dev, "i2c");
 881     s->bus = bus;
 882
 883     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_i2c_ops, s,
 884                           "i2c", 0x1000);
 885     sysbus_init_mmio(sbd, &s->iomem);
 886     /* ??? For now we only implement the master interface.  */
 887     stellaris_i2c_reset(s);
 888     vmstate_register(dev, -1, &vmstate_stellaris_i2c, s);
 889     return 0;
 890 }
 891
 892 /* Analogue to Digital Converter.  This is only partially implemented,
 893    enough for applications that use a combined ADC and timer tick.  */
 894
 895 #define STELLARIS_ADC_EM_CONTROLLER 0
 896 #define STELLARIS_ADC_EM_COMP       1
 897 #define STELLARIS_ADC_EM_EXTERNAL   4
 898 #define STELLARIS_ADC_EM_TIMER      5
 899 #define STELLARIS_ADC_EM_PWM0       6
 900 #define STELLARIS_ADC_EM_PWM1       7
 901 #define STELLARIS_ADC_EM_PWM2       8
 902
 903 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 904 #define STELLARIS_ADC_FIFO_FULL     0x1000
 905
 906 #define TYPE_STELLARIS_ADC "stellaris-adc"
 907 #define STELLARIS_ADC(obj) \
 908     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 909
 910 typedef struct StellarisADCState {
 911     SysBusDevice parent_obj;
 912
 913     MemoryRegion iomem;
 914     uint32_t actss;
 915     uint32_t ris;
 916     uint32_t im;
 917     uint32_t emux;
 918     uint32_t ostat;
 919     uint32_t ustat;
 920     uint32_t sspri;
 921     uint32_t sac;
 922     struct {
 923         uint32_t state;
 924         uint32_t data[16];
 925     } fifo[4];
 926     uint32_t ssmux[4];
 927     uint32_t ssctl[4];
 928     uint32_t noise;
 929     qemu_irq irq[4];
 930 } stellaris_adc_state;
 931
 932 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 933 {
 934     int tail;
 935
 936     tail = s->fifo[n].state & 0xf;
 937     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 938         s->ustat |= 1 << n;
 939     } else {
 940         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 941         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 942         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 943             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 944     }
 945     return s->fifo[n].data[tail];
 946 }
 947
 948 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 949                                      uint32_t value)
 950 {
 951     int head;
 952
 953     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 954        FIFO fir each sequencer.  */
 955     head = (s->fifo[n].state >> 4) & 0xf;
 956     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 957         s->ostat |= 1 << n;
 958         return;
 959     }
 960     s->fifo[n].data[head] = value;
 961     head = (head + 1) & 0xf;
 962     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 963     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 964     if ((s->fifo[n].state & 0xf) == head)
 965         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 966 }
 967
 968 static void stellaris_adc_update(stellaris_adc_state *s)
 969 {
 970     int level;
 971     int n;
 972
 973     for (n = 0; n < 4; n++) {
 974         level = (s->ris & s->im & (1 << n)) != 0;
 975         qemu_set_irq(s->irq[n], level);
 976     }
 977 }
 978
 979 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 980 {
 981     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 982     int n;
 983
 984     for (n = 0; n < 4; n++) {
 985         if ((s->actss & (1 << n)) == 0) {
 986             continue;
 987         }
 988
 989         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 990             continue;
 991         }
 992
 993         /* Some applications use the ADC as a random number source, so introduce
 994            some variation into the signal.  */
 995         s->noise = s->noise * 314159 + 1;
 996         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 997         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 998         s->ris |= (1 << n);
 999         stellaris_adc_update(s);
1000     }
1001 }
1002
1003 static void stellaris_adc_reset(stellaris_adc_state *s)
1004 {
1005     int n;
1006
1007     for (n = 0; n < 4; n++) {
1008         s->ssmux[n] = 0;
1009         s->ssctl[n] = 0;
1010         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1011     }
1012 }
1013
1014 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1015                                    unsigned size)
1016 {
1017     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1018
1019     /* TODO: Implement this.  */
1020     if (offset >= 0x40 && offset < 0xc0) {
1021         int n;
1022         n = (offset - 0x40) >> 5;
1023         switch (offset & 0x1f) {
1024         case 0x00: /* SSMUX */
1025             return s->ssmux[n];
1026         case 0x04: /* SSCTL */
1027             return s->ssctl[n];
1028         case 0x08: /* SSFIFO */
1029             return stellaris_adc_fifo_read(s, n);
1030         case 0x0c: /* SSFSTAT */
1031             return s->fifo[n].state;
1032         default:
1033             break;
1034         }
1035     }
1036     switch (offset) {
1037     case 0x00: /* ACTSS */
1038         return s->actss;
1039     case 0x04: /* RIS */
1040         return s->ris;
1041     case 0x08: /* IM */
1042         return s->im;
1043     case 0x0c: /* ISC */
1044         return s->ris & s->im;
1045     case 0x10: /* OSTAT */
1046         return s->ostat;
1047     case 0x14: /* EMUX */
1048         return s->emux;
1049     case 0x18: /* USTAT */
1050         return s->ustat;
1051     case 0x20: /* SSPRI */
1052         return s->sspri;
1053     case 0x30: /* SAC */
1054         return s->sac;
1055     default:
1056         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1057                   (int)offset);
1058         return 0;
1059     }
1060 }
1061
1062 static void stellaris_adc_write(void *opaque, hwaddr offset,
1063                                 uint64_t value, unsigned size)
1064 {
1065     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1066
1067     /* TODO: Implement this.  */
1068     if (offset >= 0x40 && offset < 0xc0) {
1069         int n;
1070         n = (offset - 0x40) >> 5;
1071         switch (offset & 0x1f) {
1072         case 0x00: /* SSMUX */
1073             s->ssmux[n] = value & 0x33333333;
1074             return;
1075         case 0x04: /* SSCTL */
1076             if (value != 6) {
1077                 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
1078                           value);
1079             }
1080             s->ssctl[n] = value;
1081             return;
1082         default:
1083             break;
1084         }
1085     }
1086     switch (offset) {
1087     case 0x00: /* ACTSS */
1088         s->actss = value & 0xf;
1089         break;
1090     case 0x08: /* IM */
1091         s->im = value;
1092         break;
1093     case 0x0c: /* ISC */
1094         s->ris &= ~value;
1095         break;
1096     case 0x10: /* OSTAT */
1097         s->ostat &= ~value;
1098         break;
1099     case 0x14: /* EMUX */
1100         s->emux = value;
1101         break;
1102     case 0x18: /* USTAT */
1103         s->ustat &= ~value;
1104         break;
1105     case 0x20: /* SSPRI */
1106         s->sspri = value;
1107         break;
1108     case 0x28: /* PSSI */
1109         hw_error("Not implemented:  ADC sample initiate\n");
1110         break;
1111     case 0x30: /* SAC */
1112         s->sac = value;
1113         break;
1114     default:
1115         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1116     }
1117     stellaris_adc_update(s);
1118 }
1119
1120 static const MemoryRegionOps stellaris_adc_ops = {
1121     .read = stellaris_adc_read,
1122     .write = stellaris_adc_write,
1123     .endianness = DEVICE_NATIVE_ENDIAN,
1124 };
1125
1126 static const VMStateDescription vmstate_stellaris_adc = {
1127     .name = "stellaris_adc",
1128     .version_id = 1,
1129     .minimum_version_id = 1,
1130     .fields = (VMStateField[]) {
1131         VMSTATE_UINT32(actss, stellaris_adc_state),
1132         VMSTATE_UINT32(ris, stellaris_adc_state),
1133         VMSTATE_UINT32(im, stellaris_adc_state),
1134         VMSTATE_UINT32(emux, stellaris_adc_state),
1135         VMSTATE_UINT32(ostat, stellaris_adc_state),
1136         VMSTATE_UINT32(ustat, stellaris_adc_state),
1137         VMSTATE_UINT32(sspri, stellaris_adc_state),
1138         VMSTATE_UINT32(sac, stellaris_adc_state),
1139         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1140         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1141         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1142         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1143         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1144         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1145         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1146         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1147         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1148         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1149         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1150         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1151         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1152         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1153         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1154         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1155         VMSTATE_UINT32(noise, stellaris_adc_state),
1156         VMSTATE_END_OF_LIST()
1157     }
1158 };
1159
1160 static int stellaris_adc_init(SysBusDevice *sbd)
1161 {
1162     DeviceState *dev = DEVICE(sbd);
1163     stellaris_adc_state *s = STELLARIS_ADC(dev);
1164     int n;
1165
1166     for (n = 0; n < 4; n++) {
1167         sysbus_init_irq(sbd, &s->irq[n]);
1168     }
1169
1170     memory_region_init_io(&s->iomem, OBJECT(s), &stellaris_adc_ops, s,
1171                           "adc", 0x1000);
1172     sysbus_init_mmio(sbd, &s->iomem);
1173     stellaris_adc_reset(s);
1174     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1175     vmstate_register(dev, -1, &vmstate_stellaris_adc, s);
1176     return 0;
1177 }
1178
1179 /* Board init.  */
1180 static stellaris_board_info stellaris_boards[] = {
1181   { "LM3S811EVB",
1182     0,
1183     0x0032000e,
1184     0x001f001f, /* dc0 */
1185     0x001132bf,
1186     0x01071013,
1187     0x3f0f01ff,
1188     0x0000001f,
1189     BP_OLED_I2C
1190   },
1191   { "LM3S6965EVB",
1192     0x10010002,
1193     0x1073402e,
1194     0x00ff007f, /* dc0 */
1195     0x001133ff,
1196     0x030f5317,
1197     0x0f0f87ff,
1198     0x5000007f,
1199     BP_OLED_SSI | BP_GAMEPAD
1200   }
1201 };
1202
1203 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1204                            stellaris_board_info *board)
1205 {
1206     static const int uart_irq[] = {5, 6, 33, 34};
1207     static const int timer_irq[] = {19, 21, 23, 35};
1208     static const uint32_t gpio_addr[7] =
1209       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1210         0x40024000, 0x40025000, 0x40026000};
1211     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1212
1213     qemu_irq *pic;
1214     DeviceState *gpio_dev[7];
1215     qemu_irq gpio_in[7][8];
1216     qemu_irq gpio_out[7][8];
1217     qemu_irq adc;
1218     int sram_size;
1219     int flash_size;
1220     I2CBus *i2c;
1221     DeviceState *dev;
1222     int i;
1223     int j;
1224
1225     MemoryRegion *sram = g_new(MemoryRegion, 1);
1226     MemoryRegion *flash = g_new(MemoryRegion, 1);
1227     MemoryRegion *system_memory = get_system_memory();
1228
1229     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1230     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1231
1232     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1233     memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1234                            &error_abort);
1235     vmstate_register_ram_global(flash);
1236     memory_region_set_readonly(flash, true);
1237     memory_region_add_subregion(system_memory, 0, flash);
1238
1239     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1240                            &error_abort);
1241     vmstate_register_ram_global(sram);
1242     memory_region_add_subregion(system_memory, 0x20000000, sram);
1243
1244     pic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
1245                       kernel_filename, cpu_model);
1246
1247     if (board->dc1 & (1 << 16)) {
1248         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1249                                     pic[14], pic[15], pic[16], pic[17], NULL);
1250         adc = qdev_get_gpio_in(dev, 0);
1251     } else {
1252         adc = NULL;
1253     }
1254     for (i = 0; i < 4; i++) {
1255         if (board->dc2 & (0x10000 << i)) {
1256             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1257                                        0x40030000 + i * 0x1000,
1258                                        pic[timer_irq[i]]);
1259             /* TODO: This is incorrect, but we get away with it because
1260                the ADC output is only ever pulsed.  */
1261             qdev_connect_gpio_out(dev, 0, adc);
1262         }
1263     }
1264
1265     stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
1266
1267     for (i = 0; i < 7; i++) {
1268         if (board->dc4 & (1 << i)) {
1269             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1270                                                pic[gpio_irq[i]]);
1271             for (j = 0; j < 8; j++) {
1272                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1273                 gpio_out[i][j] = NULL;
1274             }
1275         }
1276     }
1277
1278     if (board->dc2 & (1 << 12)) {
1279         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);
1280         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1281         if (board->peripherals & BP_OLED_I2C) {
1282             i2c_create_slave(i2c, "ssd0303", 0x3d);
1283         }
1284     }
1285
1286     for (i = 0; i < 4; i++) {
1287         if (board->dc2 & (1 << i)) {
1288             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1289                                  pic[uart_irq[i]]);
1290         }
1291     }
1292     if (board->dc2 & (1 << 4)) {
1293         dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
1294         if (board->peripherals & BP_OLED_SSI) {
1295             void *bus;
1296             DeviceState *sddev;
1297             DeviceState *ssddev;
1298
1299             /* Some boards have both an OLED controller and SD card connected to
1300              * the same SSI port, with the SD card chip select connected to a
1301              * GPIO pin.  Technically the OLED chip select is connected to the
1302              * SSI Fss pin.  We do not bother emulating that as both devices
1303              * should never be selected simultaneously, and our OLED controller
1304              * ignores stray 0xff commands that occur when deselecting the SD
1305              * card.
1306              */
1307             bus = qdev_get_child_bus(dev, "ssi");
1308
1309             sddev = ssi_create_slave(bus, "ssi-sd");
1310             ssddev = ssi_create_slave(bus, "ssd0323");
1311             gpio_out[GPIO_D][0] = qemu_irq_split(
1312                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1313                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1314             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1315
1316             /* Make sure the select pin is high.  */
1317             qemu_irq_raise(gpio_out[GPIO_D][0]);
1318         }
1319     }
1320     if (board->dc4 & (1 << 28)) {
1321         DeviceState *enet;
1322
1323         qemu_check_nic_model(&nd_table[0], "stellaris");
1324
1325         enet = qdev_create(NULL, "stellaris_enet");
1326         qdev_set_nic_properties(enet, &nd_table[0]);
1327         qdev_init_nofail(enet);
1328         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1329         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, pic[42]);
1330     }
1331     if (board->peripherals & BP_GAMEPAD) {
1332         qemu_irq gpad_irq[5];
1333         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1334
1335         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1336         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1337         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1338         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1339         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1340
1341         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1342     }
1343     for (i = 0; i < 7; i++) {
1344         if (board->dc4 & (1 << i)) {
1345             for (j = 0; j < 8; j++) {
1346                 if (gpio_out[i][j]) {
1347                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1348                 }
1349             }
1350         }
1351     }
1352 }
1353
1354 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1355 static void lm3s811evb_init(MachineState *machine)
1356 {
1357     const char *cpu_model = machine->cpu_model;
1358     const char *kernel_filename = machine->kernel_filename;
1359     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1360 }
1361
1362 static void lm3s6965evb_init(MachineState *machine)
1363 {
1364     const char *cpu_model = machine->cpu_model;
1365     const char *kernel_filename = machine->kernel_filename;
1366     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1367 }
1368
1369 static QEMUMachine lm3s811evb_machine = {
1370     .name = "lm3s811evb",
1371     .desc = "Stellaris LM3S811EVB",
1372     .init = lm3s811evb_init,
1373 };
1374
1375 static QEMUMachine lm3s6965evb_machine = {
1376     .name = "lm3s6965evb",
1377     .desc = "Stellaris LM3S6965EVB",
1378     .init = lm3s6965evb_init,
1379 };
1380
1381 static void stellaris_machine_init(void)
1382 {
1383     qemu_register_machine(&lm3s811evb_machine);
1384     qemu_register_machine(&lm3s6965evb_machine);
1385 }
1386
1387 machine_init(stellaris_machine_init);
1388
1389 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1390 {
1391     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1392
1393     sdc->init = stellaris_i2c_init;
1394 }
1395
1396 static const TypeInfo stellaris_i2c_info = {
1397     .name          = TYPE_STELLARIS_I2C,
1398     .parent        = TYPE_SYS_BUS_DEVICE,
1399     .instance_size = sizeof(stellaris_i2c_state),
1400     .class_init    = stellaris_i2c_class_init,
1401 };
1402
1403 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1404 {
1405     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1406
1407     sdc->init = stellaris_gptm_init;
1408 }
1409
1410 static const TypeInfo stellaris_gptm_info = {
1411     .name          = TYPE_STELLARIS_GPTM,
1412     .parent        = TYPE_SYS_BUS_DEVICE,
1413     .instance_size = sizeof(gptm_state),
1414     .class_init    = stellaris_gptm_class_init,
1415 };
1416
1417 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1418 {
1419     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1420
1421     sdc->init = stellaris_adc_init;
1422 }
1423
1424 static const TypeInfo stellaris_adc_info = {
1425     .name          = TYPE_STELLARIS_ADC,
1426     .parent        = TYPE_SYS_BUS_DEVICE,
1427     .instance_size = sizeof(stellaris_adc_state),
1428     .class_init    = stellaris_adc_class_init,
1429 };
1430
1431 static void stellaris_register_types(void)
1432 {
1433     type_register_static(&stellaris_i2c_info);
1434     type_register_static(&stellaris_gptm_info);
1435     type_register_static(&stellaris_adc_info);
1436 }
1437
1438 type_init(stellaris_register_types)