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ACPI: Add definitions for the SPCR table
[qemu/ar7.git] / target-mips / msa_helper.c
blob26ffdc726eefb2ff26b01680da1ab968a952c784
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22
23 /* Data format min and max values */
24 #define DF_BITS(df) (1 << ((df) + 3))
25
26 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
27 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
28
29 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
30 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
31
32 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
33 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
34
35 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
36 #define SIGNED(x, df) \
37 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
38
39 /* Element-by-element access macros */
40 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
41
42 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
43 {
44 uint32_t i;
45
46 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
47 pwd->d[i] = pws->d[i];
48 }
49 }
50
51 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
52 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
53 uint32_t i8) \
54 { \
55 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
56 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
57 uint32_t i; \
58 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
59 DEST = OPERATION; \
60 } \
61 }
62
63 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
64 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
65 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
66 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
67
68 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
69 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
70 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
71 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
72
73 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
74 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
75 MSA_FN_IMM8(bmzi_b, pwd->b[i],
76 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
77
78 #define BIT_SELECT(dest, arg1, arg2, df) \
79 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
80 MSA_FN_IMM8(bseli_b, pwd->b[i],
81 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
82
83 #undef MSA_FN_IMM8
84
85 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
86
87 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
88 uint32_t ws, uint32_t imm)
89 {
90 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
91 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
92 wr_t wx, *pwx = &wx;
93 uint32_t i;
94
95 switch (df) {
96 case DF_BYTE:
97 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
98 pwx->b[i] = pws->b[SHF_POS(i, imm)];
99 }
100 break;
101 case DF_HALF:
102 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
103 pwx->h[i] = pws->h[SHF_POS(i, imm)];
104 }
105 break;
106 case DF_WORD:
107 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
108 pwx->w[i] = pws->w[SHF_POS(i, imm)];
109 }
110 break;
111 default:
112 assert(0);
113 }
114 msa_move_v(pwd, pwx);
115 }
116
117 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
118 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
119 uint32_t wt) \
120 { \
121 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
122 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
123 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
124 uint32_t i; \
125 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
126 DEST = OPERATION; \
127 } \
128 }
129
130 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
131 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
132 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
133 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
134 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
135 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
136 MSA_FN_VECTOR(bmz_v, pwd->d[i],
137 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
138 MSA_FN_VECTOR(bsel_v, pwd->d[i],
139 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
140 #undef BIT_MOVE_IF_NOT_ZERO
141 #undef BIT_MOVE_IF_ZERO
142 #undef BIT_SELECT
143 #undef MSA_FN_VECTOR
144
145 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
146 {
147 return arg1 + arg2;
148 }
149
150 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
151 {
152 return arg1 - arg2;
153 }
154
155 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
156 {
157 return arg1 == arg2 ? -1 : 0;
158 }
159
160 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
161 {
162 return arg1 <= arg2 ? -1 : 0;
163 }
164
165 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
166 {
167 uint64_t u_arg1 = UNSIGNED(arg1, df);
168 uint64_t u_arg2 = UNSIGNED(arg2, df);
169 return u_arg1 <= u_arg2 ? -1 : 0;
170 }
171
172 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
173 {
174 return arg1 < arg2 ? -1 : 0;
175 }
176
177 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
178 {
179 uint64_t u_arg1 = UNSIGNED(arg1, df);
180 uint64_t u_arg2 = UNSIGNED(arg2, df);
181 return u_arg1 < u_arg2 ? -1 : 0;
182 }
183
184 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
185 {
186 return arg1 > arg2 ? arg1 : arg2;
187 }
188
189 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
190 {
191 uint64_t u_arg1 = UNSIGNED(arg1, df);
192 uint64_t u_arg2 = UNSIGNED(arg2, df);
193 return u_arg1 > u_arg2 ? arg1 : arg2;
194 }
195
196 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
197 {
198 return arg1 < arg2 ? arg1 : arg2;
199 }
200
201 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
202 {
203 uint64_t u_arg1 = UNSIGNED(arg1, df);
204 uint64_t u_arg2 = UNSIGNED(arg2, df);
205 return u_arg1 < u_arg2 ? arg1 : arg2;
206 }
207
208 #define MSA_BINOP_IMM_DF(helper, func) \
209 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
210 uint32_t wd, uint32_t ws, int32_t u5) \
211 { \
212 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
213 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
214 uint32_t i; \
215 \
216 switch (df) { \
217 case DF_BYTE: \
218 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
219 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
220 } \
221 break; \
222 case DF_HALF: \
223 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
224 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
225 } \
226 break; \
227 case DF_WORD: \
228 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
229 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
230 } \
231 break; \
232 case DF_DOUBLE: \
233 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
234 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
235 } \
236 break; \
237 default: \
238 assert(0); \
239 } \
240 }
241
242 MSA_BINOP_IMM_DF(addvi, addv)
243 MSA_BINOP_IMM_DF(subvi, subv)
244 MSA_BINOP_IMM_DF(ceqi, ceq)
245 MSA_BINOP_IMM_DF(clei_s, cle_s)
246 MSA_BINOP_IMM_DF(clei_u, cle_u)
247 MSA_BINOP_IMM_DF(clti_s, clt_s)
248 MSA_BINOP_IMM_DF(clti_u, clt_u)
249 MSA_BINOP_IMM_DF(maxi_s, max_s)
250 MSA_BINOP_IMM_DF(maxi_u, max_u)
251 MSA_BINOP_IMM_DF(mini_s, min_s)
252 MSA_BINOP_IMM_DF(mini_u, min_u)
253 #undef MSA_BINOP_IMM_DF
254
255 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
256 int32_t s10)
257 {
258 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
259 uint32_t i;
260
261 switch (df) {
262 case DF_BYTE:
263 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
264 pwd->b[i] = (int8_t)s10;
265 }
266 break;
267 case DF_HALF:
268 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
269 pwd->h[i] = (int16_t)s10;
270 }
271 break;
272 case DF_WORD:
273 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
274 pwd->w[i] = (int32_t)s10;
275 }
276 break;
277 case DF_DOUBLE:
278 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
279 pwd->d[i] = (int64_t)s10;
280 }
281 break;
282 default:
283 assert(0);
284 }
285 }
286
287 /* Data format bit position and unsigned values */
288 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
289
290 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
291 {
292 int32_t b_arg2 = BIT_POSITION(arg2, df);
293 return arg1 << b_arg2;
294 }
295
296 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
297 {
298 int32_t b_arg2 = BIT_POSITION(arg2, df);
299 return arg1 >> b_arg2;
300 }
301
302 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
303 {
304 uint64_t u_arg1 = UNSIGNED(arg1, df);
305 int32_t b_arg2 = BIT_POSITION(arg2, df);
306 return u_arg1 >> b_arg2;
307 }
308
309 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
310 {
311 int32_t b_arg2 = BIT_POSITION(arg2, df);
312 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
313 }
314
315 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
316 int64_t arg2)
317 {
318 int32_t b_arg2 = BIT_POSITION(arg2, df);
319 return UNSIGNED(arg1 | (1LL << b_arg2), df);
320 }
321
322 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
323 {
324 int32_t b_arg2 = BIT_POSITION(arg2, df);
325 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
326 }
327
328 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
329 int64_t arg2)
330 {
331 uint64_t u_arg1 = UNSIGNED(arg1, df);
332 uint64_t u_dest = UNSIGNED(dest, df);
333 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
334 int32_t sh_a = DF_BITS(df) - sh_d;
335 if (sh_d == DF_BITS(df)) {
336 return u_arg1;
337 } else {
338 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
339 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
340 }
341 }
342
343 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
344 int64_t arg2)
345 {
346 uint64_t u_arg1 = UNSIGNED(arg1, df);
347 uint64_t u_dest = UNSIGNED(dest, df);
348 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
349 int32_t sh_a = DF_BITS(df) - sh_d;
350 if (sh_d == DF_BITS(df)) {
351 return u_arg1;
352 } else {
353 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
354 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
355 }
356 }
357
358 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
359 {
360 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
361 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
362 arg;
363 }
364
365 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
366 {
367 uint64_t u_arg = UNSIGNED(arg, df);
368 return u_arg < M_MAX_UINT(m+1) ? u_arg :
369 M_MAX_UINT(m+1);
370 }
371
372 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
373 {
374 int32_t b_arg2 = BIT_POSITION(arg2, df);
375 if (b_arg2 == 0) {
376 return arg1;
377 } else {
378 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
379 return (arg1 >> b_arg2) + r_bit;
380 }
381 }
382
383 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
384 {
385 uint64_t u_arg1 = UNSIGNED(arg1, df);
386 int32_t b_arg2 = BIT_POSITION(arg2, df);
387 if (b_arg2 == 0) {
388 return u_arg1;
389 } else {
390 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
391 return (u_arg1 >> b_arg2) + r_bit;
392 }
393 }
394
395 #define MSA_BINOP_IMMU_DF(helper, func) \
396 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
397 uint32_t ws, uint32_t u5) \
398 { \
399 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
400 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
401 uint32_t i; \
402 \
403 switch (df) { \
404 case DF_BYTE: \
405 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
406 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
407 } \
408 break; \
409 case DF_HALF: \
410 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
411 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
412 } \
413 break; \
414 case DF_WORD: \
415 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
416 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
417 } \
418 break; \
419 case DF_DOUBLE: \
420 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
421 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
422 } \
423 break; \
424 default: \
425 assert(0); \
426 } \
427 }
428
429 MSA_BINOP_IMMU_DF(slli, sll)
430 MSA_BINOP_IMMU_DF(srai, sra)
431 MSA_BINOP_IMMU_DF(srli, srl)
432 MSA_BINOP_IMMU_DF(bclri, bclr)
433 MSA_BINOP_IMMU_DF(bseti, bset)
434 MSA_BINOP_IMMU_DF(bnegi, bneg)
435 MSA_BINOP_IMMU_DF(sat_s, sat_s)
436 MSA_BINOP_IMMU_DF(sat_u, sat_u)
437 MSA_BINOP_IMMU_DF(srari, srar)
438 MSA_BINOP_IMMU_DF(srlri, srlr)
439 #undef MSA_BINOP_IMMU_DF
440
441 #define MSA_TEROP_IMMU_DF(helper, func) \
442 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
443 uint32_t wd, uint32_t ws, uint32_t u5) \
444 { \
445 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
446 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
447 uint32_t i; \
448 \
449 switch (df) { \
450 case DF_BYTE: \
451 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
452 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
453 u5); \
454 } \
455 break; \
456 case DF_HALF: \
457 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
458 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
459 u5); \
460 } \
461 break; \
462 case DF_WORD: \
463 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
464 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
465 u5); \
466 } \
467 break; \
468 case DF_DOUBLE: \
469 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
470 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
471 u5); \
472 } \
473 break; \
474 default: \
475 assert(0); \
476 } \
477 }
478
479 MSA_TEROP_IMMU_DF(binsli, binsl)
480 MSA_TEROP_IMMU_DF(binsri, binsr)
481 #undef MSA_TEROP_IMMU_DF
482
483 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
484 {
485 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
486 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
487 return abs_arg1 > abs_arg2 ? arg1 : arg2;
488 }
489
490 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
491 {
492 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
493 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
494 return abs_arg1 < abs_arg2 ? arg1 : arg2;
495 }
496
497 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
498 {
499 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
500 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
501 return abs_arg1 + abs_arg2;
502 }
503
504 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
505 {
506 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
507 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
508 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
509 if (abs_arg1 > max_int || abs_arg2 > max_int) {
510 return (int64_t)max_int;
511 } else {
512 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
513 }
514 }
515
516 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
517 {
518 int64_t max_int = DF_MAX_INT(df);
519 int64_t min_int = DF_MIN_INT(df);
520 if (arg1 < 0) {
521 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
522 } else {
523 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
524 }
525 }
526
527 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
528 {
529 uint64_t max_uint = DF_MAX_UINT(df);
530 uint64_t u_arg1 = UNSIGNED(arg1, df);
531 uint64_t u_arg2 = UNSIGNED(arg2, df);
532 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
533 }
534
535 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
536 {
537 /* signed shift */
538 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
539 }
540
541 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
542 {
543 uint64_t u_arg1 = UNSIGNED(arg1, df);
544 uint64_t u_arg2 = UNSIGNED(arg2, df);
545 /* unsigned shift */
546 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
547 }
548
549 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
550 {
551 /* signed shift */
552 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
553 }
554
555 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
556 {
557 uint64_t u_arg1 = UNSIGNED(arg1, df);
558 uint64_t u_arg2 = UNSIGNED(arg2, df);
559 /* unsigned shift */
560 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
561 }
562
563 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
564 {
565 int64_t max_int = DF_MAX_INT(df);
566 int64_t min_int = DF_MIN_INT(df);
567 if (arg2 > 0) {
568 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
569 } else {
570 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
571 }
572 }
573
574 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
575 {
576 uint64_t u_arg1 = UNSIGNED(arg1, df);
577 uint64_t u_arg2 = UNSIGNED(arg2, df);
578 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
579 }
580
581 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
582 {
583 uint64_t u_arg1 = UNSIGNED(arg1, df);
584 uint64_t max_uint = DF_MAX_UINT(df);
585 if (arg2 >= 0) {
586 uint64_t u_arg2 = (uint64_t)arg2;
587 return (u_arg1 > u_arg2) ?
588 (int64_t)(u_arg1 - u_arg2) :
589 0;
590 } else {
591 uint64_t u_arg2 = (uint64_t)(-arg2);
592 return (u_arg1 < max_uint - u_arg2) ?
593 (int64_t)(u_arg1 + u_arg2) :
594 (int64_t)max_uint;
595 }
596 }
597
598 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
599 {
600 uint64_t u_arg1 = UNSIGNED(arg1, df);
601 uint64_t u_arg2 = UNSIGNED(arg2, df);
602 int64_t max_int = DF_MAX_INT(df);
603 int64_t min_int = DF_MIN_INT(df);
604 if (u_arg1 > u_arg2) {
605 return u_arg1 - u_arg2 < (uint64_t)max_int ?
606 (int64_t)(u_arg1 - u_arg2) :
607 max_int;
608 } else {
609 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
610 (int64_t)(u_arg1 - u_arg2) :
611 min_int;
612 }
613 }
614
615 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
616 {
617 /* signed compare */
618 return (arg1 < arg2) ?
619 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
620 }
621
622 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
623 {
624 uint64_t u_arg1 = UNSIGNED(arg1, df);
625 uint64_t u_arg2 = UNSIGNED(arg2, df);
626 /* unsigned compare */
627 return (u_arg1 < u_arg2) ?
628 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
629 }
630
631 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
632 {
633 return arg1 * arg2;
634 }
635
636 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
637 {
638 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
639 return DF_MIN_INT(df);
640 }
641 return arg2 ? arg1 / arg2 : 0;
642 }
643
644 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
645 {
646 uint64_t u_arg1 = UNSIGNED(arg1, df);
647 uint64_t u_arg2 = UNSIGNED(arg2, df);
648 return u_arg2 ? u_arg1 / u_arg2 : 0;
649 }
650
651 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
652 {
653 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
654 return 0;
655 }
656 return arg2 ? arg1 % arg2 : 0;
657 }
658
659 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
660 {
661 uint64_t u_arg1 = UNSIGNED(arg1, df);
662 uint64_t u_arg2 = UNSIGNED(arg2, df);
663 return u_arg2 ? u_arg1 % u_arg2 : 0;
664 }
665
666 #define SIGNED_EVEN(a, df) \
667 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
668
669 #define UNSIGNED_EVEN(a, df) \
670 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
671
672 #define SIGNED_ODD(a, df) \
673 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
674
675 #define UNSIGNED_ODD(a, df) \
676 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
677
678 #define SIGNED_EXTRACT(e, o, a, df) \
679 do { \
680 e = SIGNED_EVEN(a, df); \
681 o = SIGNED_ODD(a, df); \
682 } while (0);
683
684 #define UNSIGNED_EXTRACT(e, o, a, df) \
685 do { \
686 e = UNSIGNED_EVEN(a, df); \
687 o = UNSIGNED_ODD(a, df); \
688 } while (0);
689
690 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
691 {
692 int64_t even_arg1;
693 int64_t even_arg2;
694 int64_t odd_arg1;
695 int64_t odd_arg2;
696 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
697 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
698 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
699 }
700
701 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
702 {
703 int64_t even_arg1;
704 int64_t even_arg2;
705 int64_t odd_arg1;
706 int64_t odd_arg2;
707 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
708 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
709 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
710 }
711
712 #define CONCATENATE_AND_SLIDE(s, k) \
713 do { \
714 for (i = 0; i < s; i++) { \
715 v[i] = pws->b[s * k + i]; \
716 v[i + s] = pwd->b[s * k + i]; \
717 } \
718 for (i = 0; i < s; i++) { \
719 pwd->b[s * k + i] = v[i + n]; \
720 } \
721 } while (0)
722
723 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
724 wr_t *pws, target_ulong rt)
725 {
726 uint32_t n = rt % DF_ELEMENTS(df);
727 uint8_t v[64];
728 uint32_t i, k;
729
730 switch (df) {
731 case DF_BYTE:
732 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
733 break;
734 case DF_HALF:
735 for (k = 0; k < 2; k++) {
736 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
737 }
738 break;
739 case DF_WORD:
740 for (k = 0; k < 4; k++) {
741 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
742 }
743 break;
744 case DF_DOUBLE:
745 for (k = 0; k < 8; k++) {
746 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
747 }
748 break;
749 default:
750 assert(0);
751 }
752 }
753
754 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
755 {
756 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
757 }
758
759 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
760 {
761 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
762 }
763
764 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
765 {
766 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
767 }
768
769 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
770 {
771 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
772 }
773
774 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
775 {
776 int64_t q_min = DF_MIN_INT(df);
777 int64_t q_max = DF_MAX_INT(df);
778
779 if (arg1 == q_min && arg2 == q_min) {
780 return q_max;
781 }
782 return (arg1 * arg2) >> (DF_BITS(df) - 1);
783 }
784
785 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
786 {
787 int64_t q_min = DF_MIN_INT(df);
788 int64_t q_max = DF_MAX_INT(df);
789 int64_t r_bit = 1 << (DF_BITS(df) - 2);
790
791 if (arg1 == q_min && arg2 == q_min) {
792 return q_max;
793 }
794 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
795 }
796
797 #define MSA_BINOP_DF(func) \
798 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
799 uint32_t wd, uint32_t ws, uint32_t wt) \
800 { \
801 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
802 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
803 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
804 uint32_t i; \
805 \
806 switch (df) { \
807 case DF_BYTE: \
808 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
809 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
810 } \
811 break; \
812 case DF_HALF: \
813 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
814 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
815 } \
816 break; \
817 case DF_WORD: \
818 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
819 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
820 } \
821 break; \
822 case DF_DOUBLE: \
823 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
824 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
825 } \
826 break; \
827 default: \
828 assert(0); \
829 } \
830 }
831
832 MSA_BINOP_DF(sll)
833 MSA_BINOP_DF(sra)
834 MSA_BINOP_DF(srl)
835 MSA_BINOP_DF(bclr)
836 MSA_BINOP_DF(bset)
837 MSA_BINOP_DF(bneg)
838 MSA_BINOP_DF(addv)
839 MSA_BINOP_DF(subv)
840 MSA_BINOP_DF(max_s)
841 MSA_BINOP_DF(max_u)
842 MSA_BINOP_DF(min_s)
843 MSA_BINOP_DF(min_u)
844 MSA_BINOP_DF(max_a)
845 MSA_BINOP_DF(min_a)
846 MSA_BINOP_DF(ceq)
847 MSA_BINOP_DF(clt_s)
848 MSA_BINOP_DF(clt_u)
849 MSA_BINOP_DF(cle_s)
850 MSA_BINOP_DF(cle_u)
851 MSA_BINOP_DF(add_a)
852 MSA_BINOP_DF(adds_a)
853 MSA_BINOP_DF(adds_s)
854 MSA_BINOP_DF(adds_u)
855 MSA_BINOP_DF(ave_s)
856 MSA_BINOP_DF(ave_u)
857 MSA_BINOP_DF(aver_s)
858 MSA_BINOP_DF(aver_u)
859 MSA_BINOP_DF(subs_s)
860 MSA_BINOP_DF(subs_u)
861 MSA_BINOP_DF(subsus_u)
862 MSA_BINOP_DF(subsuu_s)
863 MSA_BINOP_DF(asub_s)
864 MSA_BINOP_DF(asub_u)
865 MSA_BINOP_DF(mulv)
866 MSA_BINOP_DF(div_s)
867 MSA_BINOP_DF(div_u)
868 MSA_BINOP_DF(mod_s)
869 MSA_BINOP_DF(mod_u)
870 MSA_BINOP_DF(dotp_s)
871 MSA_BINOP_DF(dotp_u)
872 MSA_BINOP_DF(srar)
873 MSA_BINOP_DF(srlr)
874 MSA_BINOP_DF(hadd_s)
875 MSA_BINOP_DF(hadd_u)
876 MSA_BINOP_DF(hsub_s)
877 MSA_BINOP_DF(hsub_u)
878
879 MSA_BINOP_DF(mul_q)
880 MSA_BINOP_DF(mulr_q)
881 #undef MSA_BINOP_DF
882
883 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
884 uint32_t ws, uint32_t rt)
885 {
886 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
887 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
888
889 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
890 }
891
892 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
893 int64_t arg2)
894 {
895 return dest + arg1 * arg2;
896 }
897
898 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
899 int64_t arg2)
900 {
901 return dest - arg1 * arg2;
902 }
903
904 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
905 int64_t arg2)
906 {
907 int64_t even_arg1;
908 int64_t even_arg2;
909 int64_t odd_arg1;
910 int64_t odd_arg2;
911 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
912 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
913 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
914 }
915
916 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
917 int64_t arg2)
918 {
919 int64_t even_arg1;
920 int64_t even_arg2;
921 int64_t odd_arg1;
922 int64_t odd_arg2;
923 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
924 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
925 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
926 }
927
928 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
929 int64_t arg2)
930 {
931 int64_t even_arg1;
932 int64_t even_arg2;
933 int64_t odd_arg1;
934 int64_t odd_arg2;
935 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
936 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
937 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
938 }
939
940 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
941 int64_t arg2)
942 {
943 int64_t even_arg1;
944 int64_t even_arg2;
945 int64_t odd_arg1;
946 int64_t odd_arg2;
947 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
948 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
949 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
950 }
951
952 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
953 int64_t arg2)
954 {
955 int64_t q_prod, q_ret;
956
957 int64_t q_max = DF_MAX_INT(df);
958 int64_t q_min = DF_MIN_INT(df);
959
960 q_prod = arg1 * arg2;
961 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
962
963 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
964 }
965
966 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
967 int64_t arg2)
968 {
969 int64_t q_prod, q_ret;
970
971 int64_t q_max = DF_MAX_INT(df);
972 int64_t q_min = DF_MIN_INT(df);
973
974 q_prod = arg1 * arg2;
975 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
976
977 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
978 }
979
980 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
981 int64_t arg2)
982 {
983 int64_t q_prod, q_ret;
984
985 int64_t q_max = DF_MAX_INT(df);
986 int64_t q_min = DF_MIN_INT(df);
987 int64_t r_bit = 1 << (DF_BITS(df) - 2);
988
989 q_prod = arg1 * arg2;
990 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
991
992 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
993 }
994
995 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
996 int64_t arg2)
997 {
998 int64_t q_prod, q_ret;
999
1000 int64_t q_max = DF_MAX_INT(df);
1001 int64_t q_min = DF_MIN_INT(df);
1002 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1003
1004 q_prod = arg1 * arg2;
1005 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1006
1007 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1008 }
1009
1010 #define MSA_TEROP_DF(func) \
1011 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1012 uint32_t ws, uint32_t wt) \
1013 { \
1014 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1015 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1016 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1017 uint32_t i; \
1018 \
1019 switch (df) { \
1020 case DF_BYTE: \
1021 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1022 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1023 pwt->b[i]); \
1024 } \
1025 break; \
1026 case DF_HALF: \
1027 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1028 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1029 pwt->h[i]); \
1030 } \
1031 break; \
1032 case DF_WORD: \
1033 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1034 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1035 pwt->w[i]); \
1036 } \
1037 break; \
1038 case DF_DOUBLE: \
1039 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1040 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1041 pwt->d[i]); \
1042 } \
1043 break; \
1044 default: \
1045 assert(0); \
1046 } \
1047 }
1048
1049 MSA_TEROP_DF(maddv)
1050 MSA_TEROP_DF(msubv)
1051 MSA_TEROP_DF(dpadd_s)
1052 MSA_TEROP_DF(dpadd_u)
1053 MSA_TEROP_DF(dpsub_s)
1054 MSA_TEROP_DF(dpsub_u)
1055 MSA_TEROP_DF(binsl)
1056 MSA_TEROP_DF(binsr)
1057 MSA_TEROP_DF(madd_q)
1058 MSA_TEROP_DF(msub_q)
1059 MSA_TEROP_DF(maddr_q)
1060 MSA_TEROP_DF(msubr_q)
1061 #undef MSA_TEROP_DF
1062
1063 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1064 wr_t *pws, target_ulong rt)
1065 {
1066 uint32_t n = rt % DF_ELEMENTS(df);
1067 uint32_t i;
1068
1069 switch (df) {
1070 case DF_BYTE:
1071 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1072 pwd->b[i] = pws->b[n];
1073 }
1074 break;
1075 case DF_HALF:
1076 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1077 pwd->h[i] = pws->h[n];
1078 }
1079 break;
1080 case DF_WORD:
1081 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1082 pwd->w[i] = pws->w[n];
1083 }
1084 break;
1085 case DF_DOUBLE:
1086 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1087 pwd->d[i] = pws->d[n];
1088 }
1089 break;
1090 default:
1091 assert(0);
1092 }
1093 }
1094
1095 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1096 uint32_t ws, uint32_t rt)
1097 {
1098 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1099 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1100
1101 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1102 }
1103
1104 #define MSA_DO_B MSA_DO(b)
1105 #define MSA_DO_H MSA_DO(h)
1106 #define MSA_DO_W MSA_DO(w)
1107 #define MSA_DO_D MSA_DO(d)
1108
1109 #define MSA_LOOP_B MSA_LOOP(B)
1110 #define MSA_LOOP_H MSA_LOOP(H)
1111 #define MSA_LOOP_W MSA_LOOP(W)
1112 #define MSA_LOOP_D MSA_LOOP(D)
1113
1114 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1115 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1116 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1117 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1118
1119 #define MSA_LOOP(DF) \
1120 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1121 MSA_DO_ ## DF \
1122 }
1123
1124 #define MSA_FN_DF(FUNC) \
1125 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1126 uint32_t ws, uint32_t wt) \
1127 { \
1128 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1129 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1130 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1131 wr_t wx, *pwx = &wx; \
1132 uint32_t i; \
1133 switch (df) { \
1134 case DF_BYTE: \
1135 MSA_LOOP_B \
1136 break; \
1137 case DF_HALF: \
1138 MSA_LOOP_H \
1139 break; \
1140 case DF_WORD: \
1141 MSA_LOOP_W \
1142 break; \
1143 case DF_DOUBLE: \
1144 MSA_LOOP_D \
1145 break; \
1146 default: \
1147 assert(0); \
1148 } \
1149 msa_move_v(pwd, pwx); \
1150 }
1151
1152 #define MSA_LOOP_COND(DF) \
1153 (DF_ELEMENTS(DF) / 2)
1154
1155 #define Rb(pwr, i) (pwr->b[i])
1156 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1157 #define Rh(pwr, i) (pwr->h[i])
1158 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1159 #define Rw(pwr, i) (pwr->w[i])
1160 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1161 #define Rd(pwr, i) (pwr->d[i])
1162 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1163
1164 #define MSA_DO(DF) \
1165 do { \
1166 R##DF(pwx, i) = pwt->DF[2*i]; \
1167 L##DF(pwx, i) = pws->DF[2*i]; \
1168 } while (0);
1169 MSA_FN_DF(pckev_df)
1170 #undef MSA_DO
1171
1172 #define MSA_DO(DF) \
1173 do { \
1174 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1175 L##DF(pwx, i) = pws->DF[2*i+1]; \
1176 } while (0);
1177 MSA_FN_DF(pckod_df)
1178 #undef MSA_DO
1179
1180 #define MSA_DO(DF) \
1181 do { \
1182 pwx->DF[2*i] = L##DF(pwt, i); \
1183 pwx->DF[2*i+1] = L##DF(pws, i); \
1184 } while (0);
1185 MSA_FN_DF(ilvl_df)
1186 #undef MSA_DO
1187
1188 #define MSA_DO(DF) \
1189 do { \
1190 pwx->DF[2*i] = R##DF(pwt, i); \
1191 pwx->DF[2*i+1] = R##DF(pws, i); \
1192 } while (0);
1193 MSA_FN_DF(ilvr_df)
1194 #undef MSA_DO
1195
1196 #define MSA_DO(DF) \
1197 do { \
1198 pwx->DF[2*i] = pwt->DF[2*i]; \
1199 pwx->DF[2*i+1] = pws->DF[2*i]; \
1200 } while (0);
1201 MSA_FN_DF(ilvev_df)
1202 #undef MSA_DO
1203
1204 #define MSA_DO(DF) \
1205 do { \
1206 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1207 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1208 } while (0);
1209 MSA_FN_DF(ilvod_df)
1210 #undef MSA_DO
1211 #undef MSA_LOOP_COND
1212
1213 #define MSA_LOOP_COND(DF) \
1214 (DF_ELEMENTS(DF))
1215
1216 #define MSA_DO(DF) \
1217 do { \
1218 uint32_t n = DF_ELEMENTS(df); \
1219 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1220 pwx->DF[i] = \
1221 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1222 } while (0);
1223 MSA_FN_DF(vshf_df)
1224 #undef MSA_DO
1225 #undef MSA_LOOP_COND
1226 #undef MSA_FN_DF
1227
1228 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1229 uint32_t ws, uint32_t n)
1230 {
1231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1233
1234 msa_sld_df(df, pwd, pws, n);
1235 }
1236
1237 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1238 uint32_t ws, uint32_t n)
1239 {
1240 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1241 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1242
1243 msa_splat_df(df, pwd, pws, n);
1244 }
1245
1246 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1247 uint32_t ws, uint32_t n)
1248 {
1249 n %= DF_ELEMENTS(df);
1250
1251 switch (df) {
1252 case DF_BYTE:
1253 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1254 break;
1255 case DF_HALF:
1256 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1257 break;
1258 case DF_WORD:
1259 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1260 break;
1261 #ifdef TARGET_MIPS64
1262 case DF_DOUBLE:
1263 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1264 break;
1265 #endif
1266 default:
1267 assert(0);
1268 }
1269 }
1270
1271 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1272 uint32_t ws, uint32_t n)
1273 {
1274 n %= DF_ELEMENTS(df);
1275
1276 switch (df) {
1277 case DF_BYTE:
1278 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1279 break;
1280 case DF_HALF:
1281 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1282 break;
1283 case DF_WORD:
1284 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1285 break;
1286 #ifdef TARGET_MIPS64
1287 case DF_DOUBLE:
1288 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1289 break;
1290 #endif
1291 default:
1292 assert(0);
1293 }
1294 }
1295
1296 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1297 uint32_t rs_num, uint32_t n)
1298 {
1299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1300 target_ulong rs = env->active_tc.gpr[rs_num];
1301
1302 switch (df) {
1303 case DF_BYTE:
1304 pwd->b[n] = (int8_t)rs;
1305 break;
1306 case DF_HALF:
1307 pwd->h[n] = (int16_t)rs;
1308 break;
1309 case DF_WORD:
1310 pwd->w[n] = (int32_t)rs;
1311 break;
1312 case DF_DOUBLE:
1313 pwd->d[n] = (int64_t)rs;
1314 break;
1315 default:
1316 assert(0);
1317 }
1318 }
1319
1320 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1321 uint32_t ws, uint32_t n)
1322 {
1323 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1324 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1325
1326 switch (df) {
1327 case DF_BYTE:
1328 pwd->b[n] = (int8_t)pws->b[0];
1329 break;
1330 case DF_HALF:
1331 pwd->h[n] = (int16_t)pws->h[0];
1332 break;
1333 case DF_WORD:
1334 pwd->w[n] = (int32_t)pws->w[0];
1335 break;
1336 case DF_DOUBLE:
1337 pwd->d[n] = (int64_t)pws->d[0];
1338 break;
1339 default:
1340 assert(0);
1341 }
1342 }
1343
1344 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1345 {
1346 switch (cd) {
1347 case 0:
1348 break;
1349 case 1:
1350 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1351 restore_msa_fp_status(env);
1352 /* check exception */
1353 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1354 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1355 helper_raise_exception(env, EXCP_MSAFPE);
1356 }
1357 break;
1358 }
1359 }
1360
1361 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1362 {
1363 switch (cs) {
1364 case 0:
1365 return env->msair;
1366 case 1:
1367 return env->active_tc.msacsr & MSACSR_MASK;
1368 }
1369 return 0;
1370 }
1371
1372 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1373 {
1374 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1375 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1376
1377 msa_move_v(pwd, pws);
1378 }
1379
1380 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1381 {
1382 uint64_t x;
1383
1384 x = UNSIGNED(arg, df);
1385
1386 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1387 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1388 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1389 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1390 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1391 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1392
1393 return x;
1394 }
1395
1396 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1397 {
1398 uint64_t x, y;
1399 int n, c;
1400
1401 x = UNSIGNED(arg, df);
1402 n = DF_BITS(df);
1403 c = DF_BITS(df) / 2;
1404
1405 do {
1406 y = x >> c;
1407 if (y != 0) {
1408 n = n - c;
1409 x = y;
1410 }
1411 c = c >> 1;
1412 } while (c != 0);
1413
1414 return n - x;
1415 }
1416
1417 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1418 {
1419 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1420 }
1421
1422 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1423 uint32_t rs)
1424 {
1425 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1426 uint32_t i;
1427
1428 switch (df) {
1429 case DF_BYTE:
1430 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1431 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1432 }
1433 break;
1434 case DF_HALF:
1435 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1436 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1437 }
1438 break;
1439 case DF_WORD:
1440 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1441 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1442 }
1443 break;
1444 case DF_DOUBLE:
1445 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1446 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1447 }
1448 break;
1449 default:
1450 assert(0);
1451 }
1452 }
1453
1454 #define MSA_UNOP_DF(func) \
1455 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1456 uint32_t wd, uint32_t ws) \
1457 { \
1458 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1459 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1460 uint32_t i; \
1461 \
1462 switch (df) { \
1463 case DF_BYTE: \
1464 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1465 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1466 } \
1467 break; \
1468 case DF_HALF: \
1469 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1470 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1471 } \
1472 break; \
1473 case DF_WORD: \
1474 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1475 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1476 } \
1477 break; \
1478 case DF_DOUBLE: \
1479 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1480 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1481 } \
1482 break; \
1483 default: \
1484 assert(0); \
1485 } \
1486 }
1487
1488 MSA_UNOP_DF(nlzc)
1489 MSA_UNOP_DF(nloc)
1490 MSA_UNOP_DF(pcnt)
1491 #undef MSA_UNOP_DF
1492
1493 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1494 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1495
1496 #define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
1497 /* 0x7c20 */
1498 #define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
1499 /* 0x7f800020 */
1500 #define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
1501 /* 0x7ff0000000000020 */
1502
1503 static inline void clear_msacsr_cause(CPUMIPSState *env)
1504 {
1505 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1506 }
1507
1508 static inline void check_msacsr_cause(CPUMIPSState *env)
1509 {
1510 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1511 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1512 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1513 GET_FP_CAUSE(env->active_tc.msacsr));
1514 } else {
1515 helper_raise_exception(env, EXCP_MSAFPE);
1516 }
1517 }
1518
1519 /* Flush-to-zero use cases for update_msacsr() */
1520 #define CLEAR_FS_UNDERFLOW 1
1521 #define CLEAR_IS_INEXACT 2
1522 #define RECIPROCAL_INEXACT 4
1523
1524 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1525 {
1526 int ieee_ex;
1527
1528 int c;
1529 int cause;
1530 int enable;
1531
1532 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1533
1534 /* QEMU softfloat does not signal all underflow cases */
1535 if (denormal) {
1536 ieee_ex |= float_flag_underflow;
1537 }
1538
1539 c = ieee_ex_to_mips(ieee_ex);
1540 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1541
1542 /* Set Inexact (I) when flushing inputs to zero */
1543 if ((ieee_ex & float_flag_input_denormal) &&
1544 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1545 if (action & CLEAR_IS_INEXACT) {
1546 c &= ~FP_INEXACT;
1547 } else {
1548 c |= FP_INEXACT;
1549 }
1550 }
1551
1552 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1553 if ((ieee_ex & float_flag_output_denormal) &&
1554 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1555 c |= FP_INEXACT;
1556 if (action & CLEAR_FS_UNDERFLOW) {
1557 c &= ~FP_UNDERFLOW;
1558 } else {
1559 c |= FP_UNDERFLOW;
1560 }
1561 }
1562
1563 /* Set Inexact (I) when Overflow (O) is not enabled */
1564 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1565 c |= FP_INEXACT;
1566 }
1567
1568 /* Clear Exact Underflow when Underflow (U) is not enabled */
1569 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1570 (c & FP_INEXACT) == 0) {
1571 c &= ~FP_UNDERFLOW;
1572 }
1573
1574 /* Reciprocal operations set only Inexact when valid and not
1575 divide by zero */
1576 if ((action & RECIPROCAL_INEXACT) &&
1577 (c & (FP_INVALID | FP_DIV0)) == 0) {
1578 c = FP_INEXACT;
1579 }
1580
1581 cause = c & enable; /* all current enabled exceptions */
1582
1583 if (cause == 0) {
1584 /* No enabled exception, update the MSACSR Cause
1585 with all current exceptions */
1586 SET_FP_CAUSE(env->active_tc.msacsr,
1587 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1588 } else {
1589 /* Current exceptions are enabled */
1590 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1591 /* Exception(s) will trap, update MSACSR Cause
1592 with all enabled exceptions */
1593 SET_FP_CAUSE(env->active_tc.msacsr,
1594 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1595 }
1596 }
1597
1598 return c;
1599 }
1600
1601 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1602 {
1603 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1604 return c & enable;
1605 }
1606
1607 static inline float16 float16_from_float32(int32 a, flag ieee,
1608 float_status *status)
1609 {
1610 float16 f_val;
1611
1612 f_val = float32_to_float16((float32)a, ieee, status);
1613 f_val = float16_maybe_silence_nan(f_val);
1614
1615 return a < 0 ? (f_val | (1 << 15)) : f_val;
1616 }
1617
1618 static inline float32 float32_from_float64(int64 a, float_status *status)
1619 {
1620 float32 f_val;
1621
1622 f_val = float64_to_float32((float64)a, status);
1623 f_val = float32_maybe_silence_nan(f_val);
1624
1625 return a < 0 ? (f_val | (1 << 31)) : f_val;
1626 }
1627
1628 static inline float32 float32_from_float16(int16_t a, flag ieee,
1629 float_status *status)
1630 {
1631 float32 f_val;
1632
1633 f_val = float16_to_float32((float16)a, ieee, status);
1634 f_val = float32_maybe_silence_nan(f_val);
1635
1636 return a < 0 ? (f_val | (1 << 31)) : f_val;
1637 }
1638
1639 static inline float64 float64_from_float32(int32 a, float_status *status)
1640 {
1641 float64 f_val;
1642
1643 f_val = float32_to_float64((float64)a, status);
1644 f_val = float64_maybe_silence_nan(f_val);
1645
1646 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1647 }
1648
1649 static inline float32 float32_from_q16(int16_t a, float_status *status)
1650 {
1651 float32 f_val;
1652
1653 /* conversion as integer and scaling */
1654 f_val = int32_to_float32(a, status);
1655 f_val = float32_scalbn(f_val, -15, status);
1656
1657 return f_val;
1658 }
1659
1660 static inline float64 float64_from_q32(int32 a, float_status *status)
1661 {
1662 float64 f_val;
1663
1664 /* conversion as integer and scaling */
1665 f_val = int32_to_float64(a, status);
1666 f_val = float64_scalbn(f_val, -31, status);
1667
1668 return f_val;
1669 }
1670
1671 static inline int16_t float32_to_q16(float32 a, float_status *status)
1672 {
1673 int32 q_val;
1674 int32 q_min = 0xffff8000;
1675 int32 q_max = 0x00007fff;
1676
1677 int ieee_ex;
1678
1679 if (float32_is_any_nan(a)) {
1680 float_raise(float_flag_invalid, status);
1681 return 0;
1682 }
1683
1684 /* scaling */
1685 a = float32_scalbn(a, 15, status);
1686
1687 ieee_ex = get_float_exception_flags(status);
1688 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1689 , status);
1690
1691 if (ieee_ex & float_flag_overflow) {
1692 float_raise(float_flag_inexact, status);
1693 return (int32)a < 0 ? q_min : q_max;
1694 }
1695
1696 /* conversion to int */
1697 q_val = float32_to_int32(a, status);
1698
1699 ieee_ex = get_float_exception_flags(status);
1700 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1701 , status);
1702
1703 if (ieee_ex & float_flag_invalid) {
1704 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1705 , status);
1706 float_raise(float_flag_overflow | float_flag_inexact, status);
1707 return (int32)a < 0 ? q_min : q_max;
1708 }
1709
1710 if (q_val < q_min) {
1711 float_raise(float_flag_overflow | float_flag_inexact, status);
1712 return (int16_t)q_min;
1713 }
1714
1715 if (q_max < q_val) {
1716 float_raise(float_flag_overflow | float_flag_inexact, status);
1717 return (int16_t)q_max;
1718 }
1719
1720 return (int16_t)q_val;
1721 }
1722
1723 static inline int32 float64_to_q32(float64 a, float_status *status)
1724 {
1725 int64 q_val;
1726 int64 q_min = 0xffffffff80000000LL;
1727 int64 q_max = 0x000000007fffffffLL;
1728
1729 int ieee_ex;
1730
1731 if (float64_is_any_nan(a)) {
1732 float_raise(float_flag_invalid, status);
1733 return 0;
1734 }
1735
1736 /* scaling */
1737 a = float64_scalbn(a, 31, status);
1738
1739 ieee_ex = get_float_exception_flags(status);
1740 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1741 , status);
1742
1743 if (ieee_ex & float_flag_overflow) {
1744 float_raise(float_flag_inexact, status);
1745 return (int64)a < 0 ? q_min : q_max;
1746 }
1747
1748 /* conversion to integer */
1749 q_val = float64_to_int64(a, status);
1750
1751 ieee_ex = get_float_exception_flags(status);
1752 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1753 , status);
1754
1755 if (ieee_ex & float_flag_invalid) {
1756 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1757 , status);
1758 float_raise(float_flag_overflow | float_flag_inexact, status);
1759 return (int64)a < 0 ? q_min : q_max;
1760 }
1761
1762 if (q_val < q_min) {
1763 float_raise(float_flag_overflow | float_flag_inexact, status);
1764 return (int32)q_min;
1765 }
1766
1767 if (q_max < q_val) {
1768 float_raise(float_flag_overflow | float_flag_inexact, status);
1769 return (int32)q_max;
1770 }
1771
1772 return (int32)q_val;
1773 }
1774
1775 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1776 do { \
1777 float_status *status = &env->active_tc.msa_fp_status; \
1778 int c; \
1779 int64_t cond; \
1780 set_float_exception_flags(0, status); \
1781 if (!QUIET) { \
1782 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1783 } else { \
1784 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1785 } \
1786 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1787 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1788 \
1789 if (get_enabled_exceptions(env, c)) { \
1790 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
1791 } \
1792 } while (0)
1793
1794 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1795 do { \
1796 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1797 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1798 DEST = 0; \
1799 } \
1800 } while (0)
1801
1802 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1803 do { \
1804 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1805 if (DEST == 0) { \
1806 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1807 } \
1808 } while (0)
1809
1810 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1811 do { \
1812 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1813 if (DEST == 0) { \
1814 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1815 } \
1816 } while (0)
1817
1818 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1819 do { \
1820 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1821 if (DEST == 0) { \
1822 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1823 if (DEST == 0) { \
1824 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1825 } \
1826 } \
1827 } while (0)
1828
1829 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1830 do { \
1831 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1832 if (DEST == 0) { \
1833 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1834 } \
1835 } while (0)
1836
1837 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1838 do { \
1839 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1840 if (DEST == 0) { \
1841 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1842 } \
1843 } while (0)
1844
1845 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1846 do { \
1847 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1848 if (DEST == 0) { \
1849 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1850 } \
1851 } while (0)
1852
1853 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1854 wr_t *pwt, uint32_t df, int quiet)
1855 {
1856 wr_t wx, *pwx = &wx;
1857 uint32_t i;
1858
1859 clear_msacsr_cause(env);
1860
1861 switch (df) {
1862 case DF_WORD:
1863 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1864 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1865 }
1866 break;
1867 case DF_DOUBLE:
1868 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1869 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1870 }
1871 break;
1872 default:
1873 assert(0);
1874 }
1875
1876 check_msacsr_cause(env);
1877
1878 msa_move_v(pwd, pwx);
1879 }
1880
1881 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1882 wr_t *pwt, uint32_t df, int quiet)
1883 {
1884 wr_t wx, *pwx = &wx;
1885 uint32_t i;
1886
1887 clear_msacsr_cause(env);
1888
1889 switch (df) {
1890 case DF_WORD:
1891 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1892 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1893 quiet);
1894 }
1895 break;
1896 case DF_DOUBLE:
1897 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1898 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1899 quiet);
1900 }
1901 break;
1902 default:
1903 assert(0);
1904 }
1905
1906 check_msacsr_cause(env);
1907
1908 msa_move_v(pwd, pwx);
1909 }
1910
1911 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1912 wr_t *pwt, uint32_t df, int quiet)
1913 {
1914 wr_t wx, *pwx = &wx;
1915 uint32_t i;
1916
1917 clear_msacsr_cause(env);
1918
1919 switch (df) {
1920 case DF_WORD:
1921 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1922 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1923 }
1924 break;
1925 case DF_DOUBLE:
1926 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1927 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1928 }
1929 break;
1930 default:
1931 assert(0);
1932 }
1933
1934 check_msacsr_cause(env);
1935
1936 msa_move_v(pwd, pwx);
1937 }
1938
1939 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1940 wr_t *pwt, uint32_t df, int quiet)
1941 {
1942 wr_t wx, *pwx = &wx;
1943 uint32_t i;
1944
1945 clear_msacsr_cause(env);
1946
1947 switch (df) {
1948 case DF_WORD:
1949 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1950 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1951 }
1952 break;
1953 case DF_DOUBLE:
1954 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1955 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1956 }
1957 break;
1958 default:
1959 assert(0);
1960 }
1961
1962 check_msacsr_cause(env);
1963
1964 msa_move_v(pwd, pwx);
1965 }
1966
1967 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1968 wr_t *pwt, uint32_t df, int quiet)
1969 {
1970 wr_t wx, *pwx = &wx;
1971 uint32_t i;
1972
1973 clear_msacsr_cause(env);
1974
1975 switch (df) {
1976 case DF_WORD:
1977 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1978 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1979 }
1980 break;
1981 case DF_DOUBLE:
1982 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1983 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1984 }
1985 break;
1986 default:
1987 assert(0);
1988 }
1989
1990 check_msacsr_cause(env);
1991
1992 msa_move_v(pwd, pwx);
1993 }
1994
1995 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1996 wr_t *pwt, uint32_t df, int quiet)
1997 {
1998 wr_t wx, *pwx = &wx;
1999 uint32_t i;
2000
2001 clear_msacsr_cause(env);
2002
2003 switch (df) {
2004 case DF_WORD:
2005 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2006 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2007 }
2008 break;
2009 case DF_DOUBLE:
2010 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2011 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2012 }
2013 break;
2014 default:
2015 assert(0);
2016 }
2017
2018 check_msacsr_cause(env);
2019
2020 msa_move_v(pwd, pwx);
2021 }
2022
2023 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2024 wr_t *pwt, uint32_t df, int quiet)
2025 {
2026 wr_t wx, *pwx = &wx;
2027 uint32_t i;
2028
2029 clear_msacsr_cause(env);
2030
2031 switch (df) {
2032 case DF_WORD:
2033 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2034 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2035 }
2036 break;
2037 case DF_DOUBLE:
2038 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2039 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2040 }
2041 break;
2042 default:
2043 assert(0);
2044 }
2045
2046 check_msacsr_cause(env);
2047
2048 msa_move_v(pwd, pwx);
2049 }
2050
2051 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2052 wr_t *pwt, uint32_t df, int quiet)
2053 {
2054 wr_t wx, *pwx = &wx;
2055 uint32_t i;
2056
2057 clear_msacsr_cause(env);
2058
2059 switch (df) {
2060 case DF_WORD:
2061 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2062 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2063 }
2064 break;
2065 case DF_DOUBLE:
2066 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2067 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2068 }
2069 break;
2070 default:
2071 assert(0);
2072 }
2073
2074 check_msacsr_cause(env);
2075
2076 msa_move_v(pwd, pwx);
2077 }
2078
2079 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2080 wr_t *pwt, uint32_t df, int quiet)
2081 {
2082 wr_t wx, *pwx = &wx;
2083 uint32_t i;
2084
2085 clear_msacsr_cause(env);
2086
2087 switch (df) {
2088 case DF_WORD:
2089 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2090 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2091 }
2092 break;
2093 case DF_DOUBLE:
2094 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2095 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2096 }
2097 break;
2098 default:
2099 assert(0);
2100 }
2101
2102 check_msacsr_cause(env);
2103
2104 msa_move_v(pwd, pwx);
2105 }
2106
2107 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2108 wr_t *pwt, uint32_t df, int quiet)
2109 {
2110 wr_t wx, *pwx = &wx;
2111 uint32_t i;
2112
2113 clear_msacsr_cause(env);
2114
2115 switch (df) {
2116 case DF_WORD:
2117 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2118 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2119 }
2120 break;
2121 case DF_DOUBLE:
2122 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2123 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2124 }
2125 break;
2126 default:
2127 assert(0);
2128 }
2129
2130 check_msacsr_cause(env);
2131
2132 msa_move_v(pwd, pwx);
2133 }
2134
2135 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2136 wr_t *pwt, uint32_t df, int quiet) {
2137 wr_t wx, *pwx = &wx;
2138 uint32_t i;
2139
2140 clear_msacsr_cause(env);
2141
2142 switch (df) {
2143 case DF_WORD:
2144 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2145 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2146 }
2147 break;
2148 case DF_DOUBLE:
2149 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2150 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2151 }
2152 break;
2153 default:
2154 assert(0);
2155 }
2156
2157 check_msacsr_cause(env);
2158
2159 msa_move_v(pwd, pwx);
2160 }
2161
2162 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2163 uint32_t ws, uint32_t wt)
2164 {
2165 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2166 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2167 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2168 compare_af(env, pwd, pws, pwt, df, 1);
2169 }
2170
2171 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2172 uint32_t ws, uint32_t wt)
2173 {
2174 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2175 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2176 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2177 compare_un(env, pwd, pws, pwt, df, 1);
2178 }
2179
2180 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2181 uint32_t ws, uint32_t wt)
2182 {
2183 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2184 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2185 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2186 compare_eq(env, pwd, pws, pwt, df, 1);
2187 }
2188
2189 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2190 uint32_t ws, uint32_t wt)
2191 {
2192 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2193 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2194 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2195 compare_ueq(env, pwd, pws, pwt, df, 1);
2196 }
2197
2198 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2199 uint32_t ws, uint32_t wt)
2200 {
2201 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2202 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2203 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2204 compare_lt(env, pwd, pws, pwt, df, 1);
2205 }
2206
2207 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2208 uint32_t ws, uint32_t wt)
2209 {
2210 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2211 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2212 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2213 compare_ult(env, pwd, pws, pwt, df, 1);
2214 }
2215
2216 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2217 uint32_t ws, uint32_t wt)
2218 {
2219 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2220 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2221 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2222 compare_le(env, pwd, pws, pwt, df, 1);
2223 }
2224
2225 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2226 uint32_t ws, uint32_t wt)
2227 {
2228 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2229 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2230 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2231 compare_ule(env, pwd, pws, pwt, df, 1);
2232 }
2233
2234 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2235 uint32_t ws, uint32_t wt)
2236 {
2237 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2238 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2239 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2240 compare_af(env, pwd, pws, pwt, df, 0);
2241 }
2242
2243 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2244 uint32_t ws, uint32_t wt)
2245 {
2246 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2247 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2248 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2249 compare_un(env, pwd, pws, pwt, df, 0);
2250 }
2251
2252 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2253 uint32_t ws, uint32_t wt)
2254 {
2255 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2256 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2257 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2258 compare_eq(env, pwd, pws, pwt, df, 0);
2259 }
2260
2261 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2262 uint32_t ws, uint32_t wt)
2263 {
2264 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2265 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2266 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2267 compare_ueq(env, pwd, pws, pwt, df, 0);
2268 }
2269
2270 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2271 uint32_t ws, uint32_t wt)
2272 {
2273 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2274 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2275 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2276 compare_lt(env, pwd, pws, pwt, df, 0);
2277 }
2278
2279 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2280 uint32_t ws, uint32_t wt)
2281 {
2282 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2283 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2284 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2285 compare_ult(env, pwd, pws, pwt, df, 0);
2286 }
2287
2288 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2289 uint32_t ws, uint32_t wt)
2290 {
2291 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2292 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2293 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2294 compare_le(env, pwd, pws, pwt, df, 0);
2295 }
2296
2297 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2298 uint32_t ws, uint32_t wt)
2299 {
2300 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2301 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2302 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2303 compare_ule(env, pwd, pws, pwt, df, 0);
2304 }
2305
2306 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2307 uint32_t ws, uint32_t wt)
2308 {
2309 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2310 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2311 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2312 compare_or(env, pwd, pws, pwt, df, 1);
2313 }
2314
2315 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2316 uint32_t ws, uint32_t wt)
2317 {
2318 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2319 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2320 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2321 compare_une(env, pwd, pws, pwt, df, 1);
2322 }
2323
2324 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2325 uint32_t ws, uint32_t wt)
2326 {
2327 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2328 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2329 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2330 compare_ne(env, pwd, pws, pwt, df, 1);
2331 }
2332
2333 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2334 uint32_t ws, uint32_t wt)
2335 {
2336 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2337 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2338 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2339 compare_or(env, pwd, pws, pwt, df, 0);
2340 }
2341
2342 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2343 uint32_t ws, uint32_t wt)
2344 {
2345 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2346 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2347 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2348 compare_une(env, pwd, pws, pwt, df, 0);
2349 }
2350
2351 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2352 uint32_t ws, uint32_t wt)
2353 {
2354 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2355 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2356 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2357 compare_ne(env, pwd, pws, pwt, df, 0);
2358 }
2359
2360 #define float16_is_zero(ARG) 0
2361 #define float16_is_zero_or_denormal(ARG) 0
2362
2363 #define IS_DENORMAL(ARG, BITS) \
2364 (!float ## BITS ## _is_zero(ARG) \
2365 && float ## BITS ## _is_zero_or_denormal(ARG))
2366
2367 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2368 do { \
2369 float_status *status = &env->active_tc.msa_fp_status; \
2370 int c; \
2371 \
2372 set_float_exception_flags(0, status); \
2373 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2374 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2375 \
2376 if (get_enabled_exceptions(env, c)) { \
2377 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2378 } \
2379 } while (0)
2380
2381 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2382 uint32_t ws, uint32_t wt)
2383 {
2384 wr_t wx, *pwx = &wx;
2385 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2386 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2387 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2388 uint32_t i;
2389
2390 clear_msacsr_cause(env);
2391
2392 switch (df) {
2393 case DF_WORD:
2394 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2395 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2396 }
2397 break;
2398 case DF_DOUBLE:
2399 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2400 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2401 }
2402 break;
2403 default:
2404 assert(0);
2405 }
2406
2407 check_msacsr_cause(env);
2408 msa_move_v(pwd, pwx);
2409 }
2410
2411 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2412 uint32_t ws, uint32_t wt)
2413 {
2414 wr_t wx, *pwx = &wx;
2415 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2416 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2417 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2418 uint32_t i;
2419
2420 clear_msacsr_cause(env);
2421
2422 switch (df) {
2423 case DF_WORD:
2424 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2425 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2426 }
2427 break;
2428 case DF_DOUBLE:
2429 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2430 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2431 }
2432 break;
2433 default:
2434 assert(0);
2435 }
2436
2437 check_msacsr_cause(env);
2438 msa_move_v(pwd, pwx);
2439 }
2440
2441 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2442 uint32_t ws, uint32_t wt)
2443 {
2444 wr_t wx, *pwx = &wx;
2445 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2446 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2447 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2448 uint32_t i;
2449
2450 clear_msacsr_cause(env);
2451
2452 switch (df) {
2453 case DF_WORD:
2454 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2455 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2456 }
2457 break;
2458 case DF_DOUBLE:
2459 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2460 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2461 }
2462 break;
2463 default:
2464 assert(0);
2465 }
2466
2467 check_msacsr_cause(env);
2468
2469 msa_move_v(pwd, pwx);
2470 }
2471
2472 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2473 uint32_t ws, uint32_t wt)
2474 {
2475 wr_t wx, *pwx = &wx;
2476 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2477 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2478 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2479 uint32_t i;
2480
2481 clear_msacsr_cause(env);
2482
2483 switch (df) {
2484 case DF_WORD:
2485 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2486 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2487 }
2488 break;
2489 case DF_DOUBLE:
2490 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2491 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2492 }
2493 break;
2494 default:
2495 assert(0);
2496 }
2497
2498 check_msacsr_cause(env);
2499
2500 msa_move_v(pwd, pwx);
2501 }
2502
2503 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2504 do { \
2505 float_status *status = &env->active_tc.msa_fp_status; \
2506 int c; \
2507 \
2508 set_float_exception_flags(0, status); \
2509 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2510 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2511 \
2512 if (get_enabled_exceptions(env, c)) { \
2513 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2514 } \
2515 } while (0)
2516
2517 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2518 uint32_t ws, uint32_t wt)
2519 {
2520 wr_t wx, *pwx = &wx;
2521 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2522 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2523 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2524 uint32_t i;
2525
2526 clear_msacsr_cause(env);
2527
2528 switch (df) {
2529 case DF_WORD:
2530 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2531 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2532 pws->w[i], pwt->w[i], 0, 32);
2533 }
2534 break;
2535 case DF_DOUBLE:
2536 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2537 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2538 pws->d[i], pwt->d[i], 0, 64);
2539 }
2540 break;
2541 default:
2542 assert(0);
2543 }
2544
2545 check_msacsr_cause(env);
2546
2547 msa_move_v(pwd, pwx);
2548 }
2549
2550 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2551 uint32_t ws, uint32_t wt)
2552 {
2553 wr_t wx, *pwx = &wx;
2554 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2555 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2556 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2557 uint32_t i;
2558
2559 clear_msacsr_cause(env);
2560
2561 switch (df) {
2562 case DF_WORD:
2563 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2564 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2565 pws->w[i], pwt->w[i],
2566 float_muladd_negate_product, 32);
2567 }
2568 break;
2569 case DF_DOUBLE:
2570 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2571 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2572 pws->d[i], pwt->d[i],
2573 float_muladd_negate_product, 64);
2574 }
2575 break;
2576 default:
2577 assert(0);
2578 }
2579
2580 check_msacsr_cause(env);
2581
2582 msa_move_v(pwd, pwx);
2583 }
2584
2585 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2586 uint32_t ws, uint32_t wt)
2587 {
2588 wr_t wx, *pwx = &wx;
2589 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2590 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2591 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2592 uint32_t i;
2593
2594 clear_msacsr_cause(env);
2595
2596 switch (df) {
2597 case DF_WORD:
2598 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2599 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2600 pwt->w[i] > 0x200 ? 0x200 :
2601 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2602 32);
2603 }
2604 break;
2605 case DF_DOUBLE:
2606 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2607 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2608 pwt->d[i] > 0x1000 ? 0x1000 :
2609 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2610 64);
2611 }
2612 break;
2613 default:
2614 assert(0);
2615 }
2616
2617 check_msacsr_cause(env);
2618
2619 msa_move_v(pwd, pwx);
2620 }
2621
2622 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2623 do { \
2624 float_status *status = &env->active_tc.msa_fp_status; \
2625 int c; \
2626 \
2627 set_float_exception_flags(0, status); \
2628 DEST = float ## BITS ## _ ## OP(ARG, status); \
2629 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2630 \
2631 if (get_enabled_exceptions(env, c)) { \
2632 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2633 } \
2634 } while (0)
2635
2636 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2637 uint32_t ws, uint32_t wt)
2638 {
2639 wr_t wx, *pwx = &wx;
2640 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2641 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2642 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2643 uint32_t i;
2644
2645 switch (df) {
2646 case DF_WORD:
2647 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2648 /* Half precision floats come in two formats: standard
2649 IEEE and "ARM" format. The latter gains extra exponent
2650 range by omitting the NaN/Inf encodings. */
2651 flag ieee = 1;
2652
2653 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2654 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2655 }
2656 break;
2657 case DF_DOUBLE:
2658 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2659 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2660 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2661 }
2662 break;
2663 default:
2664 assert(0);
2665 }
2666
2667 check_msacsr_cause(env);
2668 msa_move_v(pwd, pwx);
2669 }
2670
2671 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2672 do { \
2673 float_status *status = &env->active_tc.msa_fp_status; \
2674 int c; \
2675 \
2676 set_float_exception_flags(0, status); \
2677 DEST = float ## BITS ## _ ## OP(ARG, status); \
2678 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2679 \
2680 if (get_enabled_exceptions(env, c)) { \
2681 DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
2682 } \
2683 } while (0)
2684
2685 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2686 uint32_t ws, uint32_t wt)
2687 {
2688 wr_t wx, *pwx = &wx;
2689 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2690 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2691 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2692 uint32_t i;
2693
2694 clear_msacsr_cause(env);
2695
2696 switch (df) {
2697 case DF_WORD:
2698 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2699 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2700 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2701 }
2702 break;
2703 case DF_DOUBLE:
2704 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2705 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2706 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2707 }
2708 break;
2709 default:
2710 assert(0);
2711 }
2712
2713 check_msacsr_cause(env);
2714
2715 msa_move_v(pwd, pwx);
2716 }
2717
2718 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
2719 !float ## BITS ## _is_any_nan(ARG1) \
2720 && float ## BITS ## _is_quiet_nan(ARG2)
2721
2722 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2723 do { \
2724 float_status *status = &env->active_tc.msa_fp_status; \
2725 int c; \
2726 \
2727 set_float_exception_flags(0, status); \
2728 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2729 c = update_msacsr(env, 0, 0); \
2730 \
2731 if (get_enabled_exceptions(env, c)) { \
2732 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2733 } \
2734 } while (0)
2735
2736 #define FMAXMIN_A(F, G, X, _S, _T, BITS) \
2737 do { \
2738 uint## BITS ##_t S = _S, T = _T; \
2739 uint## BITS ##_t as, at, xs, xt, xd; \
2740 if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
2741 T = S; \
2742 } \
2743 else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
2744 S = T; \
2745 } \
2746 as = float## BITS ##_abs(S); \
2747 at = float## BITS ##_abs(T); \
2748 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2749 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2750 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2751 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2752 } while (0)
2753
2754 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2755 uint32_t ws, uint32_t wt)
2756 {
2757 wr_t wx, *pwx = &wx;
2758 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2759 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2760 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2761 uint32_t i;
2762
2763 clear_msacsr_cause(env);
2764
2765 switch (df) {
2766 case DF_WORD:
2767 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2768 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2769 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2770 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2771 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2772 } else {
2773 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2774 }
2775 }
2776 break;
2777 case DF_DOUBLE:
2778 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2779 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2780 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2781 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2782 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2783 } else {
2784 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2785 }
2786 }
2787 break;
2788 default:
2789 assert(0);
2790 }
2791
2792 check_msacsr_cause(env);
2793
2794 msa_move_v(pwd, pwx);
2795 }
2796
2797 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2798 uint32_t ws, uint32_t wt)
2799 {
2800 wr_t wx, *pwx = &wx;
2801 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2802 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2803 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2804 uint32_t i;
2805
2806 clear_msacsr_cause(env);
2807
2808 switch (df) {
2809 case DF_WORD:
2810 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2811 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
2812 }
2813 break;
2814 case DF_DOUBLE:
2815 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2816 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
2817 }
2818 break;
2819 default:
2820 assert(0);
2821 }
2822
2823 check_msacsr_cause(env);
2824
2825 msa_move_v(pwd, pwx);
2826 }
2827
2828 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2829 uint32_t ws, uint32_t wt)
2830 {
2831 wr_t wx, *pwx = &wx;
2832 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2833 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2834 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2835 uint32_t i;
2836
2837 clear_msacsr_cause(env);
2838
2839 switch (df) {
2840 case DF_WORD:
2841 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2842 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2843 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2844 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2845 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2846 } else {
2847 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2848 }
2849 }
2850 break;
2851 case DF_DOUBLE:
2852 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2853 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2854 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2855 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2856 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2857 } else {
2858 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2859 }
2860 }
2861 break;
2862 default:
2863 assert(0);
2864 }
2865
2866 check_msacsr_cause(env);
2867
2868 msa_move_v(pwd, pwx);
2869 }
2870
2871 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2872 uint32_t ws, uint32_t wt)
2873 {
2874 wr_t wx, *pwx = &wx;
2875 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2876 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2877 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2878 uint32_t i;
2879
2880 clear_msacsr_cause(env);
2881
2882 switch (df) {
2883 case DF_WORD:
2884 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2885 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
2886 }
2887 break;
2888 case DF_DOUBLE:
2889 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2890 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
2891 }
2892 break;
2893 default:
2894 assert(0);
2895 }
2896
2897 check_msacsr_cause(env);
2898
2899 msa_move_v(pwd, pwx);
2900 }
2901
2902 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2903 uint32_t wd, uint32_t ws)
2904 {
2905 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2906 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2907 if (df == DF_WORD) {
2908 pwd->w[0] = helper_float_class_s(pws->w[0]);
2909 pwd->w[1] = helper_float_class_s(pws->w[1]);
2910 pwd->w[2] = helper_float_class_s(pws->w[2]);
2911 pwd->w[3] = helper_float_class_s(pws->w[3]);
2912 } else {
2913 pwd->d[0] = helper_float_class_d(pws->d[0]);
2914 pwd->d[1] = helper_float_class_d(pws->d[1]);
2915 }
2916 }
2917
2918 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2919 do { \
2920 float_status *status = &env->active_tc.msa_fp_status; \
2921 int c; \
2922 \
2923 set_float_exception_flags(0, status); \
2924 DEST = float ## BITS ## _ ## OP(ARG, status); \
2925 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2926 \
2927 if (get_enabled_exceptions(env, c)) { \
2928 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2929 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2930 DEST = 0; \
2931 } \
2932 } while (0)
2933
2934 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2935 uint32_t ws)
2936 {
2937 wr_t wx, *pwx = &wx;
2938 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2939 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2940 uint32_t i;
2941
2942 clear_msacsr_cause(env);
2943
2944 switch (df) {
2945 case DF_WORD:
2946 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2947 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2948 }
2949 break;
2950 case DF_DOUBLE:
2951 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2952 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2953 }
2954 break;
2955 default:
2956 assert(0);
2957 }
2958
2959 check_msacsr_cause(env);
2960
2961 msa_move_v(pwd, pwx);
2962 }
2963
2964 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2965 uint32_t ws)
2966 {
2967 wr_t wx, *pwx = &wx;
2968 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2969 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2970 uint32_t i;
2971
2972 clear_msacsr_cause(env);
2973
2974 switch (df) {
2975 case DF_WORD:
2976 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2977 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
2978 }
2979 break;
2980 case DF_DOUBLE:
2981 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2982 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
2983 }
2984 break;
2985 default:
2986 assert(0);
2987 }
2988
2989 check_msacsr_cause(env);
2990
2991 msa_move_v(pwd, pwx);
2992 }
2993
2994 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2995 uint32_t ws)
2996 {
2997 wr_t wx, *pwx = &wx;
2998 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2999 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3000 uint32_t i;
3001
3002 clear_msacsr_cause(env);
3003
3004 switch (df) {
3005 case DF_WORD:
3006 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3007 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3008 }
3009 break;
3010 case DF_DOUBLE:
3011 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3012 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3013 }
3014 break;
3015 default:
3016 assert(0);
3017 }
3018
3019 check_msacsr_cause(env);
3020
3021 msa_move_v(pwd, pwx);
3022 }
3023
3024 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3025 do { \
3026 float_status *status = &env->active_tc.msa_fp_status; \
3027 int c; \
3028 \
3029 set_float_exception_flags(0, status); \
3030 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3031 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3032 float ## BITS ## _is_quiet_nan(DEST) ? \
3033 0 : RECIPROCAL_INEXACT, \
3034 IS_DENORMAL(DEST, BITS)); \
3035 \
3036 if (get_enabled_exceptions(env, c)) { \
3037 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3038 } \
3039 } while (0)
3040
3041 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3042 uint32_t ws)
3043 {
3044 wr_t wx, *pwx = &wx;
3045 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3046 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3047 uint32_t i;
3048
3049 clear_msacsr_cause(env);
3050
3051 switch (df) {
3052 case DF_WORD:
3053 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3054 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3055 &env->active_tc.msa_fp_status), 32);
3056 }
3057 break;
3058 case DF_DOUBLE:
3059 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3060 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3061 &env->active_tc.msa_fp_status), 64);
3062 }
3063 break;
3064 default:
3065 assert(0);
3066 }
3067
3068 check_msacsr_cause(env);
3069
3070 msa_move_v(pwd, pwx);
3071 }
3072
3073 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3074 uint32_t ws)
3075 {
3076 wr_t wx, *pwx = &wx;
3077 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3078 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3079 uint32_t i;
3080
3081 clear_msacsr_cause(env);
3082
3083 switch (df) {
3084 case DF_WORD:
3085 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3086 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3087 }
3088 break;
3089 case DF_DOUBLE:
3090 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3091 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3092 }
3093 break;
3094 default:
3095 assert(0);
3096 }
3097
3098 check_msacsr_cause(env);
3099
3100 msa_move_v(pwd, pwx);
3101 }
3102
3103 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3104 uint32_t ws)
3105 {
3106 wr_t wx, *pwx = &wx;
3107 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3108 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3109 uint32_t i;
3110
3111 clear_msacsr_cause(env);
3112
3113 switch (df) {
3114 case DF_WORD:
3115 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3116 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3117 }
3118 break;
3119 case DF_DOUBLE:
3120 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3121 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3122 }
3123 break;
3124 default:
3125 assert(0);
3126 }
3127
3128 check_msacsr_cause(env);
3129
3130 msa_move_v(pwd, pwx);
3131 }
3132
3133 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3134 do { \
3135 float_status *status = &env->active_tc.msa_fp_status; \
3136 int c; \
3137 \
3138 set_float_exception_flags(0, status); \
3139 set_float_rounding_mode(float_round_down, status); \
3140 DEST = float ## BITS ## _ ## log2(ARG, status); \
3141 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3142 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3143 MSACSR_RM_MASK) >> MSACSR_RM], \
3144 status); \
3145 \
3146 set_float_exception_flags(get_float_exception_flags(status) & \
3147 (~float_flag_inexact), \
3148 status); \
3149 \
3150 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3151 \
3152 if (get_enabled_exceptions(env, c)) { \
3153 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3154 } \
3155 } while (0)
3156
3157 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3158 uint32_t ws)
3159 {
3160 wr_t wx, *pwx = &wx;
3161 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3162 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3163 uint32_t i;
3164
3165 clear_msacsr_cause(env);
3166
3167 switch (df) {
3168 case DF_WORD:
3169 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3170 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3171 }
3172 break;
3173 case DF_DOUBLE:
3174 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3175 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3176 }
3177 break;
3178 default:
3179 assert(0);
3180 }
3181
3182 check_msacsr_cause(env);
3183
3184 msa_move_v(pwd, pwx);
3185 }
3186
3187 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3188 uint32_t ws)
3189 {
3190 wr_t wx, *pwx = &wx;
3191 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3192 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3193 uint32_t i;
3194
3195 switch (df) {
3196 case DF_WORD:
3197 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3198 /* Half precision floats come in two formats: standard
3199 IEEE and "ARM" format. The latter gains extra exponent
3200 range by omitting the NaN/Inf encodings. */
3201 flag ieee = 1;
3202
3203 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3204 }
3205 break;
3206 case DF_DOUBLE:
3207 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3208 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3209 }
3210 break;
3211 default:
3212 assert(0);
3213 }
3214
3215 check_msacsr_cause(env);
3216 msa_move_v(pwd, pwx);
3217 }
3218
3219 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3220 uint32_t ws)
3221 {
3222 wr_t wx, *pwx = &wx;
3223 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3224 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3225 uint32_t i;
3226
3227 switch (df) {
3228 case DF_WORD:
3229 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3230 /* Half precision floats come in two formats: standard
3231 IEEE and "ARM" format. The latter gains extra exponent
3232 range by omitting the NaN/Inf encodings. */
3233 flag ieee = 1;
3234
3235 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3236 }
3237 break;
3238 case DF_DOUBLE:
3239 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3240 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3241 }
3242 break;
3243 default:
3244 assert(0);
3245 }
3246
3247 check_msacsr_cause(env);
3248 msa_move_v(pwd, pwx);
3249 }
3250
3251 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3252 uint32_t ws)
3253 {
3254 wr_t wx, *pwx = &wx;
3255 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3256 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3257 uint32_t i;
3258
3259 switch (df) {
3260 case DF_WORD:
3261 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3262 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3263 }
3264 break;
3265 case DF_DOUBLE:
3266 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3267 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3268 }
3269 break;
3270 default:
3271 assert(0);
3272 }
3273
3274 msa_move_v(pwd, pwx);
3275 }
3276
3277 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3278 uint32_t ws)
3279 {
3280 wr_t wx, *pwx = &wx;
3281 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3282 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3283 uint32_t i;
3284
3285 switch (df) {
3286 case DF_WORD:
3287 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3288 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3289 }
3290 break;
3291 case DF_DOUBLE:
3292 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3293 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3294 }
3295 break;
3296 default:
3297 assert(0);
3298 }
3299
3300 msa_move_v(pwd, pwx);
3301 }
3302
3303 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3304 uint32_t ws)
3305 {
3306 wr_t wx, *pwx = &wx;
3307 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3308 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3309 uint32_t i;
3310
3311 clear_msacsr_cause(env);
3312
3313 switch (df) {
3314 case DF_WORD:
3315 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3316 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3317 }
3318 break;
3319 case DF_DOUBLE:
3320 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3321 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3322 }
3323 break;
3324 default:
3325 assert(0);
3326 }
3327
3328 check_msacsr_cause(env);
3329
3330 msa_move_v(pwd, pwx);
3331 }
3332
3333 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3334 uint32_t ws)
3335 {
3336 wr_t wx, *pwx = &wx;
3337 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3338 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3339 uint32_t i;
3340
3341 clear_msacsr_cause(env);
3342
3343 switch (df) {
3344 case DF_WORD:
3345 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3346 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3347 }
3348 break;
3349 case DF_DOUBLE:
3350 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3351 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3352 }
3353 break;
3354 default:
3355 assert(0);
3356 }
3357
3358 check_msacsr_cause(env);
3359
3360 msa_move_v(pwd, pwx);
3361 }
3362
3363 #define float32_from_int32 int32_to_float32
3364 #define float32_from_uint32 uint32_to_float32
3365
3366 #define float64_from_int64 int64_to_float64
3367 #define float64_from_uint64 uint64_to_float64
3368
3369 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3370 uint32_t ws)
3371 {
3372 wr_t wx, *pwx = &wx;
3373 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3374 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3375 uint32_t i;
3376
3377 clear_msacsr_cause(env);
3378
3379 switch (df) {
3380 case DF_WORD:
3381 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3382 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3383 }
3384 break;
3385 case DF_DOUBLE:
3386 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3387 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3388 }
3389 break;
3390 default:
3391 assert(0);
3392 }
3393
3394 check_msacsr_cause(env);
3395
3396 msa_move_v(pwd, pwx);
3397 }
3398
3399 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3400 uint32_t ws)
3401 {
3402 wr_t wx, *pwx = &wx;
3403 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3404 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3405 uint32_t i;
3406
3407 clear_msacsr_cause(env);
3408
3409 switch (df) {
3410 case DF_WORD:
3411 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3412 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3413 }
3414 break;
3415 case DF_DOUBLE:
3416 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3417 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3418 }
3419 break;
3420 default:
3421 assert(0);
3422 }
3423
3424 check_msacsr_cause(env);
3425
3426 msa_move_v(pwd, pwx);
3427 }
AR7 emulation for QEMU