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ACPI: Add definitions for the SPCR table
[qemu/ar7.git] / target-arm / helper.c
blob00509b1382a455d6b8fda447538a4df55c64391c
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
11 #include "arm_ldst.h"
12 #include <zlib.h> /* For crc32 */
13
14 #ifndef CONFIG_USER_ONLY
15 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
16 int access_type, ARMMMUIdx mmu_idx,
17 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
18 target_ulong *page_size, uint32_t *fsr);
19
20 /* Definitions for the PMCCNTR and PMCR registers */
21 #define PMCRD 0x8
22 #define PMCRC 0x4
23 #define PMCRE 0x1
24 #endif
25
26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
27 {
28 int nregs;
29
30 /* VFP data registers are always little-endian. */
31 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
32 if (reg < nregs) {
33 stfq_le_p(buf, env->vfp.regs[reg]);
34 return 8;
35 }
36 if (arm_feature(env, ARM_FEATURE_NEON)) {
37 /* Aliases for Q regs. */
38 nregs += 16;
39 if (reg < nregs) {
40 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
41 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
42 return 16;
43 }
44 }
45 switch (reg - nregs) {
46 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
47 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
48 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
49 }
50 return 0;
51 }
52
53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
54 {
55 int nregs;
56
57 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
58 if (reg < nregs) {
59 env->vfp.regs[reg] = ldfq_le_p(buf);
60 return 8;
61 }
62 if (arm_feature(env, ARM_FEATURE_NEON)) {
63 nregs += 16;
64 if (reg < nregs) {
65 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
66 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
67 return 16;
68 }
69 }
70 switch (reg - nregs) {
71 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
72 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
73 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
74 }
75 return 0;
76 }
77
78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
79 {
80 switch (reg) {
81 case 0 ... 31:
82 /* 128 bit FP register */
83 stfq_le_p(buf, env->vfp.regs[reg * 2]);
84 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
85 return 16;
86 case 32:
87 /* FPSR */
88 stl_p(buf, vfp_get_fpsr(env));
89 return 4;
90 case 33:
91 /* FPCR */
92 stl_p(buf, vfp_get_fpcr(env));
93 return 4;
94 default:
95 return 0;
96 }
97 }
98
99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
100 {
101 switch (reg) {
102 case 0 ... 31:
103 /* 128 bit FP register */
104 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
105 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
106 return 16;
107 case 32:
108 /* FPSR */
109 vfp_set_fpsr(env, ldl_p(buf));
110 return 4;
111 case 33:
112 /* FPCR */
113 vfp_set_fpcr(env, ldl_p(buf));
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
121 {
122 assert(ri->fieldoffset);
123 if (cpreg_field_is_64bit(ri)) {
124 return CPREG_FIELD64(env, ri);
125 } else {
126 return CPREG_FIELD32(env, ri);
127 }
128 }
129
130 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
131 uint64_t value)
132 {
133 assert(ri->fieldoffset);
134 if (cpreg_field_is_64bit(ri)) {
135 CPREG_FIELD64(env, ri) = value;
136 } else {
137 CPREG_FIELD32(env, ri) = value;
138 }
139 }
140
141 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
142 {
143 return (char *)env + ri->fieldoffset;
144 }
145
146 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
147 {
148 /* Raw read of a coprocessor register (as needed for migration, etc). */
149 if (ri->type & ARM_CP_CONST) {
150 return ri->resetvalue;
151 } else if (ri->raw_readfn) {
152 return ri->raw_readfn(env, ri);
153 } else if (ri->readfn) {
154 return ri->readfn(env, ri);
155 } else {
156 return raw_read(env, ri);
157 }
158 }
159
160 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
161 uint64_t v)
162 {
163 /* Raw write of a coprocessor register (as needed for migration, etc).
164 * Note that constant registers are treated as write-ignored; the
165 * caller should check for success by whether a readback gives the
166 * value written.
167 */
168 if (ri->type & ARM_CP_CONST) {
169 return;
170 } else if (ri->raw_writefn) {
171 ri->raw_writefn(env, ri, v);
172 } else if (ri->writefn) {
173 ri->writefn(env, ri, v);
174 } else {
175 raw_write(env, ri, v);
176 }
177 }
178
179 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
180 {
181 /* Return true if the regdef would cause an assertion if you called
182 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
183 * program bug for it not to have the NO_RAW flag).
184 * NB that returning false here doesn't necessarily mean that calling
185 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
186 * read/write access functions which are safe for raw use" from "has
187 * read/write access functions which have side effects but has forgotten
188 * to provide raw access functions".
189 * The tests here line up with the conditions in read/write_raw_cp_reg()
190 * and assertions in raw_read()/raw_write().
191 */
192 if ((ri->type & ARM_CP_CONST) ||
193 ri->fieldoffset ||
194 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
195 return false;
196 }
197 return true;
198 }
199
200 bool write_cpustate_to_list(ARMCPU *cpu)
201 {
202 /* Write the coprocessor state from cpu->env to the (index,value) list. */
203 int i;
204 bool ok = true;
205
206 for (i = 0; i < cpu->cpreg_array_len; i++) {
207 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
208 const ARMCPRegInfo *ri;
209
210 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
211 if (!ri) {
212 ok = false;
213 continue;
214 }
215 if (ri->type & ARM_CP_NO_RAW) {
216 continue;
217 }
218 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
219 }
220 return ok;
221 }
222
223 bool write_list_to_cpustate(ARMCPU *cpu)
224 {
225 int i;
226 bool ok = true;
227
228 for (i = 0; i < cpu->cpreg_array_len; i++) {
229 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
230 uint64_t v = cpu->cpreg_values[i];
231 const ARMCPRegInfo *ri;
232
233 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
234 if (!ri) {
235 ok = false;
236 continue;
237 }
238 if (ri->type & ARM_CP_NO_RAW) {
239 continue;
240 }
241 /* Write value and confirm it reads back as written
242 * (to catch read-only registers and partially read-only
243 * registers where the incoming migration value doesn't match)
244 */
245 write_raw_cp_reg(&cpu->env, ri, v);
246 if (read_raw_cp_reg(&cpu->env, ri) != v) {
247 ok = false;
248 }
249 }
250 return ok;
251 }
252
253 static void add_cpreg_to_list(gpointer key, gpointer opaque)
254 {
255 ARMCPU *cpu = opaque;
256 uint64_t regidx;
257 const ARMCPRegInfo *ri;
258
259 regidx = *(uint32_t *)key;
260 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
261
262 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
263 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
264 /* The value array need not be initialized at this point */
265 cpu->cpreg_array_len++;
266 }
267 }
268
269 static void count_cpreg(gpointer key, gpointer opaque)
270 {
271 ARMCPU *cpu = opaque;
272 uint64_t regidx;
273 const ARMCPRegInfo *ri;
274
275 regidx = *(uint32_t *)key;
276 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
277
278 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
279 cpu->cpreg_array_len++;
280 }
281 }
282
283 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
284 {
285 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
286 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
287
288 if (aidx > bidx) {
289 return 1;
290 }
291 if (aidx < bidx) {
292 return -1;
293 }
294 return 0;
295 }
296
297 void init_cpreg_list(ARMCPU *cpu)
298 {
299 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
300 * Note that we require cpreg_tuples[] to be sorted by key ID.
301 */
302 GList *keys;
303 int arraylen;
304
305 keys = g_hash_table_get_keys(cpu->cp_regs);
306 keys = g_list_sort(keys, cpreg_key_compare);
307
308 cpu->cpreg_array_len = 0;
309
310 g_list_foreach(keys, count_cpreg, cpu);
311
312 arraylen = cpu->cpreg_array_len;
313 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
314 cpu->cpreg_values = g_new(uint64_t, arraylen);
315 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
316 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
317 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
318 cpu->cpreg_array_len = 0;
319
320 g_list_foreach(keys, add_cpreg_to_list, cpu);
321
322 assert(cpu->cpreg_array_len == arraylen);
323
324 g_list_free(keys);
325 }
326
327 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
328 {
329 ARMCPU *cpu = arm_env_get_cpu(env);
330
331 raw_write(env, ri, value);
332 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
333 }
334
335 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
336 {
337 ARMCPU *cpu = arm_env_get_cpu(env);
338
339 if (raw_read(env, ri) != value) {
340 /* Unlike real hardware the qemu TLB uses virtual addresses,
341 * not modified virtual addresses, so this causes a TLB flush.
342 */
343 tlb_flush(CPU(cpu), 1);
344 raw_write(env, ri, value);
345 }
346 }
347
348 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
349 uint64_t value)
350 {
351 ARMCPU *cpu = arm_env_get_cpu(env);
352
353 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
354 && !extended_addresses_enabled(env)) {
355 /* For VMSA (when not using the LPAE long descriptor page table
356 * format) this register includes the ASID, so do a TLB flush.
357 * For PMSA it is purely a process ID and no action is needed.
358 */
359 tlb_flush(CPU(cpu), 1);
360 }
361 raw_write(env, ri, value);
362 }
363
364 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
365 uint64_t value)
366 {
367 /* Invalidate all (TLBIALL) */
368 ARMCPU *cpu = arm_env_get_cpu(env);
369
370 tlb_flush(CPU(cpu), 1);
371 }
372
373 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
374 uint64_t value)
375 {
376 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
377 ARMCPU *cpu = arm_env_get_cpu(env);
378
379 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
380 }
381
382 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
383 uint64_t value)
384 {
385 /* Invalidate by ASID (TLBIASID) */
386 ARMCPU *cpu = arm_env_get_cpu(env);
387
388 tlb_flush(CPU(cpu), value == 0);
389 }
390
391 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
392 uint64_t value)
393 {
394 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
395 ARMCPU *cpu = arm_env_get_cpu(env);
396
397 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
398 }
399
400 /* IS variants of TLB operations must affect all cores */
401 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
402 uint64_t value)
403 {
404 CPUState *other_cs;
405
406 CPU_FOREACH(other_cs) {
407 tlb_flush(other_cs, 1);
408 }
409 }
410
411 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
412 uint64_t value)
413 {
414 CPUState *other_cs;
415
416 CPU_FOREACH(other_cs) {
417 tlb_flush(other_cs, value == 0);
418 }
419 }
420
421 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
422 uint64_t value)
423 {
424 CPUState *other_cs;
425
426 CPU_FOREACH(other_cs) {
427 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
428 }
429 }
430
431 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
432 uint64_t value)
433 {
434 CPUState *other_cs;
435
436 CPU_FOREACH(other_cs) {
437 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
438 }
439 }
440
441 static const ARMCPRegInfo cp_reginfo[] = {
442 /* Define the secure and non-secure FCSE identifier CP registers
443 * separately because there is no secure bank in V8 (no _EL3). This allows
444 * the secure register to be properly reset and migrated. There is also no
445 * v8 EL1 version of the register so the non-secure instance stands alone.
446 */
447 { .name = "FCSEIDR(NS)",
448 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
449 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
450 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
451 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
452 { .name = "FCSEIDR(S)",
453 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
454 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
455 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
456 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
457 /* Define the secure and non-secure context identifier CP registers
458 * separately because there is no secure bank in V8 (no _EL3). This allows
459 * the secure register to be properly reset and migrated. In the
460 * non-secure case, the 32-bit register will have reset and migration
461 * disabled during registration as it is handled by the 64-bit instance.
462 */
463 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
464 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
465 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
466 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
467 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
468 { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
469 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
470 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
471 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
472 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
473 REGINFO_SENTINEL
474 };
475
476 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
477 /* NB: Some of these registers exist in v8 but with more precise
478 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
479 */
480 /* MMU Domain access control / MPU write buffer control */
481 { .name = "DACR",
482 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
483 .access = PL1_RW, .resetvalue = 0,
484 .writefn = dacr_write, .raw_writefn = raw_write,
485 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
486 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
487 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
488 * For v6 and v5, these mappings are overly broad.
489 */
490 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
491 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
492 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
493 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
494 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
495 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
496 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
497 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
498 /* Cache maintenance ops; some of this space may be overridden later. */
499 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
500 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
501 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
502 REGINFO_SENTINEL
503 };
504
505 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
506 /* Not all pre-v6 cores implemented this WFI, so this is slightly
507 * over-broad.
508 */
509 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
510 .access = PL1_W, .type = ARM_CP_WFI },
511 REGINFO_SENTINEL
512 };
513
514 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
515 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
516 * is UNPREDICTABLE; we choose to NOP as most implementations do).
517 */
518 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
519 .access = PL1_W, .type = ARM_CP_WFI },
520 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
521 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
522 * OMAPCP will override this space.
523 */
524 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
525 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
526 .resetvalue = 0 },
527 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
528 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
529 .resetvalue = 0 },
530 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
531 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
532 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
533 .resetvalue = 0 },
534 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
535 * implementing it as RAZ means the "debug architecture version" bits
536 * will read as a reserved value, which should cause Linux to not try
537 * to use the debug hardware.
538 */
539 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
540 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
541 /* MMU TLB control. Note that the wildcarding means we cover not just
542 * the unified TLB ops but also the dside/iside/inner-shareable variants.
543 */
544 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
545 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
546 .type = ARM_CP_NO_RAW },
547 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
548 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
549 .type = ARM_CP_NO_RAW },
550 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
551 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
552 .type = ARM_CP_NO_RAW },
553 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
554 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
555 .type = ARM_CP_NO_RAW },
556 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
557 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
558 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
559 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
560 REGINFO_SENTINEL
561 };
562
563 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
564 uint64_t value)
565 {
566 uint32_t mask = 0;
567
568 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
569 if (!arm_feature(env, ARM_FEATURE_V8)) {
570 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
571 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
572 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
573 */
574 if (arm_feature(env, ARM_FEATURE_VFP)) {
575 /* VFP coprocessor: cp10 & cp11 [23:20] */
576 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
577
578 if (!arm_feature(env, ARM_FEATURE_NEON)) {
579 /* ASEDIS [31] bit is RAO/WI */
580 value |= (1 << 31);
581 }
582
583 /* VFPv3 and upwards with NEON implement 32 double precision
584 * registers (D0-D31).
585 */
586 if (!arm_feature(env, ARM_FEATURE_NEON) ||
587 !arm_feature(env, ARM_FEATURE_VFP3)) {
588 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
589 value |= (1 << 30);
590 }
591 }
592 value &= mask;
593 }
594 env->cp15.cpacr_el1 = value;
595 }
596
597 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
598 {
599 if (arm_feature(env, ARM_FEATURE_V8)) {
600 /* Check if CPACR accesses are to be trapped to EL2 */
601 if (arm_current_el(env) == 1 &&
602 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
603 return CP_ACCESS_TRAP_EL2;
604 /* Check if CPACR accesses are to be trapped to EL3 */
605 } else if (arm_current_el(env) < 3 &&
606 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
607 return CP_ACCESS_TRAP_EL3;
608 }
609 }
610
611 return CP_ACCESS_OK;
612 }
613
614 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
615 {
616 /* Check if CPTR accesses are set to trap to EL3 */
617 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
618 return CP_ACCESS_TRAP_EL3;
619 }
620
621 return CP_ACCESS_OK;
622 }
623
624 static const ARMCPRegInfo v6_cp_reginfo[] = {
625 /* prefetch by MVA in v6, NOP in v7 */
626 { .name = "MVA_prefetch",
627 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
628 .access = PL1_W, .type = ARM_CP_NOP },
629 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
630 .access = PL0_W, .type = ARM_CP_NOP },
631 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
632 .access = PL0_W, .type = ARM_CP_NOP },
633 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
634 .access = PL0_W, .type = ARM_CP_NOP },
635 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
636 .access = PL1_RW,
637 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
638 offsetof(CPUARMState, cp15.ifar_ns) },
639 .resetvalue = 0, },
640 /* Watchpoint Fault Address Register : should actually only be present
641 * for 1136, 1176, 11MPCore.
642 */
643 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
644 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
645 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
646 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
647 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
648 .resetvalue = 0, .writefn = cpacr_write },
649 REGINFO_SENTINEL
650 };
651
652 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
653 {
654 /* Performance monitor registers user accessibility is controlled
655 * by PMUSERENR.
656 */
657 if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
658 return CP_ACCESS_TRAP;
659 }
660 return CP_ACCESS_OK;
661 }
662
663 #ifndef CONFIG_USER_ONLY
664
665 static inline bool arm_ccnt_enabled(CPUARMState *env)
666 {
667 /* This does not support checking PMCCFILTR_EL0 register */
668
669 if (!(env->cp15.c9_pmcr & PMCRE)) {
670 return false;
671 }
672
673 return true;
674 }
675
676 void pmccntr_sync(CPUARMState *env)
677 {
678 uint64_t temp_ticks;
679
680 temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
681 get_ticks_per_sec(), 1000000);
682
683 if (env->cp15.c9_pmcr & PMCRD) {
684 /* Increment once every 64 processor clock cycles */
685 temp_ticks /= 64;
686 }
687
688 if (arm_ccnt_enabled(env)) {
689 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
690 }
691 }
692
693 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695 {
696 pmccntr_sync(env);
697
698 if (value & PMCRC) {
699 /* The counter has been reset */
700 env->cp15.c15_ccnt = 0;
701 }
702
703 /* only the DP, X, D and E bits are writable */
704 env->cp15.c9_pmcr &= ~0x39;
705 env->cp15.c9_pmcr |= (value & 0x39);
706
707 pmccntr_sync(env);
708 }
709
710 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
711 {
712 uint64_t total_ticks;
713
714 if (!arm_ccnt_enabled(env)) {
715 /* Counter is disabled, do not change value */
716 return env->cp15.c15_ccnt;
717 }
718
719 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
720 get_ticks_per_sec(), 1000000);
721
722 if (env->cp15.c9_pmcr & PMCRD) {
723 /* Increment once every 64 processor clock cycles */
724 total_ticks /= 64;
725 }
726 return total_ticks - env->cp15.c15_ccnt;
727 }
728
729 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
730 uint64_t value)
731 {
732 uint64_t total_ticks;
733
734 if (!arm_ccnt_enabled(env)) {
735 /* Counter is disabled, set the absolute value */
736 env->cp15.c15_ccnt = value;
737 return;
738 }
739
740 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
741 get_ticks_per_sec(), 1000000);
742
743 if (env->cp15.c9_pmcr & PMCRD) {
744 /* Increment once every 64 processor clock cycles */
745 total_ticks /= 64;
746 }
747 env->cp15.c15_ccnt = total_ticks - value;
748 }
749
750 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
751 uint64_t value)
752 {
753 uint64_t cur_val = pmccntr_read(env, NULL);
754
755 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
756 }
757
758 #else /* CONFIG_USER_ONLY */
759
760 void pmccntr_sync(CPUARMState *env)
761 {
762 }
763
764 #endif
765
766 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
767 uint64_t value)
768 {
769 pmccntr_sync(env);
770 env->cp15.pmccfiltr_el0 = value & 0x7E000000;
771 pmccntr_sync(env);
772 }
773
774 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
775 uint64_t value)
776 {
777 value &= (1 << 31);
778 env->cp15.c9_pmcnten |= value;
779 }
780
781 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
782 uint64_t value)
783 {
784 value &= (1 << 31);
785 env->cp15.c9_pmcnten &= ~value;
786 }
787
788 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
789 uint64_t value)
790 {
791 env->cp15.c9_pmovsr &= ~value;
792 }
793
794 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
795 uint64_t value)
796 {
797 env->cp15.c9_pmxevtyper = value & 0xff;
798 }
799
800 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
801 uint64_t value)
802 {
803 env->cp15.c9_pmuserenr = value & 1;
804 }
805
806 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
807 uint64_t value)
808 {
809 /* We have no event counters so only the C bit can be changed */
810 value &= (1 << 31);
811 env->cp15.c9_pminten |= value;
812 }
813
814 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
815 uint64_t value)
816 {
817 value &= (1 << 31);
818 env->cp15.c9_pminten &= ~value;
819 }
820
821 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
822 uint64_t value)
823 {
824 /* Note that even though the AArch64 view of this register has bits
825 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
826 * architectural requirements for bits which are RES0 only in some
827 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
828 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
829 */
830 raw_write(env, ri, value & ~0x1FULL);
831 }
832
833 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
834 {
835 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
836 * For bits that vary between AArch32/64, code needs to check the
837 * current execution mode before directly using the feature bit.
838 */
839 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
840
841 if (!arm_feature(env, ARM_FEATURE_EL2)) {
842 valid_mask &= ~SCR_HCE;
843
844 /* On ARMv7, SMD (or SCD as it is called in v7) is only
845 * supported if EL2 exists. The bit is UNK/SBZP when
846 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
847 * when EL2 is unavailable.
848 * On ARMv8, this bit is always available.
849 */
850 if (arm_feature(env, ARM_FEATURE_V7) &&
851 !arm_feature(env, ARM_FEATURE_V8)) {
852 valid_mask &= ~SCR_SMD;
853 }
854 }
855
856 /* Clear all-context RES0 bits. */
857 value &= valid_mask;
858 raw_write(env, ri, value);
859 }
860
861 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
862 {
863 ARMCPU *cpu = arm_env_get_cpu(env);
864
865 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
866 * bank
867 */
868 uint32_t index = A32_BANKED_REG_GET(env, csselr,
869 ri->secure & ARM_CP_SECSTATE_S);
870
871 return cpu->ccsidr[index];
872 }
873
874 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
875 uint64_t value)
876 {
877 raw_write(env, ri, value & 0xf);
878 }
879
880 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
881 {
882 CPUState *cs = ENV_GET_CPU(env);
883 uint64_t ret = 0;
884
885 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
886 ret |= CPSR_I;
887 }
888 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
889 ret |= CPSR_F;
890 }
891 /* External aborts are not possible in QEMU so A bit is always clear */
892 return ret;
893 }
894
895 static const ARMCPRegInfo v7_cp_reginfo[] = {
896 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
897 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
898 .access = PL1_W, .type = ARM_CP_NOP },
899 /* Performance monitors are implementation defined in v7,
900 * but with an ARM recommended set of registers, which we
901 * follow (although we don't actually implement any counters)
902 *
903 * Performance registers fall into three categories:
904 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
905 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
906 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
907 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
908 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
909 */
910 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
911 .access = PL0_RW, .type = ARM_CP_ALIAS,
912 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
913 .writefn = pmcntenset_write,
914 .accessfn = pmreg_access,
915 .raw_writefn = raw_write },
916 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
917 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
918 .access = PL0_RW, .accessfn = pmreg_access,
919 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
920 .writefn = pmcntenset_write, .raw_writefn = raw_write },
921 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
922 .access = PL0_RW,
923 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
924 .accessfn = pmreg_access,
925 .writefn = pmcntenclr_write,
926 .type = ARM_CP_ALIAS },
927 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
928 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
929 .access = PL0_RW, .accessfn = pmreg_access,
930 .type = ARM_CP_ALIAS,
931 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
932 .writefn = pmcntenclr_write },
933 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
934 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
935 .accessfn = pmreg_access,
936 .writefn = pmovsr_write,
937 .raw_writefn = raw_write },
938 /* Unimplemented so WI. */
939 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
940 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
941 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
942 * We choose to RAZ/WI.
943 */
944 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
945 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
946 .accessfn = pmreg_access },
947 #ifndef CONFIG_USER_ONLY
948 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
949 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
950 .readfn = pmccntr_read, .writefn = pmccntr_write32,
951 .accessfn = pmreg_access },
952 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
953 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
954 .access = PL0_RW, .accessfn = pmreg_access,
955 .type = ARM_CP_IO,
956 .readfn = pmccntr_read, .writefn = pmccntr_write, },
957 #endif
958 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
959 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
960 .writefn = pmccfiltr_write,
961 .access = PL0_RW, .accessfn = pmreg_access,
962 .type = ARM_CP_IO,
963 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
964 .resetvalue = 0, },
965 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
966 .access = PL0_RW,
967 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
968 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
969 .raw_writefn = raw_write },
970 /* Unimplemented, RAZ/WI. */
971 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
972 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
973 .accessfn = pmreg_access },
974 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
975 .access = PL0_R | PL1_RW,
976 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
977 .resetvalue = 0,
978 .writefn = pmuserenr_write, .raw_writefn = raw_write },
979 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
980 .access = PL1_RW,
981 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
982 .resetvalue = 0,
983 .writefn = pmintenset_write, .raw_writefn = raw_write },
984 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
985 .access = PL1_RW, .type = ARM_CP_ALIAS,
986 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
987 .resetvalue = 0, .writefn = pmintenclr_write, },
988 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
989 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
990 .access = PL1_RW, .writefn = vbar_write,
991 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
992 offsetof(CPUARMState, cp15.vbar_ns) },
993 .resetvalue = 0 },
994 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
995 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
996 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
997 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
998 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
999 .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1000 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1001 offsetof(CPUARMState, cp15.csselr_ns) } },
1002 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1003 * just RAZ for all cores:
1004 */
1005 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1006 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1007 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1008 /* Auxiliary fault status registers: these also are IMPDEF, and we
1009 * choose to RAZ/WI for all cores.
1010 */
1011 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1012 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1013 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1014 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1015 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1016 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1017 /* MAIR can just read-as-written because we don't implement caches
1018 * and so don't need to care about memory attributes.
1019 */
1020 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1021 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1022 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1023 .resetvalue = 0 },
1024 /* For non-long-descriptor page tables these are PRRR and NMRR;
1025 * regardless they still act as reads-as-written for QEMU.
1026 */
1027 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1028 * allows them to assign the correct fieldoffset based on the endianness
1029 * handled in the field definitions.
1030 */
1031 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1032 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1033 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1034 offsetof(CPUARMState, cp15.mair0_ns) },
1035 .resetfn = arm_cp_reset_ignore },
1036 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1037 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1038 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1039 offsetof(CPUARMState, cp15.mair1_ns) },
1040 .resetfn = arm_cp_reset_ignore },
1041 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1042 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1043 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1044 /* 32 bit ITLB invalidates */
1045 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1046 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1047 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1048 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1049 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1050 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1051 /* 32 bit DTLB invalidates */
1052 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1053 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1054 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1055 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1056 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1057 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1058 /* 32 bit TLB invalidates */
1059 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1060 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1061 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1062 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1063 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1064 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1065 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1066 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1067 REGINFO_SENTINEL
1068 };
1069
1070 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1071 /* 32 bit TLB invalidates, Inner Shareable */
1072 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1073 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1074 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1075 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1076 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1077 .type = ARM_CP_NO_RAW, .access = PL1_W,
1078 .writefn = tlbiasid_is_write },
1079 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1080 .type = ARM_CP_NO_RAW, .access = PL1_W,
1081 .writefn = tlbimvaa_is_write },
1082 REGINFO_SENTINEL
1083 };
1084
1085 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1086 uint64_t value)
1087 {
1088 value &= 1;
1089 env->teecr = value;
1090 }
1091
1092 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
1093 {
1094 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1095 return CP_ACCESS_TRAP;
1096 }
1097 return CP_ACCESS_OK;
1098 }
1099
1100 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1101 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1102 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1103 .resetvalue = 0,
1104 .writefn = teecr_write },
1105 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1106 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1107 .accessfn = teehbr_access, .resetvalue = 0 },
1108 REGINFO_SENTINEL
1109 };
1110
1111 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1112 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1113 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1114 .access = PL0_RW,
1115 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1116 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1117 .access = PL0_RW,
1118 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1119 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1120 .resetfn = arm_cp_reset_ignore },
1121 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1122 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1123 .access = PL0_R|PL1_W,
1124 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1125 .resetvalue = 0},
1126 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1127 .access = PL0_R|PL1_W,
1128 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1129 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1130 .resetfn = arm_cp_reset_ignore },
1131 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1132 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1133 .access = PL1_RW,
1134 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1135 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1136 .access = PL1_RW,
1137 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1138 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1139 .resetvalue = 0 },
1140 REGINFO_SENTINEL
1141 };
1142
1143 #ifndef CONFIG_USER_ONLY
1144
1145 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1146 {
1147 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1148 if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1149 return CP_ACCESS_TRAP;
1150 }
1151 return CP_ACCESS_OK;
1152 }
1153
1154 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1155 {
1156 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1157 if (arm_current_el(env) == 0 &&
1158 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1159 return CP_ACCESS_TRAP;
1160 }
1161 return CP_ACCESS_OK;
1162 }
1163
1164 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1165 {
1166 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1167 * EL0[PV]TEN is zero.
1168 */
1169 if (arm_current_el(env) == 0 &&
1170 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1171 return CP_ACCESS_TRAP;
1172 }
1173 return CP_ACCESS_OK;
1174 }
1175
1176 static CPAccessResult gt_pct_access(CPUARMState *env,
1177 const ARMCPRegInfo *ri)
1178 {
1179 return gt_counter_access(env, GTIMER_PHYS);
1180 }
1181
1182 static CPAccessResult gt_vct_access(CPUARMState *env,
1183 const ARMCPRegInfo *ri)
1184 {
1185 return gt_counter_access(env, GTIMER_VIRT);
1186 }
1187
1188 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1189 {
1190 return gt_timer_access(env, GTIMER_PHYS);
1191 }
1192
1193 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1194 {
1195 return gt_timer_access(env, GTIMER_VIRT);
1196 }
1197
1198 static uint64_t gt_get_countervalue(CPUARMState *env)
1199 {
1200 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1201 }
1202
1203 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1204 {
1205 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1206
1207 if (gt->ctl & 1) {
1208 /* Timer enabled: calculate and set current ISTATUS, irq, and
1209 * reset timer to when ISTATUS next has to change
1210 */
1211 uint64_t count = gt_get_countervalue(&cpu->env);
1212 /* Note that this must be unsigned 64 bit arithmetic: */
1213 int istatus = count >= gt->cval;
1214 uint64_t nexttick;
1215
1216 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1217 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1218 (istatus && !(gt->ctl & 2)));
1219 if (istatus) {
1220 /* Next transition is when count rolls back over to zero */
1221 nexttick = UINT64_MAX;
1222 } else {
1223 /* Next transition is when we hit cval */
1224 nexttick = gt->cval;
1225 }
1226 /* Note that the desired next expiry time might be beyond the
1227 * signed-64-bit range of a QEMUTimer -- in this case we just
1228 * set the timer for as far in the future as possible. When the
1229 * timer expires we will reset the timer for any remaining period.
1230 */
1231 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1232 nexttick = INT64_MAX / GTIMER_SCALE;
1233 }
1234 timer_mod(cpu->gt_timer[timeridx], nexttick);
1235 } else {
1236 /* Timer disabled: ISTATUS and timer output always clear */
1237 gt->ctl &= ~4;
1238 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1239 timer_del(cpu->gt_timer[timeridx]);
1240 }
1241 }
1242
1243 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1244 {
1245 ARMCPU *cpu = arm_env_get_cpu(env);
1246 int timeridx = ri->opc1 & 1;
1247
1248 timer_del(cpu->gt_timer[timeridx]);
1249 }
1250
1251 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1252 {
1253 return gt_get_countervalue(env);
1254 }
1255
1256 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1257 uint64_t value)
1258 {
1259 int timeridx = ri->opc1 & 1;
1260
1261 env->cp15.c14_timer[timeridx].cval = value;
1262 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1263 }
1264
1265 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1266 {
1267 int timeridx = ri->crm & 1;
1268
1269 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1270 gt_get_countervalue(env));
1271 }
1272
1273 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1274 uint64_t value)
1275 {
1276 int timeridx = ri->crm & 1;
1277
1278 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1279 sextract64(value, 0, 32);
1280 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1281 }
1282
1283 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1284 uint64_t value)
1285 {
1286 ARMCPU *cpu = arm_env_get_cpu(env);
1287 int timeridx = ri->crm & 1;
1288 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1289
1290 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1291 if ((oldval ^ value) & 1) {
1292 /* Enable toggled */
1293 gt_recalc_timer(cpu, timeridx);
1294 } else if ((oldval ^ value) & 2) {
1295 /* IMASK toggled: don't need to recalculate,
1296 * just set the interrupt line based on ISTATUS
1297 */
1298 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1299 (oldval & 4) && !(value & 2));
1300 }
1301 }
1302
1303 void arm_gt_ptimer_cb(void *opaque)
1304 {
1305 ARMCPU *cpu = opaque;
1306
1307 gt_recalc_timer(cpu, GTIMER_PHYS);
1308 }
1309
1310 void arm_gt_vtimer_cb(void *opaque)
1311 {
1312 ARMCPU *cpu = opaque;
1313
1314 gt_recalc_timer(cpu, GTIMER_VIRT);
1315 }
1316
1317 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1318 /* Note that CNTFRQ is purely reads-as-written for the benefit
1319 * of software; writing it doesn't actually change the timer frequency.
1320 * Our reset value matches the fixed frequency we implement the timer at.
1321 */
1322 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1323 .type = ARM_CP_ALIAS,
1324 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1325 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1326 .resetfn = arm_cp_reset_ignore,
1327 },
1328 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1329 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1330 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1331 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1332 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1333 },
1334 /* overall control: mostly access permissions */
1335 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1336 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1337 .access = PL1_RW,
1338 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1339 .resetvalue = 0,
1340 },
1341 /* per-timer control */
1342 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1343 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1344 .accessfn = gt_ptimer_access,
1345 .fieldoffset = offsetoflow32(CPUARMState,
1346 cp15.c14_timer[GTIMER_PHYS].ctl),
1347 .resetfn = arm_cp_reset_ignore,
1348 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1349 },
1350 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1351 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1352 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1353 .accessfn = gt_ptimer_access,
1354 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1355 .resetvalue = 0,
1356 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1357 },
1358 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1359 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1360 .accessfn = gt_vtimer_access,
1361 .fieldoffset = offsetoflow32(CPUARMState,
1362 cp15.c14_timer[GTIMER_VIRT].ctl),
1363 .resetfn = arm_cp_reset_ignore,
1364 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1365 },
1366 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1367 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1368 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1369 .accessfn = gt_vtimer_access,
1370 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1371 .resetvalue = 0,
1372 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1373 },
1374 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1375 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1376 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1377 .accessfn = gt_ptimer_access,
1378 .readfn = gt_tval_read, .writefn = gt_tval_write,
1379 },
1380 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1381 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1382 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1383 .accessfn = gt_ptimer_access,
1384 .readfn = gt_tval_read, .writefn = gt_tval_write,
1385 },
1386 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1387 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1388 .accessfn = gt_vtimer_access,
1389 .readfn = gt_tval_read, .writefn = gt_tval_write,
1390 },
1391 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1392 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1393 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1394 .accessfn = gt_vtimer_access,
1395 .readfn = gt_tval_read, .writefn = gt_tval_write,
1396 },
1397 /* The counter itself */
1398 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1399 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1400 .accessfn = gt_pct_access,
1401 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1402 },
1403 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1404 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1405 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1406 .accessfn = gt_pct_access,
1407 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1408 },
1409 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1410 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1411 .accessfn = gt_vct_access,
1412 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1413 },
1414 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1415 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1416 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1417 .accessfn = gt_vct_access,
1418 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1419 },
1420 /* Comparison value, indicating when the timer goes off */
1421 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1422 .access = PL1_RW | PL0_R,
1423 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1424 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1425 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1426 .writefn = gt_cval_write, .raw_writefn = raw_write,
1427 },
1428 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1429 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1430 .access = PL1_RW | PL0_R,
1431 .type = ARM_CP_IO,
1432 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1433 .resetvalue = 0, .accessfn = gt_ptimer_access,
1434 .writefn = gt_cval_write, .raw_writefn = raw_write,
1435 },
1436 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1437 .access = PL1_RW | PL0_R,
1438 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1439 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1440 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1441 .writefn = gt_cval_write, .raw_writefn = raw_write,
1442 },
1443 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1444 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1445 .access = PL1_RW | PL0_R,
1446 .type = ARM_CP_IO,
1447 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1448 .resetvalue = 0, .accessfn = gt_vtimer_access,
1449 .writefn = gt_cval_write, .raw_writefn = raw_write,
1450 },
1451 REGINFO_SENTINEL
1452 };
1453
1454 #else
1455 /* In user-mode none of the generic timer registers are accessible,
1456 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1457 * so instead just don't register any of them.
1458 */
1459 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1460 REGINFO_SENTINEL
1461 };
1462
1463 #endif
1464
1465 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1466 {
1467 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1468 raw_write(env, ri, value);
1469 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1470 raw_write(env, ri, value & 0xfffff6ff);
1471 } else {
1472 raw_write(env, ri, value & 0xfffff1ff);
1473 }
1474 }
1475
1476 #ifndef CONFIG_USER_ONLY
1477 /* get_phys_addr() isn't present for user-mode-only targets */
1478
1479 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481 if (ri->opc2 & 4) {
1482 /* Other states are only available with TrustZone; in
1483 * a non-TZ implementation these registers don't exist
1484 * at all, which is an Uncategorized trap. This underdecoding
1485 * is safe because the reginfo is NO_RAW.
1486 */
1487 return CP_ACCESS_TRAP_UNCATEGORIZED;
1488 }
1489 return CP_ACCESS_OK;
1490 }
1491
1492 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1493 int access_type, ARMMMUIdx mmu_idx)
1494 {
1495 hwaddr phys_addr;
1496 target_ulong page_size;
1497 int prot;
1498 uint32_t fsr;
1499 bool ret;
1500 uint64_t par64;
1501 MemTxAttrs attrs = {};
1502
1503 ret = get_phys_addr(env, value, access_type, mmu_idx,
1504 &phys_addr, &attrs, &prot, &page_size, &fsr);
1505 if (extended_addresses_enabled(env)) {
1506 /* fsr is a DFSR/IFSR value for the long descriptor
1507 * translation table format, but with WnR always clear.
1508 * Convert it to a 64-bit PAR.
1509 */
1510 par64 = (1 << 11); /* LPAE bit always set */
1511 if (!ret) {
1512 par64 |= phys_addr & ~0xfffULL;
1513 if (!attrs.secure) {
1514 par64 |= (1 << 9); /* NS */
1515 }
1516 /* We don't set the ATTR or SH fields in the PAR. */
1517 } else {
1518 par64 |= 1; /* F */
1519 par64 |= (fsr & 0x3f) << 1; /* FS */
1520 /* Note that S2WLK and FSTAGE are always zero, because we don't
1521 * implement virtualization and therefore there can't be a stage 2
1522 * fault.
1523 */
1524 }
1525 } else {
1526 /* fsr is a DFSR/IFSR value for the short descriptor
1527 * translation table format (with WnR always clear).
1528 * Convert it to a 32-bit PAR.
1529 */
1530 if (!ret) {
1531 /* We do not set any attribute bits in the PAR */
1532 if (page_size == (1 << 24)
1533 && arm_feature(env, ARM_FEATURE_V7)) {
1534 par64 = (phys_addr & 0xff000000) | (1 << 1);
1535 } else {
1536 par64 = phys_addr & 0xfffff000;
1537 }
1538 if (!attrs.secure) {
1539 par64 |= (1 << 9); /* NS */
1540 }
1541 } else {
1542 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1543 ((fsr & 0xf) << 1) | 1;
1544 }
1545 }
1546 return par64;
1547 }
1548
1549 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1550 {
1551 int access_type = ri->opc2 & 1;
1552 uint64_t par64;
1553 ARMMMUIdx mmu_idx;
1554 int el = arm_current_el(env);
1555 bool secure = arm_is_secure_below_el3(env);
1556
1557 switch (ri->opc2 & 6) {
1558 case 0:
1559 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
1560 switch (el) {
1561 case 3:
1562 mmu_idx = ARMMMUIdx_S1E3;
1563 break;
1564 case 2:
1565 mmu_idx = ARMMMUIdx_S1NSE1;
1566 break;
1567 case 1:
1568 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1569 break;
1570 default:
1571 g_assert_not_reached();
1572 }
1573 break;
1574 case 2:
1575 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
1576 switch (el) {
1577 case 3:
1578 mmu_idx = ARMMMUIdx_S1SE0;
1579 break;
1580 case 2:
1581 mmu_idx = ARMMMUIdx_S1NSE0;
1582 break;
1583 case 1:
1584 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1585 break;
1586 default:
1587 g_assert_not_reached();
1588 }
1589 break;
1590 case 4:
1591 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
1592 mmu_idx = ARMMMUIdx_S12NSE1;
1593 break;
1594 case 6:
1595 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
1596 mmu_idx = ARMMMUIdx_S12NSE0;
1597 break;
1598 default:
1599 g_assert_not_reached();
1600 }
1601
1602 par64 = do_ats_write(env, value, access_type, mmu_idx);
1603
1604 A32_BANKED_CURRENT_REG_SET(env, par, par64);
1605 }
1606
1607 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
1608 uint64_t value)
1609 {
1610 int access_type = ri->opc2 & 1;
1611 ARMMMUIdx mmu_idx;
1612 int secure = arm_is_secure_below_el3(env);
1613
1614 switch (ri->opc2 & 6) {
1615 case 0:
1616 switch (ri->opc1) {
1617 case 0: /* AT S1E1R, AT S1E1W */
1618 mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
1619 break;
1620 case 4: /* AT S1E2R, AT S1E2W */
1621 mmu_idx = ARMMMUIdx_S1E2;
1622 break;
1623 case 6: /* AT S1E3R, AT S1E3W */
1624 mmu_idx = ARMMMUIdx_S1E3;
1625 break;
1626 default:
1627 g_assert_not_reached();
1628 }
1629 break;
1630 case 2: /* AT S1E0R, AT S1E0W */
1631 mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
1632 break;
1633 case 4: /* AT S12E1R, AT S12E1W */
1634 mmu_idx = ARMMMUIdx_S12NSE1;
1635 break;
1636 case 6: /* AT S12E0R, AT S12E0W */
1637 mmu_idx = ARMMMUIdx_S12NSE0;
1638 break;
1639 default:
1640 g_assert_not_reached();
1641 }
1642
1643 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
1644 }
1645 #endif
1646
1647 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1648 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1649 .access = PL1_RW, .resetvalue = 0,
1650 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
1651 offsetoflow32(CPUARMState, cp15.par_ns) },
1652 .writefn = par_write },
1653 #ifndef CONFIG_USER_ONLY
1654 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1655 .access = PL1_W, .accessfn = ats_access,
1656 .writefn = ats_write, .type = ARM_CP_NO_RAW },
1657 #endif
1658 REGINFO_SENTINEL
1659 };
1660
1661 /* Return basic MPU access permission bits. */
1662 static uint32_t simple_mpu_ap_bits(uint32_t val)
1663 {
1664 uint32_t ret;
1665 uint32_t mask;
1666 int i;
1667 ret = 0;
1668 mask = 3;
1669 for (i = 0; i < 16; i += 2) {
1670 ret |= (val >> i) & mask;
1671 mask <<= 2;
1672 }
1673 return ret;
1674 }
1675
1676 /* Pad basic MPU access permission bits to extended format. */
1677 static uint32_t extended_mpu_ap_bits(uint32_t val)
1678 {
1679 uint32_t ret;
1680 uint32_t mask;
1681 int i;
1682 ret = 0;
1683 mask = 3;
1684 for (i = 0; i < 16; i += 2) {
1685 ret |= (val & mask) << i;
1686 mask <<= 2;
1687 }
1688 return ret;
1689 }
1690
1691 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1692 uint64_t value)
1693 {
1694 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1695 }
1696
1697 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1698 {
1699 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1700 }
1701
1702 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1703 uint64_t value)
1704 {
1705 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1706 }
1707
1708 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1709 {
1710 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1711 }
1712
1713 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1714 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1715 .access = PL1_RW, .type = ARM_CP_ALIAS,
1716 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1717 .resetvalue = 0,
1718 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1719 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1720 .access = PL1_RW, .type = ARM_CP_ALIAS,
1721 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1722 .resetvalue = 0,
1723 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1724 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1725 .access = PL1_RW,
1726 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1727 .resetvalue = 0, },
1728 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1729 .access = PL1_RW,
1730 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1731 .resetvalue = 0, },
1732 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1733 .access = PL1_RW,
1734 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1735 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1736 .access = PL1_RW,
1737 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1738 /* Protection region base and size registers */
1739 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1740 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1741 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1742 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1743 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1744 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1745 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1746 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1747 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1748 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1749 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1750 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1751 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1752 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1753 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1754 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1755 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1756 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1757 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1758 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1759 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1760 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1761 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1762 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1763 REGINFO_SENTINEL
1764 };
1765
1766 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1767 uint64_t value)
1768 {
1769 TCR *tcr = raw_ptr(env, ri);
1770 int maskshift = extract32(value, 0, 3);
1771
1772 if (!arm_feature(env, ARM_FEATURE_V8)) {
1773 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1774 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1775 * using Long-desciptor translation table format */
1776 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1777 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1778 /* In an implementation that includes the Security Extensions
1779 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1780 * Short-descriptor translation table format.
1781 */
1782 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1783 } else {
1784 value &= TTBCR_N;
1785 }
1786 }
1787
1788 /* Update the masks corresponding to the the TCR bank being written
1789 * Note that we always calculate mask and base_mask, but
1790 * they are only used for short-descriptor tables (ie if EAE is 0);
1791 * for long-descriptor tables the TCR fields are used differently
1792 * and the mask and base_mask values are meaningless.
1793 */
1794 tcr->raw_tcr = value;
1795 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1796 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
1797 }
1798
1799 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1800 uint64_t value)
1801 {
1802 ARMCPU *cpu = arm_env_get_cpu(env);
1803
1804 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1805 /* With LPAE the TTBCR could result in a change of ASID
1806 * via the TTBCR.A1 bit, so do a TLB flush.
1807 */
1808 tlb_flush(CPU(cpu), 1);
1809 }
1810 vmsa_ttbcr_raw_write(env, ri, value);
1811 }
1812
1813 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1814 {
1815 TCR *tcr = raw_ptr(env, ri);
1816
1817 /* Reset both the TCR as well as the masks corresponding to the bank of
1818 * the TCR being reset.
1819 */
1820 tcr->raw_tcr = 0;
1821 tcr->mask = 0;
1822 tcr->base_mask = 0xffffc000u;
1823 }
1824
1825 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1826 uint64_t value)
1827 {
1828 ARMCPU *cpu = arm_env_get_cpu(env);
1829 TCR *tcr = raw_ptr(env, ri);
1830
1831 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1832 tlb_flush(CPU(cpu), 1);
1833 tcr->raw_tcr = value;
1834 }
1835
1836 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1837 uint64_t value)
1838 {
1839 /* 64 bit accesses to the TTBRs can change the ASID and so we
1840 * must flush the TLB.
1841 */
1842 if (cpreg_field_is_64bit(ri)) {
1843 ARMCPU *cpu = arm_env_get_cpu(env);
1844
1845 tlb_flush(CPU(cpu), 1);
1846 }
1847 raw_write(env, ri, value);
1848 }
1849
1850 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
1851 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1852 .access = PL1_RW, .type = ARM_CP_ALIAS,
1853 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
1854 offsetoflow32(CPUARMState, cp15.dfsr_ns) },
1855 .resetfn = arm_cp_reset_ignore, },
1856 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1857 .access = PL1_RW, .resetvalue = 0,
1858 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
1859 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
1860 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
1861 .access = PL1_RW, .resetvalue = 0,
1862 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
1863 offsetof(CPUARMState, cp15.dfar_ns) } },
1864 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
1865 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1866 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1867 .resetvalue = 0, },
1868 REGINFO_SENTINEL
1869 };
1870
1871 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1872 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1873 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1874 .access = PL1_RW,
1875 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1876 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1877 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
1878 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1879 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
1880 offsetof(CPUARMState, cp15.ttbr0_ns) } },
1881 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1882 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
1883 .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
1884 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
1885 offsetof(CPUARMState, cp15.ttbr1_ns) } },
1886 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1887 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1888 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1889 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1890 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
1891 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1892 .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
1893 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1894 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
1895 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
1896 REGINFO_SENTINEL
1897 };
1898
1899 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1900 uint64_t value)
1901 {
1902 env->cp15.c15_ticonfig = value & 0xe7;
1903 /* The OS_TYPE bit in this register changes the reported CPUID! */
1904 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1905 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1906 }
1907
1908 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1909 uint64_t value)
1910 {
1911 env->cp15.c15_threadid = value & 0xffff;
1912 }
1913
1914 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1915 uint64_t value)
1916 {
1917 /* Wait-for-interrupt (deprecated) */
1918 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1919 }
1920
1921 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1922 uint64_t value)
1923 {
1924 /* On OMAP there are registers indicating the max/min index of dcache lines
1925 * containing a dirty line; cache flush operations have to reset these.
1926 */
1927 env->cp15.c15_i_max = 0x000;
1928 env->cp15.c15_i_min = 0xff0;
1929 }
1930
1931 static const ARMCPRegInfo omap_cp_reginfo[] = {
1932 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1933 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1934 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1935 .resetvalue = 0, },
1936 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1937 .access = PL1_RW, .type = ARM_CP_NOP },
1938 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1939 .access = PL1_RW,
1940 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1941 .writefn = omap_ticonfig_write },
1942 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1943 .access = PL1_RW,
1944 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1945 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1946 .access = PL1_RW, .resetvalue = 0xff0,
1947 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1948 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1949 .access = PL1_RW,
1950 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1951 .writefn = omap_threadid_write },
1952 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1953 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1954 .type = ARM_CP_NO_RAW,
1955 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1956 /* TODO: Peripheral port remap register:
1957 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1958 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1959 * when MMU is off.
1960 */
1961 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1962 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1963 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
1964 .writefn = omap_cachemaint_write },
1965 { .name = "C9", .cp = 15, .crn = 9,
1966 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1967 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1968 REGINFO_SENTINEL
1969 };
1970
1971 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1972 uint64_t value)
1973 {
1974 env->cp15.c15_cpar = value & 0x3fff;
1975 }
1976
1977 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1978 { .name = "XSCALE_CPAR",
1979 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1980 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1981 .writefn = xscale_cpar_write, },
1982 { .name = "XSCALE_AUXCR",
1983 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1984 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1985 .resetvalue = 0, },
1986 /* XScale specific cache-lockdown: since we have no cache we NOP these
1987 * and hope the guest does not really rely on cache behaviour.
1988 */
1989 { .name = "XSCALE_LOCK_ICACHE_LINE",
1990 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1991 .access = PL1_W, .type = ARM_CP_NOP },
1992 { .name = "XSCALE_UNLOCK_ICACHE",
1993 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1994 .access = PL1_W, .type = ARM_CP_NOP },
1995 { .name = "XSCALE_DCACHE_LOCK",
1996 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1997 .access = PL1_RW, .type = ARM_CP_NOP },
1998 { .name = "XSCALE_UNLOCK_DCACHE",
1999 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2000 .access = PL1_W, .type = ARM_CP_NOP },
2001 REGINFO_SENTINEL
2002 };
2003
2004 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2005 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2006 * implementation of this implementation-defined space.
2007 * Ideally this should eventually disappear in favour of actually
2008 * implementing the correct behaviour for all cores.
2009 */
2010 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2011 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2012 .access = PL1_RW,
2013 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2014 .resetvalue = 0 },
2015 REGINFO_SENTINEL
2016 };
2017
2018 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2019 /* Cache status: RAZ because we have no cache so it's always clean */
2020 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2021 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2022 .resetvalue = 0 },
2023 REGINFO_SENTINEL
2024 };
2025
2026 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2027 /* We never have a a block transfer operation in progress */
2028 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2029 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2030 .resetvalue = 0 },
2031 /* The cache ops themselves: these all NOP for QEMU */
2032 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2033 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2034 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2035 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2036 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2037 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2038 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2039 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2040 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2041 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2042 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2043 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2044 REGINFO_SENTINEL
2045 };
2046
2047 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2048 /* The cache test-and-clean instructions always return (1 << 30)
2049 * to indicate that there are no dirty cache lines.
2050 */
2051 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2052 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2053 .resetvalue = (1 << 30) },
2054 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2055 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2056 .resetvalue = (1 << 30) },
2057 REGINFO_SENTINEL
2058 };
2059
2060 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2061 /* Ignore ReadBuffer accesses */
2062 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2063 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2064 .access = PL1_RW, .resetvalue = 0,
2065 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2066 REGINFO_SENTINEL
2067 };
2068
2069 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2070 {
2071 ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2072 uint64_t mpidr = cpu->mp_affinity;
2073
2074 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2075 mpidr |= (1U << 31);
2076 /* Cores which are uniprocessor (non-coherent)
2077 * but still implement the MP extensions set
2078 * bit 30. (For instance, Cortex-R5).
2079 */
2080 if (cpu->mp_is_up) {
2081 mpidr |= (1u << 30);
2082 }
2083 }
2084 return mpidr;
2085 }
2086
2087 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2088 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2089 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2090 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2091 REGINFO_SENTINEL
2092 };
2093
2094 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2095 /* NOP AMAIR0/1 */
2096 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2097 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2098 .access = PL1_RW, .type = ARM_CP_CONST,
2099 .resetvalue = 0 },
2100 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2101 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2102 .access = PL1_RW, .type = ARM_CP_CONST,
2103 .resetvalue = 0 },
2104 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2105 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2106 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2107 offsetof(CPUARMState, cp15.par_ns)} },
2108 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2109 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2110 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2111 offsetof(CPUARMState, cp15.ttbr0_ns) },
2112 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2113 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2114 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2115 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2116 offsetof(CPUARMState, cp15.ttbr1_ns) },
2117 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
2118 REGINFO_SENTINEL
2119 };
2120
2121 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2122 {
2123 return vfp_get_fpcr(env);
2124 }
2125
2126 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2127 uint64_t value)
2128 {
2129 vfp_set_fpcr(env, value);
2130 }
2131
2132 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2133 {
2134 return vfp_get_fpsr(env);
2135 }
2136
2137 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2138 uint64_t value)
2139 {
2140 vfp_set_fpsr(env, value);
2141 }
2142
2143 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
2144 {
2145 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2146 return CP_ACCESS_TRAP;
2147 }
2148 return CP_ACCESS_OK;
2149 }
2150
2151 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2152 uint64_t value)
2153 {
2154 env->daif = value & PSTATE_DAIF;
2155 }
2156
2157 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2158 const ARMCPRegInfo *ri)
2159 {
2160 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2161 * SCTLR_EL1.UCI is set.
2162 */
2163 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2164 return CP_ACCESS_TRAP;
2165 }
2166 return CP_ACCESS_OK;
2167 }
2168
2169 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2170 * Page D4-1736 (DDI0487A.b)
2171 */
2172
2173 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
2174 uint64_t value)
2175 {
2176 /* Invalidate by VA (AArch64 version) */
2177 ARMCPU *cpu = arm_env_get_cpu(env);
2178 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2179
2180 tlb_flush_page(CPU(cpu), pageaddr);
2181 }
2182
2183 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
2184 uint64_t value)
2185 {
2186 /* Invalidate by VA, all ASIDs (AArch64 version) */
2187 ARMCPU *cpu = arm_env_get_cpu(env);
2188 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2189
2190 tlb_flush_page(CPU(cpu), pageaddr);
2191 }
2192
2193 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2194 uint64_t value)
2195 {
2196 /* Invalidate by ASID (AArch64 version) */
2197 ARMCPU *cpu = arm_env_get_cpu(env);
2198 int asid = extract64(value, 48, 16);
2199 tlb_flush(CPU(cpu), asid == 0);
2200 }
2201
2202 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2203 uint64_t value)
2204 {
2205 CPUState *other_cs;
2206 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2207
2208 CPU_FOREACH(other_cs) {
2209 tlb_flush_page(other_cs, pageaddr);
2210 }
2211 }
2212
2213 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2214 uint64_t value)
2215 {
2216 CPUState *other_cs;
2217 uint64_t pageaddr = sextract64(value << 12, 0, 56);
2218
2219 CPU_FOREACH(other_cs) {
2220 tlb_flush_page(other_cs, pageaddr);
2221 }
2222 }
2223
2224 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2225 uint64_t value)
2226 {
2227 CPUState *other_cs;
2228 int asid = extract64(value, 48, 16);
2229
2230 CPU_FOREACH(other_cs) {
2231 tlb_flush(other_cs, asid == 0);
2232 }
2233 }
2234
2235 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2236 {
2237 /* We don't implement EL2, so the only control on DC ZVA is the
2238 * bit in the SCTLR which can prohibit access for EL0.
2239 */
2240 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
2241 return CP_ACCESS_TRAP;
2242 }
2243 return CP_ACCESS_OK;
2244 }
2245
2246 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2247 {
2248 ARMCPU *cpu = arm_env_get_cpu(env);
2249 int dzp_bit = 1 << 4;
2250
2251 /* DZP indicates whether DC ZVA access is allowed */
2252 if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2253 dzp_bit = 0;
2254 }
2255 return cpu->dcz_blocksize | dzp_bit;
2256 }
2257
2258 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2259 {
2260 if (!(env->pstate & PSTATE_SP)) {
2261 /* Access to SP_EL0 is undefined if it's being used as
2262 * the stack pointer.
2263 */
2264 return CP_ACCESS_TRAP_UNCATEGORIZED;
2265 }
2266 return CP_ACCESS_OK;
2267 }
2268
2269 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2270 {
2271 return env->pstate & PSTATE_SP;
2272 }
2273
2274 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2275 {
2276 update_spsel(env, val);
2277 }
2278
2279 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2280 uint64_t value)
2281 {
2282 ARMCPU *cpu = arm_env_get_cpu(env);
2283
2284 if (raw_read(env, ri) == value) {
2285 /* Skip the TLB flush if nothing actually changed; Linux likes
2286 * to do a lot of pointless SCTLR writes.
2287 */
2288 return;
2289 }
2290
2291 raw_write(env, ri, value);
2292 /* ??? Lots of these bits are not implemented. */
2293 /* This may enable/disable the MMU, so do a TLB flush. */
2294 tlb_flush(CPU(cpu), 1);
2295 }
2296
2297 static const ARMCPRegInfo v8_cp_reginfo[] = {
2298 /* Minimal set of EL0-visible registers. This will need to be expanded
2299 * significantly for system emulation of AArch64 CPUs.
2300 */
2301 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2302 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2303 .access = PL0_RW, .type = ARM_CP_NZCV },
2304 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2305 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2306 .type = ARM_CP_NO_RAW,
2307 .access = PL0_RW, .accessfn = aa64_daif_access,
2308 .fieldoffset = offsetof(CPUARMState, daif),
2309 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2310 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2311 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2312 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2313 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2314 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2315 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2316 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2317 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2318 .access = PL0_R, .type = ARM_CP_NO_RAW,
2319 .readfn = aa64_dczid_read },
2320 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2321 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2322 .access = PL0_W, .type = ARM_CP_DC_ZVA,
2323 #ifndef CONFIG_USER_ONLY
2324 /* Avoid overhead of an access check that always passes in user-mode */
2325 .accessfn = aa64_zva_access,
2326 #endif
2327 },
2328 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2329 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2330 .access = PL1_R, .type = ARM_CP_CURRENTEL },
2331 /* Cache ops: all NOPs since we don't emulate caches */
2332 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2333 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2334 .access = PL1_W, .type = ARM_CP_NOP },
2335 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2336 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2337 .access = PL1_W, .type = ARM_CP_NOP },
2338 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2339 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2340 .access = PL0_W, .type = ARM_CP_NOP,
2341 .accessfn = aa64_cacheop_access },
2342 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2343 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2344 .access = PL1_W, .type = ARM_CP_NOP },
2345 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2346 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2347 .access = PL1_W, .type = ARM_CP_NOP },
2348 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2349 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2350 .access = PL0_W, .type = ARM_CP_NOP,
2351 .accessfn = aa64_cacheop_access },
2352 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2353 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2354 .access = PL1_W, .type = ARM_CP_NOP },
2355 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2356 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2357 .access = PL0_W, .type = ARM_CP_NOP,
2358 .accessfn = aa64_cacheop_access },
2359 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2360 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2361 .access = PL0_W, .type = ARM_CP_NOP,
2362 .accessfn = aa64_cacheop_access },
2363 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2364 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2365 .access = PL1_W, .type = ARM_CP_NOP },
2366 /* TLBI operations */
2367 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
2368 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
2369 .access = PL2_W, .type = ARM_CP_NO_RAW,
2370 .writefn = tlbiall_write },
2371 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
2372 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
2373 .access = PL2_W, .type = ARM_CP_NO_RAW,
2374 .writefn = tlbiall_write },
2375 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2376 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2377 .access = PL1_W, .type = ARM_CP_NO_RAW,
2378 .writefn = tlbiall_is_write },
2379 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2380 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2381 .access = PL1_W, .type = ARM_CP_NO_RAW,
2382 .writefn = tlbi_aa64_va_is_write },
2383 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2384 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2385 .access = PL1_W, .type = ARM_CP_NO_RAW,
2386 .writefn = tlbi_aa64_asid_is_write },
2387 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2388 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2389 .access = PL1_W, .type = ARM_CP_NO_RAW,
2390 .writefn = tlbi_aa64_vaa_is_write },
2391 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2392 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2393 .access = PL1_W, .type = ARM_CP_NO_RAW,
2394 .writefn = tlbi_aa64_va_is_write },
2395 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2396 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2397 .access = PL1_W, .type = ARM_CP_NO_RAW,
2398 .writefn = tlbi_aa64_vaa_is_write },
2399 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2400 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2401 .access = PL1_W, .type = ARM_CP_NO_RAW,
2402 .writefn = tlbiall_write },
2403 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2404 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2405 .access = PL1_W, .type = ARM_CP_NO_RAW,
2406 .writefn = tlbi_aa64_va_write },
2407 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2408 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2409 .access = PL1_W, .type = ARM_CP_NO_RAW,
2410 .writefn = tlbi_aa64_asid_write },
2411 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2412 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2413 .access = PL1_W, .type = ARM_CP_NO_RAW,
2414 .writefn = tlbi_aa64_vaa_write },
2415 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2416 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2417 .access = PL1_W, .type = ARM_CP_NO_RAW,
2418 .writefn = tlbi_aa64_va_write },
2419 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2420 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2421 .access = PL1_W, .type = ARM_CP_NO_RAW,
2422 .writefn = tlbi_aa64_vaa_write },
2423 #ifndef CONFIG_USER_ONLY
2424 /* 64 bit address translation operations */
2425 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2426 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2427 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2428 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2429 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2430 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2431 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2432 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2433 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2434 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2435 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2436 .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
2437 #endif
2438 /* TLB invalidate last level of translation table walk */
2439 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2440 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
2441 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2442 .type = ARM_CP_NO_RAW, .access = PL1_W,
2443 .writefn = tlbimvaa_is_write },
2444 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2445 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
2446 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2447 .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
2448 /* 32 bit cache operations */
2449 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2450 .type = ARM_CP_NOP, .access = PL1_W },
2451 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2452 .type = ARM_CP_NOP, .access = PL1_W },
2453 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2454 .type = ARM_CP_NOP, .access = PL1_W },
2455 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2456 .type = ARM_CP_NOP, .access = PL1_W },
2457 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2458 .type = ARM_CP_NOP, .access = PL1_W },
2459 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2460 .type = ARM_CP_NOP, .access = PL1_W },
2461 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2462 .type = ARM_CP_NOP, .access = PL1_W },
2463 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2464 .type = ARM_CP_NOP, .access = PL1_W },
2465 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2466 .type = ARM_CP_NOP, .access = PL1_W },
2467 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2468 .type = ARM_CP_NOP, .access = PL1_W },
2469 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2470 .type = ARM_CP_NOP, .access = PL1_W },
2471 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2472 .type = ARM_CP_NOP, .access = PL1_W },
2473 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2474 .type = ARM_CP_NOP, .access = PL1_W },
2475 /* MMU Domain access control / MPU write buffer control */
2476 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2477 .access = PL1_RW, .resetvalue = 0,
2478 .writefn = dacr_write, .raw_writefn = raw_write,
2479 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
2480 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
2481 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2482 .type = ARM_CP_ALIAS,
2483 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2484 .access = PL1_RW,
2485 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2486 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2487 .type = ARM_CP_ALIAS,
2488 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2489 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
2490 /* We rely on the access checks not allowing the guest to write to the
2491 * state field when SPSel indicates that it's being used as the stack
2492 * pointer.
2493 */
2494 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2495 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2496 .access = PL1_RW, .accessfn = sp_el0_access,
2497 .type = ARM_CP_ALIAS,
2498 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2499 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
2500 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
2501 .access = PL2_RW, .type = ARM_CP_ALIAS,
2502 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
2503 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2504 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2505 .type = ARM_CP_NO_RAW,
2506 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2507 REGINFO_SENTINEL
2508 };
2509
2510 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2511 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
2512 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2513 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2514 .access = PL2_RW,
2515 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2516 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2517 .type = ARM_CP_NO_RAW,
2518 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2519 .access = PL2_RW,
2520 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2521 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
2522 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
2523 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2524 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
2525 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
2526 .access = PL2_RW, .type = ARM_CP_CONST,
2527 .resetvalue = 0 },
2528 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
2529 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
2530 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2531 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
2532 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
2533 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2534 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
2535 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
2536 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2537 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
2538 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
2539 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2540 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
2541 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
2542 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2543 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
2544 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
2545 .resetvalue = 0 },
2546 REGINFO_SENTINEL
2547 };
2548
2549 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2550 {
2551 ARMCPU *cpu = arm_env_get_cpu(env);
2552 uint64_t valid_mask = HCR_MASK;
2553
2554 if (arm_feature(env, ARM_FEATURE_EL3)) {
2555 valid_mask &= ~HCR_HCD;
2556 } else {
2557 valid_mask &= ~HCR_TSC;
2558 }
2559
2560 /* Clear RES0 bits. */
2561 value &= valid_mask;
2562
2563 /* These bits change the MMU setup:
2564 * HCR_VM enables stage 2 translation
2565 * HCR_PTW forbids certain page-table setups
2566 * HCR_DC Disables stage1 and enables stage2 translation
2567 */
2568 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2569 tlb_flush(CPU(cpu), 1);
2570 }
2571 raw_write(env, ri, value);
2572 }
2573
2574 static const ARMCPRegInfo el2_cp_reginfo[] = {
2575 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2576 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2577 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2578 .writefn = hcr_write },
2579 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
2580 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
2581 .access = PL2_RW, .resetvalue = 0,
2582 .writefn = dacr_write, .raw_writefn = raw_write,
2583 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
2584 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2585 .type = ARM_CP_ALIAS,
2586 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2587 .access = PL2_RW,
2588 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2589 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2590 .type = ARM_CP_ALIAS,
2591 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2592 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2593 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
2594 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
2595 .access = PL2_RW, .resetvalue = 0,
2596 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
2597 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2598 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2599 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2600 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2601 .type = ARM_CP_ALIAS,
2602 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2603 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2604 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2605 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2606 .access = PL2_RW, .writefn = vbar_write,
2607 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2608 .resetvalue = 0 },
2609 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
2610 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
2611 .access = PL3_RW, .type = ARM_CP_ALIAS,
2612 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
2613 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
2614 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
2615 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
2616 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
2617 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
2618 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
2619 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
2620 .resetvalue = 0 },
2621 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
2622 .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
2623 .access = PL2_RW, .type = ARM_CP_ALIAS,
2624 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
2625 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
2626 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
2627 .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
2628 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2629 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
2630 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
2631 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
2632 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
2633 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
2634 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
2635 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
2636 .access = PL2_RW, .resetvalue = 0,
2637 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
2638 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
2639 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
2640 .access = PL2_RW, .resetvalue = 0,
2641 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
2642 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
2643 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2644 .resetvalue = 0,
2645 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
2646 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
2647 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
2648 .type = ARM_CP_NO_RAW, .access = PL2_W,
2649 .writefn = tlbiall_write },
2650 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
2651 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
2652 .type = ARM_CP_NO_RAW, .access = PL2_W,
2653 .writefn = tlbi_aa64_vaa_write },
2654 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
2655 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
2656 .type = ARM_CP_NO_RAW, .access = PL2_W,
2657 .writefn = tlbi_aa64_vaa_write },
2658 REGINFO_SENTINEL
2659 };
2660
2661 static const ARMCPRegInfo el3_cp_reginfo[] = {
2662 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2663 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2664 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2665 .resetvalue = 0, .writefn = scr_write },
2666 { .name = "SCR", .type = ARM_CP_ALIAS,
2667 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
2668 .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
2669 .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
2670 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
2671 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
2672 .access = PL3_RW, .resetvalue = 0,
2673 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
2674 { .name = "SDER",
2675 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
2676 .access = PL3_RW, .resetvalue = 0,
2677 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
2678 /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
2679 { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
2680 .access = PL3_W | PL1_R, .resetvalue = 0,
2681 .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
2682 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
2683 .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
2684 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
2685 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
2686 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
2687 .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
2688 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
2689 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
2690 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
2691 .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2692 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
2693 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
2694 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
2695 .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
2696 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2697 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
2698 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2699 .type = ARM_CP_ALIAS,
2700 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2701 .access = PL3_RW,
2702 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2703 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2704 .type = ARM_CP_ALIAS,
2705 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2706 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2707 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2708 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2709 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2710 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2711 .type = ARM_CP_ALIAS,
2712 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2713 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2714 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2715 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2716 .access = PL3_RW, .writefn = vbar_write,
2717 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2718 .resetvalue = 0 },
2719 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
2720 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
2721 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
2722 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
2723 REGINFO_SENTINEL
2724 };
2725
2726 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2727 {
2728 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2729 * but the AArch32 CTR has its own reginfo struct)
2730 */
2731 if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
2732 return CP_ACCESS_TRAP;
2733 }
2734 return CP_ACCESS_OK;
2735 }
2736
2737 static const ARMCPRegInfo debug_cp_reginfo[] = {
2738 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2739 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2740 * unlike DBGDRAR it is never accessible from EL0.
2741 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2742 * accessor.
2743 */
2744 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2745 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2746 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2747 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2748 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2749 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2750 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2751 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2752 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2753 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2754 .access = PL1_RW,
2755 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2756 .resetvalue = 0 },
2757 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2758 * We don't implement the configurable EL0 access.
2759 */
2760 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2761 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2762 .type = ARM_CP_ALIAS,
2763 .access = PL1_R,
2764 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2765 .resetfn = arm_cp_reset_ignore },
2766 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2767 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2768 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2769 .access = PL1_W, .type = ARM_CP_NOP },
2770 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2771 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2772 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2773 .access = PL1_RW, .type = ARM_CP_NOP },
2774 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2775 * implement vector catch debug events yet.
2776 */
2777 { .name = "DBGVCR",
2778 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2779 .access = PL1_RW, .type = ARM_CP_NOP },
2780 REGINFO_SENTINEL
2781 };
2782
2783 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2784 /* 64 bit access versions of the (dummy) debug registers */
2785 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2786 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2787 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2788 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2789 REGINFO_SENTINEL
2790 };
2791
2792 void hw_watchpoint_update(ARMCPU *cpu, int n)
2793 {
2794 CPUARMState *env = &cpu->env;
2795 vaddr len = 0;
2796 vaddr wvr = env->cp15.dbgwvr[n];
2797 uint64_t wcr = env->cp15.dbgwcr[n];
2798 int mask;
2799 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2800
2801 if (env->cpu_watchpoint[n]) {
2802 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2803 env->cpu_watchpoint[n] = NULL;
2804 }
2805
2806 if (!extract64(wcr, 0, 1)) {
2807 /* E bit clear : watchpoint disabled */
2808 return;
2809 }
2810
2811 switch (extract64(wcr, 3, 2)) {
2812 case 0:
2813 /* LSC 00 is reserved and must behave as if the wp is disabled */
2814 return;
2815 case 1:
2816 flags |= BP_MEM_READ;
2817 break;
2818 case 2:
2819 flags |= BP_MEM_WRITE;
2820 break;
2821 case 3:
2822 flags |= BP_MEM_ACCESS;
2823 break;
2824 }
2825
2826 /* Attempts to use both MASK and BAS fields simultaneously are
2827 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2828 * thus generating a watchpoint for every byte in the masked region.
2829 */
2830 mask = extract64(wcr, 24, 4);
2831 if (mask == 1 || mask == 2) {
2832 /* Reserved values of MASK; we must act as if the mask value was
2833 * some non-reserved value, or as if the watchpoint were disabled.
2834 * We choose the latter.
2835 */
2836 return;
2837 } else if (mask) {
2838 /* Watchpoint covers an aligned area up to 2GB in size */
2839 len = 1ULL << mask;
2840 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2841 * whether the watchpoint fires when the unmasked bits match; we opt
2842 * to generate the exceptions.
2843 */
2844 wvr &= ~(len - 1);
2845 } else {
2846 /* Watchpoint covers bytes defined by the byte address select bits */
2847 int bas = extract64(wcr, 5, 8);
2848 int basstart;
2849
2850 if (bas == 0) {
2851 /* This must act as if the watchpoint is disabled */
2852 return;
2853 }
2854
2855 if (extract64(wvr, 2, 1)) {
2856 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2857 * ignored, and BAS[3:0] define which bytes to watch.
2858 */
2859 bas &= 0xf;
2860 }
2861 /* The BAS bits are supposed to be programmed to indicate a contiguous
2862 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2863 * we fire for each byte in the word/doubleword addressed by the WVR.
2864 * We choose to ignore any non-zero bits after the first range of 1s.
2865 */
2866 basstart = ctz32(bas);
2867 len = cto32(bas >> basstart);
2868 wvr += basstart;
2869 }
2870
2871 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2872 &env->cpu_watchpoint[n]);
2873 }
2874
2875 void hw_watchpoint_update_all(ARMCPU *cpu)
2876 {
2877 int i;
2878 CPUARMState *env = &cpu->env;
2879
2880 /* Completely clear out existing QEMU watchpoints and our array, to
2881 * avoid possible stale entries following migration load.
2882 */
2883 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2884 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2885
2886 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2887 hw_watchpoint_update(cpu, i);
2888 }
2889 }
2890
2891 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2892 uint64_t value)
2893 {
2894 ARMCPU *cpu = arm_env_get_cpu(env);
2895 int i = ri->crm;
2896
2897 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2898 * register reads and behaves as if values written are sign extended.
2899 * Bits [1:0] are RES0.
2900 */
2901 value = sextract64(value, 0, 49) & ~3ULL;
2902
2903 raw_write(env, ri, value);
2904 hw_watchpoint_update(cpu, i);
2905 }
2906
2907 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2908 uint64_t value)
2909 {
2910 ARMCPU *cpu = arm_env_get_cpu(env);
2911 int i = ri->crm;
2912
2913 raw_write(env, ri, value);
2914 hw_watchpoint_update(cpu, i);
2915 }
2916
2917 void hw_breakpoint_update(ARMCPU *cpu, int n)
2918 {
2919 CPUARMState *env = &cpu->env;
2920 uint64_t bvr = env->cp15.dbgbvr[n];
2921 uint64_t bcr = env->cp15.dbgbcr[n];
2922 vaddr addr;
2923 int bt;
2924 int flags = BP_CPU;
2925
2926 if (env->cpu_breakpoint[n]) {
2927 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2928 env->cpu_breakpoint[n] = NULL;
2929 }
2930
2931 if (!extract64(bcr, 0, 1)) {
2932 /* E bit clear : watchpoint disabled */
2933 return;
2934 }
2935
2936 bt = extract64(bcr, 20, 4);
2937
2938 switch (bt) {
2939 case 4: /* unlinked address mismatch (reserved if AArch64) */
2940 case 5: /* linked address mismatch (reserved if AArch64) */
2941 qemu_log_mask(LOG_UNIMP,
2942 "arm: address mismatch breakpoint types not implemented");
2943 return;
2944 case 0: /* unlinked address match */
2945 case 1: /* linked address match */
2946 {
2947 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2948 * we behave as if the register was sign extended. Bits [1:0] are
2949 * RES0. The BAS field is used to allow setting breakpoints on 16
2950 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2951 * a bp will fire if the addresses covered by the bp and the addresses
2952 * covered by the insn overlap but the insn doesn't start at the
2953 * start of the bp address range. We choose to require the insn and
2954 * the bp to have the same address. The constraints on writing to
2955 * BAS enforced in dbgbcr_write mean we have only four cases:
2956 * 0b0000 => no breakpoint
2957 * 0b0011 => breakpoint on addr
2958 * 0b1100 => breakpoint on addr + 2
2959 * 0b1111 => breakpoint on addr
2960 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2961 */
2962 int bas = extract64(bcr, 5, 4);
2963 addr = sextract64(bvr, 0, 49) & ~3ULL;
2964 if (bas == 0) {
2965 return;
2966 }
2967 if (bas == 0xc) {
2968 addr += 2;
2969 }
2970 break;
2971 }
2972 case 2: /* unlinked context ID match */
2973 case 8: /* unlinked VMID match (reserved if no EL2) */
2974 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2975 qemu_log_mask(LOG_UNIMP,
2976 "arm: unlinked context breakpoint types not implemented");
2977 return;
2978 case 9: /* linked VMID match (reserved if no EL2) */
2979 case 11: /* linked context ID and VMID match (reserved if no EL2) */
2980 case 3: /* linked context ID match */
2981 default:
2982 /* We must generate no events for Linked context matches (unless
2983 * they are linked to by some other bp/wp, which is handled in
2984 * updates for the linking bp/wp). We choose to also generate no events
2985 * for reserved values.
2986 */
2987 return;
2988 }
2989
2990 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2991 }
2992
2993 void hw_breakpoint_update_all(ARMCPU *cpu)
2994 {
2995 int i;
2996 CPUARMState *env = &cpu->env;
2997
2998 /* Completely clear out existing QEMU breakpoints and our array, to
2999 * avoid possible stale entries following migration load.
3000 */
3001 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
3002 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
3003
3004 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
3005 hw_breakpoint_update(cpu, i);
3006 }
3007 }
3008
3009 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3010 uint64_t value)
3011 {
3012 ARMCPU *cpu = arm_env_get_cpu(env);
3013 int i = ri->crm;
3014
3015 raw_write(env, ri, value);
3016 hw_breakpoint_update(cpu, i);
3017 }
3018
3019 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3020 uint64_t value)
3021 {
3022 ARMCPU *cpu = arm_env_get_cpu(env);
3023 int i = ri->crm;
3024
3025 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
3026 * copy of BAS[0].
3027 */
3028 value = deposit64(value, 6, 1, extract64(value, 5, 1));
3029 value = deposit64(value, 8, 1, extract64(value, 7, 1));
3030
3031 raw_write(env, ri, value);
3032 hw_breakpoint_update(cpu, i);
3033 }
3034
3035 static void define_debug_regs(ARMCPU *cpu)
3036 {
3037 /* Define v7 and v8 architectural debug registers.
3038 * These are just dummy implementations for now.
3039 */
3040 int i;
3041 int wrps, brps, ctx_cmps;
3042 ARMCPRegInfo dbgdidr = {
3043 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
3044 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
3045 };
3046
3047 /* Note that all these register fields hold "number of Xs minus 1". */
3048 brps = extract32(cpu->dbgdidr, 24, 4);
3049 wrps = extract32(cpu->dbgdidr, 28, 4);
3050 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
3051
3052 assert(ctx_cmps <= brps);
3053
3054 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
3055 * of the debug registers such as number of breakpoints;
3056 * check that if they both exist then they agree.
3057 */
3058 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
3059 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
3060 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
3061 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
3062 }
3063
3064 define_one_arm_cp_reg(cpu, &dbgdidr);
3065 define_arm_cp_regs(cpu, debug_cp_reginfo);
3066
3067 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
3068 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
3069 }
3070
3071 for (i = 0; i < brps + 1; i++) {
3072 ARMCPRegInfo dbgregs[] = {
3073 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
3074 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
3075 .access = PL1_RW,
3076 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
3077 .writefn = dbgbvr_write, .raw_writefn = raw_write
3078 },
3079 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
3080 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
3081 .access = PL1_RW,
3082 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
3083 .writefn = dbgbcr_write, .raw_writefn = raw_write
3084 },
3085 REGINFO_SENTINEL
3086 };
3087 define_arm_cp_regs(cpu, dbgregs);
3088 }
3089
3090 for (i = 0; i < wrps + 1; i++) {
3091 ARMCPRegInfo dbgregs[] = {
3092 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
3093 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
3094 .access = PL1_RW,
3095 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
3096 .writefn = dbgwvr_write, .raw_writefn = raw_write
3097 },
3098 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
3099 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
3100 .access = PL1_RW,
3101 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
3102 .writefn = dbgwcr_write, .raw_writefn = raw_write
3103 },
3104 REGINFO_SENTINEL
3105 };
3106 define_arm_cp_regs(cpu, dbgregs);
3107 }
3108 }
3109
3110 void register_cp_regs_for_features(ARMCPU *cpu)
3111 {
3112 /* Register all the coprocessor registers based on feature bits */
3113 CPUARMState *env = &cpu->env;
3114 if (arm_feature(env, ARM_FEATURE_M)) {
3115 /* M profile has no coprocessor registers */
3116 return;
3117 }
3118
3119 define_arm_cp_regs(cpu, cp_reginfo);
3120 if (!arm_feature(env, ARM_FEATURE_V8)) {
3121 /* Must go early as it is full of wildcards that may be
3122 * overridden by later definitions.
3123 */
3124 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
3125 }
3126
3127 if (arm_feature(env, ARM_FEATURE_V6)) {
3128 /* The ID registers all have impdef reset values */
3129 ARMCPRegInfo v6_idregs[] = {
3130 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
3131 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3132 .access = PL1_R, .type = ARM_CP_CONST,
3133 .resetvalue = cpu->id_pfr0 },
3134 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
3135 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
3136 .access = PL1_R, .type = ARM_CP_CONST,
3137 .resetvalue = cpu->id_pfr1 },
3138 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
3139 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
3140 .access = PL1_R, .type = ARM_CP_CONST,
3141 .resetvalue = cpu->id_dfr0 },
3142 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
3143 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
3144 .access = PL1_R, .type = ARM_CP_CONST,
3145 .resetvalue = cpu->id_afr0 },
3146 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
3147 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
3148 .access = PL1_R, .type = ARM_CP_CONST,
3149 .resetvalue = cpu->id_mmfr0 },
3150 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
3151 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
3152 .access = PL1_R, .type = ARM_CP_CONST,
3153 .resetvalue = cpu->id_mmfr1 },
3154 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
3155 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
3156 .access = PL1_R, .type = ARM_CP_CONST,
3157 .resetvalue = cpu->id_mmfr2 },
3158 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
3159 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
3160 .access = PL1_R, .type = ARM_CP_CONST,
3161 .resetvalue = cpu->id_mmfr3 },
3162 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
3163 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
3164 .access = PL1_R, .type = ARM_CP_CONST,
3165 .resetvalue = cpu->id_isar0 },
3166 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
3167 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
3168 .access = PL1_R, .type = ARM_CP_CONST,
3169 .resetvalue = cpu->id_isar1 },
3170 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
3171 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3172 .access = PL1_R, .type = ARM_CP_CONST,
3173 .resetvalue = cpu->id_isar2 },
3174 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
3175 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
3176 .access = PL1_R, .type = ARM_CP_CONST,
3177 .resetvalue = cpu->id_isar3 },
3178 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
3179 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
3180 .access = PL1_R, .type = ARM_CP_CONST,
3181 .resetvalue = cpu->id_isar4 },
3182 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
3183 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
3184 .access = PL1_R, .type = ARM_CP_CONST,
3185 .resetvalue = cpu->id_isar5 },
3186 /* 6..7 are as yet unallocated and must RAZ */
3187 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
3188 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
3189 .resetvalue = 0 },
3190 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
3191 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
3192 .resetvalue = 0 },
3193 REGINFO_SENTINEL
3194 };
3195 define_arm_cp_regs(cpu, v6_idregs);
3196 define_arm_cp_regs(cpu, v6_cp_reginfo);
3197 } else {
3198 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
3199 }
3200 if (arm_feature(env, ARM_FEATURE_V6K)) {
3201 define_arm_cp_regs(cpu, v6k_cp_reginfo);
3202 }
3203 if (arm_feature(env, ARM_FEATURE_V7MP) &&
3204 !arm_feature(env, ARM_FEATURE_MPU)) {
3205 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
3206 }
3207 if (arm_feature(env, ARM_FEATURE_V7)) {
3208 /* v7 performance monitor control register: same implementor
3209 * field as main ID register, and we implement only the cycle
3210 * count register.
3211 */
3212 #ifndef CONFIG_USER_ONLY
3213 ARMCPRegInfo pmcr = {
3214 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
3215 .access = PL0_RW,
3216 .type = ARM_CP_IO | ARM_CP_ALIAS,
3217 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
3218 .accessfn = pmreg_access, .writefn = pmcr_write,
3219 .raw_writefn = raw_write,
3220 };
3221 ARMCPRegInfo pmcr64 = {
3222 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
3223 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
3224 .access = PL0_RW, .accessfn = pmreg_access,
3225 .type = ARM_CP_IO,
3226 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
3227 .resetvalue = cpu->midr & 0xff000000,
3228 .writefn = pmcr_write, .raw_writefn = raw_write,
3229 };
3230 define_one_arm_cp_reg(cpu, &pmcr);
3231 define_one_arm_cp_reg(cpu, &pmcr64);
3232 #endif
3233 ARMCPRegInfo clidr = {
3234 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
3235 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
3236 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
3237 };
3238 define_one_arm_cp_reg(cpu, &clidr);
3239 define_arm_cp_regs(cpu, v7_cp_reginfo);
3240 define_debug_regs(cpu);
3241 } else {
3242 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
3243 }
3244 if (arm_feature(env, ARM_FEATURE_V8)) {
3245 /* AArch64 ID registers, which all have impdef reset values */
3246 ARMCPRegInfo v8_idregs[] = {
3247 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
3248 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
3249 .access = PL1_R, .type = ARM_CP_CONST,
3250 .resetvalue = cpu->id_aa64pfr0 },
3251 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
3252 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
3253 .access = PL1_R, .type = ARM_CP_CONST,
3254 .resetvalue = cpu->id_aa64pfr1},
3255 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
3256 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
3257 .access = PL1_R, .type = ARM_CP_CONST,
3258 /* We mask out the PMUVer field, because we don't currently
3259 * implement the PMU. Not advertising it prevents the guest
3260 * from trying to use it and getting UNDEFs on registers we
3261 * don't implement.
3262 */
3263 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
3264 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
3265 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
3266 .access = PL1_R, .type = ARM_CP_CONST,
3267 .resetvalue = cpu->id_aa64dfr1 },
3268 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
3269 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
3270 .access = PL1_R, .type = ARM_CP_CONST,
3271 .resetvalue = cpu->id_aa64afr0 },
3272 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
3273 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
3274 .access = PL1_R, .type = ARM_CP_CONST,
3275 .resetvalue = cpu->id_aa64afr1 },
3276 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
3277 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
3278 .access = PL1_R, .type = ARM_CP_CONST,
3279 .resetvalue = cpu->id_aa64isar0 },
3280 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
3281 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
3282 .access = PL1_R, .type = ARM_CP_CONST,
3283 .resetvalue = cpu->id_aa64isar1 },
3284 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
3285 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3286 .access = PL1_R, .type = ARM_CP_CONST,
3287 .resetvalue = cpu->id_aa64mmfr0 },
3288 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
3289 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
3290 .access = PL1_R, .type = ARM_CP_CONST,
3291 .resetvalue = cpu->id_aa64mmfr1 },
3292 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
3293 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
3294 .access = PL1_R, .type = ARM_CP_CONST,
3295 .resetvalue = cpu->mvfr0 },
3296 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
3297 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
3298 .access = PL1_R, .type = ARM_CP_CONST,
3299 .resetvalue = cpu->mvfr1 },
3300 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
3301 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
3302 .access = PL1_R, .type = ARM_CP_CONST,
3303 .resetvalue = cpu->mvfr2 },
3304 REGINFO_SENTINEL
3305 };
3306 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
3307 if (!arm_feature(env, ARM_FEATURE_EL3) &&
3308 !arm_feature(env, ARM_FEATURE_EL2)) {
3309 ARMCPRegInfo rvbar = {
3310 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
3311 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3312 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
3313 };
3314 define_one_arm_cp_reg(cpu, &rvbar);
3315 }
3316 define_arm_cp_regs(cpu, v8_idregs);
3317 define_arm_cp_regs(cpu, v8_cp_reginfo);
3318 }
3319 if (arm_feature(env, ARM_FEATURE_EL2)) {
3320 define_arm_cp_regs(cpu, el2_cp_reginfo);
3321 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
3322 if (!arm_feature(env, ARM_FEATURE_EL3)) {
3323 ARMCPRegInfo rvbar = {
3324 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
3325 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
3326 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
3327 };
3328 define_one_arm_cp_reg(cpu, &rvbar);
3329 }
3330 } else {
3331 /* If EL2 is missing but higher ELs are enabled, we need to
3332 * register the no_el2 reginfos.
3333 */
3334 if (arm_feature(env, ARM_FEATURE_EL3)) {
3335 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
3336 }
3337 }
3338 if (arm_feature(env, ARM_FEATURE_EL3)) {
3339 define_arm_cp_regs(cpu, el3_cp_reginfo);
3340 ARMCPRegInfo rvbar = {
3341 .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
3342 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
3343 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
3344 };
3345 define_one_arm_cp_reg(cpu, &rvbar);
3346 }
3347 if (arm_feature(env, ARM_FEATURE_MPU)) {
3348 /* These are the MPU registers prior to PMSAv6. Any new
3349 * PMSA core later than the ARM946 will require that we
3350 * implement the PMSAv6 or PMSAv7 registers, which are
3351 * completely different.
3352 */
3353 assert(!arm_feature(env, ARM_FEATURE_V6));
3354 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
3355 } else {
3356 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
3357 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
3358 }
3359 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
3360 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
3361 }
3362 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
3363 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
3364 }
3365 if (arm_feature(env, ARM_FEATURE_VAPA)) {
3366 define_arm_cp_regs(cpu, vapa_cp_reginfo);
3367 }
3368 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
3369 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
3370 }
3371 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
3372 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
3373 }
3374 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
3375 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
3376 }
3377 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
3378 define_arm_cp_regs(cpu, omap_cp_reginfo);
3379 }
3380 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
3381 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
3382 }
3383 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3384 define_arm_cp_regs(cpu, xscale_cp_reginfo);
3385 }
3386 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
3387 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
3388 }
3389 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3390 define_arm_cp_regs(cpu, lpae_cp_reginfo);
3391 }
3392 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
3393 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
3394 * be read-only (ie write causes UNDEF exception).
3395 */
3396 {
3397 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
3398 /* Pre-v8 MIDR space.
3399 * Note that the MIDR isn't a simple constant register because
3400 * of the TI925 behaviour where writes to another register can
3401 * cause the MIDR value to change.
3402 *
3403 * Unimplemented registers in the c15 0 0 0 space default to
3404 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
3405 * and friends override accordingly.
3406 */
3407 { .name = "MIDR",
3408 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
3409 .access = PL1_R, .resetvalue = cpu->midr,
3410 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
3411 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
3412 .type = ARM_CP_OVERRIDE },
3413 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
3414 { .name = "DUMMY",
3415 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
3416 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3417 { .name = "DUMMY",
3418 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
3419 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3420 { .name = "DUMMY",
3421 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
3422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3423 { .name = "DUMMY",
3424 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
3425 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3426 { .name = "DUMMY",
3427 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
3428 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3429 REGINFO_SENTINEL
3430 };
3431 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
3432 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
3433 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
3434 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
3435 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
3436 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
3437 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
3438 .access = PL1_R, .resetvalue = cpu->midr },
3439 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
3440 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
3441 .access = PL1_R, .resetvalue = cpu->midr },
3442 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
3443 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
3444 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
3445 REGINFO_SENTINEL
3446 };
3447 ARMCPRegInfo id_cp_reginfo[] = {
3448 /* These are common to v8 and pre-v8 */
3449 { .name = "CTR",
3450 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
3451 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3452 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
3453 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
3454 .access = PL0_R, .accessfn = ctr_el0_access,
3455 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
3456 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
3457 { .name = "TCMTR",
3458 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
3459 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
3460 REGINFO_SENTINEL
3461 };
3462 /* TLBTR is specific to VMSA */
3463 ARMCPRegInfo id_tlbtr_reginfo = {
3464 .name = "TLBTR",
3465 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
3466 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
3467 };
3468 ARMCPRegInfo crn0_wi_reginfo = {
3469 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
3470 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
3471 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
3472 };
3473 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
3474 arm_feature(env, ARM_FEATURE_STRONGARM)) {
3475 ARMCPRegInfo *r;
3476 /* Register the blanket "writes ignored" value first to cover the
3477 * whole space. Then update the specific ID registers to allow write
3478 * access, so that they ignore writes rather than causing them to
3479 * UNDEF.
3480 */
3481 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
3482 for (r = id_pre_v8_midr_cp_reginfo;
3483 r->type != ARM_CP_SENTINEL; r++) {
3484 r->access = PL1_RW;
3485 }
3486 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
3487 r->access = PL1_RW;
3488 }
3489 id_tlbtr_reginfo.access = PL1_RW;
3490 }
3491 if (arm_feature(env, ARM_FEATURE_V8)) {
3492 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
3493 } else {
3494 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
3495 }
3496 define_arm_cp_regs(cpu, id_cp_reginfo);
3497 if (!arm_feature(env, ARM_FEATURE_MPU)) {
3498 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
3499 }
3500 }
3501
3502 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
3503 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
3504 }
3505
3506 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
3507 ARMCPRegInfo auxcr = {
3508 .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
3509 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
3510 .access = PL1_RW, .type = ARM_CP_CONST,
3511 .resetvalue = cpu->reset_auxcr
3512 };
3513 define_one_arm_cp_reg(cpu, &auxcr);
3514 }
3515
3516 if (arm_feature(env, ARM_FEATURE_CBAR)) {
3517 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3518 /* 32 bit view is [31:18] 0...0 [43:32]. */
3519 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
3520 | extract64(cpu->reset_cbar, 32, 12);
3521 ARMCPRegInfo cbar_reginfo[] = {
3522 { .name = "CBAR",
3523 .type = ARM_CP_CONST,
3524 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3525 .access = PL1_R, .resetvalue = cpu->reset_cbar },
3526 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
3527 .type = ARM_CP_CONST,
3528 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
3529 .access = PL1_R, .resetvalue = cbar32 },
3530 REGINFO_SENTINEL
3531 };
3532 /* We don't implement a r/w 64 bit CBAR currently */
3533 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
3534 define_arm_cp_regs(cpu, cbar_reginfo);
3535 } else {
3536 ARMCPRegInfo cbar = {
3537 .name = "CBAR",
3538 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
3539 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
3540 .fieldoffset = offsetof(CPUARMState,
3541 cp15.c15_config_base_address)
3542 };
3543 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
3544 cbar.access = PL1_R;
3545 cbar.fieldoffset = 0;
3546 cbar.type = ARM_CP_CONST;
3547 }
3548 define_one_arm_cp_reg(cpu, &cbar);
3549 }
3550 }
3551
3552 /* Generic registers whose values depend on the implementation */
3553 {
3554 ARMCPRegInfo sctlr = {
3555 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
3556 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3557 .access = PL1_RW,
3558 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
3559 offsetof(CPUARMState, cp15.sctlr_ns) },
3560 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
3561 .raw_writefn = raw_write,
3562 };
3563 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3564 /* Normally we would always end the TB on an SCTLR write, but Linux
3565 * arch/arm/mach-pxa/sleep.S expects two instructions following
3566 * an MMU enable to execute from cache. Imitate this behaviour.
3567 */
3568 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
3569 }
3570 define_one_arm_cp_reg(cpu, &sctlr);
3571 }
3572 }
3573
3574 ARMCPU *cpu_arm_init(const char *cpu_model)
3575 {
3576 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
3577 }
3578
3579 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
3580 {
3581 CPUState *cs = CPU(cpu);
3582 CPUARMState *env = &cpu->env;
3583
3584 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
3585 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
3586 aarch64_fpu_gdb_set_reg,
3587 34, "aarch64-fpu.xml", 0);
3588 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
3589 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3590 51, "arm-neon.xml", 0);
3591 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
3592 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3593 35, "arm-vfp3.xml", 0);
3594 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
3595 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
3596 19, "arm-vfp.xml", 0);
3597 }
3598 }
3599
3600 /* Sort alphabetically by type name, except for "any". */
3601 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
3602 {
3603 ObjectClass *class_a = (ObjectClass *)a;
3604 ObjectClass *class_b = (ObjectClass *)b;
3605 const char *name_a, *name_b;
3606
3607 name_a = object_class_get_name(class_a);
3608 name_b = object_class_get_name(class_b);
3609 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
3610 return 1;
3611 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
3612 return -1;
3613 } else {
3614 return strcmp(name_a, name_b);
3615 }
3616 }
3617
3618 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
3619 {
3620 ObjectClass *oc = data;
3621 CPUListState *s = user_data;
3622 const char *typename;
3623 char *name;
3624
3625 typename = object_class_get_name(oc);
3626 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
3627 (*s->cpu_fprintf)(s->file, " %s\n",
3628 name);
3629 g_free(name);
3630 }
3631
3632 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3633 {
3634 CPUListState s = {
3635 .file = f,
3636 .cpu_fprintf = cpu_fprintf,
3637 };
3638 GSList *list;
3639
3640 list = object_class_get_list(TYPE_ARM_CPU, false);
3641 list = g_slist_sort(list, arm_cpu_list_compare);
3642 (*cpu_fprintf)(f, "Available CPUs:\n");
3643 g_slist_foreach(list, arm_cpu_list_entry, &s);
3644 g_slist_free(list);
3645 #ifdef CONFIG_KVM
3646 /* The 'host' CPU type is dynamically registered only if KVM is
3647 * enabled, so we have to special-case it here:
3648 */
3649 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
3650 #endif
3651 }
3652
3653 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
3654 {
3655 ObjectClass *oc = data;
3656 CpuDefinitionInfoList **cpu_list = user_data;
3657 CpuDefinitionInfoList *entry;
3658 CpuDefinitionInfo *info;
3659 const char *typename;
3660
3661 typename = object_class_get_name(oc);
3662 info = g_malloc0(sizeof(*info));
3663 info->name = g_strndup(typename,
3664 strlen(typename) - strlen("-" TYPE_ARM_CPU));
3665
3666 entry = g_malloc0(sizeof(*entry));
3667 entry->value = info;
3668 entry->next = *cpu_list;
3669 *cpu_list = entry;
3670 }
3671
3672 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
3673 {
3674 CpuDefinitionInfoList *cpu_list = NULL;
3675 GSList *list;
3676
3677 list = object_class_get_list(TYPE_ARM_CPU, false);
3678 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
3679 g_slist_free(list);
3680
3681 return cpu_list;
3682 }
3683
3684 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
3685 void *opaque, int state, int secstate,
3686 int crm, int opc1, int opc2)
3687 {
3688 /* Private utility function for define_one_arm_cp_reg_with_opaque():
3689 * add a single reginfo struct to the hash table.
3690 */
3691 uint32_t *key = g_new(uint32_t, 1);
3692 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
3693 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3694 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
3695
3696 /* Reset the secure state to the specific incoming state. This is
3697 * necessary as the register may have been defined with both states.
3698 */
3699 r2->secure = secstate;
3700
3701 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3702 /* Register is banked (using both entries in array).
3703 * Overwriting fieldoffset as the array is only used to define
3704 * banked registers but later only fieldoffset is used.
3705 */
3706 r2->fieldoffset = r->bank_fieldoffsets[ns];
3707 }
3708
3709 if (state == ARM_CP_STATE_AA32) {
3710 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
3711 /* If the register is banked then we don't need to migrate or
3712 * reset the 32-bit instance in certain cases:
3713 *
3714 * 1) If the register has both 32-bit and 64-bit instances then we
3715 * can count on the 64-bit instance taking care of the
3716 * non-secure bank.
3717 * 2) If ARMv8 is enabled then we can count on a 64-bit version
3718 * taking care of the secure bank. This requires that separate
3719 * 32 and 64-bit definitions are provided.
3720 */
3721 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
3722 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
3723 r2->type |= ARM_CP_ALIAS;
3724 r2->resetfn = arm_cp_reset_ignore;
3725 }
3726 } else if ((secstate != r->secure) && !ns) {
3727 /* The register is not banked so we only want to allow migration of
3728 * the non-secure instance.
3729 */
3730 r2->type |= ARM_CP_ALIAS;
3731 r2->resetfn = arm_cp_reset_ignore;
3732 }
3733
3734 if (r->state == ARM_CP_STATE_BOTH) {
3735 /* We assume it is a cp15 register if the .cp field is left unset.
3736 */
3737 if (r2->cp == 0) {
3738 r2->cp = 15;
3739 }
3740
3741 #ifdef HOST_WORDS_BIGENDIAN
3742 if (r2->fieldoffset) {
3743 r2->fieldoffset += sizeof(uint32_t);
3744 }
3745 #endif
3746 }
3747 }
3748 if (state == ARM_CP_STATE_AA64) {
3749 /* To allow abbreviation of ARMCPRegInfo
3750 * definitions, we treat cp == 0 as equivalent to
3751 * the value for "standard guest-visible sysreg".
3752 * STATE_BOTH definitions are also always "standard
3753 * sysreg" in their AArch64 view (the .cp value may
3754 * be non-zero for the benefit of the AArch32 view).
3755 */
3756 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
3757 r2->cp = CP_REG_ARM64_SYSREG_CP;
3758 }
3759 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
3760 r2->opc0, opc1, opc2);
3761 } else {
3762 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
3763 }
3764 if (opaque) {
3765 r2->opaque = opaque;
3766 }
3767 /* reginfo passed to helpers is correct for the actual access,
3768 * and is never ARM_CP_STATE_BOTH:
3769 */
3770 r2->state = state;
3771 /* Make sure reginfo passed to helpers for wildcarded regs
3772 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
3773 */
3774 r2->crm = crm;
3775 r2->opc1 = opc1;
3776 r2->opc2 = opc2;
3777 /* By convention, for wildcarded registers only the first
3778 * entry is used for migration; the others are marked as
3779 * ALIAS so we don't try to transfer the register
3780 * multiple times. Special registers (ie NOP/WFI) are
3781 * never migratable and not even raw-accessible.
3782 */
3783 if ((r->type & ARM_CP_SPECIAL)) {
3784 r2->type |= ARM_CP_NO_RAW;
3785 }
3786 if (((r->crm == CP_ANY) && crm != 0) ||
3787 ((r->opc1 == CP_ANY) && opc1 != 0) ||
3788 ((r->opc2 == CP_ANY) && opc2 != 0)) {
3789 r2->type |= ARM_CP_ALIAS;
3790 }
3791
3792 /* Check that raw accesses are either forbidden or handled. Note that
3793 * we can't assert this earlier because the setup of fieldoffset for
3794 * banked registers has to be done first.
3795 */
3796 if (!(r2->type & ARM_CP_NO_RAW)) {
3797 assert(!raw_accessors_invalid(r2));
3798 }
3799
3800 /* Overriding of an existing definition must be explicitly
3801 * requested.
3802 */
3803 if (!(r->type & ARM_CP_OVERRIDE)) {
3804 ARMCPRegInfo *oldreg;
3805 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
3806 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
3807 fprintf(stderr, "Register redefined: cp=%d %d bit "
3808 "crn=%d crm=%d opc1=%d opc2=%d, "
3809 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
3810 r2->crn, r2->crm, r2->opc1, r2->opc2,
3811 oldreg->name, r2->name);
3812 g_assert_not_reached();
3813 }
3814 }
3815 g_hash_table_insert(cpu->cp_regs, key, r2);
3816 }
3817
3818
3819 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
3820 const ARMCPRegInfo *r, void *opaque)
3821 {
3822 /* Define implementations of coprocessor registers.
3823 * We store these in a hashtable because typically
3824 * there are less than 150 registers in a space which
3825 * is 16*16*16*8*8 = 262144 in size.
3826 * Wildcarding is supported for the crm, opc1 and opc2 fields.
3827 * If a register is defined twice then the second definition is
3828 * used, so this can be used to define some generic registers and
3829 * then override them with implementation specific variations.
3830 * At least one of the original and the second definition should
3831 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
3832 * against accidental use.
3833 *
3834 * The state field defines whether the register is to be
3835 * visible in the AArch32 or AArch64 execution state. If the
3836 * state is set to ARM_CP_STATE_BOTH then we synthesise a
3837 * reginfo structure for the AArch32 view, which sees the lower
3838 * 32 bits of the 64 bit register.
3839 *
3840 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
3841 * be wildcarded. AArch64 registers are always considered to be 64
3842 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
3843 * the register, if any.
3844 */
3845 int crm, opc1, opc2, state;
3846 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
3847 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
3848 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
3849 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
3850 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
3851 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
3852 /* 64 bit registers have only CRm and Opc1 fields */
3853 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
3854 /* op0 only exists in the AArch64 encodings */
3855 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
3856 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
3857 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
3858 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
3859 * encodes a minimum access level for the register. We roll this
3860 * runtime check into our general permission check code, so check
3861 * here that the reginfo's specified permissions are strict enough
3862 * to encompass the generic architectural permission check.
3863 */
3864 if (r->state != ARM_CP_STATE_AA32) {
3865 int mask = 0;
3866 switch (r->opc1) {
3867 case 0: case 1: case 2:
3868 /* min_EL EL1 */
3869 mask = PL1_RW;
3870 break;
3871 case 3:
3872 /* min_EL EL0 */
3873 mask = PL0_RW;
3874 break;
3875 case 4:
3876 /* min_EL EL2 */
3877 mask = PL2_RW;
3878 break;
3879 case 5:
3880 /* unallocated encoding, so not possible */
3881 assert(false);
3882 break;
3883 case 6:
3884 /* min_EL EL3 */
3885 mask = PL3_RW;
3886 break;
3887 case 7:
3888 /* min_EL EL1, secure mode only (we don't check the latter) */
3889 mask = PL1_RW;
3890 break;
3891 default:
3892 /* broken reginfo with out-of-range opc1 */
3893 assert(false);
3894 break;
3895 }
3896 /* assert our permissions are not too lax (stricter is fine) */
3897 assert((r->access & ~mask) == 0);
3898 }
3899
3900 /* Check that the register definition has enough info to handle
3901 * reads and writes if they are permitted.
3902 */
3903 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3904 if (r->access & PL3_R) {
3905 assert((r->fieldoffset ||
3906 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3907 r->readfn);
3908 }
3909 if (r->access & PL3_W) {
3910 assert((r->fieldoffset ||
3911 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
3912 r->writefn);
3913 }
3914 }
3915 /* Bad type field probably means missing sentinel at end of reg list */
3916 assert(cptype_valid(r->type));
3917 for (crm = crmmin; crm <= crmmax; crm++) {
3918 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3919 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3920 for (state = ARM_CP_STATE_AA32;
3921 state <= ARM_CP_STATE_AA64; state++) {
3922 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3923 continue;
3924 }
3925 if (state == ARM_CP_STATE_AA32) {
3926 /* Under AArch32 CP registers can be common
3927 * (same for secure and non-secure world) or banked.
3928 */
3929 switch (r->secure) {
3930 case ARM_CP_SECSTATE_S:
3931 case ARM_CP_SECSTATE_NS:
3932 add_cpreg_to_hashtable(cpu, r, opaque, state,
3933 r->secure, crm, opc1, opc2);
3934 break;
3935 default:
3936 add_cpreg_to_hashtable(cpu, r, opaque, state,
3937 ARM_CP_SECSTATE_S,
3938 crm, opc1, opc2);
3939 add_cpreg_to_hashtable(cpu, r, opaque, state,
3940 ARM_CP_SECSTATE_NS,
3941 crm, opc1, opc2);
3942 break;
3943 }
3944 } else {
3945 /* AArch64 registers get mapped to non-secure instance
3946 * of AArch32 */
3947 add_cpreg_to_hashtable(cpu, r, opaque, state,
3948 ARM_CP_SECSTATE_NS,
3949 crm, opc1, opc2);
3950 }
3951 }
3952 }
3953 }
3954 }
3955 }
3956
3957 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3958 const ARMCPRegInfo *regs, void *opaque)
3959 {
3960 /* Define a whole list of registers */
3961 const ARMCPRegInfo *r;
3962 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3963 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3964 }
3965 }
3966
3967 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3968 {
3969 return g_hash_table_lookup(cpregs, &encoded_cp);
3970 }
3971
3972 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3973 uint64_t value)
3974 {
3975 /* Helper coprocessor write function for write-ignore registers */
3976 }
3977
3978 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3979 {
3980 /* Helper coprocessor write function for read-as-zero registers */
3981 return 0;
3982 }
3983
3984 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3985 {
3986 /* Helper coprocessor reset function for do-nothing-on-reset registers */
3987 }
3988
3989 static int bad_mode_switch(CPUARMState *env, int mode)
3990 {
3991 /* Return true if it is not valid for us to switch to
3992 * this CPU mode (ie all the UNPREDICTABLE cases in
3993 * the ARM ARM CPSRWriteByInstr pseudocode).
3994 */
3995 switch (mode) {
3996 case ARM_CPU_MODE_USR:
3997 case ARM_CPU_MODE_SYS:
3998 case ARM_CPU_MODE_SVC:
3999 case ARM_CPU_MODE_ABT:
4000 case ARM_CPU_MODE_UND:
4001 case ARM_CPU_MODE_IRQ:
4002 case ARM_CPU_MODE_FIQ:
4003 return 0;
4004 case ARM_CPU_MODE_MON:
4005 return !arm_is_secure(env);
4006 default:
4007 return 1;
4008 }
4009 }
4010
4011 uint32_t cpsr_read(CPUARMState *env)
4012 {
4013 int ZF;
4014 ZF = (env->ZF == 0);
4015 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
4016 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
4017 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
4018 | ((env->condexec_bits & 0xfc) << 8)
4019 | (env->GE << 16) | (env->daif & CPSR_AIF);
4020 }
4021
4022 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
4023 {
4024 uint32_t changed_daif;
4025
4026 if (mask & CPSR_NZCV) {
4027 env->ZF = (~val) & CPSR_Z;
4028 env->NF = val;
4029 env->CF = (val >> 29) & 1;
4030 env->VF = (val << 3) & 0x80000000;
4031 }
4032 if (mask & CPSR_Q)
4033 env->QF = ((val & CPSR_Q) != 0);
4034 if (mask & CPSR_T)
4035 env->thumb = ((val & CPSR_T) != 0);
4036 if (mask & CPSR_IT_0_1) {
4037 env->condexec_bits &= ~3;
4038 env->condexec_bits |= (val >> 25) & 3;
4039 }
4040 if (mask & CPSR_IT_2_7) {
4041 env->condexec_bits &= 3;
4042 env->condexec_bits |= (val >> 8) & 0xfc;
4043 }
4044 if (mask & CPSR_GE) {
4045 env->GE = (val >> 16) & 0xf;
4046 }
4047
4048 /* In a V7 implementation that includes the security extensions but does
4049 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
4050 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
4051 * bits respectively.
4052 *
4053 * In a V8 implementation, it is permitted for privileged software to
4054 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
4055 */
4056 if (!arm_feature(env, ARM_FEATURE_V8) &&
4057 arm_feature(env, ARM_FEATURE_EL3) &&
4058 !arm_feature(env, ARM_FEATURE_EL2) &&
4059 !arm_is_secure(env)) {
4060
4061 changed_daif = (env->daif ^ val) & mask;
4062
4063 if (changed_daif & CPSR_A) {
4064 /* Check to see if we are allowed to change the masking of async
4065 * abort exceptions from a non-secure state.
4066 */
4067 if (!(env->cp15.scr_el3 & SCR_AW)) {
4068 qemu_log_mask(LOG_GUEST_ERROR,
4069 "Ignoring attempt to switch CPSR_A flag from "
4070 "non-secure world with SCR.AW bit clear\n");
4071 mask &= ~CPSR_A;
4072 }
4073 }
4074
4075 if (changed_daif & CPSR_F) {
4076 /* Check to see if we are allowed to change the masking of FIQ
4077 * exceptions from a non-secure state.
4078 */
4079 if (!(env->cp15.scr_el3 & SCR_FW)) {
4080 qemu_log_mask(LOG_GUEST_ERROR,
4081 "Ignoring attempt to switch CPSR_F flag from "
4082 "non-secure world with SCR.FW bit clear\n");
4083 mask &= ~CPSR_F;
4084 }
4085
4086 /* Check whether non-maskable FIQ (NMFI) support is enabled.
4087 * If this bit is set software is not allowed to mask
4088 * FIQs, but is allowed to set CPSR_F to 0.
4089 */
4090 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
4091 (val & CPSR_F)) {
4092 qemu_log_mask(LOG_GUEST_ERROR,
4093 "Ignoring attempt to enable CPSR_F flag "
4094 "(non-maskable FIQ [NMFI] support enabled)\n");
4095 mask &= ~CPSR_F;
4096 }
4097 }
4098 }
4099
4100 env->daif &= ~(CPSR_AIF & mask);
4101 env->daif |= val & CPSR_AIF & mask;
4102
4103 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
4104 if (bad_mode_switch(env, val & CPSR_M)) {
4105 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
4106 * We choose to ignore the attempt and leave the CPSR M field
4107 * untouched.
4108 */
4109 mask &= ~CPSR_M;
4110 } else {
4111 switch_mode(env, val & CPSR_M);
4112 }
4113 }
4114 mask &= ~CACHED_CPSR_BITS;
4115 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
4116 }
4117
4118 /* Sign/zero extend */
4119 uint32_t HELPER(sxtb16)(uint32_t x)
4120 {
4121 uint32_t res;
4122 res = (uint16_t)(int8_t)x;
4123 res |= (uint32_t)(int8_t)(x >> 16) << 16;
4124 return res;
4125 }
4126
4127 uint32_t HELPER(uxtb16)(uint32_t x)
4128 {
4129 uint32_t res;
4130 res = (uint16_t)(uint8_t)x;
4131 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
4132 return res;
4133 }
4134
4135 uint32_t HELPER(clz)(uint32_t x)
4136 {
4137 return clz32(x);
4138 }
4139
4140 int32_t HELPER(sdiv)(int32_t num, int32_t den)
4141 {
4142 if (den == 0)
4143 return 0;
4144 if (num == INT_MIN && den == -1)
4145 return INT_MIN;
4146 return num / den;
4147 }
4148
4149 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
4150 {
4151 if (den == 0)
4152 return 0;
4153 return num / den;
4154 }
4155
4156 uint32_t HELPER(rbit)(uint32_t x)
4157 {
4158 x = ((x & 0xff000000) >> 24)
4159 | ((x & 0x00ff0000) >> 8)
4160 | ((x & 0x0000ff00) << 8)
4161 | ((x & 0x000000ff) << 24);
4162 x = ((x & 0xf0f0f0f0) >> 4)
4163 | ((x & 0x0f0f0f0f) << 4);
4164 x = ((x & 0x88888888) >> 3)
4165 | ((x & 0x44444444) >> 1)
4166 | ((x & 0x22222222) << 1)
4167 | ((x & 0x11111111) << 3);
4168 return x;
4169 }
4170
4171 #if defined(CONFIG_USER_ONLY)
4172
4173 /* These should probably raise undefined insn exceptions. */
4174 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4175 {
4176 ARMCPU *cpu = arm_env_get_cpu(env);
4177
4178 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
4179 }
4180
4181 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4182 {
4183 ARMCPU *cpu = arm_env_get_cpu(env);
4184
4185 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
4186 return 0;
4187 }
4188
4189 void switch_mode(CPUARMState *env, int mode)
4190 {
4191 ARMCPU *cpu = arm_env_get_cpu(env);
4192
4193 if (mode != ARM_CPU_MODE_USR) {
4194 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
4195 }
4196 }
4197
4198 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4199 {
4200 ARMCPU *cpu = arm_env_get_cpu(env);
4201
4202 cpu_abort(CPU(cpu), "banked r13 write\n");
4203 }
4204
4205 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4206 {
4207 ARMCPU *cpu = arm_env_get_cpu(env);
4208
4209 cpu_abort(CPU(cpu), "banked r13 read\n");
4210 return 0;
4211 }
4212
4213 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4214 uint32_t cur_el, bool secure)
4215 {
4216 return 1;
4217 }
4218
4219 void aarch64_sync_64_to_32(CPUARMState *env)
4220 {
4221 g_assert_not_reached();
4222 }
4223
4224 #else
4225
4226 /* Map CPU modes onto saved register banks. */
4227 int bank_number(int mode)
4228 {
4229 switch (mode) {
4230 case ARM_CPU_MODE_USR:
4231 case ARM_CPU_MODE_SYS:
4232 return 0;
4233 case ARM_CPU_MODE_SVC:
4234 return 1;
4235 case ARM_CPU_MODE_ABT:
4236 return 2;
4237 case ARM_CPU_MODE_UND:
4238 return 3;
4239 case ARM_CPU_MODE_IRQ:
4240 return 4;
4241 case ARM_CPU_MODE_FIQ:
4242 return 5;
4243 case ARM_CPU_MODE_HYP:
4244 return 6;
4245 case ARM_CPU_MODE_MON:
4246 return 7;
4247 }
4248 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
4249 }
4250
4251 void switch_mode(CPUARMState *env, int mode)
4252 {
4253 int old_mode;
4254 int i;
4255
4256 old_mode = env->uncached_cpsr & CPSR_M;
4257 if (mode == old_mode)
4258 return;
4259
4260 if (old_mode == ARM_CPU_MODE_FIQ) {
4261 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
4262 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
4263 } else if (mode == ARM_CPU_MODE_FIQ) {
4264 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
4265 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
4266 }
4267
4268 i = bank_number(old_mode);
4269 env->banked_r13[i] = env->regs[13];
4270 env->banked_r14[i] = env->regs[14];
4271 env->banked_spsr[i] = env->spsr;
4272
4273 i = bank_number(mode);
4274 env->regs[13] = env->banked_r13[i];
4275 env->regs[14] = env->banked_r14[i];
4276 env->spsr = env->banked_spsr[i];
4277 }
4278
4279 /* Physical Interrupt Target EL Lookup Table
4280 *
4281 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
4282 *
4283 * The below multi-dimensional table is used for looking up the target
4284 * exception level given numerous condition criteria. Specifically, the
4285 * target EL is based on SCR and HCR routing controls as well as the
4286 * currently executing EL and secure state.
4287 *
4288 * Dimensions:
4289 * target_el_table[2][2][2][2][2][4]
4290 * | | | | | +--- Current EL
4291 * | | | | +------ Non-secure(0)/Secure(1)
4292 * | | | +--------- HCR mask override
4293 * | | +------------ SCR exec state control
4294 * | +--------------- SCR mask override
4295 * +------------------ 32-bit(0)/64-bit(1) EL3
4296 *
4297 * The table values are as such:
4298 * 0-3 = EL0-EL3
4299 * -1 = Cannot occur
4300 *
4301 * The ARM ARM target EL table includes entries indicating that an "exception
4302 * is not taken". The two cases where this is applicable are:
4303 * 1) An exception is taken from EL3 but the SCR does not have the exception
4304 * routed to EL3.
4305 * 2) An exception is taken from EL2 but the HCR does not have the exception
4306 * routed to EL2.
4307 * In these two cases, the below table contain a target of EL1. This value is
4308 * returned as it is expected that the consumer of the table data will check
4309 * for "target EL >= current EL" to ensure the exception is not taken.
4310 *
4311 * SCR HCR
4312 * 64 EA AMO From
4313 * BIT IRQ IMO Non-secure Secure
4314 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
4315 */
4316 const int8_t target_el_table[2][2][2][2][2][4] = {
4317 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4318 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
4319 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
4320 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
4321 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4322 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
4323 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
4324 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
4325 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
4326 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
4327 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
4328 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
4329 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4330 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
4331 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
4332 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
4333 };
4334
4335 /*
4336 * Determine the target EL for physical exceptions
4337 */
4338 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
4339 uint32_t cur_el, bool secure)
4340 {
4341 CPUARMState *env = cs->env_ptr;
4342 int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
4343 int scr;
4344 int hcr;
4345 int target_el;
4346 int is64 = arm_el_is_aa64(env, 3);
4347
4348 switch (excp_idx) {
4349 case EXCP_IRQ:
4350 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
4351 hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
4352 break;
4353 case EXCP_FIQ:
4354 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
4355 hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
4356 break;
4357 default:
4358 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
4359 hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
4360 break;
4361 };
4362
4363 /* If HCR.TGE is set then HCR is treated as being 1 */
4364 hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
4365
4366 /* Perform a table-lookup for the target EL given the current state */
4367 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
4368
4369 assert(target_el > 0);
4370
4371 return target_el;
4372 }
4373
4374 static void v7m_push(CPUARMState *env, uint32_t val)
4375 {
4376 CPUState *cs = CPU(arm_env_get_cpu(env));
4377
4378 env->regs[13] -= 4;
4379 stl_phys(cs->as, env->regs[13], val);
4380 }
4381
4382 static uint32_t v7m_pop(CPUARMState *env)
4383 {
4384 CPUState *cs = CPU(arm_env_get_cpu(env));
4385 uint32_t val;
4386
4387 val = ldl_phys(cs->as, env->regs[13]);
4388 env->regs[13] += 4;
4389 return val;
4390 }
4391
4392 /* Switch to V7M main or process stack pointer. */
4393 static void switch_v7m_sp(CPUARMState *env, int process)
4394 {
4395 uint32_t tmp;
4396 if (env->v7m.current_sp != process) {
4397 tmp = env->v7m.other_sp;
4398 env->v7m.other_sp = env->regs[13];
4399 env->regs[13] = tmp;
4400 env->v7m.current_sp = process;
4401 }
4402 }
4403
4404 static void do_v7m_exception_exit(CPUARMState *env)
4405 {
4406 uint32_t type;
4407 uint32_t xpsr;
4408
4409 type = env->regs[15];
4410 if (env->v7m.exception != 0)
4411 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
4412
4413 /* Switch to the target stack. */
4414 switch_v7m_sp(env, (type & 4) != 0);
4415 /* Pop registers. */
4416 env->regs[0] = v7m_pop(env);
4417 env->regs[1] = v7m_pop(env);
4418 env->regs[2] = v7m_pop(env);
4419 env->regs[3] = v7m_pop(env);
4420 env->regs[12] = v7m_pop(env);
4421 env->regs[14] = v7m_pop(env);
4422 env->regs[15] = v7m_pop(env);
4423 if (env->regs[15] & 1) {
4424 qemu_log_mask(LOG_GUEST_ERROR,
4425 "M profile return from interrupt with misaligned "
4426 "PC is UNPREDICTABLE\n");
4427 /* Actual hardware seems to ignore the lsbit, and there are several
4428 * RTOSes out there which incorrectly assume the r15 in the stack
4429 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
4430 */
4431 env->regs[15] &= ~1U;
4432 }
4433 xpsr = v7m_pop(env);
4434 xpsr_write(env, xpsr, 0xfffffdff);
4435 /* Undo stack alignment. */
4436 if (xpsr & 0x200)
4437 env->regs[13] |= 4;
4438 /* ??? The exception return type specifies Thread/Handler mode. However
4439 this is also implied by the xPSR value. Not sure what to do
4440 if there is a mismatch. */
4441 /* ??? Likewise for mismatches between the CONTROL register and the stack
4442 pointer. */
4443 }
4444
4445 void arm_v7m_cpu_do_interrupt(CPUState *cs)
4446 {
4447 ARMCPU *cpu = ARM_CPU(cs);
4448 CPUARMState *env = &cpu->env;
4449 uint32_t xpsr = xpsr_read(env);
4450 uint32_t lr;
4451 uint32_t addr;
4452
4453 arm_log_exception(cs->exception_index);
4454
4455 lr = 0xfffffff1;
4456 if (env->v7m.current_sp)
4457 lr |= 4;
4458 if (env->v7m.exception == 0)
4459 lr |= 8;
4460
4461 /* For exceptions we just mark as pending on the NVIC, and let that
4462 handle it. */
4463 /* TODO: Need to escalate if the current priority is higher than the
4464 one we're raising. */
4465 switch (cs->exception_index) {
4466 case EXCP_UDEF:
4467 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
4468 return;
4469 case EXCP_SWI:
4470 /* The PC already points to the next instruction. */
4471 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
4472 return;
4473 case EXCP_PREFETCH_ABORT:
4474 case EXCP_DATA_ABORT:
4475 /* TODO: if we implemented the MPU registers, this is where we
4476 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
4477 */
4478 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
4479 return;
4480 case EXCP_BKPT:
4481 if (semihosting_enabled) {
4482 int nr;
4483 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4484 if (nr == 0xab) {
4485 env->regs[15] += 2;
4486 env->regs[0] = do_arm_semihosting(env);
4487 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4488 return;
4489 }
4490 }
4491 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
4492 return;
4493 case EXCP_IRQ:
4494 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
4495 break;
4496 case EXCP_EXCEPTION_EXIT:
4497 do_v7m_exception_exit(env);
4498 return;
4499 default:
4500 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4501 return; /* Never happens. Keep compiler happy. */
4502 }
4503
4504 /* Align stack pointer. */
4505 /* ??? Should only do this if Configuration Control Register
4506 STACKALIGN bit is set. */
4507 if (env->regs[13] & 4) {
4508 env->regs[13] -= 4;
4509 xpsr |= 0x200;
4510 }
4511 /* Switch to the handler mode. */
4512 v7m_push(env, xpsr);
4513 v7m_push(env, env->regs[15]);
4514 v7m_push(env, env->regs[14]);
4515 v7m_push(env, env->regs[12]);
4516 v7m_push(env, env->regs[3]);
4517 v7m_push(env, env->regs[2]);
4518 v7m_push(env, env->regs[1]);
4519 v7m_push(env, env->regs[0]);
4520 switch_v7m_sp(env, 0);
4521 /* Clear IT bits */
4522 env->condexec_bits = 0;
4523 env->regs[14] = lr;
4524 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
4525 env->regs[15] = addr & 0xfffffffe;
4526 env->thumb = addr & 1;
4527 }
4528
4529 /* Function used to synchronize QEMU's AArch64 register set with AArch32
4530 * register set. This is necessary when switching between AArch32 and AArch64
4531 * execution state.
4532 */
4533 void aarch64_sync_32_to_64(CPUARMState *env)
4534 {
4535 int i;
4536 uint32_t mode = env->uncached_cpsr & CPSR_M;
4537
4538 /* We can blanket copy R[0:7] to X[0:7] */
4539 for (i = 0; i < 8; i++) {
4540 env->xregs[i] = env->regs[i];
4541 }
4542
4543 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
4544 * Otherwise, they come from the banked user regs.
4545 */
4546 if (mode == ARM_CPU_MODE_FIQ) {
4547 for (i = 8; i < 13; i++) {
4548 env->xregs[i] = env->usr_regs[i - 8];
4549 }
4550 } else {
4551 for (i = 8; i < 13; i++) {
4552 env->xregs[i] = env->regs[i];
4553 }
4554 }
4555
4556 /* Registers x13-x23 are the various mode SP and FP registers. Registers
4557 * r13 and r14 are only copied if we are in that mode, otherwise we copy
4558 * from the mode banked register.
4559 */
4560 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4561 env->xregs[13] = env->regs[13];
4562 env->xregs[14] = env->regs[14];
4563 } else {
4564 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
4565 /* HYP is an exception in that it is copied from r14 */
4566 if (mode == ARM_CPU_MODE_HYP) {
4567 env->xregs[14] = env->regs[14];
4568 } else {
4569 env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
4570 }
4571 }
4572
4573 if (mode == ARM_CPU_MODE_HYP) {
4574 env->xregs[15] = env->regs[13];
4575 } else {
4576 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
4577 }
4578
4579 if (mode == ARM_CPU_MODE_IRQ) {
4580 env->xregs[16] = env->regs[13];
4581 env->xregs[17] = env->regs[14];
4582 } else {
4583 env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
4584 env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
4585 }
4586
4587 if (mode == ARM_CPU_MODE_SVC) {
4588 env->xregs[18] = env->regs[13];
4589 env->xregs[19] = env->regs[14];
4590 } else {
4591 env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
4592 env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
4593 }
4594
4595 if (mode == ARM_CPU_MODE_ABT) {
4596 env->xregs[20] = env->regs[13];
4597 env->xregs[21] = env->regs[14];
4598 } else {
4599 env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
4600 env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
4601 }
4602
4603 if (mode == ARM_CPU_MODE_UND) {
4604 env->xregs[22] = env->regs[13];
4605 env->xregs[23] = env->regs[14];
4606 } else {
4607 env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
4608 env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
4609 }
4610
4611 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4612 * mode, then we can copy from r8-r14. Otherwise, we copy from the
4613 * FIQ bank for r8-r14.
4614 */
4615 if (mode == ARM_CPU_MODE_FIQ) {
4616 for (i = 24; i < 31; i++) {
4617 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
4618 }
4619 } else {
4620 for (i = 24; i < 29; i++) {
4621 env->xregs[i] = env->fiq_regs[i - 24];
4622 }
4623 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
4624 env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
4625 }
4626
4627 env->pc = env->regs[15];
4628 }
4629
4630 /* Function used to synchronize QEMU's AArch32 register set with AArch64
4631 * register set. This is necessary when switching between AArch32 and AArch64
4632 * execution state.
4633 */
4634 void aarch64_sync_64_to_32(CPUARMState *env)
4635 {
4636 int i;
4637 uint32_t mode = env->uncached_cpsr & CPSR_M;
4638
4639 /* We can blanket copy X[0:7] to R[0:7] */
4640 for (i = 0; i < 8; i++) {
4641 env->regs[i] = env->xregs[i];
4642 }
4643
4644 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
4645 * Otherwise, we copy x8-x12 into the banked user regs.
4646 */
4647 if (mode == ARM_CPU_MODE_FIQ) {
4648 for (i = 8; i < 13; i++) {
4649 env->usr_regs[i - 8] = env->xregs[i];
4650 }
4651 } else {
4652 for (i = 8; i < 13; i++) {
4653 env->regs[i] = env->xregs[i];
4654 }
4655 }
4656
4657 /* Registers r13 & r14 depend on the current mode.
4658 * If we are in a given mode, we copy the corresponding x registers to r13
4659 * and r14. Otherwise, we copy the x register to the banked r13 and r14
4660 * for the mode.
4661 */
4662 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
4663 env->regs[13] = env->xregs[13];
4664 env->regs[14] = env->xregs[14];
4665 } else {
4666 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
4667
4668 /* HYP is an exception in that it does not have its own banked r14 but
4669 * shares the USR r14
4670 */
4671 if (mode == ARM_CPU_MODE_HYP) {
4672 env->regs[14] = env->xregs[14];
4673 } else {
4674 env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
4675 }
4676 }
4677
4678 if (mode == ARM_CPU_MODE_HYP) {
4679 env->regs[13] = env->xregs[15];
4680 } else {
4681 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
4682 }
4683
4684 if (mode == ARM_CPU_MODE_IRQ) {
4685 env->regs[13] = env->xregs[16];
4686 env->regs[14] = env->xregs[17];
4687 } else {
4688 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
4689 env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
4690 }
4691
4692 if (mode == ARM_CPU_MODE_SVC) {
4693 env->regs[13] = env->xregs[18];
4694 env->regs[14] = env->xregs[19];
4695 } else {
4696 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
4697 env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
4698 }
4699
4700 if (mode == ARM_CPU_MODE_ABT) {
4701 env->regs[13] = env->xregs[20];
4702 env->regs[14] = env->xregs[21];
4703 } else {
4704 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
4705 env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
4706 }
4707
4708 if (mode == ARM_CPU_MODE_UND) {
4709 env->regs[13] = env->xregs[22];
4710 env->regs[14] = env->xregs[23];
4711 } else {
4712 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
4713 env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
4714 }
4715
4716 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
4717 * mode, then we can copy to r8-r14. Otherwise, we copy to the
4718 * FIQ bank for r8-r14.
4719 */
4720 if (mode == ARM_CPU_MODE_FIQ) {
4721 for (i = 24; i < 31; i++) {
4722 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
4723 }
4724 } else {
4725 for (i = 24; i < 29; i++) {
4726 env->fiq_regs[i - 24] = env->xregs[i];
4727 }
4728 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
4729 env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
4730 }
4731
4732 env->regs[15] = env->pc;
4733 }
4734
4735 /* Handle a CPU exception. */
4736 void arm_cpu_do_interrupt(CPUState *cs)
4737 {
4738 ARMCPU *cpu = ARM_CPU(cs);
4739 CPUARMState *env = &cpu->env;
4740 uint32_t addr;
4741 uint32_t mask;
4742 int new_mode;
4743 uint32_t offset;
4744 uint32_t moe;
4745
4746 assert(!IS_M(env));
4747
4748 arm_log_exception(cs->exception_index);
4749
4750 if (arm_is_psci_call(cpu, cs->exception_index)) {
4751 arm_handle_psci_call(cpu);
4752 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
4753 return;
4754 }
4755
4756 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
4757 switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
4758 case EC_BREAKPOINT:
4759 case EC_BREAKPOINT_SAME_EL:
4760 moe = 1;
4761 break;
4762 case EC_WATCHPOINT:
4763 case EC_WATCHPOINT_SAME_EL:
4764 moe = 10;
4765 break;
4766 case EC_AA32_BKPT:
4767 moe = 3;
4768 break;
4769 case EC_VECTORCATCH:
4770 moe = 5;
4771 break;
4772 default:
4773 moe = 0;
4774 break;
4775 }
4776
4777 if (moe) {
4778 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
4779 }
4780
4781 /* TODO: Vectored interrupt controller. */
4782 switch (cs->exception_index) {
4783 case EXCP_UDEF:
4784 new_mode = ARM_CPU_MODE_UND;
4785 addr = 0x04;
4786 mask = CPSR_I;
4787 if (env->thumb)
4788 offset = 2;
4789 else
4790 offset = 4;
4791 break;
4792 case EXCP_SWI:
4793 if (semihosting_enabled) {
4794 /* Check for semihosting interrupt. */
4795 if (env->thumb) {
4796 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
4797 & 0xff;
4798 } else {
4799 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
4800 & 0xffffff;
4801 }
4802 /* Only intercept calls from privileged modes, to provide some
4803 semblance of security. */
4804 if (((mask == 0x123456 && !env->thumb)
4805 || (mask == 0xab && env->thumb))
4806 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4807 env->regs[0] = do_arm_semihosting(env);
4808 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4809 return;
4810 }
4811 }
4812 new_mode = ARM_CPU_MODE_SVC;
4813 addr = 0x08;
4814 mask = CPSR_I;
4815 /* The PC already points to the next instruction. */
4816 offset = 0;
4817 break;
4818 case EXCP_BKPT:
4819 /* See if this is a semihosting syscall. */
4820 if (env->thumb && semihosting_enabled) {
4821 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
4822 if (mask == 0xab
4823 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
4824 env->regs[15] += 2;
4825 env->regs[0] = do_arm_semihosting(env);
4826 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
4827 return;
4828 }
4829 }
4830 env->exception.fsr = 2;
4831 /* Fall through to prefetch abort. */
4832 case EXCP_PREFETCH_ABORT:
4833 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
4834 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
4835 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
4836 env->exception.fsr, (uint32_t)env->exception.vaddress);
4837 new_mode = ARM_CPU_MODE_ABT;
4838 addr = 0x0c;
4839 mask = CPSR_A | CPSR_I;
4840 offset = 4;
4841 break;
4842 case EXCP_DATA_ABORT:
4843 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
4844 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
4845 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4846 env->exception.fsr,
4847 (uint32_t)env->exception.vaddress);
4848 new_mode = ARM_CPU_MODE_ABT;
4849 addr = 0x10;
4850 mask = CPSR_A | CPSR_I;
4851 offset = 8;
4852 break;
4853 case EXCP_IRQ:
4854 new_mode = ARM_CPU_MODE_IRQ;
4855 addr = 0x18;
4856 /* Disable IRQ and imprecise data aborts. */
4857 mask = CPSR_A | CPSR_I;
4858 offset = 4;
4859 if (env->cp15.scr_el3 & SCR_IRQ) {
4860 /* IRQ routed to monitor mode */
4861 new_mode = ARM_CPU_MODE_MON;
4862 mask |= CPSR_F;
4863 }
4864 break;
4865 case EXCP_FIQ:
4866 new_mode = ARM_CPU_MODE_FIQ;
4867 addr = 0x1c;
4868 /* Disable FIQ, IRQ and imprecise data aborts. */
4869 mask = CPSR_A | CPSR_I | CPSR_F;
4870 if (env->cp15.scr_el3 & SCR_FIQ) {
4871 /* FIQ routed to monitor mode */
4872 new_mode = ARM_CPU_MODE_MON;
4873 }
4874 offset = 4;
4875 break;
4876 case EXCP_SMC:
4877 new_mode = ARM_CPU_MODE_MON;
4878 addr = 0x08;
4879 mask = CPSR_A | CPSR_I | CPSR_F;
4880 offset = 0;
4881 break;
4882 default:
4883 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
4884 return; /* Never happens. Keep compiler happy. */
4885 }
4886
4887 if (new_mode == ARM_CPU_MODE_MON) {
4888 addr += env->cp15.mvbar;
4889 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
4890 /* High vectors. When enabled, base address cannot be remapped. */
4891 addr += 0xffff0000;
4892 } else {
4893 /* ARM v7 architectures provide a vector base address register to remap
4894 * the interrupt vector table.
4895 * This register is only followed in non-monitor mode, and is banked.
4896 * Note: only bits 31:5 are valid.
4897 */
4898 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
4899 }
4900
4901 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
4902 env->cp15.scr_el3 &= ~SCR_NS;
4903 }
4904
4905 switch_mode (env, new_mode);
4906 /* For exceptions taken to AArch32 we must clear the SS bit in both
4907 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
4908 */
4909 env->uncached_cpsr &= ~PSTATE_SS;
4910 env->spsr = cpsr_read(env);
4911 /* Clear IT bits. */
4912 env->condexec_bits = 0;
4913 /* Switch to the new mode, and to the correct instruction set. */
4914 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
4915 env->daif |= mask;
4916 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
4917 * and we should just guard the thumb mode on V4 */
4918 if (arm_feature(env, ARM_FEATURE_V4T)) {
4919 env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
4920 }
4921 env->regs[14] = env->regs[15] + offset;
4922 env->regs[15] = addr;
4923 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
4924 }
4925
4926
4927 /* Return the exception level which controls this address translation regime */
4928 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
4929 {
4930 switch (mmu_idx) {
4931 case ARMMMUIdx_S2NS:
4932 case ARMMMUIdx_S1E2:
4933 return 2;
4934 case ARMMMUIdx_S1E3:
4935 return 3;
4936 case ARMMMUIdx_S1SE0:
4937 return arm_el_is_aa64(env, 3) ? 1 : 3;
4938 case ARMMMUIdx_S1SE1:
4939 case ARMMMUIdx_S1NSE0:
4940 case ARMMMUIdx_S1NSE1:
4941 return 1;
4942 default:
4943 g_assert_not_reached();
4944 }
4945 }
4946
4947 /* Return true if this address translation regime is secure */
4948 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
4949 {
4950 switch (mmu_idx) {
4951 case ARMMMUIdx_S12NSE0:
4952 case ARMMMUIdx_S12NSE1:
4953 case ARMMMUIdx_S1NSE0:
4954 case ARMMMUIdx_S1NSE1:
4955 case ARMMMUIdx_S1E2:
4956 case ARMMMUIdx_S2NS:
4957 return false;
4958 case ARMMMUIdx_S1E3:
4959 case ARMMMUIdx_S1SE0:
4960 case ARMMMUIdx_S1SE1:
4961 return true;
4962 default:
4963 g_assert_not_reached();
4964 }
4965 }
4966
4967 /* Return the SCTLR value which controls this address translation regime */
4968 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
4969 {
4970 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
4971 }
4972
4973 /* Return true if the specified stage of address translation is disabled */
4974 static inline bool regime_translation_disabled(CPUARMState *env,
4975 ARMMMUIdx mmu_idx)
4976 {
4977 if (mmu_idx == ARMMMUIdx_S2NS) {
4978 return (env->cp15.hcr_el2 & HCR_VM) == 0;
4979 }
4980 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
4981 }
4982
4983 /* Return the TCR controlling this translation regime */
4984 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
4985 {
4986 if (mmu_idx == ARMMMUIdx_S2NS) {
4987 /* TODO: return VTCR_EL2 */
4988 g_assert_not_reached();
4989 }
4990 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
4991 }
4992
4993 /* Return the TTBR associated with this translation regime */
4994 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
4995 int ttbrn)
4996 {
4997 if (mmu_idx == ARMMMUIdx_S2NS) {
4998 /* TODO: return VTTBR_EL2 */
4999 g_assert_not_reached();
5000 }
5001 if (ttbrn == 0) {
5002 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
5003 } else {
5004 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
5005 }
5006 }
5007
5008 /* Return true if the translation regime is using LPAE format page tables */
5009 static inline bool regime_using_lpae_format(CPUARMState *env,
5010 ARMMMUIdx mmu_idx)
5011 {
5012 int el = regime_el(env, mmu_idx);
5013 if (el == 2 || arm_el_is_aa64(env, el)) {
5014 return true;
5015 }
5016 if (arm_feature(env, ARM_FEATURE_LPAE)
5017 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
5018 return true;
5019 }
5020 return false;
5021 }
5022
5023 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
5024 {
5025 switch (mmu_idx) {
5026 case ARMMMUIdx_S1SE0:
5027 case ARMMMUIdx_S1NSE0:
5028 return true;
5029 default:
5030 return false;
5031 case ARMMMUIdx_S12NSE0:
5032 case ARMMMUIdx_S12NSE1:
5033 g_assert_not_reached();
5034 }
5035 }
5036
5037 /* Translate section/page access permissions to page
5038 * R/W protection flags
5039 *
5040 * @env: CPUARMState
5041 * @mmu_idx: MMU index indicating required translation regime
5042 * @ap: The 3-bit access permissions (AP[2:0])
5043 * @domain_prot: The 2-bit domain access permissions
5044 */
5045 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
5046 int ap, int domain_prot)
5047 {
5048 bool is_user = regime_is_user(env, mmu_idx);
5049
5050 if (domain_prot == 3) {
5051 return PAGE_READ | PAGE_WRITE;
5052 }
5053
5054 switch (ap) {
5055 case 0:
5056 if (arm_feature(env, ARM_FEATURE_V7)) {
5057 return 0;
5058 }
5059 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
5060 case SCTLR_S:
5061 return is_user ? 0 : PAGE_READ;
5062 case SCTLR_R:
5063 return PAGE_READ;
5064 default:
5065 return 0;
5066 }
5067 case 1:
5068 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5069 case 2:
5070 if (is_user) {
5071 return PAGE_READ;
5072 } else {
5073 return PAGE_READ | PAGE_WRITE;
5074 }
5075 case 3:
5076 return PAGE_READ | PAGE_WRITE;
5077 case 4: /* Reserved. */
5078 return 0;
5079 case 5:
5080 return is_user ? 0 : PAGE_READ;
5081 case 6:
5082 return PAGE_READ;
5083 case 7:
5084 if (!arm_feature(env, ARM_FEATURE_V6K)) {
5085 return 0;
5086 }
5087 return PAGE_READ;
5088 default:
5089 g_assert_not_reached();
5090 }
5091 }
5092
5093 /* Translate section/page access permissions to page
5094 * R/W protection flags.
5095 *
5096 * @ap: The 2-bit simple AP (AP[2:1])
5097 * @is_user: TRUE if accessing from PL0
5098 */
5099 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
5100 {
5101 switch (ap) {
5102 case 0:
5103 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
5104 case 1:
5105 return PAGE_READ | PAGE_WRITE;
5106 case 2:
5107 return is_user ? 0 : PAGE_READ;
5108 case 3:
5109 return PAGE_READ;
5110 default:
5111 g_assert_not_reached();
5112 }
5113 }
5114
5115 static inline int
5116 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
5117 {
5118 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
5119 }
5120
5121 /* Translate section/page access permissions to protection flags
5122 *
5123 * @env: CPUARMState
5124 * @mmu_idx: MMU index indicating required translation regime
5125 * @is_aa64: TRUE if AArch64
5126 * @ap: The 2-bit simple AP (AP[2:1])
5127 * @ns: NS (non-secure) bit
5128 * @xn: XN (execute-never) bit
5129 * @pxn: PXN (privileged execute-never) bit
5130 */
5131 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
5132 int ap, int ns, int xn, int pxn)
5133 {
5134 bool is_user = regime_is_user(env, mmu_idx);
5135 int prot_rw, user_rw;
5136 bool have_wxn;
5137 int wxn = 0;
5138
5139 assert(mmu_idx != ARMMMUIdx_S2NS);
5140
5141 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
5142 if (is_user) {
5143 prot_rw = user_rw;
5144 } else {
5145 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
5146 }
5147
5148 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
5149 return prot_rw;
5150 }
5151
5152 /* TODO have_wxn should be replaced with
5153 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
5154 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
5155 * compatible processors have EL2, which is required for [U]WXN.
5156 */
5157 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
5158
5159 if (have_wxn) {
5160 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
5161 }
5162
5163 if (is_aa64) {
5164 switch (regime_el(env, mmu_idx)) {
5165 case 1:
5166 if (!is_user) {
5167 xn = pxn || (user_rw & PAGE_WRITE);
5168 }
5169 break;
5170 case 2:
5171 case 3:
5172 break;
5173 }
5174 } else if (arm_feature(env, ARM_FEATURE_V7)) {
5175 switch (regime_el(env, mmu_idx)) {
5176 case 1:
5177 case 3:
5178 if (is_user) {
5179 xn = xn || !(user_rw & PAGE_READ);
5180 } else {
5181 int uwxn = 0;
5182 if (have_wxn) {
5183 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
5184 }
5185 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
5186 (uwxn && (user_rw & PAGE_WRITE));
5187 }
5188 break;
5189 case 2:
5190 break;
5191 }
5192 } else {
5193 xn = wxn = 0;
5194 }
5195
5196 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
5197 return prot_rw;
5198 }
5199 return prot_rw | PAGE_EXEC;
5200 }
5201
5202 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
5203 uint32_t *table, uint32_t address)
5204 {
5205 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
5206 TCR *tcr = regime_tcr(env, mmu_idx);
5207
5208 if (address & tcr->mask) {
5209 if (tcr->raw_tcr & TTBCR_PD1) {
5210 /* Translation table walk disabled for TTBR1 */
5211 return false;
5212 }
5213 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
5214 } else {
5215 if (tcr->raw_tcr & TTBCR_PD0) {
5216 /* Translation table walk disabled for TTBR0 */
5217 return false;
5218 }
5219 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
5220 }
5221 *table |= (address >> 18) & 0x3ffc;
5222 return true;
5223 }
5224
5225 /* All loads done in the course of a page table walk go through here.
5226 * TODO: rather than ignoring errors from physical memory reads (which
5227 * are external aborts in ARM terminology) we should propagate this
5228 * error out so that we can turn it into a Data Abort if this walk
5229 * was being done for a CPU load/store or an address translation instruction
5230 * (but not if it was for a debug access).
5231 */
5232 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5233 {
5234 MemTxAttrs attrs = {};
5235
5236 attrs.secure = is_secure;
5237 return address_space_ldl(cs->as, addr, attrs, NULL);
5238 }
5239
5240 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure)
5241 {
5242 MemTxAttrs attrs = {};
5243
5244 attrs.secure = is_secure;
5245 return address_space_ldq(cs->as, addr, attrs, NULL);
5246 }
5247
5248 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
5249 int access_type, ARMMMUIdx mmu_idx,
5250 hwaddr *phys_ptr, int *prot,
5251 target_ulong *page_size, uint32_t *fsr)
5252 {
5253 CPUState *cs = CPU(arm_env_get_cpu(env));
5254 int code;
5255 uint32_t table;
5256 uint32_t desc;
5257 int type;
5258 int ap;
5259 int domain = 0;
5260 int domain_prot;
5261 hwaddr phys_addr;
5262 uint32_t dacr;
5263
5264 /* Pagetable walk. */
5265 /* Lookup l1 descriptor. */
5266 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5267 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5268 code = 5;
5269 goto do_fault;
5270 }
5271 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5272 type = (desc & 3);
5273 domain = (desc >> 5) & 0x0f;
5274 if (regime_el(env, mmu_idx) == 1) {
5275 dacr = env->cp15.dacr_ns;
5276 } else {
5277 dacr = env->cp15.dacr_s;
5278 }
5279 domain_prot = (dacr >> (domain * 2)) & 3;
5280 if (type == 0) {
5281 /* Section translation fault. */
5282 code = 5;
5283 goto do_fault;
5284 }
5285 if (domain_prot == 0 || domain_prot == 2) {
5286 if (type == 2)
5287 code = 9; /* Section domain fault. */
5288 else
5289 code = 11; /* Page domain fault. */
5290 goto do_fault;
5291 }
5292 if (type == 2) {
5293 /* 1Mb section. */
5294 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5295 ap = (desc >> 10) & 3;
5296 code = 13;
5297 *page_size = 1024 * 1024;
5298 } else {
5299 /* Lookup l2 entry. */
5300 if (type == 1) {
5301 /* Coarse pagetable. */
5302 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5303 } else {
5304 /* Fine pagetable. */
5305 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
5306 }
5307 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5308 switch (desc & 3) {
5309 case 0: /* Page translation fault. */
5310 code = 7;
5311 goto do_fault;
5312 case 1: /* 64k page. */
5313 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5314 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
5315 *page_size = 0x10000;
5316 break;
5317 case 2: /* 4k page. */
5318 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5319 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
5320 *page_size = 0x1000;
5321 break;
5322 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
5323 if (type == 1) {
5324 /* ARMv6/XScale extended small page format */
5325 if (arm_feature(env, ARM_FEATURE_XSCALE)
5326 || arm_feature(env, ARM_FEATURE_V6)) {
5327 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5328 *page_size = 0x1000;
5329 } else {
5330 /* UNPREDICTABLE in ARMv5; we choose to take a
5331 * page translation fault.
5332 */
5333 code = 7;
5334 goto do_fault;
5335 }
5336 } else {
5337 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
5338 *page_size = 0x400;
5339 }
5340 ap = (desc >> 4) & 3;
5341 break;
5342 default:
5343 /* Never happens, but compiler isn't smart enough to tell. */
5344 abort();
5345 }
5346 code = 15;
5347 }
5348 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
5349 *prot |= *prot ? PAGE_EXEC : 0;
5350 if (!(*prot & (1 << access_type))) {
5351 /* Access permission fault. */
5352 goto do_fault;
5353 }
5354 *phys_ptr = phys_addr;
5355 return false;
5356 do_fault:
5357 *fsr = code | (domain << 4);
5358 return true;
5359 }
5360
5361 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
5362 int access_type, ARMMMUIdx mmu_idx,
5363 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
5364 target_ulong *page_size, uint32_t *fsr)
5365 {
5366 CPUState *cs = CPU(arm_env_get_cpu(env));
5367 int code;
5368 uint32_t table;
5369 uint32_t desc;
5370 uint32_t xn;
5371 uint32_t pxn = 0;
5372 int type;
5373 int ap;
5374 int domain = 0;
5375 int domain_prot;
5376 hwaddr phys_addr;
5377 uint32_t dacr;
5378 bool ns;
5379
5380 /* Pagetable walk. */
5381 /* Lookup l1 descriptor. */
5382 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
5383 /* Section translation fault if page walk is disabled by PD0 or PD1 */
5384 code = 5;
5385 goto do_fault;
5386 }
5387 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5388 type = (desc & 3);
5389 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
5390 /* Section translation fault, or attempt to use the encoding
5391 * which is Reserved on implementations without PXN.
5392 */
5393 code = 5;
5394 goto do_fault;
5395 }
5396 if ((type == 1) || !(desc & (1 << 18))) {
5397 /* Page or Section. */
5398 domain = (desc >> 5) & 0x0f;
5399 }
5400 if (regime_el(env, mmu_idx) == 1) {
5401 dacr = env->cp15.dacr_ns;
5402 } else {
5403 dacr = env->cp15.dacr_s;
5404 }
5405 domain_prot = (dacr >> (domain * 2)) & 3;
5406 if (domain_prot == 0 || domain_prot == 2) {
5407 if (type != 1) {
5408 code = 9; /* Section domain fault. */
5409 } else {
5410 code = 11; /* Page domain fault. */
5411 }
5412 goto do_fault;
5413 }
5414 if (type != 1) {
5415 if (desc & (1 << 18)) {
5416 /* Supersection. */
5417 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
5418 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
5419 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
5420 *page_size = 0x1000000;
5421 } else {
5422 /* Section. */
5423 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
5424 *page_size = 0x100000;
5425 }
5426 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
5427 xn = desc & (1 << 4);
5428 pxn = desc & 1;
5429 code = 13;
5430 ns = extract32(desc, 19, 1);
5431 } else {
5432 if (arm_feature(env, ARM_FEATURE_PXN)) {
5433 pxn = (desc >> 2) & 1;
5434 }
5435 ns = extract32(desc, 3, 1);
5436 /* Lookup l2 entry. */
5437 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
5438 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
5439 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
5440 switch (desc & 3) {
5441 case 0: /* Page translation fault. */
5442 code = 7;
5443 goto do_fault;
5444 case 1: /* 64k page. */
5445 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
5446 xn = desc & (1 << 15);
5447 *page_size = 0x10000;
5448 break;
5449 case 2: case 3: /* 4k page. */
5450 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
5451 xn = desc & 1;
5452 *page_size = 0x1000;
5453 break;
5454 default:
5455 /* Never happens, but compiler isn't smart enough to tell. */
5456 abort();
5457 }
5458 code = 15;
5459 }
5460 if (domain_prot == 3) {
5461 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5462 } else {
5463 if (pxn && !regime_is_user(env, mmu_idx)) {
5464 xn = 1;
5465 }
5466 if (xn && access_type == 2)
5467 goto do_fault;
5468
5469 if (arm_feature(env, ARM_FEATURE_V6K) &&
5470 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
5471 /* The simplified model uses AP[0] as an access control bit. */
5472 if ((ap & 1) == 0) {
5473 /* Access flag fault. */
5474 code = (code == 15) ? 6 : 3;
5475 goto do_fault;
5476 }
5477 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
5478 } else {
5479 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
5480 }
5481 if (*prot && !xn) {
5482 *prot |= PAGE_EXEC;
5483 }
5484 if (!(*prot & (1 << access_type))) {
5485 /* Access permission fault. */
5486 goto do_fault;
5487 }
5488 }
5489 if (ns) {
5490 /* The NS bit will (as required by the architecture) have no effect if
5491 * the CPU doesn't support TZ or this is a non-secure translation
5492 * regime, because the attribute will already be non-secure.
5493 */
5494 attrs->secure = false;
5495 }
5496 *phys_ptr = phys_addr;
5497 return false;
5498 do_fault:
5499 *fsr = code | (domain << 4);
5500 return true;
5501 }
5502
5503 /* Fault type for long-descriptor MMU fault reporting; this corresponds
5504 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
5505 */
5506 typedef enum {
5507 translation_fault = 1,
5508 access_fault = 2,
5509 permission_fault = 3,
5510 } MMUFaultType;
5511
5512 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
5513 int access_type, ARMMMUIdx mmu_idx,
5514 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
5515 target_ulong *page_size_ptr, uint32_t *fsr)
5516 {
5517 CPUState *cs = CPU(arm_env_get_cpu(env));
5518 /* Read an LPAE long-descriptor translation table. */
5519 MMUFaultType fault_type = translation_fault;
5520 uint32_t level = 1;
5521 uint32_t epd;
5522 int32_t tsz;
5523 uint32_t tg;
5524 uint64_t ttbr;
5525 int ttbr_select;
5526 hwaddr descaddr, descmask;
5527 uint32_t tableattrs;
5528 target_ulong page_size;
5529 uint32_t attrs;
5530 int32_t granule_sz = 9;
5531 int32_t va_size = 32;
5532 int32_t tbi = 0;
5533 TCR *tcr = regime_tcr(env, mmu_idx);
5534 int ap, ns, xn, pxn;
5535 uint32_t el = regime_el(env, mmu_idx);
5536 bool ttbr1_valid = true;
5537
5538 /* TODO:
5539 * This code does not handle the different format TCR for VTCR_EL2.
5540 * This code also does not support shareability levels.
5541 * Attribute and permission bit handling should also be checked when adding
5542 * support for those page table walks.
5543 */
5544 if (arm_el_is_aa64(env, el)) {
5545 va_size = 64;
5546 if (el > 1) {
5547 tbi = extract64(tcr->raw_tcr, 20, 1);
5548 } else {
5549 if (extract64(address, 55, 1)) {
5550 tbi = extract64(tcr->raw_tcr, 38, 1);
5551 } else {
5552 tbi = extract64(tcr->raw_tcr, 37, 1);
5553 }
5554 }
5555 tbi *= 8;
5556
5557 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
5558 * invalid.
5559 */
5560 if (el > 1) {
5561 ttbr1_valid = false;
5562 }
5563 }
5564
5565 /* Determine whether this address is in the region controlled by
5566 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
5567 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
5568 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
5569 */
5570 uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
5571 if (va_size == 64) {
5572 t0sz = MIN(t0sz, 39);
5573 t0sz = MAX(t0sz, 16);
5574 }
5575 uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
5576 if (va_size == 64) {
5577 t1sz = MIN(t1sz, 39);
5578 t1sz = MAX(t1sz, 16);
5579 }
5580 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
5581 /* there is a ttbr0 region and we are in it (high bits all zero) */
5582 ttbr_select = 0;
5583 } else if (ttbr1_valid && t1sz &&
5584 !extract64(~address, va_size - t1sz, t1sz - tbi)) {
5585 /* there is a ttbr1 region and we are in it (high bits all one) */
5586 ttbr_select = 1;
5587 } else if (!t0sz) {
5588 /* ttbr0 region is "everything not in the ttbr1 region" */
5589 ttbr_select = 0;
5590 } else if (!t1sz && ttbr1_valid) {
5591 /* ttbr1 region is "everything not in the ttbr0 region" */
5592 ttbr_select = 1;
5593 } else {
5594 /* in the gap between the two regions, this is a Translation fault */
5595 fault_type = translation_fault;
5596 goto do_fault;
5597 }
5598
5599 /* Note that QEMU ignores shareability and cacheability attributes,
5600 * so we don't need to do anything with the SH, ORGN, IRGN fields
5601 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
5602 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
5603 * implement any ASID-like capability so we can ignore it (instead
5604 * we will always flush the TLB any time the ASID is changed).
5605 */
5606 if (ttbr_select == 0) {
5607 ttbr = regime_ttbr(env, mmu_idx, 0);
5608 epd = extract32(tcr->raw_tcr, 7, 1);
5609 tsz = t0sz;
5610
5611 tg = extract32(tcr->raw_tcr, 14, 2);
5612 if (tg == 1) { /* 64KB pages */
5613 granule_sz = 13;
5614 }
5615 if (tg == 2) { /* 16KB pages */
5616 granule_sz = 11;
5617 }
5618 } else {
5619 /* We should only be here if TTBR1 is valid */
5620 assert(ttbr1_valid);
5621
5622 ttbr = regime_ttbr(env, mmu_idx, 1);
5623 epd = extract32(tcr->raw_tcr, 23, 1);
5624 tsz = t1sz;
5625
5626 tg = extract32(tcr->raw_tcr, 30, 2);
5627 if (tg == 3) { /* 64KB pages */
5628 granule_sz = 13;
5629 }
5630 if (tg == 1) { /* 16KB pages */
5631 granule_sz = 11;
5632 }
5633 }
5634
5635 /* Here we should have set up all the parameters for the translation:
5636 * va_size, ttbr, epd, tsz, granule_sz, tbi
5637 */
5638
5639 if (epd) {
5640 /* Translation table walk disabled => Translation fault on TLB miss
5641 * Note: This is always 0 on 64-bit EL2 and EL3.
5642 */
5643 goto do_fault;
5644 }
5645
5646 /* The starting level depends on the virtual address size (which can be
5647 * up to 48 bits) and the translation granule size. It indicates the number
5648 * of strides (granule_sz bits at a time) needed to consume the bits
5649 * of the input address. In the pseudocode this is:
5650 * level = 4 - RoundUp((inputsize - grainsize) / stride)
5651 * where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
5652 * our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
5653 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
5654 * = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
5655 * = 4 - (va_size - tsz - 4) / granule_sz;
5656 */
5657 level = 4 - (va_size - tsz - 4) / granule_sz;
5658
5659 /* Clear the vaddr bits which aren't part of the within-region address,
5660 * so that we don't have to special case things when calculating the
5661 * first descriptor address.
5662 */
5663 if (tsz) {
5664 address &= (1ULL << (va_size - tsz)) - 1;
5665 }
5666
5667 descmask = (1ULL << (granule_sz + 3)) - 1;
5668
5669 /* Now we can extract the actual base address from the TTBR */
5670 descaddr = extract64(ttbr, 0, 48);
5671 descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
5672
5673 /* Secure accesses start with the page table in secure memory and
5674 * can be downgraded to non-secure at any step. Non-secure accesses
5675 * remain non-secure. We implement this by just ORing in the NSTable/NS
5676 * bits at each step.
5677 */
5678 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
5679 for (;;) {
5680 uint64_t descriptor;
5681 bool nstable;
5682
5683 descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
5684 descaddr &= ~7ULL;
5685 nstable = extract32(tableattrs, 4, 1);
5686 descriptor = arm_ldq_ptw(cs, descaddr, !nstable);
5687 if (!(descriptor & 1) ||
5688 (!(descriptor & 2) && (level == 3))) {
5689 /* Invalid, or the Reserved level 3 encoding */
5690 goto do_fault;
5691 }
5692 descaddr = descriptor & 0xfffffff000ULL;
5693
5694 if ((descriptor & 2) && (level < 3)) {
5695 /* Table entry. The top five bits are attributes which may
5696 * propagate down through lower levels of the table (and
5697 * which are all arranged so that 0 means "no effect", so
5698 * we can gather them up by ORing in the bits at each level).
5699 */
5700 tableattrs |= extract64(descriptor, 59, 5);
5701 level++;
5702 continue;
5703 }
5704 /* Block entry at level 1 or 2, or page entry at level 3.
5705 * These are basically the same thing, although the number
5706 * of bits we pull in from the vaddr varies.
5707 */
5708 page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
5709 descaddr |= (address & (page_size - 1));
5710 /* Extract attributes from the descriptor and merge with table attrs */
5711 attrs = extract64(descriptor, 2, 10)
5712 | (extract64(descriptor, 52, 12) << 10);
5713 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
5714 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
5715 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
5716 * means "force PL1 access only", which means forcing AP[1] to 0.
5717 */
5718 if (extract32(tableattrs, 2, 1)) {
5719 attrs &= ~(1 << 4);
5720 }
5721 attrs |= nstable << 3; /* NS */
5722 break;
5723 }
5724 /* Here descaddr is the final physical address, and attributes
5725 * are all in attrs.
5726 */
5727 fault_type = access_fault;
5728 if ((attrs & (1 << 8)) == 0) {
5729 /* Access flag */
5730 goto do_fault;
5731 }
5732
5733 ap = extract32(attrs, 4, 2);
5734 ns = extract32(attrs, 3, 1);
5735 xn = extract32(attrs, 12, 1);
5736 pxn = extract32(attrs, 11, 1);
5737
5738 *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
5739
5740 fault_type = permission_fault;
5741 if (!(*prot & (1 << access_type))) {
5742 goto do_fault;
5743 }
5744
5745 if (ns) {
5746 /* The NS bit will (as required by the architecture) have no effect if
5747 * the CPU doesn't support TZ or this is a non-secure translation
5748 * regime, because the attribute will already be non-secure.
5749 */
5750 txattrs->secure = false;
5751 }
5752 *phys_ptr = descaddr;
5753 *page_size_ptr = page_size;
5754 return false;
5755
5756 do_fault:
5757 /* Long-descriptor format IFSR/DFSR value */
5758 *fsr = (1 << 9) | (fault_type << 2) | level;
5759 return true;
5760 }
5761
5762 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
5763 int access_type, ARMMMUIdx mmu_idx,
5764 hwaddr *phys_ptr, int *prot, uint32_t *fsr)
5765 {
5766 int n;
5767 uint32_t mask;
5768 uint32_t base;
5769 bool is_user = regime_is_user(env, mmu_idx);
5770
5771 *phys_ptr = address;
5772 for (n = 7; n >= 0; n--) {
5773 base = env->cp15.c6_region[n];
5774 if ((base & 1) == 0) {
5775 continue;
5776 }
5777 mask = 1 << ((base >> 1) & 0x1f);
5778 /* Keep this shift separate from the above to avoid an
5779 (undefined) << 32. */
5780 mask = (mask << 1) - 1;
5781 if (((base ^ address) & ~mask) == 0) {
5782 break;
5783 }
5784 }
5785 if (n < 0) {
5786 *fsr = 2;
5787 return true;
5788 }
5789
5790 if (access_type == 2) {
5791 mask = env->cp15.pmsav5_insn_ap;
5792 } else {
5793 mask = env->cp15.pmsav5_data_ap;
5794 }
5795 mask = (mask >> (n * 4)) & 0xf;
5796 switch (mask) {
5797 case 0:
5798 *fsr = 1;
5799 return true;
5800 case 1:
5801 if (is_user) {
5802 *fsr = 1;
5803 return true;
5804 }
5805 *prot = PAGE_READ | PAGE_WRITE;
5806 break;
5807 case 2:
5808 *prot = PAGE_READ;
5809 if (!is_user) {
5810 *prot |= PAGE_WRITE;
5811 }
5812 break;
5813 case 3:
5814 *prot = PAGE_READ | PAGE_WRITE;
5815 break;
5816 case 5:
5817 if (is_user) {
5818 *fsr = 1;
5819 return true;
5820 }
5821 *prot = PAGE_READ;
5822 break;
5823 case 6:
5824 *prot = PAGE_READ;
5825 break;
5826 default:
5827 /* Bad permission. */
5828 *fsr = 1;
5829 return true;
5830 }
5831 *prot |= PAGE_EXEC;
5832 return false;
5833 }
5834
5835 /* get_phys_addr - get the physical address for this virtual address
5836 *
5837 * Find the physical address corresponding to the given virtual address,
5838 * by doing a translation table walk on MMU based systems or using the
5839 * MPU state on MPU based systems.
5840 *
5841 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
5842 * prot and page_size may not be filled in, and the populated fsr value provides
5843 * information on why the translation aborted, in the format of a
5844 * DFSR/IFSR fault register, with the following caveats:
5845 * * we honour the short vs long DFSR format differences.
5846 * * the WnR bit is never set (the caller must do this).
5847 * * for MPU based systems we don't bother to return a full FSR format
5848 * value.
5849 *
5850 * @env: CPUARMState
5851 * @address: virtual address to get physical address for
5852 * @access_type: 0 for read, 1 for write, 2 for execute
5853 * @mmu_idx: MMU index indicating required translation regime
5854 * @phys_ptr: set to the physical address corresponding to the virtual address
5855 * @attrs: set to the memory transaction attributes to use
5856 * @prot: set to the permissions for the page containing phys_ptr
5857 * @page_size: set to the size of the page containing phys_ptr
5858 * @fsr: set to the DFSR/IFSR value on failure
5859 */
5860 static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
5861 int access_type, ARMMMUIdx mmu_idx,
5862 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
5863 target_ulong *page_size, uint32_t *fsr)
5864 {
5865 if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
5866 /* TODO: when we support EL2 we should here call ourselves recursively
5867 * to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
5868 * functions will also need changing to perform ARMMMUIdx_S2NS loads
5869 * rather than direct physical memory loads when appropriate.
5870 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
5871 */
5872 assert(!arm_feature(env, ARM_FEATURE_EL2));
5873 mmu_idx += ARMMMUIdx_S1NSE0;
5874 }
5875
5876 /* The page table entries may downgrade secure to non-secure, but
5877 * cannot upgrade an non-secure translation regime's attributes
5878 * to secure.
5879 */
5880 attrs->secure = regime_is_secure(env, mmu_idx);
5881 attrs->user = regime_is_user(env, mmu_idx);
5882
5883 /* Fast Context Switch Extension. This doesn't exist at all in v8.
5884 * In v7 and earlier it affects all stage 1 translations.
5885 */
5886 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
5887 && !arm_feature(env, ARM_FEATURE_V8)) {
5888 if (regime_el(env, mmu_idx) == 3) {
5889 address += env->cp15.fcseidr_s;
5890 } else {
5891 address += env->cp15.fcseidr_ns;
5892 }
5893 }
5894
5895 if (regime_translation_disabled(env, mmu_idx)) {
5896 /* MMU/MPU disabled. */
5897 *phys_ptr = address;
5898 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
5899 *page_size = TARGET_PAGE_SIZE;
5900 return 0;
5901 }
5902
5903 if (arm_feature(env, ARM_FEATURE_MPU)) {
5904 *page_size = TARGET_PAGE_SIZE;
5905 return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
5906 phys_ptr, prot, fsr);
5907 }
5908
5909 if (regime_using_lpae_format(env, mmu_idx)) {
5910 return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
5911 attrs, prot, page_size, fsr);
5912 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
5913 return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
5914 attrs, prot, page_size, fsr);
5915 } else {
5916 return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
5917 prot, page_size, fsr);
5918 }
5919 }
5920
5921 /* Walk the page table and (if the mapping exists) add the page
5922 * to the TLB. Return false on success, or true on failure. Populate
5923 * fsr with ARM DFSR/IFSR fault register format value on failure.
5924 */
5925 bool arm_tlb_fill(CPUState *cs, vaddr address,
5926 int access_type, int mmu_idx, uint32_t *fsr)
5927 {
5928 ARMCPU *cpu = ARM_CPU(cs);
5929 CPUARMState *env = &cpu->env;
5930 hwaddr phys_addr;
5931 target_ulong page_size;
5932 int prot;
5933 int ret;
5934 MemTxAttrs attrs = {};
5935
5936 ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
5937 &attrs, &prot, &page_size, fsr);
5938 if (!ret) {
5939 /* Map a single [sub]page. */
5940 phys_addr &= TARGET_PAGE_MASK;
5941 address &= TARGET_PAGE_MASK;
5942 tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
5943 prot, mmu_idx, page_size);
5944 return 0;
5945 }
5946
5947 return ret;
5948 }
5949
5950 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
5951 {
5952 ARMCPU *cpu = ARM_CPU(cs);
5953 CPUARMState *env = &cpu->env;
5954 hwaddr phys_addr;
5955 target_ulong page_size;
5956 int prot;
5957 bool ret;
5958 uint32_t fsr;
5959 MemTxAttrs attrs = {};
5960
5961 ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
5962 &attrs, &prot, &page_size, &fsr);
5963
5964 if (ret) {
5965 return -1;
5966 }
5967
5968 return phys_addr;
5969 }
5970
5971 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
5972 {
5973 if ((env->uncached_cpsr & CPSR_M) == mode) {
5974 env->regs[13] = val;
5975 } else {
5976 env->banked_r13[bank_number(mode)] = val;
5977 }
5978 }
5979
5980 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
5981 {
5982 if ((env->uncached_cpsr & CPSR_M) == mode) {
5983 return env->regs[13];
5984 } else {
5985 return env->banked_r13[bank_number(mode)];
5986 }
5987 }
5988
5989 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5990 {
5991 ARMCPU *cpu = arm_env_get_cpu(env);
5992
5993 switch (reg) {
5994 case 0: /* APSR */
5995 return xpsr_read(env) & 0xf8000000;
5996 case 1: /* IAPSR */
5997 return xpsr_read(env) & 0xf80001ff;
5998 case 2: /* EAPSR */
5999 return xpsr_read(env) & 0xff00fc00;
6000 case 3: /* xPSR */
6001 return xpsr_read(env) & 0xff00fdff;
6002 case 5: /* IPSR */
6003 return xpsr_read(env) & 0x000001ff;
6004 case 6: /* EPSR */
6005 return xpsr_read(env) & 0x0700fc00;
6006 case 7: /* IEPSR */
6007 return xpsr_read(env) & 0x0700edff;
6008 case 8: /* MSP */
6009 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
6010 case 9: /* PSP */
6011 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
6012 case 16: /* PRIMASK */
6013 return (env->daif & PSTATE_I) != 0;
6014 case 17: /* BASEPRI */
6015 case 18: /* BASEPRI_MAX */
6016 return env->v7m.basepri;
6017 case 19: /* FAULTMASK */
6018 return (env->daif & PSTATE_F) != 0;
6019 case 20: /* CONTROL */
6020 return env->v7m.control;
6021 default:
6022 /* ??? For debugging only. */
6023 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
6024 return 0;
6025 }
6026 }
6027
6028 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
6029 {
6030 ARMCPU *cpu = arm_env_get_cpu(env);
6031
6032 switch (reg) {
6033 case 0: /* APSR */
6034 xpsr_write(env, val, 0xf8000000);
6035 break;
6036 case 1: /* IAPSR */
6037 xpsr_write(env, val, 0xf8000000);
6038 break;
6039 case 2: /* EAPSR */
6040 xpsr_write(env, val, 0xfe00fc00);
6041 break;
6042 case 3: /* xPSR */
6043 xpsr_write(env, val, 0xfe00fc00);
6044 break;
6045 case 5: /* IPSR */
6046 /* IPSR bits are readonly. */
6047 break;
6048 case 6: /* EPSR */
6049 xpsr_write(env, val, 0x0600fc00);
6050 break;
6051 case 7: /* IEPSR */
6052 xpsr_write(env, val, 0x0600fc00);
6053 break;
6054 case 8: /* MSP */
6055 if (env->v7m.current_sp)
6056 env->v7m.other_sp = val;
6057 else
6058 env->regs[13] = val;
6059 break;
6060 case 9: /* PSP */
6061 if (env->v7m.current_sp)
6062 env->regs[13] = val;
6063 else
6064 env->v7m.other_sp = val;
6065 break;
6066 case 16: /* PRIMASK */
6067 if (val & 1) {
6068 env->daif |= PSTATE_I;
6069 } else {
6070 env->daif &= ~PSTATE_I;
6071 }
6072 break;
6073 case 17: /* BASEPRI */
6074 env->v7m.basepri = val & 0xff;
6075 break;
6076 case 18: /* BASEPRI_MAX */
6077 val &= 0xff;
6078 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
6079 env->v7m.basepri = val;
6080 break;
6081 case 19: /* FAULTMASK */
6082 if (val & 1) {
6083 env->daif |= PSTATE_F;
6084 } else {
6085 env->daif &= ~PSTATE_F;
6086 }
6087 break;
6088 case 20: /* CONTROL */
6089 env->v7m.control = val & 3;
6090 switch_v7m_sp(env, (val & 2) != 0);
6091 break;
6092 default:
6093 /* ??? For debugging only. */
6094 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
6095 return;
6096 }
6097 }
6098
6099 #endif
6100
6101 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
6102 {
6103 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
6104 * Note that we do not implement the (architecturally mandated)
6105 * alignment fault for attempts to use this on Device memory
6106 * (which matches the usual QEMU behaviour of not implementing either
6107 * alignment faults or any memory attribute handling).
6108 */
6109
6110 ARMCPU *cpu = arm_env_get_cpu(env);
6111 uint64_t blocklen = 4 << cpu->dcz_blocksize;
6112 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
6113
6114 #ifndef CONFIG_USER_ONLY
6115 {
6116 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
6117 * the block size so we might have to do more than one TLB lookup.
6118 * We know that in fact for any v8 CPU the page size is at least 4K
6119 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
6120 * 1K as an artefact of legacy v5 subpage support being present in the
6121 * same QEMU executable.
6122 */
6123 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
6124 void *hostaddr[maxidx];
6125 int try, i;
6126 unsigned mmu_idx = cpu_mmu_index(env);
6127 TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
6128
6129 for (try = 0; try < 2; try++) {
6130
6131 for (i = 0; i < maxidx; i++) {
6132 hostaddr[i] = tlb_vaddr_to_host(env,
6133 vaddr + TARGET_PAGE_SIZE * i,
6134 1, mmu_idx);
6135 if (!hostaddr[i]) {
6136 break;
6137 }
6138 }
6139 if (i == maxidx) {
6140 /* If it's all in the TLB it's fair game for just writing to;
6141 * we know we don't need to update dirty status, etc.
6142 */
6143 for (i = 0; i < maxidx - 1; i++) {
6144 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
6145 }
6146 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
6147 return;
6148 }
6149 /* OK, try a store and see if we can populate the tlb. This
6150 * might cause an exception if the memory isn't writable,
6151 * in which case we will longjmp out of here. We must for
6152 * this purpose use the actual register value passed to us
6153 * so that we get the fault address right.
6154 */
6155 helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
6156 /* Now we can populate the other TLB entries, if any */
6157 for (i = 0; i < maxidx; i++) {
6158 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
6159 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
6160 helper_ret_stb_mmu(env, va, 0, oi, GETRA());
6161 }
6162 }
6163 }
6164
6165 /* Slow path (probably attempt to do this to an I/O device or
6166 * similar, or clearing of a block of code we have translations
6167 * cached for). Just do a series of byte writes as the architecture
6168 * demands. It's not worth trying to use a cpu_physical_memory_map(),
6169 * memset(), unmap() sequence here because:
6170 * + we'd need to account for the blocksize being larger than a page
6171 * + the direct-RAM access case is almost always going to be dealt
6172 * with in the fastpath code above, so there's no speed benefit
6173 * + we would have to deal with the map returning NULL because the
6174 * bounce buffer was in use
6175 */
6176 for (i = 0; i < blocklen; i++) {
6177 helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
6178 }
6179 }
6180 #else
6181 memset(g2h(vaddr), 0, blocklen);
6182 #endif
6183 }
6184
6185 /* Note that signed overflow is undefined in C. The following routines are
6186 careful to use unsigned types where modulo arithmetic is required.
6187 Failure to do so _will_ break on newer gcc. */
6188
6189 /* Signed saturating arithmetic. */
6190
6191 /* Perform 16-bit signed saturating addition. */
6192 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
6193 {
6194 uint16_t res;
6195
6196 res = a + b;
6197 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
6198 if (a & 0x8000)
6199 res = 0x8000;
6200 else
6201 res = 0x7fff;
6202 }
6203 return res;
6204 }
6205
6206 /* Perform 8-bit signed saturating addition. */
6207 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
6208 {
6209 uint8_t res;
6210
6211 res = a + b;
6212 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
6213 if (a & 0x80)
6214 res = 0x80;
6215 else
6216 res = 0x7f;
6217 }
6218 return res;
6219 }
6220
6221 /* Perform 16-bit signed saturating subtraction. */
6222 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
6223 {
6224 uint16_t res;
6225
6226 res = a - b;
6227 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
6228 if (a & 0x8000)
6229 res = 0x8000;
6230 else
6231 res = 0x7fff;
6232 }
6233 return res;
6234 }
6235
6236 /* Perform 8-bit signed saturating subtraction. */
6237 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
6238 {
6239 uint8_t res;
6240
6241 res = a - b;
6242 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
6243 if (a & 0x80)
6244 res = 0x80;
6245 else
6246 res = 0x7f;
6247 }
6248 return res;
6249 }
6250
6251 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
6252 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
6253 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
6254 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
6255 #define PFX q
6256
6257 #include "op_addsub.h"
6258
6259 /* Unsigned saturating arithmetic. */
6260 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6261 {
6262 uint16_t res;
6263 res = a + b;
6264 if (res < a)
6265 res = 0xffff;
6266 return res;
6267 }
6268
6269 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6270 {
6271 if (a > b)
6272 return a - b;
6273 else
6274 return 0;
6275 }
6276
6277 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
6278 {
6279 uint8_t res;
6280 res = a + b;
6281 if (res < a)
6282 res = 0xff;
6283 return res;
6284 }
6285
6286 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
6287 {
6288 if (a > b)
6289 return a - b;
6290 else
6291 return 0;
6292 }
6293
6294 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
6295 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
6296 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
6297 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
6298 #define PFX uq
6299
6300 #include "op_addsub.h"
6301
6302 /* Signed modulo arithmetic. */
6303 #define SARITH16(a, b, n, op) do { \
6304 int32_t sum; \
6305 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6306 RESULT(sum, n, 16); \
6307 if (sum >= 0) \
6308 ge |= 3 << (n * 2); \
6309 } while(0)
6310
6311 #define SARITH8(a, b, n, op) do { \
6312 int32_t sum; \
6313 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6314 RESULT(sum, n, 8); \
6315 if (sum >= 0) \
6316 ge |= 1 << n; \
6317 } while(0)
6318
6319
6320 #define ADD16(a, b, n) SARITH16(a, b, n, +)
6321 #define SUB16(a, b, n) SARITH16(a, b, n, -)
6322 #define ADD8(a, b, n) SARITH8(a, b, n, +)
6323 #define SUB8(a, b, n) SARITH8(a, b, n, -)
6324 #define PFX s
6325 #define ARITH_GE
6326
6327 #include "op_addsub.h"
6328
6329 /* Unsigned modulo arithmetic. */
6330 #define ADD16(a, b, n) do { \
6331 uint32_t sum; \
6332 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
6333 RESULT(sum, n, 16); \
6334 if ((sum >> 16) == 1) \
6335 ge |= 3 << (n * 2); \
6336 } while(0)
6337
6338 #define ADD8(a, b, n) do { \
6339 uint32_t sum; \
6340 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
6341 RESULT(sum, n, 8); \
6342 if ((sum >> 8) == 1) \
6343 ge |= 1 << n; \
6344 } while(0)
6345
6346 #define SUB16(a, b, n) do { \
6347 uint32_t sum; \
6348 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
6349 RESULT(sum, n, 16); \
6350 if ((sum >> 16) == 0) \
6351 ge |= 3 << (n * 2); \
6352 } while(0)
6353
6354 #define SUB8(a, b, n) do { \
6355 uint32_t sum; \
6356 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
6357 RESULT(sum, n, 8); \
6358 if ((sum >> 8) == 0) \
6359 ge |= 1 << n; \
6360 } while(0)
6361
6362 #define PFX u
6363 #define ARITH_GE
6364
6365 #include "op_addsub.h"
6366
6367 /* Halved signed arithmetic. */
6368 #define ADD16(a, b, n) \
6369 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
6370 #define SUB16(a, b, n) \
6371 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
6372 #define ADD8(a, b, n) \
6373 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
6374 #define SUB8(a, b, n) \
6375 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
6376 #define PFX sh
6377
6378 #include "op_addsub.h"
6379
6380 /* Halved unsigned arithmetic. */
6381 #define ADD16(a, b, n) \
6382 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6383 #define SUB16(a, b, n) \
6384 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
6385 #define ADD8(a, b, n) \
6386 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6387 #define SUB8(a, b, n) \
6388 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
6389 #define PFX uh
6390
6391 #include "op_addsub.h"
6392
6393 static inline uint8_t do_usad(uint8_t a, uint8_t b)
6394 {
6395 if (a > b)
6396 return a - b;
6397 else
6398 return b - a;
6399 }
6400
6401 /* Unsigned sum of absolute byte differences. */
6402 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
6403 {
6404 uint32_t sum;
6405 sum = do_usad(a, b);
6406 sum += do_usad(a >> 8, b >> 8);
6407 sum += do_usad(a >> 16, b >>16);
6408 sum += do_usad(a >> 24, b >> 24);
6409 return sum;
6410 }
6411
6412 /* For ARMv6 SEL instruction. */
6413 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
6414 {
6415 uint32_t mask;
6416
6417 mask = 0;
6418 if (flags & 1)
6419 mask |= 0xff;
6420 if (flags & 2)
6421 mask |= 0xff00;
6422 if (flags & 4)
6423 mask |= 0xff0000;
6424 if (flags & 8)
6425 mask |= 0xff000000;
6426 return (a & mask) | (b & ~mask);
6427 }
6428
6429 /* VFP support. We follow the convention used for VFP instructions:
6430 Single precision routines have a "s" suffix, double precision a
6431 "d" suffix. */
6432
6433 /* Convert host exception flags to vfp form. */
6434 static inline int vfp_exceptbits_from_host(int host_bits)
6435 {
6436 int target_bits = 0;
6437
6438 if (host_bits & float_flag_invalid)
6439 target_bits |= 1;
6440 if (host_bits & float_flag_divbyzero)
6441 target_bits |= 2;
6442 if (host_bits & float_flag_overflow)
6443 target_bits |= 4;
6444 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
6445 target_bits |= 8;
6446 if (host_bits & float_flag_inexact)
6447 target_bits |= 0x10;
6448 if (host_bits & float_flag_input_denormal)
6449 target_bits |= 0x80;
6450 return target_bits;
6451 }
6452
6453 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
6454 {
6455 int i;
6456 uint32_t fpscr;
6457
6458 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
6459 | (env->vfp.vec_len << 16)
6460 | (env->vfp.vec_stride << 20);
6461 i = get_float_exception_flags(&env->vfp.fp_status);
6462 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
6463 fpscr |= vfp_exceptbits_from_host(i);
6464 return fpscr;
6465 }
6466
6467 uint32_t vfp_get_fpscr(CPUARMState *env)
6468 {
6469 return HELPER(vfp_get_fpscr)(env);
6470 }
6471
6472 /* Convert vfp exception flags to target form. */
6473 static inline int vfp_exceptbits_to_host(int target_bits)
6474 {
6475 int host_bits = 0;
6476
6477 if (target_bits & 1)
6478 host_bits |= float_flag_invalid;
6479 if (target_bits & 2)
6480 host_bits |= float_flag_divbyzero;
6481 if (target_bits & 4)
6482 host_bits |= float_flag_overflow;
6483 if (target_bits & 8)
6484 host_bits |= float_flag_underflow;
6485 if (target_bits & 0x10)
6486 host_bits |= float_flag_inexact;
6487 if (target_bits & 0x80)
6488 host_bits |= float_flag_input_denormal;
6489 return host_bits;
6490 }
6491
6492 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
6493 {
6494 int i;
6495 uint32_t changed;
6496
6497 changed = env->vfp.xregs[ARM_VFP_FPSCR];
6498 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
6499 env->vfp.vec_len = (val >> 16) & 7;
6500 env->vfp.vec_stride = (val >> 20) & 3;
6501
6502 changed ^= val;
6503 if (changed & (3 << 22)) {
6504 i = (val >> 22) & 3;
6505 switch (i) {
6506 case FPROUNDING_TIEEVEN:
6507 i = float_round_nearest_even;
6508 break;
6509 case FPROUNDING_POSINF:
6510 i = float_round_up;
6511 break;
6512 case FPROUNDING_NEGINF:
6513 i = float_round_down;
6514 break;
6515 case FPROUNDING_ZERO:
6516 i = float_round_to_zero;
6517 break;
6518 }
6519 set_float_rounding_mode(i, &env->vfp.fp_status);
6520 }
6521 if (changed & (1 << 24)) {
6522 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6523 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
6524 }
6525 if (changed & (1 << 25))
6526 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
6527
6528 i = vfp_exceptbits_to_host(val);
6529 set_float_exception_flags(i, &env->vfp.fp_status);
6530 set_float_exception_flags(0, &env->vfp.standard_fp_status);
6531 }
6532
6533 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
6534 {
6535 HELPER(vfp_set_fpscr)(env, val);
6536 }
6537
6538 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
6539
6540 #define VFP_BINOP(name) \
6541 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
6542 { \
6543 float_status *fpst = fpstp; \
6544 return float32_ ## name(a, b, fpst); \
6545 } \
6546 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
6547 { \
6548 float_status *fpst = fpstp; \
6549 return float64_ ## name(a, b, fpst); \
6550 }
6551 VFP_BINOP(add)
6552 VFP_BINOP(sub)
6553 VFP_BINOP(mul)
6554 VFP_BINOP(div)
6555 VFP_BINOP(min)
6556 VFP_BINOP(max)
6557 VFP_BINOP(minnum)
6558 VFP_BINOP(maxnum)
6559 #undef VFP_BINOP
6560
6561 float32 VFP_HELPER(neg, s)(float32 a)
6562 {
6563 return float32_chs(a);
6564 }
6565
6566 float64 VFP_HELPER(neg, d)(float64 a)
6567 {
6568 return float64_chs(a);
6569 }
6570
6571 float32 VFP_HELPER(abs, s)(float32 a)
6572 {
6573 return float32_abs(a);
6574 }
6575
6576 float64 VFP_HELPER(abs, d)(float64 a)
6577 {
6578 return float64_abs(a);
6579 }
6580
6581 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
6582 {
6583 return float32_sqrt(a, &env->vfp.fp_status);
6584 }
6585
6586 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
6587 {
6588 return float64_sqrt(a, &env->vfp.fp_status);
6589 }
6590
6591 /* XXX: check quiet/signaling case */
6592 #define DO_VFP_cmp(p, type) \
6593 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
6594 { \
6595 uint32_t flags; \
6596 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
6597 case 0: flags = 0x6; break; \
6598 case -1: flags = 0x8; break; \
6599 case 1: flags = 0x2; break; \
6600 default: case 2: flags = 0x3; break; \
6601 } \
6602 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6603 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6604 } \
6605 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
6606 { \
6607 uint32_t flags; \
6608 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
6609 case 0: flags = 0x6; break; \
6610 case -1: flags = 0x8; break; \
6611 case 1: flags = 0x2; break; \
6612 default: case 2: flags = 0x3; break; \
6613 } \
6614 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
6615 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
6616 }
6617 DO_VFP_cmp(s, float32)
6618 DO_VFP_cmp(d, float64)
6619 #undef DO_VFP_cmp
6620
6621 /* Integer to float and float to integer conversions */
6622
6623 #define CONV_ITOF(name, fsz, sign) \
6624 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
6625 { \
6626 float_status *fpst = fpstp; \
6627 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
6628 }
6629
6630 #define CONV_FTOI(name, fsz, sign, round) \
6631 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
6632 { \
6633 float_status *fpst = fpstp; \
6634 if (float##fsz##_is_any_nan(x)) { \
6635 float_raise(float_flag_invalid, fpst); \
6636 return 0; \
6637 } \
6638 return float##fsz##_to_##sign##int32##round(x, fpst); \
6639 }
6640
6641 #define FLOAT_CONVS(name, p, fsz, sign) \
6642 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
6643 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
6644 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
6645
6646 FLOAT_CONVS(si, s, 32, )
6647 FLOAT_CONVS(si, d, 64, )
6648 FLOAT_CONVS(ui, s, 32, u)
6649 FLOAT_CONVS(ui, d, 64, u)
6650
6651 #undef CONV_ITOF
6652 #undef CONV_FTOI
6653 #undef FLOAT_CONVS
6654
6655 /* floating point conversion */
6656 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
6657 {
6658 float64 r = float32_to_float64(x, &env->vfp.fp_status);
6659 /* ARM requires that S<->D conversion of any kind of NaN generates
6660 * a quiet NaN by forcing the most significant frac bit to 1.
6661 */
6662 return float64_maybe_silence_nan(r);
6663 }
6664
6665 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
6666 {
6667 float32 r = float64_to_float32(x, &env->vfp.fp_status);
6668 /* ARM requires that S<->D conversion of any kind of NaN generates
6669 * a quiet NaN by forcing the most significant frac bit to 1.
6670 */
6671 return float32_maybe_silence_nan(r);
6672 }
6673
6674 /* VFP3 fixed point conversion. */
6675 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6676 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
6677 void *fpstp) \
6678 { \
6679 float_status *fpst = fpstp; \
6680 float##fsz tmp; \
6681 tmp = itype##_to_##float##fsz(x, fpst); \
6682 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
6683 }
6684
6685 /* Notice that we want only input-denormal exception flags from the
6686 * scalbn operation: the other possible flags (overflow+inexact if
6687 * we overflow to infinity, output-denormal) aren't correct for the
6688 * complete scale-and-convert operation.
6689 */
6690 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
6691 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
6692 uint32_t shift, \
6693 void *fpstp) \
6694 { \
6695 float_status *fpst = fpstp; \
6696 int old_exc_flags = get_float_exception_flags(fpst); \
6697 float##fsz tmp; \
6698 if (float##fsz##_is_any_nan(x)) { \
6699 float_raise(float_flag_invalid, fpst); \
6700 return 0; \
6701 } \
6702 tmp = float##fsz##_scalbn(x, shift, fpst); \
6703 old_exc_flags |= get_float_exception_flags(fpst) \
6704 & float_flag_input_denormal; \
6705 set_float_exception_flags(old_exc_flags, fpst); \
6706 return float##fsz##_to_##itype##round(tmp, fpst); \
6707 }
6708
6709 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
6710 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6711 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
6712 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6713
6714 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
6715 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
6716 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
6717
6718 VFP_CONV_FIX(sh, d, 64, 64, int16)
6719 VFP_CONV_FIX(sl, d, 64, 64, int32)
6720 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
6721 VFP_CONV_FIX(uh, d, 64, 64, uint16)
6722 VFP_CONV_FIX(ul, d, 64, 64, uint32)
6723 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
6724 VFP_CONV_FIX(sh, s, 32, 32, int16)
6725 VFP_CONV_FIX(sl, s, 32, 32, int32)
6726 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
6727 VFP_CONV_FIX(uh, s, 32, 32, uint16)
6728 VFP_CONV_FIX(ul, s, 32, 32, uint32)
6729 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
6730 #undef VFP_CONV_FIX
6731 #undef VFP_CONV_FIX_FLOAT
6732 #undef VFP_CONV_FLOAT_FIX_ROUND
6733
6734 /* Set the current fp rounding mode and return the old one.
6735 * The argument is a softfloat float_round_ value.
6736 */
6737 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
6738 {
6739 float_status *fp_status = &env->vfp.fp_status;
6740
6741 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6742 set_float_rounding_mode(rmode, fp_status);
6743
6744 return prev_rmode;
6745 }
6746
6747 /* Set the current fp rounding mode in the standard fp status and return
6748 * the old one. This is for NEON instructions that need to change the
6749 * rounding mode but wish to use the standard FPSCR values for everything
6750 * else. Always set the rounding mode back to the correct value after
6751 * modifying it.
6752 * The argument is a softfloat float_round_ value.
6753 */
6754 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
6755 {
6756 float_status *fp_status = &env->vfp.standard_fp_status;
6757
6758 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
6759 set_float_rounding_mode(rmode, fp_status);
6760
6761 return prev_rmode;
6762 }
6763
6764 /* Half precision conversions. */
6765 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
6766 {
6767 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6768 float32 r = float16_to_float32(make_float16(a), ieee, s);
6769 if (ieee) {
6770 return float32_maybe_silence_nan(r);
6771 }
6772 return r;
6773 }
6774
6775 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
6776 {
6777 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6778 float16 r = float32_to_float16(a, ieee, s);
6779 if (ieee) {
6780 r = float16_maybe_silence_nan(r);
6781 }
6782 return float16_val(r);
6783 }
6784
6785 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6786 {
6787 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
6788 }
6789
6790 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6791 {
6792 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
6793 }
6794
6795 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
6796 {
6797 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
6798 }
6799
6800 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
6801 {
6802 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
6803 }
6804
6805 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
6806 {
6807 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6808 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
6809 if (ieee) {
6810 return float64_maybe_silence_nan(r);
6811 }
6812 return r;
6813 }
6814
6815 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
6816 {
6817 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
6818 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
6819 if (ieee) {
6820 r = float16_maybe_silence_nan(r);
6821 }
6822 return float16_val(r);
6823 }
6824
6825 #define float32_two make_float32(0x40000000)
6826 #define float32_three make_float32(0x40400000)
6827 #define float32_one_point_five make_float32(0x3fc00000)
6828
6829 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
6830 {
6831 float_status *s = &env->vfp.standard_fp_status;
6832 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6833 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6834 if (!(float32_is_zero(a) || float32_is_zero(b))) {
6835 float_raise(float_flag_input_denormal, s);
6836 }
6837 return float32_two;
6838 }
6839 return float32_sub(float32_two, float32_mul(a, b, s), s);
6840 }
6841
6842 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
6843 {
6844 float_status *s = &env->vfp.standard_fp_status;
6845 float32 product;
6846 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
6847 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
6848 if (!(float32_is_zero(a) || float32_is_zero(b))) {
6849 float_raise(float_flag_input_denormal, s);
6850 }
6851 return float32_one_point_five;
6852 }
6853 product = float32_mul(a, b, s);
6854 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
6855 }
6856
6857 /* NEON helpers. */
6858
6859 /* Constants 256 and 512 are used in some helpers; we avoid relying on
6860 * int->float conversions at run-time. */
6861 #define float64_256 make_float64(0x4070000000000000LL)
6862 #define float64_512 make_float64(0x4080000000000000LL)
6863 #define float32_maxnorm make_float32(0x7f7fffff)
6864 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
6865
6866 /* Reciprocal functions
6867 *
6868 * The algorithm that must be used to calculate the estimate
6869 * is specified by the ARM ARM, see FPRecipEstimate()
6870 */
6871
6872 static float64 recip_estimate(float64 a, float_status *real_fp_status)
6873 {
6874 /* These calculations mustn't set any fp exception flags,
6875 * so we use a local copy of the fp_status.
6876 */
6877 float_status dummy_status = *real_fp_status;
6878 float_status *s = &dummy_status;
6879 /* q = (int)(a * 512.0) */
6880 float64 q = float64_mul(float64_512, a, s);
6881 int64_t q_int = float64_to_int64_round_to_zero(q, s);
6882
6883 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
6884 q = int64_to_float64(q_int, s);
6885 q = float64_add(q, float64_half, s);
6886 q = float64_div(q, float64_512, s);
6887 q = float64_div(float64_one, q, s);
6888
6889 /* s = (int)(256.0 * r + 0.5) */
6890 q = float64_mul(q, float64_256, s);
6891 q = float64_add(q, float64_half, s);
6892 q_int = float64_to_int64_round_to_zero(q, s);
6893
6894 /* return (double)s / 256.0 */
6895 return float64_div(int64_to_float64(q_int, s), float64_256, s);
6896 }
6897
6898 /* Common wrapper to call recip_estimate */
6899 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
6900 {
6901 uint64_t val64 = float64_val(num);
6902 uint64_t frac = extract64(val64, 0, 52);
6903 int64_t exp = extract64(val64, 52, 11);
6904 uint64_t sbit;
6905 float64 scaled, estimate;
6906
6907 /* Generate the scaled number for the estimate function */
6908 if (exp == 0) {
6909 if (extract64(frac, 51, 1) == 0) {
6910 exp = -1;
6911 frac = extract64(frac, 0, 50) << 2;
6912 } else {
6913 frac = extract64(frac, 0, 51) << 1;
6914 }
6915 }
6916
6917 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
6918 scaled = make_float64((0x3feULL << 52)
6919 | extract64(frac, 44, 8) << 44);
6920
6921 estimate = recip_estimate(scaled, fpst);
6922
6923 /* Build new result */
6924 val64 = float64_val(estimate);
6925 sbit = 0x8000000000000000ULL & val64;
6926 exp = off - exp;
6927 frac = extract64(val64, 0, 52);
6928
6929 if (exp == 0) {
6930 frac = 1ULL << 51 | extract64(frac, 1, 51);
6931 } else if (exp == -1) {
6932 frac = 1ULL << 50 | extract64(frac, 2, 50);
6933 exp = 0;
6934 }
6935
6936 return make_float64(sbit | (exp << 52) | frac);
6937 }
6938
6939 static bool round_to_inf(float_status *fpst, bool sign_bit)
6940 {
6941 switch (fpst->float_rounding_mode) {
6942 case float_round_nearest_even: /* Round to Nearest */
6943 return true;
6944 case float_round_up: /* Round to +Inf */
6945 return !sign_bit;
6946 case float_round_down: /* Round to -Inf */
6947 return sign_bit;
6948 case float_round_to_zero: /* Round to Zero */
6949 return false;
6950 }
6951
6952 g_assert_not_reached();
6953 }
6954
6955 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
6956 {
6957 float_status *fpst = fpstp;
6958 float32 f32 = float32_squash_input_denormal(input, fpst);
6959 uint32_t f32_val = float32_val(f32);
6960 uint32_t f32_sbit = 0x80000000ULL & f32_val;
6961 int32_t f32_exp = extract32(f32_val, 23, 8);
6962 uint32_t f32_frac = extract32(f32_val, 0, 23);
6963 float64 f64, r64;
6964 uint64_t r64_val;
6965 int64_t r64_exp;
6966 uint64_t r64_frac;
6967
6968 if (float32_is_any_nan(f32)) {
6969 float32 nan = f32;
6970 if (float32_is_signaling_nan(f32)) {
6971 float_raise(float_flag_invalid, fpst);
6972 nan = float32_maybe_silence_nan(f32);
6973 }
6974 if (fpst->default_nan_mode) {
6975 nan = float32_default_nan;
6976 }
6977 return nan;
6978 } else if (float32_is_infinity(f32)) {
6979 return float32_set_sign(float32_zero, float32_is_neg(f32));
6980 } else if (float32_is_zero(f32)) {
6981 float_raise(float_flag_divbyzero, fpst);
6982 return float32_set_sign(float32_infinity, float32_is_neg(f32));
6983 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
6984 /* Abs(value) < 2.0^-128 */
6985 float_raise(float_flag_overflow | float_flag_inexact, fpst);
6986 if (round_to_inf(fpst, f32_sbit)) {
6987 return float32_set_sign(float32_infinity, float32_is_neg(f32));
6988 } else {
6989 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
6990 }
6991 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
6992 float_raise(float_flag_underflow, fpst);
6993 return float32_set_sign(float32_zero, float32_is_neg(f32));
6994 }
6995
6996
6997 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
6998 r64 = call_recip_estimate(f64, 253, fpst);
6999 r64_val = float64_val(r64);
7000 r64_exp = extract64(r64_val, 52, 11);
7001 r64_frac = extract64(r64_val, 0, 52);
7002
7003 /* result = sign : result_exp<7:0> : fraction<51:29>; */
7004 return make_float32(f32_sbit |
7005 (r64_exp & 0xff) << 23 |
7006 extract64(r64_frac, 29, 24));
7007 }
7008
7009 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
7010 {
7011 float_status *fpst = fpstp;
7012 float64 f64 = float64_squash_input_denormal(input, fpst);
7013 uint64_t f64_val = float64_val(f64);
7014 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
7015 int64_t f64_exp = extract64(f64_val, 52, 11);
7016 float64 r64;
7017 uint64_t r64_val;
7018 int64_t r64_exp;
7019 uint64_t r64_frac;
7020
7021 /* Deal with any special cases */
7022 if (float64_is_any_nan(f64)) {
7023 float64 nan = f64;
7024 if (float64_is_signaling_nan(f64)) {
7025 float_raise(float_flag_invalid, fpst);
7026 nan = float64_maybe_silence_nan(f64);
7027 }
7028 if (fpst->default_nan_mode) {
7029 nan = float64_default_nan;
7030 }
7031 return nan;
7032 } else if (float64_is_infinity(f64)) {
7033 return float64_set_sign(float64_zero, float64_is_neg(f64));
7034 } else if (float64_is_zero(f64)) {
7035 float_raise(float_flag_divbyzero, fpst);
7036 return float64_set_sign(float64_infinity, float64_is_neg(f64));
7037 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
7038 /* Abs(value) < 2.0^-1024 */
7039 float_raise(float_flag_overflow | float_flag_inexact, fpst);
7040 if (round_to_inf(fpst, f64_sbit)) {
7041 return float64_set_sign(float64_infinity, float64_is_neg(f64));
7042 } else {
7043 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
7044 }
7045 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
7046 float_raise(float_flag_underflow, fpst);
7047 return float64_set_sign(float64_zero, float64_is_neg(f64));
7048 }
7049
7050 r64 = call_recip_estimate(f64, 2045, fpst);
7051 r64_val = float64_val(r64);
7052 r64_exp = extract64(r64_val, 52, 11);
7053 r64_frac = extract64(r64_val, 0, 52);
7054
7055 /* result = sign : result_exp<10:0> : fraction<51:0> */
7056 return make_float64(f64_sbit |
7057 ((r64_exp & 0x7ff) << 52) |
7058 r64_frac);
7059 }
7060
7061 /* The algorithm that must be used to calculate the estimate
7062 * is specified by the ARM ARM.
7063 */
7064 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
7065 {
7066 /* These calculations mustn't set any fp exception flags,
7067 * so we use a local copy of the fp_status.
7068 */
7069 float_status dummy_status = *real_fp_status;
7070 float_status *s = &dummy_status;
7071 float64 q;
7072 int64_t q_int;
7073
7074 if (float64_lt(a, float64_half, s)) {
7075 /* range 0.25 <= a < 0.5 */
7076
7077 /* a in units of 1/512 rounded down */
7078 /* q0 = (int)(a * 512.0); */
7079 q = float64_mul(float64_512, a, s);
7080 q_int = float64_to_int64_round_to_zero(q, s);
7081
7082 /* reciprocal root r */
7083 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
7084 q = int64_to_float64(q_int, s);
7085 q = float64_add(q, float64_half, s);
7086 q = float64_div(q, float64_512, s);
7087 q = float64_sqrt(q, s);
7088 q = float64_div(float64_one, q, s);
7089 } else {
7090 /* range 0.5 <= a < 1.0 */
7091
7092 /* a in units of 1/256 rounded down */
7093 /* q1 = (int)(a * 256.0); */
7094 q = float64_mul(float64_256, a, s);
7095 int64_t q_int = float64_to_int64_round_to_zero(q, s);
7096
7097 /* reciprocal root r */
7098 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
7099 q = int64_to_float64(q_int, s);
7100 q = float64_add(q, float64_half, s);
7101 q = float64_div(q, float64_256, s);
7102 q = float64_sqrt(q, s);
7103 q = float64_div(float64_one, q, s);
7104 }
7105 /* r in units of 1/256 rounded to nearest */
7106 /* s = (int)(256.0 * r + 0.5); */
7107
7108 q = float64_mul(q, float64_256,s );
7109 q = float64_add(q, float64_half, s);
7110 q_int = float64_to_int64_round_to_zero(q, s);
7111
7112 /* return (double)s / 256.0;*/
7113 return float64_div(int64_to_float64(q_int, s), float64_256, s);
7114 }
7115
7116 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
7117 {
7118 float_status *s = fpstp;
7119 float32 f32 = float32_squash_input_denormal(input, s);
7120 uint32_t val = float32_val(f32);
7121 uint32_t f32_sbit = 0x80000000 & val;
7122 int32_t f32_exp = extract32(val, 23, 8);
7123 uint32_t f32_frac = extract32(val, 0, 23);
7124 uint64_t f64_frac;
7125 uint64_t val64;
7126 int result_exp;
7127 float64 f64;
7128
7129 if (float32_is_any_nan(f32)) {
7130 float32 nan = f32;
7131 if (float32_is_signaling_nan(f32)) {
7132 float_raise(float_flag_invalid, s);
7133 nan = float32_maybe_silence_nan(f32);
7134 }
7135 if (s->default_nan_mode) {
7136 nan = float32_default_nan;
7137 }
7138 return nan;
7139 } else if (float32_is_zero(f32)) {
7140 float_raise(float_flag_divbyzero, s);
7141 return float32_set_sign(float32_infinity, float32_is_neg(f32));
7142 } else if (float32_is_neg(f32)) {
7143 float_raise(float_flag_invalid, s);
7144 return float32_default_nan;
7145 } else if (float32_is_infinity(f32)) {
7146 return float32_zero;
7147 }
7148
7149 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7150 * preserving the parity of the exponent. */
7151
7152 f64_frac = ((uint64_t) f32_frac) << 29;
7153 if (f32_exp == 0) {
7154 while (extract64(f64_frac, 51, 1) == 0) {
7155 f64_frac = f64_frac << 1;
7156 f32_exp = f32_exp-1;
7157 }
7158 f64_frac = extract64(f64_frac, 0, 51) << 1;
7159 }
7160
7161 if (extract64(f32_exp, 0, 1) == 0) {
7162 f64 = make_float64(((uint64_t) f32_sbit) << 32
7163 | (0x3feULL << 52)
7164 | f64_frac);
7165 } else {
7166 f64 = make_float64(((uint64_t) f32_sbit) << 32
7167 | (0x3fdULL << 52)
7168 | f64_frac);
7169 }
7170
7171 result_exp = (380 - f32_exp) / 2;
7172
7173 f64 = recip_sqrt_estimate(f64, s);
7174
7175 val64 = float64_val(f64);
7176
7177 val = ((result_exp & 0xff) << 23)
7178 | ((val64 >> 29) & 0x7fffff);
7179 return make_float32(val);
7180 }
7181
7182 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
7183 {
7184 float_status *s = fpstp;
7185 float64 f64 = float64_squash_input_denormal(input, s);
7186 uint64_t val = float64_val(f64);
7187 uint64_t f64_sbit = 0x8000000000000000ULL & val;
7188 int64_t f64_exp = extract64(val, 52, 11);
7189 uint64_t f64_frac = extract64(val, 0, 52);
7190 int64_t result_exp;
7191 uint64_t result_frac;
7192
7193 if (float64_is_any_nan(f64)) {
7194 float64 nan = f64;
7195 if (float64_is_signaling_nan(f64)) {
7196 float_raise(float_flag_invalid, s);
7197 nan = float64_maybe_silence_nan(f64);
7198 }
7199 if (s->default_nan_mode) {
7200 nan = float64_default_nan;
7201 }
7202 return nan;
7203 } else if (float64_is_zero(f64)) {
7204 float_raise(float_flag_divbyzero, s);
7205 return float64_set_sign(float64_infinity, float64_is_neg(f64));
7206 } else if (float64_is_neg(f64)) {
7207 float_raise(float_flag_invalid, s);
7208 return float64_default_nan;
7209 } else if (float64_is_infinity(f64)) {
7210 return float64_zero;
7211 }
7212
7213 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
7214 * preserving the parity of the exponent. */
7215
7216 if (f64_exp == 0) {
7217 while (extract64(f64_frac, 51, 1) == 0) {
7218 f64_frac = f64_frac << 1;
7219 f64_exp = f64_exp - 1;
7220 }
7221 f64_frac = extract64(f64_frac, 0, 51) << 1;
7222 }
7223
7224 if (extract64(f64_exp, 0, 1) == 0) {
7225 f64 = make_float64(f64_sbit
7226 | (0x3feULL << 52)
7227 | f64_frac);
7228 } else {
7229 f64 = make_float64(f64_sbit
7230 | (0x3fdULL << 52)
7231 | f64_frac);
7232 }
7233
7234 result_exp = (3068 - f64_exp) / 2;
7235
7236 f64 = recip_sqrt_estimate(f64, s);
7237
7238 result_frac = extract64(float64_val(f64), 0, 52);
7239
7240 return make_float64(f64_sbit |
7241 ((result_exp & 0x7ff) << 52) |
7242 result_frac);
7243 }
7244
7245 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
7246 {
7247 float_status *s = fpstp;
7248 float64 f64;
7249
7250 if ((a & 0x80000000) == 0) {
7251 return 0xffffffff;
7252 }
7253
7254 f64 = make_float64((0x3feULL << 52)
7255 | ((int64_t)(a & 0x7fffffff) << 21));
7256
7257 f64 = recip_estimate(f64, s);
7258
7259 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
7260 }
7261
7262 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
7263 {
7264 float_status *fpst = fpstp;
7265 float64 f64;
7266
7267 if ((a & 0xc0000000) == 0) {
7268 return 0xffffffff;
7269 }
7270
7271 if (a & 0x80000000) {
7272 f64 = make_float64((0x3feULL << 52)
7273 | ((uint64_t)(a & 0x7fffffff) << 21));
7274 } else { /* bits 31-30 == '01' */
7275 f64 = make_float64((0x3fdULL << 52)
7276 | ((uint64_t)(a & 0x3fffffff) << 22));
7277 }
7278
7279 f64 = recip_sqrt_estimate(f64, fpst);
7280
7281 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
7282 }
7283
7284 /* VFPv4 fused multiply-accumulate */
7285 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
7286 {
7287 float_status *fpst = fpstp;
7288 return float32_muladd(a, b, c, 0, fpst);
7289 }
7290
7291 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
7292 {
7293 float_status *fpst = fpstp;
7294 return float64_muladd(a, b, c, 0, fpst);
7295 }
7296
7297 /* ARMv8 round to integral */
7298 float32 HELPER(rints_exact)(float32 x, void *fp_status)
7299 {
7300 return float32_round_to_int(x, fp_status);
7301 }
7302
7303 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
7304 {
7305 return float64_round_to_int(x, fp_status);
7306 }
7307
7308 float32 HELPER(rints)(float32 x, void *fp_status)
7309 {
7310 int old_flags = get_float_exception_flags(fp_status), new_flags;
7311 float32 ret;
7312
7313 ret = float32_round_to_int(x, fp_status);
7314
7315 /* Suppress any inexact exceptions the conversion produced */
7316 if (!(old_flags & float_flag_inexact)) {
7317 new_flags = get_float_exception_flags(fp_status);
7318 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7319 }
7320
7321 return ret;
7322 }
7323
7324 float64 HELPER(rintd)(float64 x, void *fp_status)
7325 {
7326 int old_flags = get_float_exception_flags(fp_status), new_flags;
7327 float64 ret;
7328
7329 ret = float64_round_to_int(x, fp_status);
7330
7331 new_flags = get_float_exception_flags(fp_status);
7332
7333 /* Suppress any inexact exceptions the conversion produced */
7334 if (!(old_flags & float_flag_inexact)) {
7335 new_flags = get_float_exception_flags(fp_status);
7336 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
7337 }
7338
7339 return ret;
7340 }
7341
7342 /* Convert ARM rounding mode to softfloat */
7343 int arm_rmode_to_sf(int rmode)
7344 {
7345 switch (rmode) {
7346 case FPROUNDING_TIEAWAY:
7347 rmode = float_round_ties_away;
7348 break;
7349 case FPROUNDING_ODD:
7350 /* FIXME: add support for TIEAWAY and ODD */
7351 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
7352 rmode);
7353 case FPROUNDING_TIEEVEN:
7354 default:
7355 rmode = float_round_nearest_even;
7356 break;
7357 case FPROUNDING_POSINF:
7358 rmode = float_round_up;
7359 break;
7360 case FPROUNDING_NEGINF:
7361 rmode = float_round_down;
7362 break;
7363 case FPROUNDING_ZERO:
7364 rmode = float_round_to_zero;
7365 break;
7366 }
7367 return rmode;
7368 }
7369
7370 /* CRC helpers.
7371 * The upper bytes of val (above the number specified by 'bytes') must have
7372 * been zeroed out by the caller.
7373 */
7374 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
7375 {
7376 uint8_t buf[4];
7377
7378 stl_le_p(buf, val);
7379
7380 /* zlib crc32 converts the accumulator and output to one's complement. */
7381 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
7382 }
7383
7384 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
7385 {
7386 uint8_t buf[4];
7387
7388 stl_le_p(buf, val);
7389
7390 /* Linux crc32c converts the output to one's complement. */
7391 return crc32c(acc, buf, bytes) ^ 0xffffffff;
7392 }
AR7 emulation for QEMU