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ACPI: Add definitions for the SPCR table
[qemu/ar7.git] / disas / s390.c
blob974460c814d7da641af8cfe764c2f9ec4045a808
1 /* opcodes/s390-dis.c revision 1.12 */
2 /* s390-dis.c -- Disassemble S390 instructions
3 Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
4 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
5
6 This file is part of GDB, GAS and the GNU binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "qemu-common.h"
24 #include "disas/bfd.h"
25
26 /* include/opcode/s390.h revision 1.9 */
27 /* s390.h -- Header file for S390 opcode table
28 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
29 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
30
31 This file is part of BFD, the Binary File Descriptor library.
32
33 This program is free software; you can redistribute it and/or modify
34 it under the terms of the GNU General Public License as published by
35 the Free Software Foundation; either version 2 of the License, or
36 (at your option) any later version.
37
38 This program is distributed in the hope that it will be useful,
39 but WITHOUT ANY WARRANTY; without even the implied warranty of
40 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 GNU General Public License for more details.
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
46 02110-1301, USA. */
47
48 #ifndef S390_H
49 #define S390_H
50
51 /* List of instruction sets variations. */
52
53 enum s390_opcode_mode_val
54 {
55 S390_OPCODE_ESA = 0,
56 S390_OPCODE_ZARCH
57 };
58
59 enum s390_opcode_cpu_val
60 {
61 S390_OPCODE_G5 = 0,
62 S390_OPCODE_G6,
63 S390_OPCODE_Z900,
64 S390_OPCODE_Z990,
65 S390_OPCODE_Z9_109,
66 S390_OPCODE_Z9_EC,
67 S390_OPCODE_Z10
68 };
69
70 /* The opcode table is an array of struct s390_opcode. */
71
72 struct s390_opcode
73 {
74 /* The opcode name. */
75 const char * name;
76
77 /* The opcode itself. Those bits which will be filled in with
78 operands are zeroes. */
79 unsigned char opcode[6];
80
81 /* The opcode mask. This is used by the disassembler. This is a
82 mask containing ones indicating those bits which must match the
83 opcode field, and zeroes indicating those bits which need not
84 match (and are presumably filled in by operands). */
85 unsigned char mask[6];
86
87 /* The opcode length in bytes. */
88 int oplen;
89
90 /* An array of operand codes. Each code is an index into the
91 operand table. They appear in the order which the operands must
92 appear in assembly code, and are terminated by a zero. */
93 unsigned char operands[6];
94
95 /* Bitmask of execution modes this opcode is available for. */
96 unsigned int modes;
97
98 /* First cpu this opcode is available for. */
99 enum s390_opcode_cpu_val min_cpu;
100 };
101
102 /* The table itself is sorted by major opcode number, and is otherwise
103 in the order in which the disassembler should consider
104 instructions. */
105 /* QEMU: Mark these static. */
106 static const struct s390_opcode s390_opcodes[];
107 static const int s390_num_opcodes;
108
109 /* Values defined for the flags field of a struct powerpc_opcode. */
110
111 /* The operands table is an array of struct s390_operand. */
112
113 struct s390_operand
114 {
115 /* The number of bits in the operand. */
116 int bits;
117
118 /* How far the operand is left shifted in the instruction. */
119 int shift;
120
121 /* One bit syntax flags. */
122 unsigned long flags;
123 };
124
125 /* Elements in the table are retrieved by indexing with values from
126 the operands field of the powerpc_opcodes table. */
127
128 static const struct s390_operand s390_operands[];
129
130 /* Values defined for the flags field of a struct s390_operand. */
131
132 /* This operand names a register. The disassembler uses this to print
133 register names with a leading 'r'. */
134 #define S390_OPERAND_GPR 0x1
135
136 /* This operand names a floating point register. The disassembler
137 prints these with a leading 'f'. */
138 #define S390_OPERAND_FPR 0x2
139
140 /* This operand names an access register. The disassembler
141 prints these with a leading 'a'. */
142 #define S390_OPERAND_AR 0x4
143
144 /* This operand names a control register. The disassembler
145 prints these with a leading 'c'. */
146 #define S390_OPERAND_CR 0x8
147
148 /* This operand is a displacement. */
149 #define S390_OPERAND_DISP 0x10
150
151 /* This operand names a base register. */
152 #define S390_OPERAND_BASE 0x20
153
154 /* This operand names an index register, it can be skipped. */
155 #define S390_OPERAND_INDEX 0x40
156
157 /* This operand is a relative branch displacement. The disassembler
158 prints these symbolically if possible. */
159 #define S390_OPERAND_PCREL 0x80
160
161 /* This operand takes signed values. */
162 #define S390_OPERAND_SIGNED 0x100
163
164 /* This operand is a length. */
165 #define S390_OPERAND_LENGTH 0x200
166
167 /* This operand is optional. Only a single operand at the end of
168 the instruction may be optional. */
169 #define S390_OPERAND_OPTIONAL 0x400
170
171 /* QEMU-ADD */
172 /* ??? Not quite the format the assembler takes, but easy to implement
173 without recourse to the table generator. */
174 #define S390_OPERAND_CCODE 0x800
175
176 static const char s390_ccode_name[16][4] = {
177 "n", /* 0000 */
178 "o", /* 0001 */
179 "h", /* 0010 */
180 "nle", /* 0011 */
181 "l", /* 0100 */
182 "nhe", /* 0101 */
183 "lh", /* 0110 */
184 "ne", /* 0111 */
185 "e", /* 1000 */
186 "nlh", /* 1001 */
187 "he", /* 1010 */
188 "nl", /* 1011 */
189 "le", /* 1100 */
190 "nh", /* 1101 */
191 "no", /* 1110 */
192 "a" /* 1111 */
193 };
194 /* QEMU-END */
195
196 #endif /* S390_H */
197
198 static int init_flag = 0;
199 static int opc_index[256];
200
201 /* QEMU: We've disabled the architecture check below. */
202 /* static int current_arch_mask = 0; */
203
204 /* Set up index table for first opcode byte. */
205
206 static void
207 init_disasm (struct disassemble_info *info)
208 {
209 const struct s390_opcode *opcode;
210 const struct s390_opcode *opcode_end;
211
212 memset (opc_index, 0, sizeof (opc_index));
213 opcode_end = s390_opcodes + s390_num_opcodes;
214 for (opcode = s390_opcodes; opcode < opcode_end; opcode++)
215 {
216 opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes;
217 while ((opcode < opcode_end) &&
218 (opcode[1].opcode[0] == opcode->opcode[0]))
219 opcode++;
220 }
221
222 #ifdef QEMU_DISABLE
223 switch (info->mach)
224 {
225 case bfd_mach_s390_31:
226 current_arch_mask = 1 << S390_OPCODE_ESA;
227 break;
228 case bfd_mach_s390_64:
229 current_arch_mask = 1 << S390_OPCODE_ZARCH;
230 break;
231 default:
232 abort ();
233 }
234 #endif /* QEMU_DISABLE */
235
236 init_flag = 1;
237 }
238
239 /* Extracts an operand value from an instruction. */
240
241 static inline unsigned int
242 s390_extract_operand (unsigned char *insn, const struct s390_operand *operand)
243 {
244 unsigned int val;
245 int bits;
246
247 /* Extract fragments of the operand byte for byte. */
248 insn += operand->shift / 8;
249 bits = (operand->shift & 7) + operand->bits;
250 val = 0;
251 do
252 {
253 val <<= 8;
254 val |= (unsigned int) *insn++;
255 bits -= 8;
256 }
257 while (bits > 0);
258 val >>= -bits;
259 val &= ((1U << (operand->bits - 1)) << 1) - 1;
260
261 /* Check for special long displacement case. */
262 if (operand->bits == 20 && operand->shift == 20)
263 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8;
264
265 /* Sign extend value if the operand is signed or pc relative. */
266 if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
267 && (val & (1U << (operand->bits - 1))))
268 val |= (-1U << (operand->bits - 1)) << 1;
269
270 /* Double value if the operand is pc relative. */
271 if (operand->flags & S390_OPERAND_PCREL)
272 val <<= 1;
273
274 /* Length x in an instructions has real length x + 1. */
275 if (operand->flags & S390_OPERAND_LENGTH)
276 val++;
277 return val;
278 }
279
280 /* Print a S390 instruction. */
281
282 int
283 print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
284 {
285 bfd_byte buffer[6];
286 const struct s390_opcode *opcode;
287 const struct s390_opcode *opcode_end;
288 unsigned int value;
289 int status, opsize, bufsize;
290 char separator;
291
292 if (init_flag == 0)
293 init_disasm (info);
294
295 /* The output looks better if we put 6 bytes on a line. */
296 info->bytes_per_line = 6;
297
298 /* Every S390 instruction is max 6 bytes long. */
299 memset (buffer, 0, 6);
300 status = (*info->read_memory_func) (memaddr, buffer, 6, info);
301 if (status != 0)
302 {
303 for (bufsize = 0; bufsize < 6; bufsize++)
304 if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0)
305 break;
306 if (bufsize <= 0)
307 {
308 (*info->memory_error_func) (status, memaddr, info);
309 return -1;
310 }
311 /* Opsize calculation looks strange but it works
312 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
313 11xxxxxx -> 6 bytes. */
314 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
315 status = opsize > bufsize;
316 }
317 else
318 {
319 bufsize = 6;
320 opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
321 }
322
323 if (status == 0)
324 {
325 /* Find the first match in the opcode table. */
326 opcode_end = s390_opcodes + s390_num_opcodes;
327 for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
328 (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]);
329 opcode++)
330 {
331 const struct s390_operand *operand;
332 const unsigned char *opindex;
333
334 #ifdef QEMU_DISABLE
335 /* Check architecture. */
336 if (!(opcode->modes & current_arch_mask))
337 continue;
338 #endif /* QEMU_DISABLE */
339
340 /* Check signature of the opcode. */
341 if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
342 || (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
343 || (buffer[3] & opcode->mask[3]) != opcode->opcode[3]
344 || (buffer[4] & opcode->mask[4]) != opcode->opcode[4]
345 || (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
346 continue;
347
348 /* The instruction is valid. */
349 /* QEMU-MOD */
350 (*info->fprintf_func) (info->stream, "%s", opcode->name);
351
352 if (s390_operands[opcode->operands[0]].flags & S390_OPERAND_CCODE)
353 separator = 0;
354 else
355 separator = '\t';
356 /* QEMU-END */
357
358 /* Extract the operands. */
359 for (opindex = opcode->operands; *opindex != 0; opindex++)
360 {
361 unsigned int value;
362
363 operand = s390_operands + *opindex;
364 value = s390_extract_operand (buffer, operand);
365
366 if ((operand->flags & S390_OPERAND_INDEX) && value == 0)
367 continue;
368 if ((operand->flags & S390_OPERAND_BASE) &&
369 value == 0 && separator == '(')
370 {
371 separator = ',';
372 continue;
373 }
374
375 if (separator)
376 (*info->fprintf_func) (info->stream, "%c", separator);
377
378 if (operand->flags & S390_OPERAND_GPR)
379 (*info->fprintf_func) (info->stream, "%%r%i", value);
380 else if (operand->flags & S390_OPERAND_FPR)
381 (*info->fprintf_func) (info->stream, "%%f%i", value);
382 else if (operand->flags & S390_OPERAND_AR)
383 (*info->fprintf_func) (info->stream, "%%a%i", value);
384 else if (operand->flags & S390_OPERAND_CR)
385 (*info->fprintf_func) (info->stream, "%%c%i", value);
386 else if (operand->flags & S390_OPERAND_PCREL)
387 (*info->print_address_func) (memaddr + (int) value, info);
388 else if (operand->flags & S390_OPERAND_SIGNED)
389 (*info->fprintf_func) (info->stream, "%i", (int) value);
390 /* QEMU-ADD */
391 else if (operand->flags & S390_OPERAND_CCODE)
392 {
393 (*info->fprintf_func) (info->stream, "%s",
394 s390_ccode_name[(int) value]);
395 separator = '\t';
396 continue;
397 }
398 /* QEMU-END */
399 else
400 (*info->fprintf_func) (info->stream, "%u", value);
401
402 if (operand->flags & S390_OPERAND_DISP)
403 {
404 separator = '(';
405 }
406 else if (operand->flags & S390_OPERAND_BASE)
407 {
408 (*info->fprintf_func) (info->stream, ")");
409 separator = ',';
410 }
411 else
412 separator = ',';
413 }
414
415 /* Found instruction, printed it, return its size. */
416 return opsize;
417 }
418 /* No matching instruction found, fall through to hex print. */
419 }
420
421 if (bufsize >= 4)
422 {
423 value = (unsigned int) buffer[0];
424 value = (value << 8) + (unsigned int) buffer[1];
425 value = (value << 8) + (unsigned int) buffer[2];
426 value = (value << 8) + (unsigned int) buffer[3];
427 (*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
428 return 4;
429 }
430 else if (bufsize >= 2)
431 {
432 value = (unsigned int) buffer[0];
433 value = (value << 8) + (unsigned int) buffer[1];
434 (*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
435 return 2;
436 }
437 else
438 {
439 value = (unsigned int) buffer[0];
440 (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
441 return 1;
442 }
443 }
444
445 /* opcodes/s390-opc.c revision 1.16 */
446 /* s390-opc.c -- S390 opcode list
447 Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
448 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
449
450 This file is part of GDB, GAS, and the GNU binutils.
451
452 This program is free software; you can redistribute it and/or modify
453 it under the terms of the GNU General Public License as published by
454 the Free Software Foundation; either version 2 of the License, or
455 (at your option) any later version.
456
457 This program is distributed in the hope that it will be useful,
458 but WITHOUT ANY WARRANTY; without even the implied warranty of
459 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
460 GNU General Public License for more details.
461
462 You should have received a copy of the GNU General Public License
463 along with this program; if not, write to the Free Software
464 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
465 02110-1301, USA. */
466
467 /* This file holds the S390 opcode table. The opcode table
468 includes almost all of the extended instruction mnemonics. This
469 permits the disassembler to use them, and simplifies the assembler
470 logic, at the cost of increasing the table size. The table is
471 strictly constant data, so the compiler should be able to put it in
472 the .text section.
473
474 This file also holds the operand table. All knowledge about
475 inserting operands into instructions and vice-versa is kept in this
476 file. */
477
478 /* The operands table.
479 The fields are bits, shift, insert, extract, flags. */
480
481 static const struct s390_operand s390_operands[] =
482 {
483 #define UNUSED 0
484 { 0, 0, 0 }, /* Indicates the end of the operand list */
485
486 #define R_8 1 /* GPR starting at position 8 */
487 { 4, 8, S390_OPERAND_GPR },
488 #define R_12 2 /* GPR starting at position 12 */
489 { 4, 12, S390_OPERAND_GPR },
490 #define R_16 3 /* GPR starting at position 16 */
491 { 4, 16, S390_OPERAND_GPR },
492 #define R_20 4 /* GPR starting at position 20 */
493 { 4, 20, S390_OPERAND_GPR },
494 #define R_24 5 /* GPR starting at position 24 */
495 { 4, 24, S390_OPERAND_GPR },
496 #define R_28 6 /* GPR starting at position 28 */
497 { 4, 28, S390_OPERAND_GPR },
498 #define R_32 7 /* GPR starting at position 32 */
499 { 4, 32, S390_OPERAND_GPR },
500
501 #define F_8 8 /* FPR starting at position 8 */
502 { 4, 8, S390_OPERAND_FPR },
503 #define F_12 9 /* FPR starting at position 12 */
504 { 4, 12, S390_OPERAND_FPR },
505 #define F_16 10 /* FPR starting at position 16 */
506 { 4, 16, S390_OPERAND_FPR },
507 #define F_20 11 /* FPR starting at position 16 */
508 { 4, 16, S390_OPERAND_FPR },
509 #define F_24 12 /* FPR starting at position 24 */
510 { 4, 24, S390_OPERAND_FPR },
511 #define F_28 13 /* FPR starting at position 28 */
512 { 4, 28, S390_OPERAND_FPR },
513 #define F_32 14 /* FPR starting at position 32 */
514 { 4, 32, S390_OPERAND_FPR },
515
516 #define A_8 15 /* Access reg. starting at position 8 */
517 { 4, 8, S390_OPERAND_AR },
518 #define A_12 16 /* Access reg. starting at position 12 */
519 { 4, 12, S390_OPERAND_AR },
520 #define A_24 17 /* Access reg. starting at position 24 */
521 { 4, 24, S390_OPERAND_AR },
522 #define A_28 18 /* Access reg. starting at position 28 */
523 { 4, 28, S390_OPERAND_AR },
524
525 #define C_8 19 /* Control reg. starting at position 8 */
526 { 4, 8, S390_OPERAND_CR },
527 #define C_12 20 /* Control reg. starting at position 12 */
528 { 4, 12, S390_OPERAND_CR },
529
530 #define B_16 21 /* Base register starting at position 16 */
531 { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
532 #define B_32 22 /* Base register starting at position 32 */
533 { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
534
535 #define X_12 23 /* Index register starting at position 12 */
536 { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
537
538 #define D_20 24 /* Displacement starting at position 20 */
539 { 12, 20, S390_OPERAND_DISP },
540 #define D_36 25 /* Displacement starting at position 36 */
541 { 12, 36, S390_OPERAND_DISP },
542 #define D20_20 26 /* 20 bit displacement starting at 20 */
543 { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
544
545 #define L4_8 27 /* 4 bit length starting at position 8 */
546 { 4, 8, S390_OPERAND_LENGTH },
547 #define L4_12 28 /* 4 bit length starting at position 12 */
548 { 4, 12, S390_OPERAND_LENGTH },
549 #define L8_8 29 /* 8 bit length starting at position 8 */
550 { 8, 8, S390_OPERAND_LENGTH },
551
552 #define U4_8 30 /* 4 bit unsigned value starting at 8 */
553 { 4, 8, 0 },
554 #define U4_12 31 /* 4 bit unsigned value starting at 12 */
555 { 4, 12, 0 },
556 #define U4_16 32 /* 4 bit unsigned value starting at 16 */
557 { 4, 16, 0 },
558 #define U4_20 33 /* 4 bit unsigned value starting at 20 */
559 { 4, 20, 0 },
560 #define U8_8 34 /* 8 bit unsigned value starting at 8 */
561 { 8, 8, 0 },
562 #define U8_16 35 /* 8 bit unsigned value starting at 16 */
563 { 8, 16, 0 },
564 #define I16_16 36 /* 16 bit signed value starting at 16 */
565 { 16, 16, S390_OPERAND_SIGNED },
566 #define U16_16 37 /* 16 bit unsigned value starting at 16 */
567 { 16, 16, 0 },
568 #define J16_16 38 /* PC relative jump offset at 16 */
569 { 16, 16, S390_OPERAND_PCREL },
570 #define J32_16 39 /* PC relative long offset at 16 */
571 { 32, 16, S390_OPERAND_PCREL },
572 #define I32_16 40 /* 32 bit signed value starting at 16 */
573 { 32, 16, S390_OPERAND_SIGNED },
574 #define U32_16 41 /* 32 bit unsigned value starting at 16 */
575 { 32, 16, 0 },
576 #define M_16 42 /* 4 bit optional mask starting at 16 */
577 { 4, 16, S390_OPERAND_OPTIONAL },
578 #define RO_28 43 /* optional GPR starting at position 28 */
579 { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
580
581 /* QEMU-ADD: */
582 #define M4_12 44 /* 4-bit condition-code starting at 12 */
583 { 4, 12, S390_OPERAND_CCODE },
584 #define M4_32 45 /* 4-bit condition-code starting at 32 */
585 { 4, 32, S390_OPERAND_CCODE },
586 #define I8_32 46 /* 8 bit signed value starting at 32 */
587 { 8, 32, S390_OPERAND_SIGNED },
588 #define U8_24 47 /* 8 bit unsigned value starting at 24 */
589 { 8, 24, 0 },
590 #define U8_32 48 /* 8 bit unsigned value starting at 32 */
591 { 8, 32, 0 },
592 #define I16_32 49
593 { 16, 32, S390_OPERAND_SIGNED },
594 #define M4_16 50 /* 4-bit condition-code starting at 12 */
595 { 4, 16, S390_OPERAND_CCODE },
596 #define I8_16 51
597 { 8, 16, S390_OPERAND_SIGNED },
598 /* QEMU-END */
599 };
600
601
602 /* Macros used to form opcodes. */
603
604 /* 8/16/48 bit opcodes. */
605 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
606 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
607 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
608 (x >> 16) & 255, (x >> 8) & 255, x & 255}
609
610 /* The new format of the INSTR_x_y and MASK_x_y defines is based
611 on the following rules:
612 1) the middle part of the definition (x in INSTR_x_y) is the official
613 names of the instruction format that you can find in the principals
614 of operation.
615 2) the last part of the definition (y in INSTR_x_y) gives you an idea
616 which operands the binary represenation of the instruction has.
617 The meanings of the letters in y are:
618 a - access register
619 c - control register
620 d - displacement, 12 bit
621 f - floating pointer register
622 i - signed integer, 4, 8, 16 or 32 bit
623 l - length, 4 or 8 bit
624 p - pc relative
625 r - general purpose register
626 u - unsigned integer, 4, 8, 16 or 32 bit
627 m - mode field, 4 bit
628 0 - operand skipped.
629 The order of the letters reflects the layout of the format in
630 storage and not the order of the paramaters of the instructions.
631 The use of the letters is not a 100% match with the PoP but it is
632 quite close.
633
634 For example the instruction "mvo" is defined in the PoP as follows:
635
636 MVO D1(L1,B1),D2(L2,B2) [SS]
637
638 --------------------------------------
639 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
640 --------------------------------------
641 0 8 12 16 20 32 36
642
643 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
644
645 #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
646 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
647 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
648 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
649 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
650 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
651 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
652 #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
653 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
654 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
655 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
656 #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
657 #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
658 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
659 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
660 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
661 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
662 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
663 #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
664 #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
665 #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
666 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
667 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
668 /* Actually efpc and sfpc do not take an optional operand.
669 This is just a workaround for existing code e.g. glibc. */
670 #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
671 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
672 /* QEMU-MOD */
673 #define INSTR_RRF_F0FF2 4, { F_24,F_28,F_16,0,0,0 } /* e.g. cpsdr */
674 /* QEMU-END */
675 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
676 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
677 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
678 #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */
679 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
680 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
681 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
682 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
683 #define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
684 #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
685 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
686 #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
687 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
688 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
689 #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
690 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
691 #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
692 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
693 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
694 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
695 #define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */
696 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
697 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
698 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
699 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
700 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
701 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
702 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
703 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
704 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
705 #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
706 #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
707 #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
708 #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
709 #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
710 #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
711 #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
712 #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
713 #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
714 #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
715 #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
716 #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
717 #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
718 #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
719 #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
720 #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
721 #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
722 #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
723 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
724 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
725 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
726 #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
727 #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
728 #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
729
730 #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
731 #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
732 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
733 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
734 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
735 #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
736 #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
737 #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
738 #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
739 #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
740 #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
741 #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
742 #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
743 #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
744 #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
745 #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
746 #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
747 #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
748 #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
749 #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
750 #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
751 #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
752 #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
753 #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
754 #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
755 #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
756 #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
757 #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
758 #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
759 #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
760 #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
761 #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
762 #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
763 #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
764 #define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
765 #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
766 #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
767 #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
768 #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
769 #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
770 #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
771 #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
772 #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
773 #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
774 #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
775 #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
776 #define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
777 #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
778 #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
779 #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
780 #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
781 #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
782 #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
783 #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
784 #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
785 #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
786 #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
787 #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
788 #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
789 #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
790 #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
791 #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
792 #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
793 #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
794 #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
795 #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
796 #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
797 #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
798 #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
799 #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
800 #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
801 #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
802 #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
803 #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
804 #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
805 #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
806 #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
807 #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
808 #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
809 #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
810
811 /* QEMU-ADD: */
812 #define INSTR_RIE_MRRP 6, { M4_32, R_8, R_12, J16_16, 0, 0 } /* e.g. crj */
813 #define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
814
815 #define INSTR_RIE_MRIP 6, { M4_12, R_8, I8_32, J16_16, 0, 0 } /* e.g. cij */
816 #define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
817
818 #define INSTR_RIE_RRIII 6, { R_8, R_12, U8_16, U8_24, U8_32, 0 } /* risbg */
819 #define MASK_RIE_RRIII { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
820 #define INSTR_RIE_MRI 6, { M4_32, R_8, I16_16, 0, 0, 0 } /* e.g. cit */
821 #define MASK_RIE_MRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
822 #define INSTR_RIE_MRU 6, { M4_32, R_8, U16_16, 0, 0, 0 } /* e.g. clfit */
823 #define MASK_RIE_MRU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
824 #define INSTR_RIE_RRI 6, { R_8, R_12, I16_16, 0, 0, 0 }
825 #define MASK_RIE_RRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
826
827 #define INSTR_RXY_URRD 6, { U8_8, D20_20, X_12, B_16, 0, 0 }
828 #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
829
830 #define INSTR_SIL_DRI 6, { D_20, B_16, I16_32, 0, 0, 0 }
831 #define MASK_SIL_DRI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
832
833 #define INSTR_RSY_MRRD 6, { M4_12, R_8, D20_20, B_16, 0, 0 }
834 #define MASK_SRY_MRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
835
836 #define INSTR_RRF_MRR 6, { M4_16, R_24, R_28, 0, 0, 0 }
837 #define MASK_RRF_MRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
838
839 #define INSTR_SIY_DRI 6, { D20_20, B_16, I8_16, 0, 0, 0 }
840 #define MASK_SIY_DRI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
841 /* QEMU-END */
842
843 /* include "s390-opc.tab" generated from opcodes/s390-opc.txt rev 1.17 */
844 /* The opcode table. This file was generated by s390-mkopc.
845
846 The format of the opcode table is:
847
848 NAME OPCODE MASK OPERANDS
849
850 Name is the name of the instruction.
851 OPCODE is the instruction opcode.
852 MASK is the opcode mask; this is used to tell the disassembler
853 which bits in the actual opcode must match OPCODE.
854 OPERANDS is the list of operands.
855
856 The disassembler reads the table in order and prints the first
857 instruction which matches. */
858
859 static const struct s390_opcode s390_opcodes[] =
860 {
861 { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
862 { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
863 { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
864 { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
865 { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
866 { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
867 { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
868 { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
869 { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
870 { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0},
871 { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2},
872 { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0},
873 { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
874 { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
875 { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
876 { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
877 { "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
878 { "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
879 { "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
880 { "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
881 { "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
882 { "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
883 { "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
884 { "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
885 { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
886 { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
887 { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
888 { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
889 { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
890 { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
891 { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
892 { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
893 { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
894 { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
895 { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
896 { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
897 { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
898 { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
899 { "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
900 { "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
901 { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
902 { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
903 { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
904 { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
905 { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
906 { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
907 { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
908 { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
909 { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
910 { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
911 { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
912 { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
913 { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
914 { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
915 { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
916 { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
917 { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
918 { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
919 { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
920 { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
921 { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
922 { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
923 { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
924 { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
925 { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
926 { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
927 { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
928 { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
929 { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
930 /* QEMU-ADD: */
931 { "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
932 { "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
933 { "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
934 { "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
935 { "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
936 { "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
937 { "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
938 { "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
939 { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
940 { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
941 { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
942 { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
943 { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
944 { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRIII, INSTR_RIE_RRIII, 3, 6},
945 { "cit", OP48(0xec0000000072LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
946 { "cgit", OP48(0xec0000000070LL), MASK_RIE_MRI, INSTR_RIE_MRI, 3, 6},
947 { "clfit", OP48(0xec0000000073LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
948 { "clgit", OP48(0xec0000000071LL), MASK_RIE_MRU, INSTR_RIE_MRU, 3, 6},
949 { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
950 { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
951 { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
952 { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI, INSTR_RIE_RRI, 3, 6},
953 /* QEMU-END */
954 { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0},
955 { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
956 { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
957 { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
958 { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
959 { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
960 { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
961 { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
962 { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
963 { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0},
964 { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
965 { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
966 { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
967 { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
968 { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
969 { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
970 { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
971 { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
972 { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
973 { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
974 { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
975 { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
976 { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
977 { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
978 { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
979 { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
980 { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
981 { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
982 { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
983 { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
984 { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
985 { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
986 { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
987 { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
988 { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
989 { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
990 { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
991 { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
992 { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
993 { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
994 { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
995 { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
996 { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
997 { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2},
998 { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
999 { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1000 { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1001 { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1002 { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1003 { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1004 { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1005 { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1006 { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1007 { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1008 { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1009 { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1010 { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1011 { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
1012 { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
1013 /* QEMU-ADD: */
1014 { "loc", OP48(0xeb00000000f2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1015 { "locg", OP48(0xeb00000000e2LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1016 { "stoc", OP48(0xeb00000000f3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1017 { "stocg", OP48(0xeb00000000e3LL), MASK_SRY_MRRD, INSTR_RSY_MRRD, 3, 6},
1018 { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1019 { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1020 { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1021 { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 6},
1022 { "asi", OP48(0xeb000000006aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1023 { "alsi", OP48(0xeb000000006eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1024 { "agsi", OP48(0xeb000000007aLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1025 { "algsi", OP48(0xeb000000007eLL), MASK_SIY_DRI, INSTR_SIY_DRI, 3, 6},
1026 /* QEMU-END */
1027 { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1028 { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0},
1029 { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1030 { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1031 { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1032 { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1033 { "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2},
1034 { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
1035 /* QEMU-ADD: */
1036 { "mvhhi", OP16(0xe544LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1037 { "mvghi", OP16(0xe548LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1038 { "mvhi", OP16(0xe54cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1039 { "chhsi", OP16(0xe554LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1040 { "clhhsi", OP16(0xe555LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1041 { "cghsi", OP16(0xe558LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1042 { "clghsi", OP16(0xe559LL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1043 { "chsi", OP16(0xe55cLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1044 { "clfhsi", OP16(0xe55dLL), MASK_SIL_DRI, INSTR_SIL_DRI, 3, 6},
1045 /* QEMU-END */
1046 { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1047 { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1048 { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1049 { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1050 { "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1051 { "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1052 { "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1053 { "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1054 { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1055 { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1056 { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1057 { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1058 { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1059 { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1060 { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1061 { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1062 { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1063 { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1064 { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1065 { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1066 { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1067 { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1068 { "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1069 { "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1070 { "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1071 { "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1072 { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1073 { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1074 { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1075 { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1076 { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1077 { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1078 { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1079 { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1080 { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1081 { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1082 { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1083 { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1084 { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1085 { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1086 { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1087 { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1088 { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1089 { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1090 { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1091 { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1092 { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1093 { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1094 { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1095 { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1096 { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1097 { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1098 { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1099 { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1100 { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1101 { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1102 { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1103 { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1104 { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1105 { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1106 { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1107 { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1108 { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1109 { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1110 { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1111 { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1112 { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1113 { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1114 { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1115 { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1116 { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1117 { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1118 { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1119 { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1120 { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1121 { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1122 { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1123 { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
1124 { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
1125 { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1126 { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1127 { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1128 { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1129 { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1130 { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1131 { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1132 { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1133 { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1134 { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1135 { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1136 { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1137 { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1138 { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1139 { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1140 { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1141 { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1142 { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1143 { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1144 { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1145 { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1146 { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1147 { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1148 { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1149 { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1150 { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1151 { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1152 { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1153 { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1154 { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1155 { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1156 { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1157 { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1158 { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1159 { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1160 { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1161 { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1162 { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1163 { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1164 { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1165 { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1166 { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
1167 { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
1168 { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
1169 /* QEMU-ADD: */
1170 { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 3, 6},
1171 /* QEMU-END */
1172 { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1173 { "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1174 { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1175 { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1176 { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1177 { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1178 { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1179 { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1180 { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
1181 { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1182 { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1183 { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1184 { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1185 { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1186 { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1187 { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
1188 { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1189 { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
1190 { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4},
1191 /* QEMU-ADD: */
1192 { "exrl", OP16(0xc600ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1193 { "pfdrl", OP16(0xc602ll), MASK_RIL_UP, INSTR_RIL_UP, 3, 6},
1194 { "cghrl", OP16(0xc604ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1195 { "chrl", OP16(0xc605ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1196 { "clghrl", OP16(0xc606ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1197 { "clhrl", OP16(0xc607ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1198 { "cgrl", OP16(0xc608ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1199 { "clgrl", OP16(0xc60all), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1200 { "cgfrl", OP16(0xc60cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1201 { "crl", OP16(0xc60dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1202 { "clgfrl", OP16(0xc60ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1203 { "clrl", OP16(0xc60fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1204
1205 { "llhrl", OP16(0xc400ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1206 { "lghrl", OP16(0xc404ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1207 { "lhrl", OP16(0xc405ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1208 { "llghrl", OP16(0xc406ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1209 { "sthrl", OP16(0xc407ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1210 { "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1211 { "stgrl", OP16(0xc40bll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1212 { "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1213 { "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1214 { "llgfrl", OP16(0xc40ell), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1215 { "strl", OP16(0xc40fll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
1216 /* QEMU-END */
1217 { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1218 { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1219 { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1220 { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1221 { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1222 { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1223 { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1224 { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1225 { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1226 { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1227 /* QEMU-ADD: */
1228 { "msfi", OP16(0xc201ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1229 { "msgfi", OP16(0xc200ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
1230 /* QEMU-END */
1231 { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1232 { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1233 { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1234 { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1235 { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1236 { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1237 { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1238 { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1239 { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1240 { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1241 { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1242 { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1243 { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1244 { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1245 { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1246 { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1247 { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1248 { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1249 { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1250 { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1251 { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
1252 { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1253 { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1254 { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1255 { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1256 { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1257 { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1258 { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1259 { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1260 { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1261 { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
1262 { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1263 { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2},
1264 { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
1265 { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
1266 { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1267 { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1268 { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
1269 { "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1270 { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1271 { "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1272 { "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1273 { "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1274 { "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1275 { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4},
1276 { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2},
1277 { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1278 { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1279 { "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1280 { "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1281 { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1282 { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1283 { "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1284 { "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1285 { "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1286 { "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1287 { "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1288 { "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1289 { "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
1290 { "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1291 { "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3},
1292 { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1293 { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3},
1294 { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1295 { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1296 { "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1297 { "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1298 { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1299 { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1300 { "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1301 { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1302 { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1303 { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1304 { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1305 { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1306 { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1307 { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1308 { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1309 { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1310 { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1311 { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1312 { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1313 { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1314 { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1315 { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1316 { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
1317 { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
1318 { "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1319 { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1320 { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1321 { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1322 { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1323 { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1324 { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1325 { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1326 { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1327 { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1328 { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1329 { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1330 { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1331 { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1332 { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1333 { "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1334 { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1335 { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1336 { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1337 { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1338 { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1339 { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1340 { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
1341 { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1342 { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1343 { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1344 { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1345 { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1346 { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1347 /* QEMU-ADD: */
1348 { "crt", OP16(0xb972LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1349 { "cgrt", OP16(0xb960LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1350 { "clrt", OP16(0xb973LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1351 { "clgrt", OP16(0xb961LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 6},
1352 { "locr", OP16(0xb9f2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1353 { "locgr", OP16(0xb9e2LL), MASK_RRF_MRR, INSTR_RRF_MRR, 3, 6},
1354 { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 6},
1355 { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1356 { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1357 { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1358 { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1359 { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1360 { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1361 { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1362 { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1363 { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1364 { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1365 { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1366 { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1367 { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1368 { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 3, 6},
1369 /* QEMU-END */
1370 { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1371 { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
1372 { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1373 { "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1374 { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1375 { "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1376 { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1377 { "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1378 { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1379 { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1380 { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
1381 { "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
1382 { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1383 { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1384 { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1385 { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1386 { "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1387 { "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1388 { "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1389 { "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1390 { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1391 { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1392 { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1393 { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1394 { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1395 { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1396 { "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1397 { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1398 { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
1399 { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1400 { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1401 { "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1402 { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1403 { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1404 { "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1405 { "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1406 { "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1407 { "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1408 { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1409 { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1410 { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
1411 { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
1412 { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1413 { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1414 { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1415 { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
1416 { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
1417 { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1418 { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1419 { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1420 { "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1421 { "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1422 { "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1423 { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
1424 { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1425 { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1426 { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1427 { "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1428 { "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1429 { "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1430 { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1431 { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1432 { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
1433 { "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1434 { "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1435 { "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
1436 { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1437 { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1438 { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
1439 { "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1440 { "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1441 { "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
1442 { "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1443 { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5},
1444 { "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
1445 { "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1446 { "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1447 { "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1448 { "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1449 { "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1450 { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1451 { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5},
1452 { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1453 { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
1454 { "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1455 { "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1456 { "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1457 { "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1458 { "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1459 { "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1460 { "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1461 { "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1462 { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1463 { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1464 { "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1465 { "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1466 { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1467 { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
1468 { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1469 { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1470 { "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1471 { "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1472 { "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1473 { "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1474 { "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1475 { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1476 { "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
1477 { "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1478 { "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1479 { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1480 { "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1481 { "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1482 { "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1483 { "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1484 { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1485 { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1486 { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1487 { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1488 { "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1489 { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1490 { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1491 { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
1492 { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1493 { "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1494 { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1495 { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
1496 { "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1497 { "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1498 { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1499 { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1500 { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1501 { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1502 { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1503 { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1504 { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1505 { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1506 { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1507 { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1508 { "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1509 { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1510 { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1511 { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1512 { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1513 { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1514 { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1515 { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1516 { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
1517 { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1518 { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1519 { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1520 { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1521 { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1522 { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1523 { "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1524 { "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1525 { "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1526 { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1527 { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1528 { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1529 { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1530 { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
1531 /* QEMU-ADD: */
1532 { "clfebr", OP16(0xb39cLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1533 { "clfdbr", OP16(0xb39dLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1534 { "clfxbr", OP16(0xb39eLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1535 { "clgebr", OP16(0xb3acLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1536 { "clgdbr", OP16(0xb3adLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1537 { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1538 { "celfbr", OP16(0xb390LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1539 { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1540 { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1541 { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1542 { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1543 { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 3, 6},
1544 /* QEMU-END */
1545 { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1546 { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5},
1547 { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5},
1548 { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2},
1549 { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2},
1550 { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4},
1551 { "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1552 { "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1553 { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1554 { "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1555 { "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1556 { "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1557 { "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1558 { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1559 { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1560 { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1561 { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1562 { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4},
1563 { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1564 { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1565 { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1566 { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0},
1567 { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1568 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1569 { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1570 { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1571 { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1572 { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1573 { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1574 { "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1575 { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1576 { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1577 { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1578 { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1579 { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0},
1580 { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1581 { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0},
1582 { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
1583 { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1584 { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1585 { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1586 { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0},
1587 { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1588 { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1589 { "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1590 { "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1591 { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1592 { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1593 { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0},
1594 { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0},
1595 { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1596 { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1597 { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0},
1598 { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0},
1599 { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1600 { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1601 { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1602 { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1603 { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1604 { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0},
1605 { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0},
1606 { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1607 { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1608 { "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
1609 { "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0},
1610 { "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
1611 { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1612 { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1613 { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1614 { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1615 { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1616 { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1617 { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1618 { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1619 { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1620 { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
1621 { "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
1622 { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1623 { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1624 { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1625 { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1626 { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1627 { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1628 { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1629 { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0},
1630 { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0},
1631 { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
1632 { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1633 { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1634 { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1635 { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1636 { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1637 { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1638 { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1639 { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1640 { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1641 { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1642 { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1643 { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1644 { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1645 { "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1646 { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1647 { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1648 { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1649 { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1650 { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1651 { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1652 { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1653 { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1654 { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1655 { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1656 { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1657 { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1658 { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1659 { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1660 { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1661 { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1662 { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1663 { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1664 { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1665 { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1666 { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
1667 { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1668 { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1669 { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1670 { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1671 { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1672 { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1673 { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
1674 { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
1675 { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2},
1676 { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1677 { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
1678 { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0},
1679 { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1680 { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1681 { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1682 { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1683 { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1684 { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
1685 { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1686 { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1687 { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1688 { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1689 { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1690 { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1691 { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1692 { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1693 { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1694 { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1695 { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1696 { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1697 { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1698 { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1699 { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1700 { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
1701 { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1702 { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
1703 { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1704 { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1705 { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1706 { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1707 { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1708 { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1709 { "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1710 { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1711 { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
1712 { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1713 { "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1714 { "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1715 { "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1716 { "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1717 { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1718 { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1719 { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1720 { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
1721 { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1722 { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1723 { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1724 { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
1725 { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
1726 { "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1727 { "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0},
1728 { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1729 { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1730 { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1731 { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1732 { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1733 { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1734 { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1735 { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1736 { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1737 { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1738 { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1739 { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1740 { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1741 { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1742 { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1743 { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1744 { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1745 { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1746 { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1747 { "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1748 { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
1749 { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1750 { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1751 { "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1752 { "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1753 { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1754 { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1755 { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1756 { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1757 { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1758 { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1759 { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1760 { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1761 { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1762 { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1763 { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1764 { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1765 { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1766 { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1767 { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1768 { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1769 { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1770 { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1771 { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1772 { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1773 { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1774 { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1775 { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1776 { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1777 { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1778 { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1779 { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1780 { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1781 { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1782 { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1783 { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1784 { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1785 { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1786 { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1787 { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1788 { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1789 { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1790 { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1791 { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1792 { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0},
1793 { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
1794 { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1795 { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1796 { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1797 { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1798 { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1799 { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1800 { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
1801 { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1802 { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1803 { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1804 { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1805 { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1806 { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1807 { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1808 { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1809 { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1810 { "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1811 { "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1812 { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1813 { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1814 { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1815 { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1816 { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1817 { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1818 { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1819 { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1820 { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1821 { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1822 { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1823 { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1824 { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1825 { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1826 { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1827 { "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1828 { "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1829 { "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1830 { "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1831 { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1832 { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1833 { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1834 { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1835 { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
1836 { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1837 { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1838 { "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1839 { "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1840 { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1841 { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1842 { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1843 { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1844 { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1845 { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1846 { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1847 { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1848 { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1849 { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1850 { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1851 { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1852 { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1853 { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1854 { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1855 { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1856 { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1857 { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0},
1858 { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1859 { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1860 { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1861 { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1862 { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1863 { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1864 { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1865 { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1866 { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1867 { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1868 { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1869 { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1870 { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1871 { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1872 { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1873 { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1874 { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1875 { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1876 { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1877 { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1878 { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1879 { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0},
1880 { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
1881 { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1882 { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
1883 { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0},
1884 { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0},
1885 { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2},
1886 { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2},
1887 { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2},
1888 { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2},
1889 { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5},
1890 { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
1891 { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
1892 { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
1893 };
1894
1895 static const int s390_num_opcodes =
1896 sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);
AR7 emulation for QEMU