target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "cpu.h"
  27 #include "qemu/module.h"
  28 #include "hw/qdev-properties.h"
  29 #include "exec/exec-all.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 static const struct {
  33     const char *name;
  34     uint8_t version_id;
  35 } mb_cpu_lookup[] = {
  36     /* These key value are as per MBV field in PVR0 */
  37     {"5.00.a", 0x01},
  38     {"5.00.b", 0x02},
  39     {"5.00.c", 0x03},
  40     {"6.00.a", 0x04},
  41     {"6.00.b", 0x06},
  42     {"7.00.a", 0x05},
  43     {"7.00.b", 0x07},
  44     {"7.10.a", 0x08},
  45     {"7.10.b", 0x09},
  46     {"7.10.c", 0x0a},
  47     {"7.10.d", 0x0b},
  48     {"7.20.a", 0x0c},
  49     {"7.20.b", 0x0d},
  50     {"7.20.c", 0x0e},
  51     {"7.20.d", 0x0f},
  52     {"7.30.a", 0x10},
  53     {"7.30.b", 0x11},
  54     {"8.00.a", 0x12},
  55     {"8.00.b", 0x13},
  56     {"8.10.a", 0x14},
  57     {"8.20.a", 0x15},
  58     {"8.20.b", 0x16},
  59     {"8.30.a", 0x17},
  60     {"8.40.a", 0x18},
  61     {"8.40.b", 0x19},
  62     {"8.50.a", 0x1A},
  63     {"9.0", 0x1B},
  64     {"9.1", 0x1D},
  65     {"9.2", 0x1F},
  66     {"9.3", 0x20},
  67     {"9.4", 0x21},
  68     {"9.5", 0x22},
  69     {"9.6", 0x23},
  70     {"10.0", 0x24},
  71     {NULL, 0},
  72 };
  73
  74 /* If no specific version gets selected, default to the following.  */
  75 #define DEFAULT_CPU_VERSION "10.0"
  76
  77 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  78 {
  79     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  80
  81     cpu->env.pc = value;
  82     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  83     cpu->env.iflags = 0;
  84 }
  85
  86 static void mb_cpu_synchronize_from_tb(CPUState *cs,
  87                                        const TranslationBlock *tb)
  88 {
  89     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  90
  91     cpu->env.pc = tb->pc;
  92     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
  93 }
  94
  95 static bool mb_cpu_has_work(CPUState *cs)
  96 {
  97     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  98 }
  99
 100 #ifndef CONFIG_USER_ONLY
 101 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 102 {
 103     MicroBlazeCPU *cpu = opaque;
 104     CPUState *cs = CPU(cpu);
 105     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 106
 107     if (level) {
 108         cpu_interrupt(cs, type);
 109     } else {
 110         cpu_reset_interrupt(cs, type);
 111     }
 112 }
 113 #endif
 114
 115 static void mb_cpu_reset(DeviceState *dev)
 116 {
 117     CPUState *s = CPU(dev);
 118     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 119     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 120     CPUMBState *env = &cpu->env;
 121
 122     mcc->parent_reset(dev);
 123
 124     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 125     env->res_addr = RES_ADDR_NONE;
 126
 127     /* Disable stack protector.  */
 128     env->shr = ~0;
 129
 130     env->pc = cpu->cfg.base_vectors;
 131
 132 #if defined(CONFIG_USER_ONLY)
 133     /* start in user mode with interrupts enabled.  */
 134     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 135 #else
 136     mb_cpu_write_msr(env, 0);
 137     mmu_init(&env->mmu);
 138 #endif
 139 }
 140
 141 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 142 {
 143     info->mach = bfd_arch_microblaze;
 144     info->print_insn = print_insn_microblaze;
 145 }
 146
 147 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 148 {
 149     CPUState *cs = CPU(dev);
 150     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 151     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 152     uint8_t version_code = 0;
 153     const char *version;
 154     int i = 0;
 155     Error *local_err = NULL;
 156
 157     cpu_exec_realizefn(cs, &local_err);
 158     if (local_err != NULL) {
 159         error_propagate(errp, local_err);
 160         return;
 161     }
 162
 163     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 164         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 165                    cpu->cfg.addr_size);
 166         return;
 167     }
 168
 169     qemu_init_vcpu(cs);
 170
 171     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 172     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 173         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 174             version_code = mb_cpu_lookup[i].version_id;
 175             break;
 176         }
 177     }
 178
 179     if (!version_code) {
 180         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 181     }
 182
 183     cpu->cfg.pvr_regs[0] =
 184         (PVR0_USE_EXC_MASK |
 185          PVR0_USE_ICACHE_MASK |
 186          PVR0_USE_DCACHE_MASK |
 187          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 188          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 189          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 190          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 191          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 192          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 193          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 194          (version_code << PVR0_VERSION_SHIFT) |
 195          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 196          cpu->cfg.pvr_user1);
 197
 198     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
 199
 200     cpu->cfg.pvr_regs[2] =
 201         (PVR2_D_OPB_MASK |
 202          PVR2_D_LMB_MASK |
 203          PVR2_I_OPB_MASK |
 204          PVR2_I_LMB_MASK |
 205          PVR2_FPU_EXC_MASK |
 206          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 207          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 208          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 209          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 210          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 211          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 212          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 213          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 214          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
 215          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
 216          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
 217          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
 218          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
 219          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
 220
 221     cpu->cfg.pvr_regs[5] |=
 222         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
 223
 224     cpu->cfg.pvr_regs[10] =
 225         (0x0c000000 | /* Default to spartan 3a dsp family.  */
 226          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
 227
 228     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 229                              16 << 17);
 230
 231     cpu->cfg.mmu = 3;
 232     cpu->cfg.mmu_tlb_access = 3;
 233     cpu->cfg.mmu_zones = 16;
 234     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 235
 236     mcc->parent_realize(dev, errp);
 237 }
 238
 239 static void mb_cpu_initfn(Object *obj)
 240 {
 241     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 242     CPUMBState *env = &cpu->env;
 243
 244     cpu_set_cpustate_pointers(cpu);
 245
 246     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 247
 248 #ifndef CONFIG_USER_ONLY
 249     /* Inbound IRQ and FIR lines */
 250     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 251 #endif
 252 }
 253
 254 static Property mb_properties[] = {
 255     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 256     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 257                      false),
 258     /*
 259      * This is the C_ADDR_SIZE synth-time configuration option of the
 260      * MicroBlaze cores. Supported values range between 32 and 64.
 261      *
 262      * When set to > 32, 32bit MicroBlaze can emit load/stores
 263      * with extended addressing.
 264      */
 265     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 266     /* If use-fpu > 0 - FPU is enabled
 267      * If use-fpu = 2 - Floating point conversion and square root instructions
 268      *                  are enabled
 269      */
 270     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 271     /* If use-hw-mul > 0 - Multiplier is enabled
 272      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 273      */
 274     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 275     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 276     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 277     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 278     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 279     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 280     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 281                      false),
 282     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 283     /* Enables bus exceptions on failed data accesses (load/stores).  */
 284     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 285                      cfg.dopb_bus_exception, false),
 286     /* Enables bus exceptions on failed instruction fetches.  */
 287     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 288                      cfg.iopb_bus_exception, false),
 289     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 290                      cfg.illegal_opcode_exception, false),
 291     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 292                      cfg.div_zero_exception, false),
 293     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 294                      cfg.unaligned_exceptions, false),
 295     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 296                      cfg.opcode_0_illegal, false),
 297     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 298     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 299     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 300     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 301     DEFINE_PROP_END_OF_LIST(),
 302 };
 303
 304 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 305 {
 306     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 307 }
 308
 309 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 310 {
 311     DeviceClass *dc = DEVICE_CLASS(oc);
 312     CPUClass *cc = CPU_CLASS(oc);
 313     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 314
 315     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 316                                     &mcc->parent_realize);
 317     device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset);
 318
 319     cc->class_by_name = mb_cpu_class_by_name;
 320     cc->has_work = mb_cpu_has_work;
 321     cc->do_interrupt = mb_cpu_do_interrupt;
 322     cc->do_unaligned_access = mb_cpu_do_unaligned_access;
 323     cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 324     cc->dump_state = mb_cpu_dump_state;
 325     cc->set_pc = mb_cpu_set_pc;
 326     cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
 327     cc->gdb_read_register = mb_cpu_gdb_read_register;
 328     cc->gdb_write_register = mb_cpu_gdb_write_register;
 329     cc->tlb_fill = mb_cpu_tlb_fill;
 330 #ifndef CONFIG_USER_ONLY
 331     cc->do_transaction_failed = mb_cpu_transaction_failed;
 332     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 333     dc->vmsd = &vmstate_mb_cpu;
 334 #endif
 335     device_class_set_props(dc, mb_properties);
 336     cc->gdb_num_core_regs = 32 + 27;
 337
 338     cc->disas_set_info = mb_disas_set_info;
 339     cc->tcg_initialize = mb_tcg_init;
 340 }
 341
 342 static const TypeInfo mb_cpu_type_info = {
 343     .name = TYPE_MICROBLAZE_CPU,
 344     .parent = TYPE_CPU,
 345     .instance_size = sizeof(MicroBlazeCPU),
 346     .instance_init = mb_cpu_initfn,
 347     .class_size = sizeof(MicroBlazeCPUClass),
 348     .class_init = mb_cpu_class_init,
 349 };
 350
 351 static void mb_cpu_register_types(void)
 352 {
 353     type_register_static(&mb_cpu_type_info);
 354 }
 355
 356 type_init(mb_cpu_register_types)