hw/pci-host/sabre.c

   1 /*
   2  * QEMU Ultrasparc Sabre PCI host (PBM)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  * Copyright (c) 2018 Mark Cave-Ayland
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "hw/irq.h"
  35 #include "hw/pci-bridge/simba.h"
  36 #include "hw/pci-host/sabre.h"
  37 #include "exec/address-spaces.h"
  38 #include "qapi/error.h"
  39 #include "qemu/log.h"
  40 #include "qemu/module.h"
  41 #include "sysemu/runstate.h"
  42 #include "trace.h"
  43
  44 /*
  45  * Chipset docs:
  46  * PBM: "UltraSPARC IIi User's Manual",
  47  * https://web.archive.org/web/20030403110020/http://www.sun.com/processors/manuals/805-0087.pdf
  48  */
  49
  50 #define PBM_PCI_IMR_MASK    0x7fffffff
  51 #define PBM_PCI_IMR_ENABLED 0x80000000
  52
  53 #define POR          (1U << 31)
  54 #define SOFT_POR     (1U << 30)
  55 #define SOFT_XIR     (1U << 29)
  56 #define BTN_POR      (1U << 28)
  57 #define BTN_XIR      (1U << 27)
  58 #define RESET_MASK   0xf8000000
  59 #define RESET_WCMASK 0x98000000
  60 #define RESET_WMASK  0x60000000
  61
  62 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
  63
  64 static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
  65 {
  66     trace_sabre_set_request(irq_num);
  67     s->irq_request = irq_num;
  68     qemu_set_irq(s->ivec_irqs[irq_num], 1);
  69 }
  70
  71 static inline void sabre_check_irqs(SabreState *s)
  72 {
  73     unsigned int i;
  74
  75     /* Previous request is not acknowledged, resubmit */
  76     if (s->irq_request != NO_IRQ_REQUEST) {
  77         sabre_set_request(s, s->irq_request);
  78         return;
  79     }
  80     /* no request pending */
  81     if (s->pci_irq_in == 0ULL) {
  82         return;
  83     }
  84     for (i = 0; i < 32; i++) {
  85         if (s->pci_irq_in & (1ULL << i)) {
  86             if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
  87                 sabre_set_request(s, i);
  88                 return;
  89             }
  90         }
  91     }
  92     for (i = 32; i < 64; i++) {
  93         if (s->pci_irq_in & (1ULL << i)) {
  94             if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
  95                 sabre_set_request(s, i);
  96                 break;
  97             }
  98         }
  99     }
 100 }
 101
 102 static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
 103 {
 104     trace_sabre_clear_request(irq_num);
 105     qemu_set_irq(s->ivec_irqs[irq_num], 0);
 106     s->irq_request = NO_IRQ_REQUEST;
 107 }
 108
 109 static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 110 {
 111     IOMMUState *is = opaque;
 112
 113     return &is->iommu_as;
 114 }
 115
 116 static void sabre_config_write(void *opaque, hwaddr addr,
 117                                uint64_t val, unsigned size)
 118 {
 119     SabreState *s = opaque;
 120
 121     trace_sabre_config_write(addr, val);
 122
 123     switch (addr) {
 124     case 0x30 ... 0x4f: /* DMA error registers */
 125         /* XXX: not implemented yet */
 126         break;
 127     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 128         if (addr & 4) {
 129             unsigned int ino = (addr & 0x3f) >> 3;
 130             s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 131             s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 132             if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
 133                 sabre_clear_request(s, ino);
 134             }
 135             sabre_check_irqs(s);
 136         }
 137         break;
 138     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 139         if (addr & 4) {
 140             unsigned int ino = ((addr & 0xff) >> 3);
 141             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
 142             s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 143             if ((s->irq_request == (ino | 0x20))
 144                  && !(val & ~PBM_PCI_IMR_MASK)) {
 145                 sabre_clear_request(s, ino | 0x20);
 146             }
 147             sabre_check_irqs(s);
 148         }
 149         break;
 150     case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 151         if (addr & 4) {
 152             unsigned int ino = (addr & 0xff) >> 5;
 153             if ((s->irq_request / 4)  == ino) {
 154                 sabre_clear_request(s, s->irq_request);
 155                 sabre_check_irqs(s);
 156             }
 157         }
 158         break;
 159     case 0x1800 ... 0x1860: /* OBIO interrupt clear */
 160         if (addr & 4) {
 161             unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 162             if (s->irq_request == ino) {
 163                 sabre_clear_request(s, ino);
 164                 sabre_check_irqs(s);
 165             }
 166         }
 167         break;
 168     case 0x2000 ... 0x202f: /* PCI control */
 169         s->pci_control[(addr & 0x3f) >> 2] = val;
 170         break;
 171     case 0xf020 ... 0xf027: /* Reset control */
 172         if (addr & 4) {
 173             val &= RESET_MASK;
 174             s->reset_control &= ~(val & RESET_WCMASK);
 175             s->reset_control |= val & RESET_WMASK;
 176             if (val & SOFT_POR) {
 177                 s->nr_resets = 0;
 178                 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 179             } else if (val & SOFT_XIR) {
 180                 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 181             }
 182         }
 183         break;
 184     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 185     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 186     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 187     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 188         /* we don't care */
 189     default:
 190         break;
 191     }
 192 }
 193
 194 static uint64_t sabre_config_read(void *opaque,
 195                                   hwaddr addr, unsigned size)
 196 {
 197     SabreState *s = opaque;
 198     uint32_t val = 0;
 199
 200     switch (addr) {
 201     case 0x30 ... 0x4f: /* DMA error registers */
 202         /* XXX: not implemented yet */
 203         break;
 204     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 205         if (addr & 4) {
 206             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 207         }
 208         break;
 209     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 210         if (addr & 4) {
 211             val = s->obio_irq_map[(addr & 0xff) >> 3];
 212         }
 213         break;
 214     case 0x1080 ... 0x108f: /* PCI bus error */
 215         if (addr & 4) {
 216             val = s->pci_err_irq_map[(addr & 0xf) >> 3];
 217         }
 218         break;
 219     case 0x2000 ... 0x202f: /* PCI control */
 220         val = s->pci_control[(addr & 0x3f) >> 2];
 221         break;
 222     case 0xf020 ... 0xf027: /* Reset control */
 223         if (addr & 4) {
 224             val = s->reset_control;
 225         }
 226         break;
 227     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 228     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 229     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 230     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 231         /* we don't care */
 232     default:
 233         break;
 234     }
 235     trace_sabre_config_read(addr, val);
 236
 237     return val;
 238 }
 239
 240 static const MemoryRegionOps sabre_config_ops = {
 241     .read = sabre_config_read,
 242     .write = sabre_config_write,
 243     .endianness = DEVICE_BIG_ENDIAN,
 244 };
 245
 246 static void sabre_pci_config_write(void *opaque, hwaddr addr,
 247                                    uint64_t val, unsigned size)
 248 {
 249     SabreState *s = opaque;
 250     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 251
 252     trace_sabre_pci_config_write(addr, val);
 253     pci_data_write(phb->bus, addr, val, size);
 254 }
 255
 256 static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
 257                                       unsigned size)
 258 {
 259     uint32_t ret;
 260     SabreState *s = opaque;
 261     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 262
 263     ret = pci_data_read(phb->bus, addr, size);
 264     trace_sabre_pci_config_read(addr, ret);
 265     return ret;
 266 }
 267
 268 /* The sabre host has an IRQ line for each IRQ line of each slot.  */
 269 static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
 270 {
 271     /* Return the irq as swizzled by the PBM */
 272     return irq_num;
 273 }
 274
 275 static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
 276 {
 277     /* The on-board devices have fixed (legacy) OBIO intnos */
 278     switch (PCI_SLOT(pci_dev->devfn)) {
 279     case 1:
 280         /* Onboard NIC */
 281         return OBIO_NIC_IRQ;
 282     case 3:
 283         /* Onboard IDE */
 284         return OBIO_HDD_IRQ;
 285     default:
 286         /* Normal intno, fall through */
 287         break;
 288     }
 289
 290     return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 291 }
 292
 293 static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
 294 {
 295     return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 296 }
 297
 298 static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
 299 {
 300     SabreState *s = opaque;
 301
 302     trace_sabre_pci_set_irq(irq_num, level);
 303
 304     /* PCI IRQ map onto the first 32 INO.  */
 305     if (irq_num < 32) {
 306         if (level) {
 307             s->pci_irq_in |= 1ULL << irq_num;
 308             if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 309                 sabre_set_request(s, irq_num);
 310             }
 311         } else {
 312             s->pci_irq_in &= ~(1ULL << irq_num);
 313         }
 314     } else {
 315         /* OBIO IRQ map onto the next 32 INO.  */
 316         if (level) {
 317             trace_sabre_pci_set_obio_irq(irq_num, level);
 318             s->pci_irq_in |= 1ULL << irq_num;
 319             if ((s->irq_request == NO_IRQ_REQUEST)
 320                 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
 321                 sabre_set_request(s, irq_num);
 322             }
 323         } else {
 324             s->pci_irq_in &= ~(1ULL << irq_num);
 325         }
 326     }
 327 }
 328
 329 static void sabre_reset(DeviceState *d)
 330 {
 331     SabreState *s = SABRE(d);
 332     PCIDevice *pci_dev;
 333     unsigned int i;
 334     uint16_t cmd;
 335
 336     for (i = 0; i < 8; i++) {
 337         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 338     }
 339     for (i = 0; i < 32; i++) {
 340         s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
 341     }
 342
 343     s->irq_request = NO_IRQ_REQUEST;
 344     s->pci_irq_in = 0ULL;
 345
 346     if (s->nr_resets++ == 0) {
 347         /* Power on reset */
 348         s->reset_control = POR;
 349     }
 350
 351     /* As this is the busA PCI bridge which contains the on-board devices
 352      * attached to the ebus, ensure that we initially allow IO transactions
 353      * so that we get the early serial console until OpenBIOS can properly
 354      * configure the PCI bridge itself */
 355     pci_dev = PCI_DEVICE(s->bridgeA);
 356     cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
 357     pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO);
 358     pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
 359 }
 360
 361 static const MemoryRegionOps pci_config_ops = {
 362     .read = sabre_pci_config_read,
 363     .write = sabre_pci_config_write,
 364     .endianness = DEVICE_LITTLE_ENDIAN,
 365 };
 366
 367 static void sabre_realize(DeviceState *dev, Error **errp)
 368 {
 369     SabreState *s = SABRE(dev);
 370     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 371     PCIDevice *pci_dev;
 372
 373     memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
 374     memory_region_add_subregion(get_system_memory(), s->mem_base,
 375                                 &s->pci_mmio);
 376
 377     phb->bus = pci_register_root_bus(dev, "pci",
 378                                      pci_sabre_set_irq, pci_sabre_map_irq, s,
 379                                      &s->pci_mmio,
 380                                      &s->pci_ioport,
 381                                      0, 0x40, TYPE_PCI_BUS);
 382
 383     pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
 384
 385     /* IOMMU */
 386     memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
 387                     sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
 388     pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
 389
 390     /* APB secondary busses */
 391     pci_dev = pci_new_multifunction(PCI_DEVFN(1, 0), true,
 392                                     TYPE_SIMBA_PCI_BRIDGE);
 393     s->bridgeB = PCI_BRIDGE(pci_dev);
 394     pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
 395     pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);
 396
 397     pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), true,
 398                                     TYPE_SIMBA_PCI_BRIDGE);
 399     s->bridgeA = PCI_BRIDGE(pci_dev);
 400     pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
 401     pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);
 402 }
 403
 404 static void sabre_init(Object *obj)
 405 {
 406     SabreState *s = SABRE(obj);
 407     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 408     unsigned int i;
 409
 410     for (i = 0; i < 8; i++) {
 411         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 412     }
 413     for (i = 0; i < 2; i++) {
 414         s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
 415     }
 416     for (i = 0; i < 32; i++) {
 417         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
 418     }
 419     qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
 420     qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
 421     s->irq_request = NO_IRQ_REQUEST;
 422     s->pci_irq_in = 0ULL;
 423
 424     /* IOMMU */
 425     object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU,
 426                              (Object **) &s->iommu,
 427                              qdev_prop_allow_set_link_before_realize,
 428                              0);
 429
 430     /* sabre_config */
 431     memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
 432                           "sabre-config", 0x10000);
 433     /* at region 0 */
 434     sysbus_init_mmio(sbd, &s->sabre_config);
 435
 436     memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
 437                           "sabre-pci-config", 0x1000000);
 438     /* at region 1 */
 439     sysbus_init_mmio(sbd, &s->pci_config);
 440
 441     /* pci_ioport */
 442     memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
 443                        0x1000000);
 444
 445     /* at region 2 */
 446     sysbus_init_mmio(sbd, &s->pci_ioport);
 447 }
 448
 449 static void sabre_pci_realize(PCIDevice *d, Error **errp)
 450 {
 451     pci_set_word(d->config + PCI_COMMAND,
 452                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 453     pci_set_word(d->config + PCI_STATUS,
 454                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 455                  PCI_STATUS_DEVSEL_MEDIUM);
 456 }
 457
 458 static void sabre_pci_class_init(ObjectClass *klass, void *data)
 459 {
 460     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 461     DeviceClass *dc = DEVICE_CLASS(klass);
 462
 463     k->realize = sabre_pci_realize;
 464     k->vendor_id = PCI_VENDOR_ID_SUN;
 465     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
 466     k->class_id = PCI_CLASS_BRIDGE_HOST;
 467     /*
 468      * PCI-facing part of the host bridge, not usable without the
 469      * host-facing part, which can't be device_add'ed, yet.
 470      */
 471     dc->user_creatable = false;
 472 }
 473
 474 static const TypeInfo sabre_pci_info = {
 475     .name          = TYPE_SABRE_PCI_DEVICE,
 476     .parent        = TYPE_PCI_DEVICE,
 477     .instance_size = sizeof(SabrePCIState),
 478     .class_init    = sabre_pci_class_init,
 479     .interfaces = (InterfaceInfo[]) {
 480         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 481         { },
 482     },
 483 };
 484
 485 static char *sabre_ofw_unit_address(const SysBusDevice *dev)
 486 {
 487     SabreState *s = SABRE(dev);
 488
 489     return g_strdup_printf("%x,%x",
 490                (uint32_t)((s->special_base >> 32) & 0xffffffff),
 491                (uint32_t)(s->special_base & 0xffffffff));
 492 }
 493
 494 static Property sabre_properties[] = {
 495     DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
 496     DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
 497     DEFINE_PROP_END_OF_LIST(),
 498 };
 499
 500 static void sabre_class_init(ObjectClass *klass, void *data)
 501 {
 502     DeviceClass *dc = DEVICE_CLASS(klass);
 503     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 504
 505     dc->realize = sabre_realize;
 506     dc->reset = sabre_reset;
 507     device_class_set_props(dc, sabre_properties);
 508     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 509     dc->fw_name = "pci";
 510     sbc->explicit_ofw_unit_address = sabre_ofw_unit_address;
 511 }
 512
 513 static const TypeInfo sabre_info = {
 514     .name          = TYPE_SABRE,
 515     .parent        = TYPE_PCI_HOST_BRIDGE,
 516     .instance_size = sizeof(SabreState),
 517     .instance_init = sabre_init,
 518     .class_init    = sabre_class_init,
 519 };
 520
 521 static void sabre_register_types(void)
 522 {
 523     type_register_static(&sabre_info);
 524     type_register_static(&sabre_pci_info);
 525 }
 526
 527 type_init(sabre_register_types)