hw/ppc/spapr_irq.c

   1 /*
   2  * QEMU PowerPC sPAPR IRQ interface
   3  *
   4  * Copyright (c) 2018, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "qapi/error.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_cpu_core.h"
  16 #include "hw/ppc/spapr_xive.h"
  17 #include "hw/ppc/xics.h"
  18 #include "hw/ppc/xics_spapr.h"
  19 #include "sysemu/kvm.h"
  20
  21 #include "trace.h"
  22
  23 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
  24 {
  25     spapr->irq_map_nr = nr_msis;
  26     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
  27 }
  28
  29 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
  30                         Error **errp)
  31 {
  32     int irq;
  33
  34     /*
  35      * The 'align_mask' parameter of bitmap_find_next_zero_area()
  36      * should be one less than a power of 2; 0 means no
  37      * alignment. Adapt the 'align' value of the former allocator
  38      * to fit the requirements of bitmap_find_next_zero_area()
  39      */
  40     align -= 1;
  41
  42     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
  43                                      align);
  44     if (irq == spapr->irq_map_nr) {
  45         error_setg(errp, "can't find a free %d-IRQ block", num);
  46         return -1;
  47     }
  48
  49     bitmap_set(spapr->irq_map, irq, num);
  50
  51     return irq + SPAPR_IRQ_MSI;
  52 }
  53
  54 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
  55 {
  56     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
  57 }
  58
  59 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
  60 {
  61     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
  62 }
  63
  64
  65 /*
  66  * XICS IRQ backend.
  67  */
  68
  69 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
  70                                   int nr_irqs, Error **errp)
  71 {
  72     Error *local_err = NULL;
  73     Object *obj;
  74
  75     obj = object_new(TYPE_ICS_SIMPLE);
  76     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
  77     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
  78                                    &error_abort);
  79     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
  80     if (local_err) {
  81         goto error;
  82     }
  83     object_property_set_bool(obj, true, "realized", &local_err);
  84     if (local_err) {
  85         goto error;
  86     }
  87
  88     return ICS_BASE(obj);
  89
  90 error:
  91     error_propagate(errp, local_err);
  92     return NULL;
  93 }
  94
  95 static void spapr_irq_init_xics(sPAPRMachineState *spapr, int nr_irqs,
  96                                 Error **errp)
  97 {
  98     MachineState *machine = MACHINE(spapr);
  99     Error *local_err = NULL;
 100     bool xics_kvm = false;
 101
 102     if (kvm_enabled()) {
 103         if (machine_kernel_irqchip_allowed(machine) &&
 104             !xics_kvm_init(spapr, &local_err)) {
 105             xics_kvm = true;
 106         }
 107         if (machine_kernel_irqchip_required(machine) && !xics_kvm) {
 108             error_prepend(&local_err,
 109                           "kernel_irqchip requested but unavailable: ");
 110             goto error;
 111         }
 112         error_free(local_err);
 113         local_err = NULL;
 114     }
 115
 116     if (!xics_kvm) {
 117         xics_spapr_init(spapr);
 118     }
 119
 120     spapr->ics = spapr_ics_create(spapr, nr_irqs, &local_err);
 121
 122 error:
 123     error_propagate(errp, local_err);
 124 }
 125
 126 #define ICS_IRQ_FREE(ics, srcno)   \
 127     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 128
 129 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
 130                                 Error **errp)
 131 {
 132     ICSState *ics = spapr->ics;
 133
 134     assert(ics);
 135
 136     if (!ics_valid_irq(ics, irq)) {
 137         error_setg(errp, "IRQ %d is invalid", irq);
 138         return -1;
 139     }
 140
 141     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
 142         error_setg(errp, "IRQ %d is not free", irq);
 143         return -1;
 144     }
 145
 146     ics_set_irq_type(ics, irq - ics->offset, lsi);
 147     return 0;
 148 }
 149
 150 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
 151 {
 152     ICSState *ics = spapr->ics;
 153     uint32_t srcno = irq - ics->offset;
 154     int i;
 155
 156     if (ics_valid_irq(ics, irq)) {
 157         trace_spapr_irq_free(0, irq, num);
 158         for (i = srcno; i < srcno + num; ++i) {
 159             if (ICS_IRQ_FREE(ics, i)) {
 160                 trace_spapr_irq_free_warn(0, i);
 161             }
 162             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 163         }
 164     }
 165 }
 166
 167 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
 168 {
 169     ICSState *ics = spapr->ics;
 170     uint32_t srcno = irq - ics->offset;
 171
 172     if (ics_valid_irq(ics, irq)) {
 173         return spapr->qirqs[srcno];
 174     }
 175
 176     return NULL;
 177 }
 178
 179 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
 180 {
 181     CPUState *cs;
 182
 183     CPU_FOREACH(cs) {
 184         PowerPCCPU *cpu = POWERPC_CPU(cs);
 185
 186         icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
 187     }
 188
 189     ics_pic_print_info(spapr->ics, mon);
 190 }
 191
 192 static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
 193                                            PowerPCCPU *cpu, Error **errp)
 194 {
 195     Error *local_err = NULL;
 196     Object *obj;
 197     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
 198
 199     obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr),
 200                      &local_err);
 201     if (local_err) {
 202         error_propagate(errp, local_err);
 203         return;
 204     }
 205
 206     spapr_cpu->icp = ICP(obj);
 207 }
 208
 209 static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
 210 {
 211     if (!kvm_irqchip_in_kernel()) {
 212         CPUState *cs;
 213         CPU_FOREACH(cs) {
 214             PowerPCCPU *cpu = POWERPC_CPU(cs);
 215             icp_resend(spapr_cpu_state(cpu)->icp);
 216         }
 217     }
 218     return 0;
 219 }
 220
 221 static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
 222 {
 223     sPAPRMachineState *spapr = opaque;
 224
 225     ics_simple_set_irq(spapr->ics, srcno, val);
 226 }
 227
 228 static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp)
 229 {
 230     /* TODO: create the KVM XICS device */
 231 }
 232
 233 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
 234 #define SPAPR_IRQ_XICS_NR_MSIS     \
 235     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
 236
 237 sPAPRIrq spapr_irq_xics = {
 238     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
 239     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
 240     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 241
 242     .init        = spapr_irq_init_xics,
 243     .claim       = spapr_irq_claim_xics,
 244     .free        = spapr_irq_free_xics,
 245     .qirq        = spapr_qirq_xics,
 246     .print_info  = spapr_irq_print_info_xics,
 247     .dt_populate = spapr_dt_xics,
 248     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 249     .post_load   = spapr_irq_post_load_xics,
 250     .reset       = spapr_irq_reset_xics,
 251     .set_irq     = spapr_irq_set_irq_xics,
 252 };
 253
 254 /*
 255  * XIVE IRQ backend.
 256  */
 257 static void spapr_irq_init_xive(sPAPRMachineState *spapr, int nr_irqs,
 258                                 Error **errp)
 259 {
 260     MachineState *machine = MACHINE(spapr);
 261     uint32_t nr_servers = spapr_max_server_number(spapr);
 262     DeviceState *dev;
 263     int i;
 264
 265     /* KVM XIVE device not yet available */
 266     if (kvm_enabled()) {
 267         if (machine_kernel_irqchip_required(machine)) {
 268             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
 269             return;
 270         }
 271     }
 272
 273     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
 274     qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
 275     /*
 276      * 8 XIVE END structures per CPU. One for each available priority
 277      */
 278     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
 279     qdev_init_nofail(dev);
 280
 281     spapr->xive = SPAPR_XIVE(dev);
 282
 283     /* Enable the CPU IPIs */
 284     for (i = 0; i < nr_servers; ++i) {
 285         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
 286     }
 287
 288     spapr_xive_hcall_init(spapr);
 289 }
 290
 291 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
 292                                 Error **errp)
 293 {
 294     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
 295         error_setg(errp, "IRQ %d is invalid", irq);
 296         return -1;
 297     }
 298     return 0;
 299 }
 300
 301 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
 302 {
 303     int i;
 304
 305     for (i = irq; i < irq + num; ++i) {
 306         spapr_xive_irq_free(spapr->xive, i);
 307     }
 308 }
 309
 310 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
 311 {
 312     sPAPRXive *xive = spapr->xive;
 313
 314     if (irq >= xive->nr_irqs) {
 315         return NULL;
 316     }
 317
 318     /* The sPAPR machine/device should have claimed the IRQ before */
 319     assert(xive_eas_is_valid(&xive->eat[irq]));
 320
 321     return spapr->qirqs[irq];
 322 }
 323
 324 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
 325                                       Monitor *mon)
 326 {
 327     CPUState *cs;
 328
 329     CPU_FOREACH(cs) {
 330         PowerPCCPU *cpu = POWERPC_CPU(cs);
 331
 332         xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
 333     }
 334
 335     spapr_xive_pic_print_info(spapr->xive, mon);
 336 }
 337
 338 static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
 339                                            PowerPCCPU *cpu, Error **errp)
 340 {
 341     Error *local_err = NULL;
 342     Object *obj;
 343     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
 344
 345     obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
 346     if (local_err) {
 347         error_propagate(errp, local_err);
 348         return;
 349     }
 350
 351     spapr_cpu->tctx = XIVE_TCTX(obj);
 352
 353     /*
 354      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
 355      * don't beneficiate from the reset of the XIVE IRQ backend
 356      */
 357     spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
 358 }
 359
 360 static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
 361 {
 362     return 0;
 363 }
 364
 365 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
 366 {
 367     CPUState *cs;
 368
 369     CPU_FOREACH(cs) {
 370         PowerPCCPU *cpu = POWERPC_CPU(cs);
 371
 372         /* (TCG) Set the OS CAM line of the thread interrupt context. */
 373         spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
 374     }
 375
 376     /* Activate the XIVE MMIOs */
 377     spapr_xive_mmio_set_enabled(spapr->xive, true);
 378 }
 379
 380 static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
 381 {
 382     sPAPRMachineState *spapr = opaque;
 383
 384     xive_source_set_irq(&spapr->xive->source, srcno, val);
 385 }
 386
 387 /*
 388  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
 389  * with XICS.
 390  */
 391
 392 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
 393 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
 394
 395 sPAPRIrq spapr_irq_xive = {
 396     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
 397     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
 398     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
 399
 400     .init        = spapr_irq_init_xive,
 401     .claim       = spapr_irq_claim_xive,
 402     .free        = spapr_irq_free_xive,
 403     .qirq        = spapr_qirq_xive,
 404     .print_info  = spapr_irq_print_info_xive,
 405     .dt_populate = spapr_dt_xive,
 406     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
 407     .post_load   = spapr_irq_post_load_xive,
 408     .reset       = spapr_irq_reset_xive,
 409     .set_irq     = spapr_irq_set_irq_xive,
 410 };
 411
 412 /*
 413  * Dual XIVE and XICS IRQ backend.
 414  *
 415  * Both interrupt mode, XIVE and XICS, objects are created but the
 416  * machine starts in legacy interrupt mode (XICS). It can be changed
 417  * by the CAS negotiation process and, in that case, the new mode is
 418  * activated after an extra machine reset.
 419  */
 420
 421 /*
 422  * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
 423  * default.
 424  */
 425 static sPAPRIrq *spapr_irq_current(sPAPRMachineState *spapr)
 426 {
 427     return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
 428         &spapr_irq_xive : &spapr_irq_xics;
 429 }
 430
 431 static void spapr_irq_init_dual(sPAPRMachineState *spapr, int nr_irqs,
 432                                 Error **errp)
 433 {
 434     MachineState *machine = MACHINE(spapr);
 435     Error *local_err = NULL;
 436
 437     if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
 438         error_setg(errp, "No KVM support for the 'dual' machine");
 439         return;
 440     }
 441
 442     spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
 443     if (local_err) {
 444         error_propagate(errp, local_err);
 445         return;
 446     }
 447
 448     spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
 449     if (local_err) {
 450         error_propagate(errp, local_err);
 451         return;
 452     }
 453 }
 454
 455 static int spapr_irq_claim_dual(sPAPRMachineState *spapr, int irq, bool lsi,
 456                                 Error **errp)
 457 {
 458     Error *local_err = NULL;
 459     int ret;
 460
 461     ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err);
 462     if (local_err) {
 463         error_propagate(errp, local_err);
 464         return ret;
 465     }
 466
 467     ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err);
 468     if (local_err) {
 469         error_propagate(errp, local_err);
 470         return ret;
 471     }
 472
 473     return ret;
 474 }
 475
 476 static void spapr_irq_free_dual(sPAPRMachineState *spapr, int irq, int num)
 477 {
 478     spapr_irq_xics.free(spapr, irq, num);
 479     spapr_irq_xive.free(spapr, irq, num);
 480 }
 481
 482 static qemu_irq spapr_qirq_dual(sPAPRMachineState *spapr, int irq)
 483 {
 484     return spapr_irq_current(spapr)->qirq(spapr, irq);
 485 }
 486
 487 static void spapr_irq_print_info_dual(sPAPRMachineState *spapr, Monitor *mon)
 488 {
 489     spapr_irq_current(spapr)->print_info(spapr, mon);
 490 }
 491
 492 static void spapr_irq_dt_populate_dual(sPAPRMachineState *spapr,
 493                                        uint32_t nr_servers, void *fdt,
 494                                        uint32_t phandle)
 495 {
 496     spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle);
 497 }
 498
 499 static void spapr_irq_cpu_intc_create_dual(sPAPRMachineState *spapr,
 500                                            PowerPCCPU *cpu, Error **errp)
 501 {
 502     Error *local_err = NULL;
 503
 504     spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err);
 505     if (local_err) {
 506         error_propagate(errp, local_err);
 507         return;
 508     }
 509
 510     spapr_irq_xics.cpu_intc_create(spapr, cpu, errp);
 511 }
 512
 513 static int spapr_irq_post_load_dual(sPAPRMachineState *spapr, int version_id)
 514 {
 515     /*
 516      * Force a reset of the XIVE backend after migration. The machine
 517      * defaults to XICS at startup.
 518      */
 519     if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
 520         spapr_irq_xive.reset(spapr, &error_fatal);
 521     }
 522
 523     return spapr_irq_current(spapr)->post_load(spapr, version_id);
 524 }
 525
 526 static void spapr_irq_reset_dual(sPAPRMachineState *spapr, Error **errp)
 527 {
 528     /*
 529      * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
 530      * if selected.
 531      */
 532     spapr_xive_mmio_set_enabled(spapr->xive, false);
 533
 534     spapr_irq_current(spapr)->reset(spapr, errp);
 535 }
 536
 537 static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val)
 538 {
 539     sPAPRMachineState *spapr = opaque;
 540
 541     spapr_irq_current(spapr)->set_irq(spapr, srcno, val);
 542 }
 543
 544 /*
 545  * Define values in sync with the XIVE and XICS backend
 546  */
 547 #define SPAPR_IRQ_DUAL_NR_IRQS     0x2000
 548 #define SPAPR_IRQ_DUAL_NR_MSIS     (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
 549
 550 sPAPRIrq spapr_irq_dual = {
 551     .nr_irqs     = SPAPR_IRQ_DUAL_NR_IRQS,
 552     .nr_msis     = SPAPR_IRQ_DUAL_NR_MSIS,
 553     .ov5         = SPAPR_OV5_XIVE_BOTH,
 554
 555     .init        = spapr_irq_init_dual,
 556     .claim       = spapr_irq_claim_dual,
 557     .free        = spapr_irq_free_dual,
 558     .qirq        = spapr_qirq_dual,
 559     .print_info  = spapr_irq_print_info_dual,
 560     .dt_populate = spapr_irq_dt_populate_dual,
 561     .cpu_intc_create = spapr_irq_cpu_intc_create_dual,
 562     .post_load   = spapr_irq_post_load_dual,
 563     .reset       = spapr_irq_reset_dual,
 564     .set_irq     = spapr_irq_set_irq_dual
 565 };
 566
 567 /*
 568  * sPAPR IRQ frontend routines for devices
 569  */
 570 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
 571 {
 572     MachineState *machine = MACHINE(spapr);
 573
 574     if (machine_kernel_irqchip_split(machine)) {
 575         error_setg(errp, "kernel_irqchip split mode not supported on pseries");
 576         return;
 577     }
 578
 579     if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) {
 580         error_setg(errp,
 581                    "kernel_irqchip requested but only available with KVM");
 582         return;
 583     }
 584
 585     /* Initialize the MSI IRQ allocator. */
 586     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
 587         spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
 588     }
 589
 590     spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
 591
 592     spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
 593                                       spapr->irq->nr_irqs);
 594 }
 595
 596 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
 597 {
 598     return spapr->irq->claim(spapr, irq, lsi, errp);
 599 }
 600
 601 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
 602 {
 603     spapr->irq->free(spapr, irq, num);
 604 }
 605
 606 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
 607 {
 608     return spapr->irq->qirq(spapr, irq);
 609 }
 610
 611 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
 612 {
 613     return spapr->irq->post_load(spapr, version_id);
 614 }
 615
 616 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
 617 {
 618     if (spapr->irq->reset) {
 619         spapr->irq->reset(spapr, errp);
 620     }
 621 }
 622
 623 /*
 624  * XICS legacy routines - to deprecate one day
 625  */
 626
 627 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 628 {
 629     int first, i;
 630
 631     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 632         if (num > (ics->nr_irqs - first)) {
 633             return -1;
 634         }
 635         for (i = first; i < first + num; ++i) {
 636             if (!ICS_IRQ_FREE(ics, i)) {
 637                 break;
 638             }
 639         }
 640         if (i == (first + num)) {
 641             return first;
 642         }
 643     }
 644
 645     return -1;
 646 }
 647
 648 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
 649 {
 650     ICSState *ics = spapr->ics;
 651     int first = -1;
 652
 653     assert(ics);
 654
 655     /*
 656      * MSIMesage::data is used for storing VIRQ so
 657      * it has to be aligned to num to support multiple
 658      * MSI vectors. MSI-X is not affected by this.
 659      * The hint is used for the first IRQ, the rest should
 660      * be allocated continuously.
 661      */
 662     if (align) {
 663         assert((num == 1) || (num == 2) || (num == 4) ||
 664                (num == 8) || (num == 16) || (num == 32));
 665         first = ics_find_free_block(ics, num, num);
 666     } else {
 667         first = ics_find_free_block(ics, num, 1);
 668     }
 669
 670     if (first < 0) {
 671         error_setg(errp, "can't find a free %d-IRQ block", num);
 672         return -1;
 673     }
 674
 675     return first + ics->offset;
 676 }
 677
 678 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
 679
 680 sPAPRIrq spapr_irq_xics_legacy = {
 681     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 682     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 683     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 684
 685     .init        = spapr_irq_init_xics,
 686     .claim       = spapr_irq_claim_xics,
 687     .free        = spapr_irq_free_xics,
 688     .qirq        = spapr_qirq_xics,
 689     .print_info  = spapr_irq_print_info_xics,
 690     .dt_populate = spapr_dt_xics,
 691     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 692     .post_load   = spapr_irq_post_load_xics,
 693     .set_irq     = spapr_irq_set_irq_xics,
 694 };