target-cris/mmu.c

   1 /*
   2  *  CRIS mmu emulation.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "mmu.h"
  24
  25 #ifdef DEBUG
  26 #define D(x) x
  27 #define D_LOG(...) qemu_log(__VA_ARGS__)
  28 #else
  29 #define D(x) do { } while (0)
  30 #define D_LOG(...) do { } while (0)
  31 #endif
  32
  33 void cris_mmu_init(CPUCRISState *env)
  34 {
  35         env->mmu_rand_lfsr = 0xcccc;
  36 }
  37
  38 #define SR_POLYNOM 0x8805
  39 static inline unsigned int compute_polynom(unsigned int sr)
  40 {
  41         unsigned int i;
  42         unsigned int f;
  43
  44         f = 0;
  45         for (i = 0; i < 16; i++)
  46                 f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
  47
  48         return f;
  49 }
  50
  51 static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
  52 {
  53         unsigned int f;
  54
  55         /* Update lfsr at every fault.  */
  56         f = compute_polynom(env->mmu_rand_lfsr);
  57         env->mmu_rand_lfsr >>= 1;
  58         env->mmu_rand_lfsr |= (f << 15);
  59         env->mmu_rand_lfsr &= 0xffff;
  60 }
  61
  62 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
  63 {
  64         return (rw_gc_cfg & 12) != 0;
  65 }
  66
  67 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
  68 {
  69         return (1 << seg) & rw_mm_cfg;
  70 }
  71
  72 static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
  73 {
  74         uint32_t base;
  75         int i;
  76
  77         if (seg < 8)
  78                 base = env->sregs[SFR_RW_MM_KBASE_LO];
  79         else
  80                 base = env->sregs[SFR_RW_MM_KBASE_HI];
  81
  82         i = seg & 7;
  83         base >>= i * 4;
  84         base &= 15;
  85
  86         base <<= 28;
  87         return base;
  88 }
  89 /* Used by the tlb decoder.  */
  90 #define EXTRACT_FIELD(src, start, end) \
  91             (((src) >> start) & ((1 << (end - start + 1)) - 1))
  92
  93 static inline void set_field(uint32_t *dst, unsigned int val,
  94                              unsigned int offset, unsigned int width)
  95 {
  96         uint32_t mask;
  97
  98         mask = (1 << width) - 1;
  99         mask <<= offset;
 100         val <<= offset;
 101
 102         val &= mask;
 103         *dst &= ~(mask);
 104         *dst |= val;
 105 }
 106
 107 #ifdef DEBUG
 108 static void dump_tlb(CPUCRISState *env, int mmu)
 109 {
 110         int set;
 111         int idx;
 112         uint32_t hi, lo, tlb_vpn, tlb_pfn;
 113
 114         for (set = 0; set < 4; set++) {
 115                 for (idx = 0; idx < 16; idx++) {
 116                         lo = env->tlbsets[mmu][set][idx].lo;
 117                         hi = env->tlbsets[mmu][set][idx].hi;
 118                         tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
 119                         tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 120
 121                         printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
 122                                         set, idx, hi, lo, tlb_vpn, tlb_pfn);
 123                 }
 124         }
 125 }
 126 #endif
 127
 128 /* rw 0 = read, 1 = write, 2 = exec.  */
 129 static int cris_mmu_translate_page(struct cris_mmu_result *res,
 130                                    CPUCRISState *env, uint32_t vaddr,
 131                                    int rw, int usermode, int debug)
 132 {
 133         unsigned int vpage;
 134         unsigned int idx;
 135         uint32_t pid, lo, hi;
 136         uint32_t tlb_vpn, tlb_pfn = 0;
 137         int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
 138         int cfg_v, cfg_k, cfg_w, cfg_x;
 139         int set, match = 0;
 140         uint32_t r_cause;
 141         uint32_t r_cfg;
 142         int rwcause;
 143         int mmu = 1; /* Data mmu is default.  */
 144         int vect_base;
 145
 146         r_cause = env->sregs[SFR_R_MM_CAUSE];
 147         r_cfg = env->sregs[SFR_RW_MM_CFG];
 148         pid = env->pregs[PR_PID] & 0xff;
 149
 150         switch (rw) {
 151                 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
 152                 case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
 153                 default:
 154                 case 0: rwcause = CRIS_MMU_ERR_READ; break;
 155         }
 156
 157         /* I exception vectors 4 - 7, D 8 - 11.  */
 158         vect_base = (mmu + 1) * 4;
 159
 160         vpage = vaddr >> 13;
 161
 162         /* We know the index which to check on each set.
 163            Scan both I and D.  */
 164 #if 0
 165         for (set = 0; set < 4; set++) {
 166                 for (idx = 0; idx < 16; idx++) {
 167                         lo = env->tlbsets[mmu][set][idx].lo;
 168                         hi = env->tlbsets[mmu][set][idx].hi;
 169                         tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
 170                         tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 171
 172                         printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
 173                                         set, idx, hi, lo, tlb_vpn, tlb_pfn);
 174                 }
 175         }
 176 #endif
 177
 178         idx = vpage & 15;
 179         for (set = 0; set < 4; set++)
 180         {
 181                 lo = env->tlbsets[mmu][set][idx].lo;
 182                 hi = env->tlbsets[mmu][set][idx].hi;
 183
 184                 tlb_vpn = hi >> 13;
 185                 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
 186                 tlb_g  = EXTRACT_FIELD(lo, 4, 4);
 187
 188                 D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
 189                          mmu, set, idx, tlb_vpn, vpage, lo, hi);
 190                 if ((tlb_g || (tlb_pid == pid))
 191                     && tlb_vpn == vpage) {
 192                         match = 1;
 193                         break;
 194                 }
 195         }
 196
 197         res->bf_vec = vect_base;
 198         if (match) {
 199                 cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
 200                 cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
 201                 cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
 202                 cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);
 203
 204                 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 205                 tlb_v = EXTRACT_FIELD(lo, 3, 3);
 206                 tlb_k = EXTRACT_FIELD(lo, 2, 2);
 207                 tlb_w = EXTRACT_FIELD(lo, 1, 1);
 208                 tlb_x = EXTRACT_FIELD(lo, 0, 0);
 209
 210                 /*
 211                 set_exception_vector(0x04, i_mmu_refill);
 212                 set_exception_vector(0x05, i_mmu_invalid);
 213                 set_exception_vector(0x06, i_mmu_access);
 214                 set_exception_vector(0x07, i_mmu_execute);
 215                 set_exception_vector(0x08, d_mmu_refill);
 216                 set_exception_vector(0x09, d_mmu_invalid);
 217                 set_exception_vector(0x0a, d_mmu_access);
 218                 set_exception_vector(0x0b, d_mmu_write);
 219                 */
 220                 if (cfg_k && tlb_k && usermode) {
 221                         D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
 222                                   vaddr, lo, env->pc));
 223                         match = 0;
 224                         res->bf_vec = vect_base + 2;
 225                 } else if (rw == 1 && cfg_w && !tlb_w) {
 226                         D(printf ("tlb: write protected %x lo=%x pc=%x\n",
 227                                   vaddr, lo, env->pc));
 228                         match = 0;
 229                         /* write accesses never go through the I mmu.  */
 230                         res->bf_vec = vect_base + 3;
 231                 } else if (rw == 2 && cfg_x && !tlb_x) {
 232                         D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
 233                                  vaddr, lo, env->pc));
 234                         match = 0;
 235                         res->bf_vec = vect_base + 3;
 236                 } else if (cfg_v && !tlb_v) {
 237                         D(printf ("tlb: invalid %x\n", vaddr));
 238                         match = 0;
 239                         res->bf_vec = vect_base + 1;
 240                 }
 241
 242                 res->prot = 0;
 243                 if (match) {
 244                         res->prot |= PAGE_READ;
 245                         if (tlb_w)
 246                                 res->prot |= PAGE_WRITE;
 247                         if (mmu == 0 && (cfg_x || tlb_x))
 248                                 res->prot |= PAGE_EXEC;
 249                 }
 250                 else
 251                         D(dump_tlb(env, mmu));
 252         } else {
 253                 /* If refill, provide a randomized set.  */
 254                 set = env->mmu_rand_lfsr & 3;
 255         }
 256
 257         if (!match && !debug) {
 258                 cris_mmu_update_rand_lfsr(env);
 259
 260                 /* Compute index.  */
 261                 idx = vpage & 15;
 262
 263                 /* Update RW_MM_TLB_SEL.  */
 264                 env->sregs[SFR_RW_MM_TLB_SEL] = 0;
 265                 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
 266                 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
 267
 268                 /* Update RW_MM_CAUSE.  */
 269                 set_field(&r_cause, rwcause, 8, 2);
 270                 set_field(&r_cause, vpage, 13, 19);
 271                 set_field(&r_cause, pid, 0, 8);
 272                 env->sregs[SFR_R_MM_CAUSE] = r_cause;
 273                 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
 274         }
 275
 276         D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
 277                   " %x cause=%x sel=%x sp=%x %x %x\n",
 278                   __func__, rw, match, env->pc,
 279                   vaddr, vpage,
 280                   tlb_vpn, tlb_pfn, tlb_pid,
 281                   pid,
 282                   r_cause,
 283                   env->sregs[SFR_RW_MM_TLB_SEL],
 284                   env->regs[R_SP], env->pregs[PR_USP], env->ksp));
 285
 286         res->phy = tlb_pfn << TARGET_PAGE_BITS;
 287         return !match;
 288 }
 289
 290 void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
 291 {
 292     CRISCPU *cpu = cris_env_get_cpu(env);
 293         target_ulong vaddr;
 294         unsigned int idx;
 295         uint32_t lo, hi;
 296         uint32_t tlb_vpn;
 297         int tlb_pid, tlb_g, tlb_v;
 298         unsigned int set;
 299         unsigned int mmu;
 300
 301         pid &= 0xff;
 302         for (mmu = 0; mmu < 2; mmu++) {
 303                 for (set = 0; set < 4; set++)
 304                 {
 305                         for (idx = 0; idx < 16; idx++) {
 306                                 lo = env->tlbsets[mmu][set][idx].lo;
 307                                 hi = env->tlbsets[mmu][set][idx].hi;
 308
 309                                 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
 310                                 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
 311                                 tlb_g  = EXTRACT_FIELD(lo, 4, 4);
 312                                 tlb_v = EXTRACT_FIELD(lo, 3, 3);
 313
 314                                 if (tlb_v && !tlb_g && (tlb_pid == pid)) {
 315                                         vaddr = tlb_vpn << TARGET_PAGE_BITS;
 316                                         D_LOG("flush pid=%x vaddr=%x\n",
 317                                                   pid, vaddr);
 318                     tlb_flush_page(CPU(cpu), vaddr);
 319                                 }
 320                         }
 321                 }
 322         }
 323 }
 324
 325 int cris_mmu_translate(struct cris_mmu_result *res,
 326                        CPUCRISState *env, uint32_t vaddr,
 327                        int rw, int mmu_idx, int debug)
 328 {
 329         int seg;
 330         int miss = 0;
 331         int is_user = mmu_idx == MMU_USER_IDX;
 332         uint32_t old_srs;
 333
 334         old_srs= env->pregs[PR_SRS];
 335
 336         /* rw == 2 means exec, map the access to the insn mmu.  */
 337         env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
 338
 339         if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
 340                 res->phy = vaddr;
 341                 res->prot = PAGE_BITS;
 342                 goto done;
 343         }
 344
 345         seg = vaddr >> 28;
 346         if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
 347         {
 348                 uint32_t base;
 349
 350                 miss = 0;
 351                 base = cris_mmu_translate_seg(env, seg);
 352                 res->phy = base | (0x0fffffff & vaddr);
 353                 res->prot = PAGE_BITS;
 354         } else {
 355                 miss = cris_mmu_translate_page(res, env, vaddr, rw,
 356                                                is_user, debug);
 357         }
 358   done:
 359         env->pregs[PR_SRS] = old_srs;
 360         return miss;
 361 }