hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "monitor/monitor.h"
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/i386/ioapic.h"
  27 #include "hw/i386/ioapic_internal.h"
  28
  29 //#define DEBUG_IOAPIC
  30
  31 #ifdef DEBUG_IOAPIC
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  39
  40 /* global variable from ioapic_common.c */
  41 extern int ioapic_no;
  42
  43 static void ioapic_service(IOAPICCommonState *s)
  44 {
  45     uint8_t i;
  46     uint8_t trig_mode;
  47     uint8_t vector;
  48     uint8_t delivery_mode;
  49     uint32_t mask;
  50     uint64_t entry;
  51     uint8_t dest;
  52     uint8_t dest_mode;
  53
  54     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  55         mask = 1 << i;
  56         if (s->irr & mask) {
  57             entry = s->ioredtbl[i];
  58             if (!(entry & IOAPIC_LVT_MASKED)) {
  59                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
  60                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
  61                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  62                 delivery_mode =
  63                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
  64                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  65                     s->irr &= ~mask;
  66                 } else {
  67                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
  68                 }
  69                 if (delivery_mode == IOAPIC_DM_EXTINT) {
  70                     vector = pic_read_irq(isa_pic);
  71                 } else {
  72                     vector = entry & IOAPIC_VECTOR_MASK;
  73                 }
  74                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  75                                  vector, trig_mode);
  76             }
  77         }
  78     }
  79 }
  80
  81 static void ioapic_set_irq(void *opaque, int vector, int level)
  82 {
  83     IOAPICCommonState *s = opaque;
  84
  85     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
  86      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
  87      * the cleanest way of doing it but it should work. */
  88
  89     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
  90     if (vector == 0) {
  91         vector = 2;
  92     }
  93     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
  94         uint32_t mask = 1 << vector;
  95         uint64_t entry = s->ioredtbl[vector];
  96
  97         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
  98             IOAPIC_TRIGGER_LEVEL) {
  99             /* level triggered */
 100             if (level) {
 101                 s->irr |= mask;
 102                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 103                     ioapic_service(s);
 104                 }
 105             } else {
 106                 s->irr &= ~mask;
 107             }
 108         } else {
 109             /* According to the 82093AA manual, we must ignore edge requests
 110              * if the input pin is masked. */
 111             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 112                 s->irr |= mask;
 113                 ioapic_service(s);
 114             }
 115         }
 116     }
 117 }
 118
 119 void ioapic_eoi_broadcast(int vector)
 120 {
 121     IOAPICCommonState *s;
 122     uint64_t entry;
 123     int i, n;
 124
 125     for (i = 0; i < MAX_IOAPICS; i++) {
 126         s = ioapics[i];
 127         if (!s) {
 128             continue;
 129         }
 130         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 131             entry = s->ioredtbl[n];
 132             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 133                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 134                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 135                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 136                     ioapic_service(s);
 137                 }
 138             }
 139         }
 140     }
 141 }
 142
 143 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 144 {
 145     int i;
 146
 147     for (i = 0; i < MAX_IOAPICS; i++) {
 148         if (ioapics[i] != 0) {
 149             ioapic_print_redtbl(mon, ioapics[i]);
 150         }
 151     }
 152 }
 153
 154 static uint64_t
 155 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 156 {
 157     IOAPICCommonState *s = opaque;
 158     int index;
 159     uint32_t val = 0;
 160
 161     switch (addr & 0xff) {
 162     case IOAPIC_IOREGSEL:
 163         val = s->ioregsel;
 164         break;
 165     case IOAPIC_IOWIN:
 166         if (size != 4) {
 167             break;
 168         }
 169         switch (s->ioregsel) {
 170         case IOAPIC_REG_ID:
 171         case IOAPIC_REG_ARB:
 172             val = s->id << IOAPIC_ID_SHIFT;
 173             break;
 174         case IOAPIC_REG_VER:
 175             val = IOAPIC_VERSION |
 176                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 177             break;
 178         default:
 179             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 180             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 181                 if (s->ioregsel & 1) {
 182                     val = s->ioredtbl[index] >> 32;
 183                 } else {
 184                     val = s->ioredtbl[index] & 0xffffffff;
 185                 }
 186             }
 187         }
 188         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 189         break;
 190     }
 191     return val;
 192 }
 193
 194 static void
 195 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 196                  unsigned int size)
 197 {
 198     IOAPICCommonState *s = opaque;
 199     int index;
 200
 201     switch (addr & 0xff) {
 202     case IOAPIC_IOREGSEL:
 203         s->ioregsel = val;
 204         break;
 205     case IOAPIC_IOWIN:
 206         if (size != 4) {
 207             break;
 208         }
 209         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 210         switch (s->ioregsel) {
 211         case IOAPIC_REG_ID:
 212             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 213             break;
 214         case IOAPIC_REG_VER:
 215         case IOAPIC_REG_ARB:
 216             break;
 217         default:
 218             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 219             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 220                 if (s->ioregsel & 1) {
 221                     s->ioredtbl[index] &= 0xffffffff;
 222                     s->ioredtbl[index] |= (uint64_t)val << 32;
 223                 } else {
 224                     s->ioredtbl[index] &= ~0xffffffffULL;
 225                     s->ioredtbl[index] |= val;
 226                 }
 227                 ioapic_service(s);
 228             }
 229         }
 230         break;
 231     }
 232 }
 233
 234 static const MemoryRegionOps ioapic_io_ops = {
 235     .read = ioapic_mem_read,
 236     .write = ioapic_mem_write,
 237     .endianness = DEVICE_NATIVE_ENDIAN,
 238 };
 239
 240 static void ioapic_realize(DeviceState *dev, Error **errp)
 241 {
 242     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 243
 244     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 245                           "ioapic", 0x1000);
 246
 247     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 248
 249     ioapics[ioapic_no] = s;
 250 }
 251
 252 static void ioapic_class_init(ObjectClass *klass, void *data)
 253 {
 254     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 255     DeviceClass *dc = DEVICE_CLASS(klass);
 256
 257     k->realize = ioapic_realize;
 258     dc->reset = ioapic_reset_common;
 259 }
 260
 261 static const TypeInfo ioapic_info = {
 262     .name          = "ioapic",
 263     .parent        = TYPE_IOAPIC_COMMON,
 264     .instance_size = sizeof(IOAPICCommonState),
 265     .class_init    = ioapic_class_init,
 266 };
 267
 268 static void ioapic_register_types(void)
 269 {
 270     type_register_static(&ioapic_info);
 271 }
 272
 273 type_init(ioapic_register_types)