2 * i.MX31 Vectored Interrupt Controller
4 * Note this is NOT the PL192 provided by ARM, but
5 * a custom implementation by Freescale.
7 * Copyright (c) 2008 OKL
8 * Copyright (c) 2011 NICTA Pty Ltd
9 * Originally written by Hans Jiang
10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
12 * This code is licensed under the GPL version 2 or later. See
13 * the COPYING file in the top-level directory.
15 * TODO: implement vectors.
18 #include "hw/intc/imx_avic.h"
20 #ifndef DEBUG_IMX_AVIC
21 #define DEBUG_IMX_AVIC 0
24 #define DPRINTF(fmt, args...) \
26 if (DEBUG_IMX_AVIC) { \
27 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_AVIC, \
32 static const VMStateDescription vmstate_imx_avic
= {
33 .name
= TYPE_IMX_AVIC
,
35 .minimum_version_id
= 1,
36 .fields
= (VMStateField
[]) {
37 VMSTATE_UINT64(pending
, IMXAVICState
),
38 VMSTATE_UINT64(enabled
, IMXAVICState
),
39 VMSTATE_UINT64(is_fiq
, IMXAVICState
),
40 VMSTATE_UINT32(intcntl
, IMXAVICState
),
41 VMSTATE_UINT32(intmask
, IMXAVICState
),
42 VMSTATE_UINT32_ARRAY(prio
, IMXAVICState
, PRIO_WORDS
),
47 static inline int imx_avic_prio(IMXAVICState
*s
, int irq
)
49 uint32_t word
= irq
/ PRIO_PER_WORD
;
50 uint32_t part
= 4 * (irq
% PRIO_PER_WORD
);
51 return 0xf & (s
->prio
[word
] >> part
);
54 /* Update interrupts. */
55 static void imx_avic_update(IMXAVICState
*s
)
58 uint64_t new = s
->pending
& s
->enabled
;
61 flags
= new & s
->is_fiq
;
62 qemu_set_irq(s
->fiq
, !!flags
);
64 flags
= new & ~s
->is_fiq
;
65 if (!flags
|| (s
->intmask
== 0x1f)) {
66 qemu_set_irq(s
->irq
, !!flags
);
71 * Take interrupt if there's a pending interrupt with
72 * priority higher than the value of intmask
74 for (i
= 0; i
< IMX_AVIC_NUM_IRQS
; i
++) {
75 if (flags
& (1UL << i
)) {
76 if (imx_avic_prio(s
, i
) > s
->intmask
) {
77 qemu_set_irq(s
->irq
, 1);
82 qemu_set_irq(s
->irq
, 0);
85 static void imx_avic_set_irq(void *opaque
, int irq
, int level
)
87 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
90 DPRINTF("Raising IRQ %d, prio %d\n",
91 irq
, imx_avic_prio(s
, irq
));
92 s
->pending
|= (1ULL << irq
);
94 DPRINTF("Clearing IRQ %d, prio %d\n",
95 irq
, imx_avic_prio(s
, irq
));
96 s
->pending
&= ~(1ULL << irq
);
103 static uint64_t imx_avic_read(void *opaque
,
104 hwaddr offset
, unsigned size
)
106 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
108 DPRINTF("read(offset = 0x%" HWADDR_PRIx
")\n", offset
);
110 switch (offset
>> 2) {
111 case 0: /* INTCNTL */
114 case 1: /* Normal Interrupt Mask Register, NIMASK */
117 case 2: /* Interrupt Enable Number Register, INTENNUM */
118 case 3: /* Interrupt Disable Number Register, INTDISNUM */
121 case 4: /* Interrupt Enabled Number Register High */
122 return s
->enabled
>> 32;
124 case 5: /* Interrupt Enabled Number Register Low */
125 return s
->enabled
& 0xffffffffULL
;
127 case 6: /* Interrupt Type Register High */
128 return s
->is_fiq
>> 32;
130 case 7: /* Interrupt Type Register Low */
131 return s
->is_fiq
& 0xffffffffULL
;
133 case 8: /* Normal Interrupt Priority Register 7 */
134 case 9: /* Normal Interrupt Priority Register 6 */
135 case 10:/* Normal Interrupt Priority Register 5 */
136 case 11:/* Normal Interrupt Priority Register 4 */
137 case 12:/* Normal Interrupt Priority Register 3 */
138 case 13:/* Normal Interrupt Priority Register 2 */
139 case 14:/* Normal Interrupt Priority Register 1 */
140 case 15:/* Normal Interrupt Priority Register 0 */
141 return s
->prio
[15-(offset
>>2)];
143 case 16: /* Normal interrupt vector and status register */
146 * This returns the highest priority
147 * outstanding interrupt. Where there is more than
148 * one pending IRQ with the same priority,
149 * take the highest numbered one.
151 uint64_t flags
= s
->pending
& s
->enabled
& ~s
->is_fiq
;
155 for (i
= 63; i
>= 0; --i
) {
156 if (flags
& (1ULL<<i
)) {
157 int irq_prio
= imx_avic_prio(s
, i
);
158 if (irq_prio
> prio
) {
165 imx_avic_set_irq(s
, irq
, 0);
166 return irq
<< 16 | prio
;
168 return 0xffffffffULL
;
170 case 17:/* Fast Interrupt vector and status register */
172 uint64_t flags
= s
->pending
& s
->enabled
& s
->is_fiq
;
173 int i
= ctz64(flags
);
175 imx_avic_set_irq(opaque
, i
, 0);
178 return 0xffffffffULL
;
180 case 18:/* Interrupt source register high */
181 return s
->pending
>> 32;
183 case 19:/* Interrupt source register low */
184 return s
->pending
& 0xffffffffULL
;
186 case 20:/* Interrupt Force Register high */
187 case 21:/* Interrupt Force Register low */
190 case 22:/* Normal Interrupt Pending Register High */
191 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) >> 32;
193 case 23:/* Normal Interrupt Pending Register Low */
194 return (s
->pending
& s
->enabled
& ~s
->is_fiq
) & 0xffffffffULL
;
196 case 24: /* Fast Interrupt Pending Register High */
197 return (s
->pending
& s
->enabled
& s
->is_fiq
) >> 32;
199 case 25: /* Fast Interrupt Pending Register Low */
200 return (s
->pending
& s
->enabled
& s
->is_fiq
) & 0xffffffffULL
;
202 case 0x40: /* AVIC vector 0, use for WFI WAR */
206 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
207 HWADDR_PRIx
"\n", TYPE_IMX_AVIC
, __func__
, offset
);
212 static void imx_avic_write(void *opaque
, hwaddr offset
,
213 uint64_t val
, unsigned size
)
215 IMXAVICState
*s
= (IMXAVICState
*)opaque
;
217 /* Vector Registers not yet supported */
218 if (offset
>= 0x100 && offset
<= 0x2fc) {
219 qemu_log_mask(LOG_UNIMP
, "[%s]%s: vector %d ignored\n",
220 TYPE_IMX_AVIC
, __func__
, (int)((offset
- 0x100) >> 2));
224 DPRINTF("(0x%" HWADDR_PRIx
") = 0x%x\n", offset
, (unsigned int)val
);
226 switch (offset
>> 2) {
227 case 0: /* Interrupt Control Register, INTCNTL */
228 s
->intcntl
= val
& (ABFEN
| NIDIS
| FIDIS
| NIAD
| FIAD
| NM
);
229 if (s
->intcntl
& ABFEN
) {
230 s
->intcntl
&= ~(val
& ABFLAG
);
234 case 1: /* Normal Interrupt Mask Register, NIMASK */
235 s
->intmask
= val
& 0x1f;
238 case 2: /* Interrupt Enable Number Register, INTENNUM */
239 DPRINTF("enable(%d)\n", (int)val
);
241 s
->enabled
|= (1ULL << val
);
244 case 3: /* Interrupt Disable Number Register, INTDISNUM */
245 DPRINTF("disable(%d)\n", (int)val
);
247 s
->enabled
&= ~(1ULL << val
);
250 case 4: /* Interrupt Enable Number Register High */
251 s
->enabled
= (s
->enabled
& 0xffffffffULL
) | (val
<< 32);
254 case 5: /* Interrupt Enable Number Register Low */
255 s
->enabled
= (s
->enabled
& 0xffffffff00000000ULL
) | val
;
258 case 6: /* Interrupt Type Register High */
259 s
->is_fiq
= (s
->is_fiq
& 0xffffffffULL
) | (val
<< 32);
262 case 7: /* Interrupt Type Register Low */
263 s
->is_fiq
= (s
->is_fiq
& 0xffffffff00000000ULL
) | val
;
266 case 8: /* Normal Interrupt Priority Register 7 */
267 case 9: /* Normal Interrupt Priority Register 6 */
268 case 10:/* Normal Interrupt Priority Register 5 */
269 case 11:/* Normal Interrupt Priority Register 4 */
270 case 12:/* Normal Interrupt Priority Register 3 */
271 case 13:/* Normal Interrupt Priority Register 2 */
272 case 14:/* Normal Interrupt Priority Register 1 */
273 case 15:/* Normal Interrupt Priority Register 0 */
274 s
->prio
[15-(offset
>>2)] = val
;
277 /* Read-only registers, writes ignored */
278 case 16:/* Normal Interrupt Vector and Status register */
279 case 17:/* Fast Interrupt vector and status register */
280 case 18:/* Interrupt source register high */
281 case 19:/* Interrupt source register low */
284 case 20:/* Interrupt Force Register high */
285 s
->pending
= (s
->pending
& 0xffffffffULL
) | (val
<< 32);
288 case 21:/* Interrupt Force Register low */
289 s
->pending
= (s
->pending
& 0xffffffff00000000ULL
) | val
;
292 case 22:/* Normal Interrupt Pending Register High */
293 case 23:/* Normal Interrupt Pending Register Low */
294 case 24: /* Fast Interrupt Pending Register High */
295 case 25: /* Fast Interrupt Pending Register Low */
299 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
300 HWADDR_PRIx
"\n", TYPE_IMX_AVIC
, __func__
, offset
);
305 static const MemoryRegionOps imx_avic_ops
= {
306 .read
= imx_avic_read
,
307 .write
= imx_avic_write
,
308 .endianness
= DEVICE_NATIVE_ENDIAN
,
311 static void imx_avic_reset(DeviceState
*dev
)
313 IMXAVICState
*s
= IMX_AVIC(dev
);
320 memset(s
->prio
, 0, sizeof s
->prio
);
323 static int imx_avic_init(SysBusDevice
*sbd
)
325 DeviceState
*dev
= DEVICE(sbd
);
326 IMXAVICState
*s
= IMX_AVIC(dev
);
328 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_avic_ops
, s
,
329 TYPE_IMX_AVIC
, 0x1000);
330 sysbus_init_mmio(sbd
, &s
->iomem
);
332 qdev_init_gpio_in(dev
, imx_avic_set_irq
, IMX_AVIC_NUM_IRQS
);
333 sysbus_init_irq(sbd
, &s
->irq
);
334 sysbus_init_irq(sbd
, &s
->fiq
);
340 static void imx_avic_class_init(ObjectClass
*klass
, void *data
)
342 DeviceClass
*dc
= DEVICE_CLASS(klass
);
343 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
344 k
->init
= imx_avic_init
;
345 dc
->vmsd
= &vmstate_imx_avic
;
346 dc
->reset
= imx_avic_reset
;
347 dc
->desc
= "i.MX Advanced Vector Interrupt Controller";
350 static const TypeInfo imx_avic_info
= {
351 .name
= TYPE_IMX_AVIC
,
352 .parent
= TYPE_SYS_BUS_DEVICE
,
353 .instance_size
= sizeof(IMXAVICState
),
354 .class_init
= imx_avic_class_init
,
357 static void imx_avic_register_types(void)
359 type_register_static(&imx_avic_info
);
362 type_init(imx_avic_register_types
)