Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210619-2' into staging
[qemu/ar7.git] / target / arm / translate.h
blob2821b325e3350ee99c9d092ee9292625a44c1504
1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 #include "exec/translator.h"
5 #include "internals.h"
8 /* internal defines */
9 typedef struct DisasContext {
10 DisasContextBase base;
11 const ARMISARegisters *isar;
13 /* The address of the current instruction being translated. */
14 target_ulong pc_curr;
15 target_ulong page_start;
16 uint32_t insn;
17 /* Nonzero if this instruction has been conditionally skipped. */
18 int condjmp;
19 /* The label that will be jumped to when the instruction is skipped. */
20 TCGLabel *condlabel;
21 /* Thumb-2 conditional execution bits. */
22 int condexec_mask;
23 int condexec_cond;
24 /* M-profile ECI/ICI exception-continuable instruction state */
25 int eci;
27 * trans_ functions for insns which are continuable should set this true
28 * after decode (ie after any UNDEF checks)
30 bool eci_handled;
31 /* TCG op to rewind to if this turns out to be an invalid ECI state */
32 TCGOp *insn_eci_rewind;
33 int thumb;
34 int sctlr_b;
35 MemOp be_data;
36 #if !defined(CONFIG_USER_ONLY)
37 int user;
38 #endif
39 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
40 uint8_t tbii; /* TBI1|TBI0 for insns */
41 uint8_t tbid; /* TBI1|TBI0 for data */
42 uint8_t tcma; /* TCMA1|TCMA0 for MTE */
43 bool ns; /* Use non-secure CPREG bank on access */
44 int fp_excp_el; /* FP exception EL or 0 if enabled */
45 int sve_excp_el; /* SVE exception EL or 0 if enabled */
46 int sve_len; /* SVE vector length in bytes */
47 /* Flag indicating that exceptions from secure mode are routed to EL3. */
48 bool secure_routed_to_el3;
49 bool vfp_enabled; /* FP enabled via FPSCR.EN */
50 int vec_len;
51 int vec_stride;
52 bool v7m_handler_mode;
53 bool v8m_secure; /* true if v8M and we're in Secure mode */
54 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
55 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
56 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
57 bool v7m_lspact; /* FPCCR.LSPACT set */
58 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
59 * so that top level loop can generate correct syndrome information.
61 uint32_t svc_imm;
62 int aarch64;
63 int current_el;
64 /* Debug target exception level for single-step exceptions */
65 int debug_target_el;
66 GHashTable *cp_regs;
67 uint64_t features; /* CPU features bits */
68 /* Because unallocated encodings generate different exception syndrome
69 * information from traps due to FP being disabled, we can't do a single
70 * "is fp access disabled" check at a high level in the decode tree.
71 * To help in catching bugs where the access check was forgotten in some
72 * code path, we set this flag when the access check is done, and assert
73 * that it is set at the point where we actually touch the FP regs.
75 bool fp_access_checked;
76 bool sve_access_checked;
77 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
78 * single-step support).
80 bool ss_active;
81 bool pstate_ss;
82 /* True if the insn just emitted was a load-exclusive instruction
83 * (necessary for syndrome information for single step exceptions),
84 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
86 bool is_ldex;
87 /* True if AccType_UNPRIV should be used for LDTR et al */
88 bool unpriv;
89 /* True if v8.3-PAuth is active. */
90 bool pauth_active;
91 /* True if v8.5-MTE access to tags is enabled. */
92 bool ata;
93 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
94 bool mte_active[2];
95 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
96 bool bt;
97 /* True if any CP15 access is trapped by HSTR_EL2 */
98 bool hstr_active;
99 /* True if memory operations require alignment */
100 bool align_mem;
102 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
103 * < 0, set by the current instruction.
105 int8_t btype;
106 /* A copy of cpu->dcz_blocksize. */
107 uint8_t dcz_blocksize;
108 /* True if this page is guarded. */
109 bool guarded_page;
110 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
111 int c15_cpar;
112 /* TCG op of the current insn_start. */
113 TCGOp *insn_start;
114 #define TMP_A64_MAX 16
115 int tmp_a64_count;
116 TCGv_i64 tmp_a64[TMP_A64_MAX];
117 } DisasContext;
119 typedef struct DisasCompare {
120 TCGCond cond;
121 TCGv_i32 value;
122 bool value_global;
123 } DisasCompare;
125 /* Share the TCG temporaries common between 32 and 64 bit modes. */
126 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
127 extern TCGv_i64 cpu_exclusive_addr;
128 extern TCGv_i64 cpu_exclusive_val;
131 * Constant expanders for the decoders.
134 static inline int negate(DisasContext *s, int x)
136 return -x;
139 static inline int plus_2(DisasContext *s, int x)
141 return x + 2;
144 static inline int times_2(DisasContext *s, int x)
146 return x * 2;
149 static inline int times_4(DisasContext *s, int x)
151 return x * 4;
154 static inline int arm_dc_feature(DisasContext *dc, int feature)
156 return (dc->features & (1ULL << feature)) != 0;
159 static inline int get_mem_index(DisasContext *s)
161 return arm_to_core_mmu_idx(s->mmu_idx);
164 /* Function used to determine the target exception EL when otherwise not known
165 * or default.
167 static inline int default_exception_el(DisasContext *s)
169 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
170 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
171 * exceptions can only be routed to ELs above 1, so we target the higher of
172 * 1 or the current EL.
174 return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
175 ? 3 : MAX(1, s->current_el);
178 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
180 /* We don't need to save all of the syndrome so we mask and shift
181 * out unneeded bits to help the sleb128 encoder do a better job.
183 syn &= ARM_INSN_START_WORD2_MASK;
184 syn >>= ARM_INSN_START_WORD2_SHIFT;
186 /* We check and clear insn_start_idx to catch multiple updates. */
187 assert(s->insn_start != NULL);
188 tcg_set_insn_start_param(s->insn_start, 2, syn);
189 s->insn_start = NULL;
192 /* is_jmp field values */
193 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
194 /* CPU state was modified dynamically; exit to main loop for interrupts. */
195 #define DISAS_UPDATE_EXIT DISAS_TARGET_1
196 /* These instructions trap after executing, so the A32/T32 decoder must
197 * defer them until after the conditional execution state has been updated.
198 * WFI also needs special handling when single-stepping.
200 #define DISAS_WFI DISAS_TARGET_2
201 #define DISAS_SWI DISAS_TARGET_3
202 /* WFE */
203 #define DISAS_WFE DISAS_TARGET_4
204 #define DISAS_HVC DISAS_TARGET_5
205 #define DISAS_SMC DISAS_TARGET_6
206 #define DISAS_YIELD DISAS_TARGET_7
207 /* M profile branch which might be an exception return (and so needs
208 * custom end-of-TB code)
210 #define DISAS_BX_EXCRET DISAS_TARGET_8
212 * For instructions which want an immediate exit to the main loop, as opposed
213 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
214 * doesn't write the PC on exiting the translation loop so you need to ensure
215 * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
216 * return from cpu_tb_exec.
218 #define DISAS_EXIT DISAS_TARGET_9
219 /* CPU state was modified dynamically; no need to exit, but do not chain. */
220 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
222 #ifdef TARGET_AARCH64
223 void a64_translate_init(void);
224 void gen_a64_set_pc_im(uint64_t val);
225 extern const TranslatorOps aarch64_translator_ops;
226 #else
227 static inline void a64_translate_init(void)
231 static inline void gen_a64_set_pc_im(uint64_t val)
234 #endif
236 void arm_test_cc(DisasCompare *cmp, int cc);
237 void arm_free_cc(DisasCompare *cmp);
238 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
239 void arm_gen_test_cc(int cc, TCGLabel *label);
240 MemOp pow2_align(unsigned i);
241 void unallocated_encoding(DisasContext *s);
242 void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
243 uint32_t syn, uint32_t target_el);
245 /* Return state of Alternate Half-precision flag, caller frees result */
246 static inline TCGv_i32 get_ahp_flag(void)
248 TCGv_i32 ret = tcg_temp_new_i32();
250 tcg_gen_ld_i32(ret, cpu_env,
251 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
252 tcg_gen_extract_i32(ret, ret, 26, 1);
254 return ret;
257 /* Set bits within PSTATE. */
258 static inline void set_pstate_bits(uint32_t bits)
260 TCGv_i32 p = tcg_temp_new_i32();
262 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
264 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
265 tcg_gen_ori_i32(p, p, bits);
266 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
267 tcg_temp_free_i32(p);
270 /* Clear bits within PSTATE. */
271 static inline void clear_pstate_bits(uint32_t bits)
273 TCGv_i32 p = tcg_temp_new_i32();
275 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
277 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
278 tcg_gen_andi_i32(p, p, ~bits);
279 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
280 tcg_temp_free_i32(p);
283 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
284 static inline void gen_ss_advance(DisasContext *s)
286 if (s->ss_active) {
287 s->pstate_ss = 0;
288 clear_pstate_bits(PSTATE_SS);
292 static inline void gen_exception(int excp, uint32_t syndrome,
293 uint32_t target_el)
295 TCGv_i32 tcg_excp = tcg_const_i32(excp);
296 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
297 TCGv_i32 tcg_el = tcg_const_i32(target_el);
299 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
300 tcg_syn, tcg_el);
302 tcg_temp_free_i32(tcg_el);
303 tcg_temp_free_i32(tcg_syn);
304 tcg_temp_free_i32(tcg_excp);
307 /* Generate an architectural singlestep exception */
308 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
310 bool same_el = (s->debug_target_el == s->current_el);
313 * If singlestep is targeting a lower EL than the current one,
314 * then s->ss_active must be false and we can never get here.
316 assert(s->debug_target_el >= s->current_el);
318 gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
322 * Given a VFP floating point constant encoded into an 8 bit immediate in an
323 * instruction, expand it to the actual constant value of the specified
324 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
326 uint64_t vfp_expand_imm(int size, uint8_t imm8);
328 /* Vector operations shared between ARM and AArch64. */
329 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
330 uint32_t opr_sz, uint32_t max_sz);
331 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
332 uint32_t opr_sz, uint32_t max_sz);
333 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
334 uint32_t opr_sz, uint32_t max_sz);
335 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
336 uint32_t opr_sz, uint32_t max_sz);
337 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
338 uint32_t opr_sz, uint32_t max_sz);
340 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
341 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
342 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
343 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
345 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
346 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
347 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
348 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
349 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
350 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
352 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
353 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
354 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
355 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
356 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
358 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
359 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
360 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
361 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
362 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
363 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
364 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
365 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
367 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
368 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
369 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
370 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
372 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
373 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
374 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
375 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
376 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
377 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
378 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
379 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
381 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
382 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
383 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
384 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
386 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
387 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
388 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
389 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
391 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
392 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
393 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
394 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
396 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
397 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
398 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
399 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
402 * Forward to the isar_feature_* tests given a DisasContext pointer.
404 #define dc_isar_feature(name, ctx) \
405 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
407 /* Note that the gvec expanders operate on offsets + sizes. */
408 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
409 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
410 uint32_t, uint32_t);
411 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
412 uint32_t, uint32_t, uint32_t);
413 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
414 uint32_t, uint32_t, uint32_t);
416 /* Function prototype for gen_ functions for calling Neon helpers */
417 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
418 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
419 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
420 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
421 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
422 TCGv_i32, TCGv_i32);
423 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
424 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
425 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
426 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
427 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
428 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
429 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
430 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
431 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
432 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
433 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
434 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
435 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
436 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
439 * arm_tbflags_from_tb:
440 * @tb: the TranslationBlock
442 * Extract the flag values from @tb.
444 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
446 return (CPUARMTBFlags){ tb->flags, tb->cs_base };
450 * Enum for argument to fpstatus_ptr().
452 typedef enum ARMFPStatusFlavour {
453 FPST_FPCR,
454 FPST_FPCR_F16,
455 FPST_STD,
456 FPST_STD_F16,
457 } ARMFPStatusFlavour;
460 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
462 * We have multiple softfloat float_status fields in the Arm CPU state struct
463 * (see the comment in cpu.h for details). Return a TCGv_ptr which has
464 * been set up to point to the requested field in the CPU state struct.
465 * The options are:
467 * FPST_FPCR
468 * for non-FP16 operations controlled by the FPCR
469 * FPST_FPCR_F16
470 * for operations controlled by the FPCR where FPCR.FZ16 is to be used
471 * FPST_STD
472 * for A32/T32 Neon operations using the "standard FPSCR value"
473 * FPST_STD_F16
474 * as FPST_STD, but where FPCR.FZ16 is to be used
476 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
478 TCGv_ptr statusptr = tcg_temp_new_ptr();
479 int offset;
481 switch (flavour) {
482 case FPST_FPCR:
483 offset = offsetof(CPUARMState, vfp.fp_status);
484 break;
485 case FPST_FPCR_F16:
486 offset = offsetof(CPUARMState, vfp.fp_status_f16);
487 break;
488 case FPST_STD:
489 offset = offsetof(CPUARMState, vfp.standard_fp_status);
490 break;
491 case FPST_STD_F16:
492 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
493 break;
494 default:
495 g_assert_not_reached();
497 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
498 return statusptr;
502 * finalize_memop:
503 * @s: DisasContext
504 * @opc: size+sign+align of the memory operation
506 * Build the complete MemOp for a memory operation, including alignment
507 * and endianness.
509 * If (op & MO_AMASK) then the operation already contains the required
510 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
511 * unaligned operation, e.g. for AccType_NORMAL.
513 * In the latter case, there are configuration bits that require alignment,
514 * and this is applied here. Note that there is no way to indicate that
515 * no alignment should ever be enforced; this must be handled manually.
517 static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
519 if (s->align_mem && !(opc & MO_AMASK)) {
520 opc |= MO_ALIGN;
522 return opc | s->be_data;
525 #endif /* TARGET_ARM_TRANSLATE_H */