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Reduce the time of checkpoint for COLO
[qemu/ar7.git] / hw / ppc / mac_newworld.c
blobf9a1cc894472bb74e59d80829126680772a8d39d
1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 */
48
49 #include "qemu/osdep.h"
50 #include "qemu-common.h"
51 #include "qapi/error.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/ppc/mac.h"
55 #include "hw/input/adb.h"
56 #include "hw/ppc/mac_dbdma.h"
57 #include "hw/pci/pci.h"
58 #include "net/net.h"
59 #include "sysemu/sysemu.h"
60 #include "hw/boards.h"
61 #include "hw/nvram/fw_cfg.h"
62 #include "hw/char/escc.h"
63 #include "hw/misc/macio/macio.h"
64 #include "hw/ppc/openpic.h"
65 #include "hw/loader.h"
66 #include "hw/fw-path-provider.h"
67 #include "elf.h"
68 #include "qemu/error-report.h"
69 #include "sysemu/kvm.h"
70 #include "sysemu/reset.h"
71 #include "kvm_ppc.h"
72 #include "hw/usb.h"
73 #include "exec/address-spaces.h"
74 #include "hw/sysbus.h"
75 #include "trace.h"
76
77 #define MAX_IDE_BUS 2
78 #define CFG_ADDR 0xf0000510
79 #define TBFREQ (100UL * 1000UL * 1000UL)
80 #define CLOCKFREQ (900UL * 1000UL * 1000UL)
81 #define BUSFREQ (100UL * 1000UL * 1000UL)
82
83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
84
85 #define PROM_BASE 0xfff00000
86 #define PROM_SIZE (1 * MiB)
87
88 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
89 Error **errp)
90 {
91 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
92 }
93
94 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
95 {
96 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
97 }
98
99 static void ppc_core99_reset(void *opaque)
100 {
101 PowerPCCPU *cpu = opaque;
102
103 cpu_reset(CPU(cpu));
104 /* 970 CPUs want to get their initial IP as part of their boot protocol */
105 cpu->env.nip = PROM_BASE + 0x100;
106 }
107
108 /* PowerPC Mac99 hardware initialisation */
109 static void ppc_core99_init(MachineState *machine)
110 {
111 ram_addr_t ram_size = machine->ram_size;
112 const char *kernel_filename = machine->kernel_filename;
113 const char *kernel_cmdline = machine->kernel_cmdline;
114 const char *initrd_filename = machine->initrd_filename;
115 const char *boot_device = machine->boot_order;
116 Core99MachineState *core99_machine = CORE99_MACHINE(machine);
117 PowerPCCPU *cpu = NULL;
118 CPUPPCState *env = NULL;
119 char *filename;
120 IrqLines *openpic_irqs;
121 int linux_boot, i, j, k;
122 MemoryRegion *bios = g_new(MemoryRegion, 1);
123 hwaddr kernel_base, initrd_base, cmdline_base = 0;
124 long kernel_size, initrd_size;
125 UNINHostState *uninorth_pci;
126 PCIBus *pci_bus;
127 PCIDevice *macio;
128 ESCCState *escc;
129 bool has_pmu, has_adb;
130 MACIOIDEState *macio_ide;
131 BusState *adb_bus;
132 MacIONVRAMState *nvr;
133 int bios_size;
134 int ppc_boot_device;
135 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
136 void *fw_cfg;
137 int machine_arch;
138 SysBusDevice *s;
139 DeviceState *dev, *pic_dev;
140 hwaddr nvram_addr = 0xFFF04000;
141 uint64_t tbfreq;
142 unsigned int smp_cpus = machine->smp.cpus;
143
144 linux_boot = (kernel_filename != NULL);
145
146 /* init CPUs */
147 for (i = 0; i < smp_cpus; i++) {
148 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
149 env = &cpu->env;
150
151 /* Set time-base frequency to 100 Mhz */
152 cpu_ppc_tb_init(env, TBFREQ);
153 qemu_register_reset(ppc_core99_reset, cpu);
154 }
155
156 /* allocate RAM */
157 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
158
159 /* allocate and load firmware ROM */
160 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE,
161 &error_fatal);
162 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
163
164 if (!bios_name) {
165 bios_name = PROM_FILENAME;
166 }
167 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
168 if (filename) {
169 /* Load OpenBIOS (ELF) */
170 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
171 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
172
173 if (bios_size <= 0) {
174 /* or load binary ROM image */
175 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
176 }
177 g_free(filename);
178 } else {
179 bios_size = -1;
180 }
181 if (bios_size < 0 || bios_size > PROM_SIZE) {
182 error_report("could not load PowerPC bios '%s'", bios_name);
183 exit(1);
184 }
185
186 if (linux_boot) {
187 int bswap_needed;
188
189 #ifdef BSWAP_NEEDED
190 bswap_needed = 1;
191 #else
192 bswap_needed = 0;
193 #endif
194 kernel_base = KERNEL_LOAD_ADDR;
195
196 kernel_size = load_elf(kernel_filename, NULL,
197 translate_kernel_address, NULL, NULL, NULL,
198 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
199 if (kernel_size < 0)
200 kernel_size = load_aout(kernel_filename, kernel_base,
201 ram_size - kernel_base, bswap_needed,
202 TARGET_PAGE_SIZE);
203 if (kernel_size < 0)
204 kernel_size = load_image_targphys(kernel_filename,
205 kernel_base,
206 ram_size - kernel_base);
207 if (kernel_size < 0) {
208 error_report("could not load kernel '%s'", kernel_filename);
209 exit(1);
210 }
211 /* load initrd */
212 if (initrd_filename) {
213 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
214 initrd_size = load_image_targphys(initrd_filename, initrd_base,
215 ram_size - initrd_base);
216 if (initrd_size < 0) {
217 error_report("could not load initial ram disk '%s'",
218 initrd_filename);
219 exit(1);
220 }
221 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
222 } else {
223 initrd_base = 0;
224 initrd_size = 0;
225 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
226 }
227 ppc_boot_device = 'm';
228 } else {
229 kernel_base = 0;
230 kernel_size = 0;
231 initrd_base = 0;
232 initrd_size = 0;
233 ppc_boot_device = '\0';
234 /* We consider that NewWorld PowerMac never have any floppy drive
235 * For now, OHW cannot boot from the network.
236 */
237 for (i = 0; boot_device[i] != '\0'; i++) {
238 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
239 ppc_boot_device = boot_device[i];
240 break;
241 }
242 }
243 if (ppc_boot_device == '\0') {
244 error_report("No valid boot device for Mac99 machine");
245 exit(1);
246 }
247 }
248
249 /* UniN init */
250 dev = qdev_new(TYPE_UNI_NORTH);
251 s = SYS_BUS_DEVICE(dev);
252 sysbus_realize_and_unref(s, &error_fatal);
253 memory_region_add_subregion(get_system_memory(), 0xf8000000,
254 sysbus_mmio_get_region(s, 0));
255
256 openpic_irqs = g_new0(IrqLines, smp_cpus);
257 for (i = 0; i < smp_cpus; i++) {
258 /* Mac99 IRQ connection between OpenPIC outputs pins
259 * and PowerPC input pins
260 */
261 switch (PPC_INPUT(env)) {
262 case PPC_FLAGS_INPUT_6xx:
263 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
264 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
265 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
266 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
267 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
268 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
269 /* Not connected ? */
270 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
271 /* Check this */
272 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
273 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
274 break;
275 #if defined(TARGET_PPC64)
276 case PPC_FLAGS_INPUT_970:
277 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
278 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
279 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
280 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
281 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
282 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
283 /* Not connected ? */
284 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
285 /* Check this */
286 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
287 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
288 break;
289 #endif /* defined(TARGET_PPC64) */
290 default:
291 error_report("Bus model not supported on mac99 machine");
292 exit(1);
293 }
294 }
295
296 pic_dev = qdev_new(TYPE_OPENPIC);
297 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
298 s = SYS_BUS_DEVICE(pic_dev);
299 sysbus_realize_and_unref(s, &error_fatal);
300 k = 0;
301 for (i = 0; i < smp_cpus; i++) {
302 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
303 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
304 }
305 }
306 g_free(openpic_irqs);
307
308 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
309 /* 970 gets a U3 bus */
310 /* Uninorth AGP bus */
311 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
312 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
313 uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
314 s = SYS_BUS_DEVICE(dev);
315 /* PCI hole */
316 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
317 sysbus_mmio_get_region(s, 2));
318 /* Register 8 MB of ISA IO space */
319 memory_region_add_subregion(get_system_memory(), 0xf2000000,
320 sysbus_mmio_get_region(s, 3));
321 sysbus_mmio_map(s, 0, 0xf0800000);
322 sysbus_mmio_map(s, 1, 0xf0c00000);
323
324 for (i = 0; i < 4; i++) {
325 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
326 }
327
328 machine_arch = ARCH_MAC99_U3;
329 } else {
330 /* Use values found on a real PowerMac */
331 /* Uninorth AGP bus */
332 dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
333 s = SYS_BUS_DEVICE(dev);
334 sysbus_realize_and_unref(s, &error_fatal);
335 sysbus_mmio_map(s, 0, 0xf0800000);
336 sysbus_mmio_map(s, 1, 0xf0c00000);
337
338 for (i = 0; i < 4; i++) {
339 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
340 }
341
342 /* Uninorth internal bus */
343 dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
344 s = SYS_BUS_DEVICE(dev);
345 sysbus_realize_and_unref(s, &error_fatal);
346 sysbus_mmio_map(s, 0, 0xf4800000);
347 sysbus_mmio_map(s, 1, 0xf4c00000);
348
349 for (i = 0; i < 4; i++) {
350 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
351 }
352
353 /* Uninorth main bus */
354 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
355 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
356 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
357 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
358 s = SYS_BUS_DEVICE(dev);
359 /* PCI hole */
360 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
361 sysbus_mmio_get_region(s, 2));
362 /* Register 8 MB of ISA IO space */
363 memory_region_add_subregion(get_system_memory(), 0xf2000000,
364 sysbus_mmio_get_region(s, 3));
365 sysbus_mmio_map(s, 0, 0xf2800000);
366 sysbus_mmio_map(s, 1, 0xf2c00000);
367
368 for (i = 0; i < 4; i++) {
369 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i));
370 }
371
372 machine_arch = ARCH_MAC99;
373 }
374
375 machine->usb |= defaults_enabled() && !machine->usb_disabled;
376 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
377 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
378 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
379
380 /* Timebase Frequency */
381 if (kvm_enabled()) {
382 tbfreq = kvmppc_get_tbfreq();
383 } else {
384 tbfreq = TBFREQ;
385 }
386
387 /* init basic PC hardware */
388 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
389
390 /* MacIO */
391 macio = pci_new(-1, TYPE_NEWWORLD_MACIO);
392 dev = DEVICE(macio);
393 qdev_prop_set_uint64(dev, "frequency", tbfreq);
394 qdev_prop_set_bit(dev, "has-pmu", has_pmu);
395 qdev_prop_set_bit(dev, "has-adb", has_adb);
396 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
397 &error_abort);
398
399 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
400 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
401 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
402
403 pci_realize_and_unref(macio, pci_bus, &error_fatal);
404
405 /* We only emulate 2 out of 3 IDE controllers for now */
406 ide_drive_get(hd, ARRAY_SIZE(hd));
407
408 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
409 "ide[0]"));
410 macio_ide_init_drives(macio_ide, hd);
411
412 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
413 "ide[1]"));
414 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
415
416 if (has_adb) {
417 if (has_pmu) {
418 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu"));
419 } else {
420 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
421 }
422
423 adb_bus = qdev_get_child_bus(dev, "adb.0");
424 dev = qdev_new(TYPE_ADB_KEYBOARD);
425 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
426
427 dev = qdev_new(TYPE_ADB_MOUSE);
428 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
429 }
430
431 if (machine->usb) {
432 pci_create_simple(pci_bus, -1, "pci-ohci");
433
434 /* U3 needs to use USB for input because Linux doesn't support via-cuda
435 on PPC64 */
436 if (!has_adb || machine_arch == ARCH_MAC99_U3) {
437 USBBus *usb_bus = usb_bus_find(-1);
438
439 usb_create_simple(usb_bus, "usb-kbd");
440 usb_create_simple(usb_bus, "usb-mouse");
441 }
442 }
443
444 pci_vga_init(pci_bus);
445
446 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
447 graphic_depth = 15;
448 }
449
450 for (i = 0; i < nb_nics; i++) {
451 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL);
452 }
453
454 /* The NewWorld NVRAM is not located in the MacIO device */
455 if (kvm_enabled() && qemu_real_host_page_size > 4096) {
456 /* We can't combine read-write and read-only in a single page, so
457 move the NVRAM out of ROM again for KVM */
458 nvram_addr = 0xFFE00000;
459 }
460 dev = qdev_new(TYPE_MACIO_NVRAM);
461 qdev_prop_set_uint32(dev, "size", 0x2000);
462 qdev_prop_set_uint32(dev, "it_shift", 1);
463 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
464 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
465 nvr = MACIO_NVRAM(dev);
466 pmac_format_nvram_partition(nvr, 0x2000);
467 /* No PCI init: the BIOS will do it */
468
469 dev = qdev_new(TYPE_FW_CFG_MEM);
470 fw_cfg = FW_CFG(dev);
471 qdev_prop_set_uint32(dev, "data_width", 1);
472 qdev_prop_set_bit(dev, "dma_enabled", false);
473 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
474 OBJECT(fw_cfg));
475 s = SYS_BUS_DEVICE(dev);
476 sysbus_realize_and_unref(s, &error_fatal);
477 sysbus_mmio_map(s, 0, CFG_ADDR);
478 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
479
480 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
481 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
482 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
483 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
484 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
485 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
486 if (kernel_cmdline) {
487 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
488 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
489 } else {
490 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
491 }
492 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
493 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
494 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
495
496 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
497 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
498 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
499
500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
501
502 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
503 if (kvm_enabled()) {
504 uint8_t *hypercall;
505
506 hypercall = g_malloc(16);
507 kvmppc_get_hypercall(env, hypercall, 16);
508 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
509 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
510 }
511 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
512 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
513 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
514 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
515 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
516
517 /* MacOS NDRV VGA driver */
518 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
519 if (filename) {
520 gchar *ndrv_file;
521 gsize ndrv_size;
522
523 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
524 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
525 }
526 g_free(filename);
527 }
528
529 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
530 }
531
532 /*
533 * Implementation of an interface to adjust firmware path
534 * for the bootindex property handling.
535 */
536 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus,
537 DeviceState *dev)
538 {
539 PCIDevice *pci;
540 IDEBus *ide_bus;
541 IDEState *ide_s;
542 MACIOIDEState *macio_ide;
543
544 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) {
545 pci = PCI_DEVICE(dev);
546 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
547 }
548
549 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
550 macio_ide = MACIO_IDE(dev);
551 return g_strdup_printf("ata-3@%x", macio_ide->addr);
552 }
553
554 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
555 ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
556 ide_s = idebus_active_if(ide_bus);
557
558 if (ide_s->drive_kind == IDE_CD) {
559 return g_strdup("cdrom");
560 }
561
562 return g_strdup("disk");
563 }
564
565 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
566 return g_strdup("disk");
567 }
568
569 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
570 return g_strdup("cdrom");
571 }
572
573 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
574 return g_strdup("disk");
575 }
576
577 return NULL;
578 }
579 static int core99_kvm_type(MachineState *machine, const char *arg)
580 {
581 /* Always force PR KVM */
582 return 2;
583 }
584
585 static void core99_machine_class_init(ObjectClass *oc, void *data)
586 {
587 MachineClass *mc = MACHINE_CLASS(oc);
588 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
589
590 mc->desc = "Mac99 based PowerMAC";
591 mc->init = ppc_core99_init;
592 mc->block_default_type = IF_IDE;
593 mc->max_cpus = MAX_CPUS;
594 mc->default_boot_order = "cd";
595 mc->default_display = "std";
596 mc->kvm_type = core99_kvm_type;
597 #ifdef TARGET_PPC64
598 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1");
599 #else
600 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
601 #endif
602 mc->default_ram_id = "ppc_core99.ram";
603 mc->ignore_boot_device_suffixes = true;
604 fwc->get_dev_path = core99_fw_dev_path;
605 }
606
607 static char *core99_get_via_config(Object *obj, Error **errp)
608 {
609 Core99MachineState *cms = CORE99_MACHINE(obj);
610
611 switch (cms->via_config) {
612 default:
613 case CORE99_VIA_CONFIG_CUDA:
614 return g_strdup("cuda");
615
616 case CORE99_VIA_CONFIG_PMU:
617 return g_strdup("pmu");
618
619 case CORE99_VIA_CONFIG_PMU_ADB:
620 return g_strdup("pmu-adb");
621 }
622 }
623
624 static void core99_set_via_config(Object *obj, const char *value, Error **errp)
625 {
626 Core99MachineState *cms = CORE99_MACHINE(obj);
627
628 if (!strcmp(value, "cuda")) {
629 cms->via_config = CORE99_VIA_CONFIG_CUDA;
630 } else if (!strcmp(value, "pmu")) {
631 cms->via_config = CORE99_VIA_CONFIG_PMU;
632 } else if (!strcmp(value, "pmu-adb")) {
633 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB;
634 } else {
635 error_setg(errp, "Invalid via value");
636 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n");
637 }
638 }
639
640 static void core99_instance_init(Object *obj)
641 {
642 Core99MachineState *cms = CORE99_MACHINE(obj);
643
644 /* Default via_config is CORE99_VIA_CONFIG_CUDA */
645 cms->via_config = CORE99_VIA_CONFIG_CUDA;
646 object_property_add_str(obj, "via", core99_get_via_config,
647 core99_set_via_config);
648 object_property_set_description(obj, "via",
649 "Set VIA configuration. "
650 "Valid values are cuda, pmu and pmu-adb");
651
652 return;
653 }
654
655 static const TypeInfo core99_machine_info = {
656 .name = MACHINE_TYPE_NAME("mac99"),
657 .parent = TYPE_MACHINE,
658 .class_init = core99_machine_class_init,
659 .instance_init = core99_instance_init,
660 .instance_size = sizeof(Core99MachineState),
661 .interfaces = (InterfaceInfo[]) {
662 { TYPE_FW_PATH_PROVIDER },
663 { }
664 },
665 };
666
667 static void mac_machine_register_types(void)
668 {
669 type_register_static(&core99_machine_info);
670 }
671
672 type_init(mac_machine_register_types)
AR7 emulation for QEMU