target-arm/helper-a64.c

   1 /*
   2  *  AArch64 specific helpers
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/gdbstub.h"
  22 #include "helper.h"
  23 #include "qemu/host-utils.h"
  24 #include "sysemu/sysemu.h"
  25 #include "qemu/bitops.h"
  26
  27 /* C2.4.7 Multiply and divide */
  28 /* special cases for 0 and LLONG_MIN are mandated by the standard */
  29 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
  30 {
  31     if (den == 0) {
  32         return 0;
  33     }
  34     return num / den;
  35 }
  36
  37 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
  38 {
  39     if (den == 0) {
  40         return 0;
  41     }
  42     if (num == LLONG_MIN && den == -1) {
  43         return LLONG_MIN;
  44     }
  45     return num / den;
  46 }
  47
  48 uint64_t HELPER(clz64)(uint64_t x)
  49 {
  50     return clz64(x);
  51 }
  52
  53 uint64_t HELPER(cls64)(uint64_t x)
  54 {
  55     return clrsb64(x);
  56 }
  57
  58 uint32_t HELPER(cls32)(uint32_t x)
  59 {
  60     return clrsb32(x);
  61 }
  62
  63 uint32_t HELPER(clz32)(uint32_t x)
  64 {
  65     return clz32(x);
  66 }
  67
  68 uint64_t HELPER(rbit64)(uint64_t x)
  69 {
  70     /* assign the correct byte position */
  71     x = bswap64(x);
  72
  73     /* assign the correct nibble position */
  74     x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
  75         | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4);
  76
  77     /* assign the correct bit position */
  78     x = ((x & 0x8888888888888888ULL) >> 3)
  79         | ((x & 0x4444444444444444ULL) >> 1)
  80         | ((x & 0x2222222222222222ULL) << 1)
  81         | ((x & 0x1111111111111111ULL) << 3);
  82
  83     return x;
  84 }
  85
  86 /* Convert a softfloat float_relation_ (as returned by
  87  * the float*_compare functions) to the correct ARM
  88  * NZCV flag state.
  89  */
  90 static inline uint32_t float_rel_to_flags(int res)
  91 {
  92     uint64_t flags;
  93     switch (res) {
  94     case float_relation_equal:
  95         flags = PSTATE_Z | PSTATE_C;
  96         break;
  97     case float_relation_less:
  98         flags = PSTATE_N;
  99         break;
 100     case float_relation_greater:
 101         flags = PSTATE_C;
 102         break;
 103     case float_relation_unordered:
 104     default:
 105         flags = PSTATE_C | PSTATE_V;
 106         break;
 107     }
 108     return flags;
 109 }
 110
 111 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
 112 {
 113     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
 114 }
 115
 116 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
 117 {
 118     return float_rel_to_flags(float32_compare(x, y, fp_status));
 119 }
 120
 121 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
 122 {
 123     return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
 124 }
 125
 126 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
 127 {
 128     return float_rel_to_flags(float64_compare(x, y, fp_status));
 129 }
 130
 131 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
 132 {
 133     float_status *fpst = fpstp;
 134
 135     if ((float32_is_zero(a) && float32_is_infinity(b)) ||
 136         (float32_is_infinity(a) && float32_is_zero(b))) {
 137         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 138         return make_float32((1U << 30) |
 139                             ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
 140     }
 141     return float32_mul(a, b, fpst);
 142 }
 143
 144 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
 145 {
 146     float_status *fpst = fpstp;
 147
 148     if ((float64_is_zero(a) && float64_is_infinity(b)) ||
 149         (float64_is_infinity(a) && float64_is_zero(b))) {
 150         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 151         return make_float64((1ULL << 62) |
 152                             ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
 153     }
 154     return float64_mul(a, b, fpst);
 155 }
 156
 157 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
 158                           uint32_t rn, uint32_t numregs)
 159 {
 160     /* Helper function for SIMD TBL and TBX. We have to do the table
 161      * lookup part for the 64 bits worth of indices we're passed in.
 162      * result is the initial results vector (either zeroes for TBL
 163      * or some guest values for TBX), rn the register number where
 164      * the table starts, and numregs the number of registers in the table.
 165      * We return the results of the lookups.
 166      */
 167     int shift;
 168
 169     for (shift = 0; shift < 64; shift += 8) {
 170         int index = extract64(indices, shift, 8);
 171         if (index < 16 * numregs) {
 172             /* Convert index (a byte offset into the virtual table
 173              * which is a series of 128-bit vectors concatenated)
 174              * into the correct vfp.regs[] element plus a bit offset
 175              * into that element, bearing in mind that the table
 176              * can wrap around from V31 to V0.
 177              */
 178             int elt = (rn * 2 + (index >> 3)) % 64;
 179             int bitidx = (index & 7) * 8;
 180             uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
 181
 182             result = deposit64(result, shift, 8, val);
 183         }
 184     }
 185     return result;
 186 }
 187
 188 /* Helper function for 64 bit polynomial multiply case:
 189  * perform PolynomialMult(op1, op2) and return either the top or
 190  * bottom half of the 128 bit result.
 191  */
 192 uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2)
 193 {
 194     int bitnum;
 195     uint64_t res = 0;
 196
 197     for (bitnum = 0; bitnum < 64; bitnum++) {
 198         if (op1 & (1ULL << bitnum)) {
 199             res ^= op2 << bitnum;
 200         }
 201     }
 202     return res;
 203 }
 204 uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2)
 205 {
 206     int bitnum;
 207     uint64_t res = 0;
 208
 209     /* bit 0 of op1 can't influence the high 64 bits at all */
 210     for (bitnum = 1; bitnum < 64; bitnum++) {
 211         if (op1 & (1ULL << bitnum)) {
 212             res ^= op2 >> (64 - bitnum);
 213         }
 214     }
 215     return res;
 216 }
 217
 218 /* 64bit/double versions of the neon float compare functions */
 219 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
 220 {
 221     float_status *fpst = fpstp;
 222     return -float64_eq_quiet(a, b, fpst);
 223 }
 224
 225 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
 226 {
 227     float_status *fpst = fpstp;
 228     return -float64_le(b, a, fpst);
 229 }
 230
 231 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 232 {
 233     float_status *fpst = fpstp;
 234     return -float64_lt(b, a, fpst);
 235 }
 236
 237 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
 238  * versions, these do a fully fused multiply-add or
 239  * multiply-add-and-halve.
 240  */
 241 #define float32_two make_float32(0x40000000)
 242 #define float32_three make_float32(0x40400000)
 243 #define float32_one_point_five make_float32(0x3fc00000)
 244
 245 #define float64_two make_float64(0x4000000000000000ULL)
 246 #define float64_three make_float64(0x4008000000000000ULL)
 247 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 248
 249 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 250 {
 251     float_status *fpst = fpstp;
 252
 253     a = float32_chs(a);
 254     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 255         (float32_is_infinity(b) && float32_is_zero(a))) {
 256         return float32_two;
 257     }
 258     return float32_muladd(a, b, float32_two, 0, fpst);
 259 }
 260
 261 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
 262 {
 263     float_status *fpst = fpstp;
 264
 265     a = float64_chs(a);
 266     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 267         (float64_is_infinity(b) && float64_is_zero(a))) {
 268         return float64_two;
 269     }
 270     return float64_muladd(a, b, float64_two, 0, fpst);
 271 }
 272
 273 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 274 {
 275     float_status *fpst = fpstp;
 276
 277     a = float32_chs(a);
 278     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 279         (float32_is_infinity(b) && float32_is_zero(a))) {
 280         return float32_one_point_five;
 281     }
 282     return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
 283 }
 284
 285 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
 286 {
 287     float_status *fpst = fpstp;
 288
 289     a = float64_chs(a);
 290     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 291         (float64_is_infinity(b) && float64_is_zero(a))) {
 292         return float64_one_point_five;
 293     }
 294     return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
 295 }
 296
 297 /* Pairwise long add: add pairs of adjacent elements into
 298  * double-width elements in the result (eg _s8 is an 8x8->16 op)
 299  */
 300 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
 301 {
 302     uint64_t nsignmask = 0x0080008000800080ULL;
 303     uint64_t wsignmask = 0x8000800080008000ULL;
 304     uint64_t elementmask = 0x00ff00ff00ff00ffULL;
 305     uint64_t tmp1, tmp2;
 306     uint64_t res, signres;
 307
 308     /* Extract odd elements, sign extend each to a 16 bit field */
 309     tmp1 = a & elementmask;
 310     tmp1 ^= nsignmask;
 311     tmp1 |= wsignmask;
 312     tmp1 = (tmp1 - nsignmask) ^ wsignmask;
 313     /* Ditto for the even elements */
 314     tmp2 = (a >> 8) & elementmask;
 315     tmp2 ^= nsignmask;
 316     tmp2 |= wsignmask;
 317     tmp2 = (tmp2 - nsignmask) ^ wsignmask;
 318
 319     /* calculate the result by summing bits 0..14, 16..22, etc,
 320      * and then adjusting the sign bits 15, 23, etc manually.
 321      * This ensures the addition can't overflow the 16 bit field.
 322      */
 323     signres = (tmp1 ^ tmp2) & wsignmask;
 324     res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
 325     res ^= signres;
 326
 327     return res;
 328 }
 329
 330 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
 331 {
 332     uint64_t tmp;
 333
 334     tmp = a & 0x00ff00ff00ff00ffULL;
 335     tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
 336     return tmp;
 337 }
 338
 339 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
 340 {
 341     int32_t reslo, reshi;
 342
 343     reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
 344     reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
 345
 346     return (uint32_t)reslo | (((uint64_t)reshi) << 32);
 347 }
 348
 349 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 350 {
 351     uint64_t tmp;
 352
 353     tmp = a & 0x0000ffff0000ffffULL;
 354     tmp += (a >> 16) & 0x0000ffff0000ffffULL;
 355     return tmp;
 356 }
 357
 358 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 359 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 360 {
 361     float_status *fpst = fpstp;
 362     uint32_t val32, sbit;
 363     int32_t exp;
 364
 365     if (float32_is_any_nan(a)) {
 366         float32 nan = a;
 367         if (float32_is_signaling_nan(a)) {
 368             float_raise(float_flag_invalid, fpst);
 369             nan = float32_maybe_silence_nan(a);
 370         }
 371         if (fpst->default_nan_mode) {
 372             nan = float32_default_nan;
 373         }
 374         return nan;
 375     }
 376
 377     val32 = float32_val(a);
 378     sbit = 0x80000000ULL & val32;
 379     exp = extract32(val32, 23, 8);
 380
 381     if (exp == 0) {
 382         return make_float32(sbit | (0xfe << 23));
 383     } else {
 384         return make_float32(sbit | (~exp & 0xff) << 23);
 385     }
 386 }
 387
 388 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
 389 {
 390     float_status *fpst = fpstp;
 391     uint64_t val64, sbit;
 392     int64_t exp;
 393
 394     if (float64_is_any_nan(a)) {
 395         float64 nan = a;
 396         if (float64_is_signaling_nan(a)) {
 397             float_raise(float_flag_invalid, fpst);
 398             nan = float64_maybe_silence_nan(a);
 399         }
 400         if (fpst->default_nan_mode) {
 401             nan = float64_default_nan;
 402         }
 403         return nan;
 404     }
 405
 406     val64 = float64_val(a);
 407     sbit = 0x8000000000000000ULL & val64;
 408     exp = extract64(float64_val(a), 52, 11);
 409
 410     if (exp == 0) {
 411         return make_float64(sbit | (0x7feULL << 52));
 412     } else {
 413         return make_float64(sbit | (~exp & 0x7ffULL) << 52);
 414     }
 415 }