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readline: Add missing GCC_FMT_ATTR
[qemu/ar7.git] / target-m68k / translate.c
blob998b90a40128cbcf473990d2684bf531e6f0e85e
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/log.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 //#define DEBUG_DISPATCH 1
31
32 /* Fake floating point. */
33 #define tcg_gen_mov_f64 tcg_gen_mov_i64
34 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
35 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
36
37 #define DEFO32(name, offset) static TCGv QREG_##name;
38 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
39 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
40 #include "qregs.def"
41 #undef DEFO32
42 #undef DEFO64
43 #undef DEFF64
44
45 static TCGv_i32 cpu_halted;
46
47 static TCGv_ptr cpu_env;
48
49 static char cpu_reg_names[3*8*3 + 5*4];
50 static TCGv cpu_dregs[8];
51 static TCGv cpu_aregs[8];
52 static TCGv_i64 cpu_fregs[8];
53 static TCGv_i64 cpu_macc[4];
54
55 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
56 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
57 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP cpu_aregs[7]
60
61 static TCGv NULL_QREG;
62 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy;
65
66 #include "exec/gen-icount.h"
67
68 void m68k_tcg_init(void)
69 {
70 char *p;
71 int i;
72
73 #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
74 #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
75 #define DEFF64(name, offset) DEFO64(name, offset)
76 #include "qregs.def"
77 #undef DEFO32
78 #undef DEFO64
79 #undef DEFF64
80
81 cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
82 -offsetof(M68kCPU, env) +
83 offsetof(CPUState, halted), "HALTED");
84
85 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
86
87 p = cpu_reg_names;
88 for (i = 0; i < 8; i++) {
89 sprintf(p, "D%d", i);
90 cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
91 offsetof(CPUM68KState, dregs[i]), p);
92 p += 3;
93 sprintf(p, "A%d", i);
94 cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
95 offsetof(CPUM68KState, aregs[i]), p);
96 p += 3;
97 sprintf(p, "F%d", i);
98 cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
99 offsetof(CPUM68KState, fregs[i]), p);
100 p += 3;
101 }
102 for (i = 0; i < 4; i++) {
103 sprintf(p, "ACC%d", i);
104 cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
105 offsetof(CPUM68KState, macc[i]), p);
106 p += 5;
107 }
108
109 NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
110 store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
111 }
112
113 static inline void qemu_assert(int cond, const char *msg)
114 {
115 if (!cond) {
116 fprintf (stderr, "badness: %s\n", msg);
117 abort();
118 }
119 }
120
121 /* internal defines */
122 typedef struct DisasContext {
123 CPUM68KState *env;
124 target_ulong insn_pc; /* Start of the current instruction. */
125 target_ulong pc;
126 int is_jmp;
127 int cc_op;
128 int user;
129 uint32_t fpcr;
130 struct TranslationBlock *tb;
131 int singlestep_enabled;
132 int is_mem;
133 TCGv_i64 mactmp;
134 int done_mac;
135 } DisasContext;
136
137 #define DISAS_JUMP_NEXT 4
138
139 #if defined(CONFIG_USER_ONLY)
140 #define IS_USER(s) 1
141 #else
142 #define IS_USER(s) s->user
143 #endif
144
145 /* XXX: move that elsewhere */
146 /* ??? Fix exceptions. */
147 static void *gen_throws_exception;
148 #define gen_last_qop NULL
149
150 #define OS_BYTE 0
151 #define OS_WORD 1
152 #define OS_LONG 2
153 #define OS_SINGLE 4
154 #define OS_DOUBLE 5
155
156 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
157
158 #ifdef DEBUG_DISPATCH
159 #define DISAS_INSN(name) \
160 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
161 uint16_t insn); \
162 static void disas_##name(CPUM68KState *env, DisasContext *s, \
163 uint16_t insn) \
164 { \
165 qemu_log("Dispatch " #name "\n"); \
166 real_disas_##name(s, env, insn); \
167 } \
168 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
169 uint16_t insn)
170 #else
171 #define DISAS_INSN(name) \
172 static void disas_##name(CPUM68KState *env, DisasContext *s, \
173 uint16_t insn)
174 #endif
175
176 /* Generate a load from the specified address. Narrow values are
177 sign extended to full register width. */
178 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
179 {
180 TCGv tmp;
181 int index = IS_USER(s);
182 s->is_mem = 1;
183 tmp = tcg_temp_new_i32();
184 switch(opsize) {
185 case OS_BYTE:
186 if (sign)
187 tcg_gen_qemu_ld8s(tmp, addr, index);
188 else
189 tcg_gen_qemu_ld8u(tmp, addr, index);
190 break;
191 case OS_WORD:
192 if (sign)
193 tcg_gen_qemu_ld16s(tmp, addr, index);
194 else
195 tcg_gen_qemu_ld16u(tmp, addr, index);
196 break;
197 case OS_LONG:
198 case OS_SINGLE:
199 tcg_gen_qemu_ld32u(tmp, addr, index);
200 break;
201 default:
202 qemu_assert(0, "bad load size");
203 }
204 gen_throws_exception = gen_last_qop;
205 return tmp;
206 }
207
208 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
209 {
210 TCGv_i64 tmp;
211 int index = IS_USER(s);
212 s->is_mem = 1;
213 tmp = tcg_temp_new_i64();
214 tcg_gen_qemu_ldf64(tmp, addr, index);
215 gen_throws_exception = gen_last_qop;
216 return tmp;
217 }
218
219 /* Generate a store. */
220 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
221 {
222 int index = IS_USER(s);
223 s->is_mem = 1;
224 switch(opsize) {
225 case OS_BYTE:
226 tcg_gen_qemu_st8(val, addr, index);
227 break;
228 case OS_WORD:
229 tcg_gen_qemu_st16(val, addr, index);
230 break;
231 case OS_LONG:
232 case OS_SINGLE:
233 tcg_gen_qemu_st32(val, addr, index);
234 break;
235 default:
236 qemu_assert(0, "bad store size");
237 }
238 gen_throws_exception = gen_last_qop;
239 }
240
241 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
242 {
243 int index = IS_USER(s);
244 s->is_mem = 1;
245 tcg_gen_qemu_stf64(val, addr, index);
246 gen_throws_exception = gen_last_qop;
247 }
248
249 typedef enum {
250 EA_STORE,
251 EA_LOADU,
252 EA_LOADS
253 } ea_what;
254
255 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
256 otherwise generate a store. */
257 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
258 ea_what what)
259 {
260 if (what == EA_STORE) {
261 gen_store(s, opsize, addr, val);
262 return store_dummy;
263 } else {
264 return gen_load(s, opsize, addr, what == EA_LOADS);
265 }
266 }
267
268 /* Read a 32-bit immediate constant. */
269 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
270 {
271 uint32_t im;
272 im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
273 s->pc += 2;
274 im |= cpu_lduw_code(env, s->pc);
275 s->pc += 2;
276 return im;
277 }
278
279 /* Calculate and address index. */
280 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
281 {
282 TCGv add;
283 int scale;
284
285 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
286 if ((ext & 0x800) == 0) {
287 tcg_gen_ext16s_i32(tmp, add);
288 add = tmp;
289 }
290 scale = (ext >> 9) & 3;
291 if (scale != 0) {
292 tcg_gen_shli_i32(tmp, add, scale);
293 add = tmp;
294 }
295 return add;
296 }
297
298 /* Handle a base + index + displacement effective addresss.
299 A NULL_QREG base means pc-relative. */
300 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
301 TCGv base)
302 {
303 uint32_t offset;
304 uint16_t ext;
305 TCGv add;
306 TCGv tmp;
307 uint32_t bd, od;
308
309 offset = s->pc;
310 ext = cpu_lduw_code(env, s->pc);
311 s->pc += 2;
312
313 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
314 return NULL_QREG;
315
316 if (ext & 0x100) {
317 /* full extension word format */
318 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
319 return NULL_QREG;
320
321 if ((ext & 0x30) > 0x10) {
322 /* base displacement */
323 if ((ext & 0x30) == 0x20) {
324 bd = (int16_t)cpu_lduw_code(env, s->pc);
325 s->pc += 2;
326 } else {
327 bd = read_im32(env, s);
328 }
329 } else {
330 bd = 0;
331 }
332 tmp = tcg_temp_new();
333 if ((ext & 0x44) == 0) {
334 /* pre-index */
335 add = gen_addr_index(ext, tmp);
336 } else {
337 add = NULL_QREG;
338 }
339 if ((ext & 0x80) == 0) {
340 /* base not suppressed */
341 if (IS_NULL_QREG(base)) {
342 base = tcg_const_i32(offset + bd);
343 bd = 0;
344 }
345 if (!IS_NULL_QREG(add)) {
346 tcg_gen_add_i32(tmp, add, base);
347 add = tmp;
348 } else {
349 add = base;
350 }
351 }
352 if (!IS_NULL_QREG(add)) {
353 if (bd != 0) {
354 tcg_gen_addi_i32(tmp, add, bd);
355 add = tmp;
356 }
357 } else {
358 add = tcg_const_i32(bd);
359 }
360 if ((ext & 3) != 0) {
361 /* memory indirect */
362 base = gen_load(s, OS_LONG, add, 0);
363 if ((ext & 0x44) == 4) {
364 add = gen_addr_index(ext, tmp);
365 tcg_gen_add_i32(tmp, add, base);
366 add = tmp;
367 } else {
368 add = base;
369 }
370 if ((ext & 3) > 1) {
371 /* outer displacement */
372 if ((ext & 3) == 2) {
373 od = (int16_t)cpu_lduw_code(env, s->pc);
374 s->pc += 2;
375 } else {
376 od = read_im32(env, s);
377 }
378 } else {
379 od = 0;
380 }
381 if (od != 0) {
382 tcg_gen_addi_i32(tmp, add, od);
383 add = tmp;
384 }
385 }
386 } else {
387 /* brief extension word format */
388 tmp = tcg_temp_new();
389 add = gen_addr_index(ext, tmp);
390 if (!IS_NULL_QREG(base)) {
391 tcg_gen_add_i32(tmp, add, base);
392 if ((int8_t)ext)
393 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
394 } else {
395 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
396 }
397 add = tmp;
398 }
399 return add;
400 }
401
402 /* Update the CPU env CC_OP state. */
403 static inline void gen_flush_cc_op(DisasContext *s)
404 {
405 if (s->cc_op != CC_OP_DYNAMIC)
406 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
407 }
408
409 /* Evaluate all the CC flags. */
410 static inline void gen_flush_flags(DisasContext *s)
411 {
412 if (s->cc_op == CC_OP_FLAGS)
413 return;
414 gen_flush_cc_op(s);
415 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
416 s->cc_op = CC_OP_FLAGS;
417 }
418
419 static void gen_logic_cc(DisasContext *s, TCGv val)
420 {
421 tcg_gen_mov_i32(QREG_CC_DEST, val);
422 s->cc_op = CC_OP_LOGIC;
423 }
424
425 static void gen_update_cc_add(TCGv dest, TCGv src)
426 {
427 tcg_gen_mov_i32(QREG_CC_DEST, dest);
428 tcg_gen_mov_i32(QREG_CC_SRC, src);
429 }
430
431 static inline int opsize_bytes(int opsize)
432 {
433 switch (opsize) {
434 case OS_BYTE: return 1;
435 case OS_WORD: return 2;
436 case OS_LONG: return 4;
437 case OS_SINGLE: return 4;
438 case OS_DOUBLE: return 8;
439 default:
440 qemu_assert(0, "bad operand size");
441 return 0;
442 }
443 /* Should never happen. */
444 return -1;
445 }
446
447 /* Assign value to a register. If the width is less than the register width
448 only the low part of the register is set. */
449 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
450 {
451 TCGv tmp;
452 switch (opsize) {
453 case OS_BYTE:
454 tcg_gen_andi_i32(reg, reg, 0xffffff00);
455 tmp = tcg_temp_new();
456 tcg_gen_ext8u_i32(tmp, val);
457 tcg_gen_or_i32(reg, reg, tmp);
458 break;
459 case OS_WORD:
460 tcg_gen_andi_i32(reg, reg, 0xffff0000);
461 tmp = tcg_temp_new();
462 tcg_gen_ext16u_i32(tmp, val);
463 tcg_gen_or_i32(reg, reg, tmp);
464 break;
465 case OS_LONG:
466 case OS_SINGLE:
467 tcg_gen_mov_i32(reg, val);
468 break;
469 default:
470 qemu_assert(0, "Bad operand size");
471 break;
472 }
473 }
474
475 /* Sign or zero extend a value. */
476 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
477 {
478 TCGv tmp;
479
480 switch (opsize) {
481 case OS_BYTE:
482 tmp = tcg_temp_new();
483 if (sign)
484 tcg_gen_ext8s_i32(tmp, val);
485 else
486 tcg_gen_ext8u_i32(tmp, val);
487 break;
488 case OS_WORD:
489 tmp = tcg_temp_new();
490 if (sign)
491 tcg_gen_ext16s_i32(tmp, val);
492 else
493 tcg_gen_ext16u_i32(tmp, val);
494 break;
495 case OS_LONG:
496 case OS_SINGLE:
497 tmp = val;
498 break;
499 default:
500 qemu_assert(0, "Bad operand size");
501 }
502 return tmp;
503 }
504
505 /* Generate code for an "effective address". Does not adjust the base
506 register for autoincrement addressing modes. */
507 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
508 int opsize)
509 {
510 TCGv reg;
511 TCGv tmp;
512 uint16_t ext;
513 uint32_t offset;
514
515 switch ((insn >> 3) & 7) {
516 case 0: /* Data register direct. */
517 case 1: /* Address register direct. */
518 return NULL_QREG;
519 case 2: /* Indirect register */
520 case 3: /* Indirect postincrement. */
521 return AREG(insn, 0);
522 case 4: /* Indirect predecrememnt. */
523 reg = AREG(insn, 0);
524 tmp = tcg_temp_new();
525 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
526 return tmp;
527 case 5: /* Indirect displacement. */
528 reg = AREG(insn, 0);
529 tmp = tcg_temp_new();
530 ext = cpu_lduw_code(env, s->pc);
531 s->pc += 2;
532 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
533 return tmp;
534 case 6: /* Indirect index + displacement. */
535 reg = AREG(insn, 0);
536 return gen_lea_indexed(env, s, opsize, reg);
537 case 7: /* Other */
538 switch (insn & 7) {
539 case 0: /* Absolute short. */
540 offset = cpu_ldsw_code(env, s->pc);
541 s->pc += 2;
542 return tcg_const_i32(offset);
543 case 1: /* Absolute long. */
544 offset = read_im32(env, s);
545 return tcg_const_i32(offset);
546 case 2: /* pc displacement */
547 offset = s->pc;
548 offset += cpu_ldsw_code(env, s->pc);
549 s->pc += 2;
550 return tcg_const_i32(offset);
551 case 3: /* pc index+displacement. */
552 return gen_lea_indexed(env, s, opsize, NULL_QREG);
553 case 4: /* Immediate. */
554 default:
555 return NULL_QREG;
556 }
557 }
558 /* Should never happen. */
559 return NULL_QREG;
560 }
561
562 /* Helper function for gen_ea. Reuse the computed address between the
563 for read/write operands. */
564 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
565 uint16_t insn, int opsize, TCGv val,
566 TCGv *addrp, ea_what what)
567 {
568 TCGv tmp;
569
570 if (addrp && what == EA_STORE) {
571 tmp = *addrp;
572 } else {
573 tmp = gen_lea(env, s, insn, opsize);
574 if (IS_NULL_QREG(tmp))
575 return tmp;
576 if (addrp)
577 *addrp = tmp;
578 }
579 return gen_ldst(s, opsize, tmp, val, what);
580 }
581
582 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
583 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
584 ADDRP is non-null for readwrite operands. */
585 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
586 int opsize, TCGv val, TCGv *addrp, ea_what what)
587 {
588 TCGv reg;
589 TCGv result;
590 uint32_t offset;
591
592 switch ((insn >> 3) & 7) {
593 case 0: /* Data register direct. */
594 reg = DREG(insn, 0);
595 if (what == EA_STORE) {
596 gen_partset_reg(opsize, reg, val);
597 return store_dummy;
598 } else {
599 return gen_extend(reg, opsize, what == EA_LOADS);
600 }
601 case 1: /* Address register direct. */
602 reg = AREG(insn, 0);
603 if (what == EA_STORE) {
604 tcg_gen_mov_i32(reg, val);
605 return store_dummy;
606 } else {
607 return gen_extend(reg, opsize, what == EA_LOADS);
608 }
609 case 2: /* Indirect register */
610 reg = AREG(insn, 0);
611 return gen_ldst(s, opsize, reg, val, what);
612 case 3: /* Indirect postincrement. */
613 reg = AREG(insn, 0);
614 result = gen_ldst(s, opsize, reg, val, what);
615 /* ??? This is not exception safe. The instruction may still
616 fault after this point. */
617 if (what == EA_STORE || !addrp)
618 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
619 return result;
620 case 4: /* Indirect predecrememnt. */
621 {
622 TCGv tmp;
623 if (addrp && what == EA_STORE) {
624 tmp = *addrp;
625 } else {
626 tmp = gen_lea(env, s, insn, opsize);
627 if (IS_NULL_QREG(tmp))
628 return tmp;
629 if (addrp)
630 *addrp = tmp;
631 }
632 result = gen_ldst(s, opsize, tmp, val, what);
633 /* ??? This is not exception safe. The instruction may still
634 fault after this point. */
635 if (what == EA_STORE || !addrp) {
636 reg = AREG(insn, 0);
637 tcg_gen_mov_i32(reg, tmp);
638 }
639 }
640 return result;
641 case 5: /* Indirect displacement. */
642 case 6: /* Indirect index + displacement. */
643 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
644 case 7: /* Other */
645 switch (insn & 7) {
646 case 0: /* Absolute short. */
647 case 1: /* Absolute long. */
648 case 2: /* pc displacement */
649 case 3: /* pc index+displacement. */
650 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
651 case 4: /* Immediate. */
652 /* Sign extend values for consistency. */
653 switch (opsize) {
654 case OS_BYTE:
655 if (what == EA_LOADS) {
656 offset = cpu_ldsb_code(env, s->pc + 1);
657 } else {
658 offset = cpu_ldub_code(env, s->pc + 1);
659 }
660 s->pc += 2;
661 break;
662 case OS_WORD:
663 if (what == EA_LOADS) {
664 offset = cpu_ldsw_code(env, s->pc);
665 } else {
666 offset = cpu_lduw_code(env, s->pc);
667 }
668 s->pc += 2;
669 break;
670 case OS_LONG:
671 offset = read_im32(env, s);
672 break;
673 default:
674 qemu_assert(0, "Bad immediate operand");
675 }
676 return tcg_const_i32(offset);
677 default:
678 return NULL_QREG;
679 }
680 }
681 /* Should never happen. */
682 return NULL_QREG;
683 }
684
685 /* This generates a conditional branch, clobbering all temporaries. */
686 static void gen_jmpcc(DisasContext *s, int cond, int l1)
687 {
688 TCGv tmp;
689
690 /* TODO: Optimize compare/branch pairs rather than always flushing
691 flag state to CC_OP_FLAGS. */
692 gen_flush_flags(s);
693 switch (cond) {
694 case 0: /* T */
695 tcg_gen_br(l1);
696 break;
697 case 1: /* F */
698 break;
699 case 2: /* HI (!C && !Z) */
700 tmp = tcg_temp_new();
701 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
702 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
703 break;
704 case 3: /* LS (C || Z) */
705 tmp = tcg_temp_new();
706 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
707 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
708 break;
709 case 4: /* CC (!C) */
710 tmp = tcg_temp_new();
711 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
712 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
713 break;
714 case 5: /* CS (C) */
715 tmp = tcg_temp_new();
716 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
717 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
718 break;
719 case 6: /* NE (!Z) */
720 tmp = tcg_temp_new();
721 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
722 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
723 break;
724 case 7: /* EQ (Z) */
725 tmp = tcg_temp_new();
726 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
727 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
728 break;
729 case 8: /* VC (!V) */
730 tmp = tcg_temp_new();
731 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
733 break;
734 case 9: /* VS (V) */
735 tmp = tcg_temp_new();
736 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
737 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
738 break;
739 case 10: /* PL (!N) */
740 tmp = tcg_temp_new();
741 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
742 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
743 break;
744 case 11: /* MI (N) */
745 tmp = tcg_temp_new();
746 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
747 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
748 break;
749 case 12: /* GE (!(N ^ V)) */
750 tmp = tcg_temp_new();
751 assert(CCF_V == (CCF_N >> 2));
752 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
753 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
754 tcg_gen_andi_i32(tmp, tmp, CCF_V);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
756 break;
757 case 13: /* LT (N ^ V) */
758 tmp = tcg_temp_new();
759 assert(CCF_V == (CCF_N >> 2));
760 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
761 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
762 tcg_gen_andi_i32(tmp, tmp, CCF_V);
763 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
764 break;
765 case 14: /* GT (!(Z || (N ^ V))) */
766 tmp = tcg_temp_new();
767 assert(CCF_V == (CCF_N >> 2));
768 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
769 tcg_gen_shri_i32(tmp, tmp, 2);
770 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
771 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
772 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
773 break;
774 case 15: /* LE (Z || (N ^ V)) */
775 tmp = tcg_temp_new();
776 assert(CCF_V == (CCF_N >> 2));
777 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
778 tcg_gen_shri_i32(tmp, tmp, 2);
779 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
780 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
781 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
782 break;
783 default:
784 /* Should ever happen. */
785 abort();
786 }
787 }
788
789 DISAS_INSN(scc)
790 {
791 int l1;
792 int cond;
793 TCGv reg;
794
795 l1 = gen_new_label();
796 cond = (insn >> 8) & 0xf;
797 reg = DREG(insn, 0);
798 tcg_gen_andi_i32(reg, reg, 0xffffff00);
799 /* This is safe because we modify the reg directly, with no other values
800 live. */
801 gen_jmpcc(s, cond ^ 1, l1);
802 tcg_gen_ori_i32(reg, reg, 0xff);
803 gen_set_label(l1);
804 }
805
806 /* Force a TB lookup after an instruction that changes the CPU state. */
807 static void gen_lookup_tb(DisasContext *s)
808 {
809 gen_flush_cc_op(s);
810 tcg_gen_movi_i32(QREG_PC, s->pc);
811 s->is_jmp = DISAS_UPDATE;
812 }
813
814 /* Generate a jump to an immediate address. */
815 static void gen_jmp_im(DisasContext *s, uint32_t dest)
816 {
817 gen_flush_cc_op(s);
818 tcg_gen_movi_i32(QREG_PC, dest);
819 s->is_jmp = DISAS_JUMP;
820 }
821
822 /* Generate a jump to the address in qreg DEST. */
823 static void gen_jmp(DisasContext *s, TCGv dest)
824 {
825 gen_flush_cc_op(s);
826 tcg_gen_mov_i32(QREG_PC, dest);
827 s->is_jmp = DISAS_JUMP;
828 }
829
830 static void gen_exception(DisasContext *s, uint32_t where, int nr)
831 {
832 gen_flush_cc_op(s);
833 gen_jmp_im(s, where);
834 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
835 }
836
837 static inline void gen_addr_fault(DisasContext *s)
838 {
839 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
840 }
841
842 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
843 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
844 op_sign ? EA_LOADS : EA_LOADU); \
845 if (IS_NULL_QREG(result)) { \
846 gen_addr_fault(s); \
847 return; \
848 } \
849 } while (0)
850
851 #define DEST_EA(env, insn, opsize, val, addrp) do { \
852 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
853 if (IS_NULL_QREG(ea_result)) { \
854 gen_addr_fault(s); \
855 return; \
856 } \
857 } while (0)
858
859 /* Generate a jump to an immediate address. */
860 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
861 {
862 TranslationBlock *tb;
863
864 tb = s->tb;
865 if (unlikely(s->singlestep_enabled)) {
866 gen_exception(s, dest, EXCP_DEBUG);
867 } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
868 (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
869 tcg_gen_goto_tb(n);
870 tcg_gen_movi_i32(QREG_PC, dest);
871 tcg_gen_exit_tb((uintptr_t)tb + n);
872 } else {
873 gen_jmp_im(s, dest);
874 tcg_gen_exit_tb(0);
875 }
876 s->is_jmp = DISAS_TB_JUMP;
877 }
878
879 DISAS_INSN(undef_mac)
880 {
881 gen_exception(s, s->pc - 2, EXCP_LINEA);
882 }
883
884 DISAS_INSN(undef_fpu)
885 {
886 gen_exception(s, s->pc - 2, EXCP_LINEF);
887 }
888
889 static void QEMU_NORETURN disas_undef(CPUM68KState *env,
890 DisasContext *s, uint16_t insn);
891 DISAS_INSN(undef)
892 {
893 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
894 cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
895 }
896
897 DISAS_INSN(mulw)
898 {
899 TCGv reg;
900 TCGv tmp;
901 TCGv src;
902 int sign;
903
904 sign = (insn & 0x100) != 0;
905 reg = DREG(insn, 9);
906 tmp = tcg_temp_new();
907 if (sign)
908 tcg_gen_ext16s_i32(tmp, reg);
909 else
910 tcg_gen_ext16u_i32(tmp, reg);
911 SRC_EA(env, src, OS_WORD, sign, NULL);
912 tcg_gen_mul_i32(tmp, tmp, src);
913 tcg_gen_mov_i32(reg, tmp);
914 /* Unlike m68k, coldfire always clears the overflow bit. */
915 gen_logic_cc(s, tmp);
916 }
917
918 DISAS_INSN(divw)
919 {
920 TCGv reg;
921 TCGv tmp;
922 TCGv src;
923 int sign;
924
925 sign = (insn & 0x100) != 0;
926 reg = DREG(insn, 9);
927 if (sign) {
928 tcg_gen_ext16s_i32(QREG_DIV1, reg);
929 } else {
930 tcg_gen_ext16u_i32(QREG_DIV1, reg);
931 }
932 SRC_EA(env, src, OS_WORD, sign, NULL);
933 tcg_gen_mov_i32(QREG_DIV2, src);
934 if (sign) {
935 gen_helper_divs(cpu_env, tcg_const_i32(1));
936 } else {
937 gen_helper_divu(cpu_env, tcg_const_i32(1));
938 }
939
940 tmp = tcg_temp_new();
941 src = tcg_temp_new();
942 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
943 tcg_gen_shli_i32(src, QREG_DIV2, 16);
944 tcg_gen_or_i32(reg, tmp, src);
945 s->cc_op = CC_OP_FLAGS;
946 }
947
948 DISAS_INSN(divl)
949 {
950 TCGv num;
951 TCGv den;
952 TCGv reg;
953 uint16_t ext;
954
955 ext = cpu_lduw_code(env, s->pc);
956 s->pc += 2;
957 if (ext & 0x87f8) {
958 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
959 return;
960 }
961 num = DREG(ext, 12);
962 reg = DREG(ext, 0);
963 tcg_gen_mov_i32(QREG_DIV1, num);
964 SRC_EA(env, den, OS_LONG, 0, NULL);
965 tcg_gen_mov_i32(QREG_DIV2, den);
966 if (ext & 0x0800) {
967 gen_helper_divs(cpu_env, tcg_const_i32(0));
968 } else {
969 gen_helper_divu(cpu_env, tcg_const_i32(0));
970 }
971 if ((ext & 7) == ((ext >> 12) & 7)) {
972 /* div */
973 tcg_gen_mov_i32 (reg, QREG_DIV1);
974 } else {
975 /* rem */
976 tcg_gen_mov_i32 (reg, QREG_DIV2);
977 }
978 s->cc_op = CC_OP_FLAGS;
979 }
980
981 DISAS_INSN(addsub)
982 {
983 TCGv reg;
984 TCGv dest;
985 TCGv src;
986 TCGv tmp;
987 TCGv addr;
988 int add;
989
990 add = (insn & 0x4000) != 0;
991 reg = DREG(insn, 9);
992 dest = tcg_temp_new();
993 if (insn & 0x100) {
994 SRC_EA(env, tmp, OS_LONG, 0, &addr);
995 src = reg;
996 } else {
997 tmp = reg;
998 SRC_EA(env, src, OS_LONG, 0, NULL);
999 }
1000 if (add) {
1001 tcg_gen_add_i32(dest, tmp, src);
1002 gen_helper_xflag_lt(QREG_CC_X, dest, src);
1003 s->cc_op = CC_OP_ADD;
1004 } else {
1005 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
1006 tcg_gen_sub_i32(dest, tmp, src);
1007 s->cc_op = CC_OP_SUB;
1008 }
1009 gen_update_cc_add(dest, src);
1010 if (insn & 0x100) {
1011 DEST_EA(env, insn, OS_LONG, dest, &addr);
1012 } else {
1013 tcg_gen_mov_i32(reg, dest);
1014 }
1015 }
1016
1017
1018 /* Reverse the order of the bits in REG. */
1019 DISAS_INSN(bitrev)
1020 {
1021 TCGv reg;
1022 reg = DREG(insn, 0);
1023 gen_helper_bitrev(reg, reg);
1024 }
1025
1026 DISAS_INSN(bitop_reg)
1027 {
1028 int opsize;
1029 int op;
1030 TCGv src1;
1031 TCGv src2;
1032 TCGv tmp;
1033 TCGv addr;
1034 TCGv dest;
1035
1036 if ((insn & 0x38) != 0)
1037 opsize = OS_BYTE;
1038 else
1039 opsize = OS_LONG;
1040 op = (insn >> 6) & 3;
1041 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1042 src2 = DREG(insn, 9);
1043 dest = tcg_temp_new();
1044
1045 gen_flush_flags(s);
1046 tmp = tcg_temp_new();
1047 if (opsize == OS_BYTE)
1048 tcg_gen_andi_i32(tmp, src2, 7);
1049 else
1050 tcg_gen_andi_i32(tmp, src2, 31);
1051 src2 = tmp;
1052 tmp = tcg_temp_new();
1053 tcg_gen_shr_i32(tmp, src1, src2);
1054 tcg_gen_andi_i32(tmp, tmp, 1);
1055 tcg_gen_shli_i32(tmp, tmp, 2);
1056 /* Clear CCF_Z if bit set. */
1057 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1058 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1059
1060 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1061 switch (op) {
1062 case 1: /* bchg */
1063 tcg_gen_xor_i32(dest, src1, tmp);
1064 break;
1065 case 2: /* bclr */
1066 tcg_gen_not_i32(tmp, tmp);
1067 tcg_gen_and_i32(dest, src1, tmp);
1068 break;
1069 case 3: /* bset */
1070 tcg_gen_or_i32(dest, src1, tmp);
1071 break;
1072 default: /* btst */
1073 break;
1074 }
1075 if (op)
1076 DEST_EA(env, insn, opsize, dest, &addr);
1077 }
1078
1079 DISAS_INSN(sats)
1080 {
1081 TCGv reg;
1082 reg = DREG(insn, 0);
1083 gen_flush_flags(s);
1084 gen_helper_sats(reg, reg, QREG_CC_DEST);
1085 gen_logic_cc(s, reg);
1086 }
1087
1088 static void gen_push(DisasContext *s, TCGv val)
1089 {
1090 TCGv tmp;
1091
1092 tmp = tcg_temp_new();
1093 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1094 gen_store(s, OS_LONG, tmp, val);
1095 tcg_gen_mov_i32(QREG_SP, tmp);
1096 }
1097
1098 DISAS_INSN(movem)
1099 {
1100 TCGv addr;
1101 int i;
1102 uint16_t mask;
1103 TCGv reg;
1104 TCGv tmp;
1105 int is_load;
1106
1107 mask = cpu_lduw_code(env, s->pc);
1108 s->pc += 2;
1109 tmp = gen_lea(env, s, insn, OS_LONG);
1110 if (IS_NULL_QREG(tmp)) {
1111 gen_addr_fault(s);
1112 return;
1113 }
1114 addr = tcg_temp_new();
1115 tcg_gen_mov_i32(addr, tmp);
1116 is_load = ((insn & 0x0400) != 0);
1117 for (i = 0; i < 16; i++, mask >>= 1) {
1118 if (mask & 1) {
1119 if (i < 8)
1120 reg = DREG(i, 0);
1121 else
1122 reg = AREG(i, 0);
1123 if (is_load) {
1124 tmp = gen_load(s, OS_LONG, addr, 0);
1125 tcg_gen_mov_i32(reg, tmp);
1126 } else {
1127 gen_store(s, OS_LONG, addr, reg);
1128 }
1129 if (mask != 1)
1130 tcg_gen_addi_i32(addr, addr, 4);
1131 }
1132 }
1133 }
1134
1135 DISAS_INSN(bitop_im)
1136 {
1137 int opsize;
1138 int op;
1139 TCGv src1;
1140 uint32_t mask;
1141 int bitnum;
1142 TCGv tmp;
1143 TCGv addr;
1144
1145 if ((insn & 0x38) != 0)
1146 opsize = OS_BYTE;
1147 else
1148 opsize = OS_LONG;
1149 op = (insn >> 6) & 3;
1150
1151 bitnum = cpu_lduw_code(env, s->pc);
1152 s->pc += 2;
1153 if (bitnum & 0xff00) {
1154 disas_undef(env, s, insn);
1155 return;
1156 }
1157
1158 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1159
1160 gen_flush_flags(s);
1161 if (opsize == OS_BYTE)
1162 bitnum &= 7;
1163 else
1164 bitnum &= 31;
1165 mask = 1 << bitnum;
1166
1167 tmp = tcg_temp_new();
1168 assert (CCF_Z == (1 << 2));
1169 if (bitnum > 2)
1170 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1171 else if (bitnum < 2)
1172 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1173 else
1174 tcg_gen_mov_i32(tmp, src1);
1175 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1176 /* Clear CCF_Z if bit set. */
1177 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1178 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1179 if (op) {
1180 switch (op) {
1181 case 1: /* bchg */
1182 tcg_gen_xori_i32(tmp, src1, mask);
1183 break;
1184 case 2: /* bclr */
1185 tcg_gen_andi_i32(tmp, src1, ~mask);
1186 break;
1187 case 3: /* bset */
1188 tcg_gen_ori_i32(tmp, src1, mask);
1189 break;
1190 default: /* btst */
1191 break;
1192 }
1193 DEST_EA(env, insn, opsize, tmp, &addr);
1194 }
1195 }
1196
1197 DISAS_INSN(arith_im)
1198 {
1199 int op;
1200 uint32_t im;
1201 TCGv src1;
1202 TCGv dest;
1203 TCGv addr;
1204
1205 op = (insn >> 9) & 7;
1206 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1207 im = read_im32(env, s);
1208 dest = tcg_temp_new();
1209 switch (op) {
1210 case 0: /* ori */
1211 tcg_gen_ori_i32(dest, src1, im);
1212 gen_logic_cc(s, dest);
1213 break;
1214 case 1: /* andi */
1215 tcg_gen_andi_i32(dest, src1, im);
1216 gen_logic_cc(s, dest);
1217 break;
1218 case 2: /* subi */
1219 tcg_gen_mov_i32(dest, src1);
1220 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1221 tcg_gen_subi_i32(dest, dest, im);
1222 gen_update_cc_add(dest, tcg_const_i32(im));
1223 s->cc_op = CC_OP_SUB;
1224 break;
1225 case 3: /* addi */
1226 tcg_gen_mov_i32(dest, src1);
1227 tcg_gen_addi_i32(dest, dest, im);
1228 gen_update_cc_add(dest, tcg_const_i32(im));
1229 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1230 s->cc_op = CC_OP_ADD;
1231 break;
1232 case 5: /* eori */
1233 tcg_gen_xori_i32(dest, src1, im);
1234 gen_logic_cc(s, dest);
1235 break;
1236 case 6: /* cmpi */
1237 tcg_gen_mov_i32(dest, src1);
1238 tcg_gen_subi_i32(dest, dest, im);
1239 gen_update_cc_add(dest, tcg_const_i32(im));
1240 s->cc_op = CC_OP_SUB;
1241 break;
1242 default:
1243 abort();
1244 }
1245 if (op != 6) {
1246 DEST_EA(env, insn, OS_LONG, dest, &addr);
1247 }
1248 }
1249
1250 DISAS_INSN(byterev)
1251 {
1252 TCGv reg;
1253
1254 reg = DREG(insn, 0);
1255 tcg_gen_bswap32_i32(reg, reg);
1256 }
1257
1258 DISAS_INSN(move)
1259 {
1260 TCGv src;
1261 TCGv dest;
1262 int op;
1263 int opsize;
1264
1265 switch (insn >> 12) {
1266 case 1: /* move.b */
1267 opsize = OS_BYTE;
1268 break;
1269 case 2: /* move.l */
1270 opsize = OS_LONG;
1271 break;
1272 case 3: /* move.w */
1273 opsize = OS_WORD;
1274 break;
1275 default:
1276 abort();
1277 }
1278 SRC_EA(env, src, opsize, 1, NULL);
1279 op = (insn >> 6) & 7;
1280 if (op == 1) {
1281 /* movea */
1282 /* The value will already have been sign extended. */
1283 dest = AREG(insn, 9);
1284 tcg_gen_mov_i32(dest, src);
1285 } else {
1286 /* normal move */
1287 uint16_t dest_ea;
1288 dest_ea = ((insn >> 9) & 7) | (op << 3);
1289 DEST_EA(env, dest_ea, opsize, src, NULL);
1290 /* This will be correct because loads sign extend. */
1291 gen_logic_cc(s, src);
1292 }
1293 }
1294
1295 DISAS_INSN(negx)
1296 {
1297 TCGv reg;
1298
1299 gen_flush_flags(s);
1300 reg = DREG(insn, 0);
1301 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1302 }
1303
1304 DISAS_INSN(lea)
1305 {
1306 TCGv reg;
1307 TCGv tmp;
1308
1309 reg = AREG(insn, 9);
1310 tmp = gen_lea(env, s, insn, OS_LONG);
1311 if (IS_NULL_QREG(tmp)) {
1312 gen_addr_fault(s);
1313 return;
1314 }
1315 tcg_gen_mov_i32(reg, tmp);
1316 }
1317
1318 DISAS_INSN(clr)
1319 {
1320 int opsize;
1321
1322 switch ((insn >> 6) & 3) {
1323 case 0: /* clr.b */
1324 opsize = OS_BYTE;
1325 break;
1326 case 1: /* clr.w */
1327 opsize = OS_WORD;
1328 break;
1329 case 2: /* clr.l */
1330 opsize = OS_LONG;
1331 break;
1332 default:
1333 abort();
1334 }
1335 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1336 gen_logic_cc(s, tcg_const_i32(0));
1337 }
1338
1339 static TCGv gen_get_ccr(DisasContext *s)
1340 {
1341 TCGv dest;
1342
1343 gen_flush_flags(s);
1344 dest = tcg_temp_new();
1345 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1346 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1347 return dest;
1348 }
1349
1350 DISAS_INSN(move_from_ccr)
1351 {
1352 TCGv reg;
1353 TCGv ccr;
1354
1355 ccr = gen_get_ccr(s);
1356 reg = DREG(insn, 0);
1357 gen_partset_reg(OS_WORD, reg, ccr);
1358 }
1359
1360 DISAS_INSN(neg)
1361 {
1362 TCGv reg;
1363 TCGv src1;
1364
1365 reg = DREG(insn, 0);
1366 src1 = tcg_temp_new();
1367 tcg_gen_mov_i32(src1, reg);
1368 tcg_gen_neg_i32(reg, src1);
1369 s->cc_op = CC_OP_SUB;
1370 gen_update_cc_add(reg, src1);
1371 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1372 s->cc_op = CC_OP_SUB;
1373 }
1374
1375 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1376 {
1377 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1378 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1379 if (!ccr_only) {
1380 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1381 }
1382 }
1383
1384 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1385 int ccr_only)
1386 {
1387 TCGv tmp;
1388 TCGv reg;
1389
1390 s->cc_op = CC_OP_FLAGS;
1391 if ((insn & 0x38) == 0)
1392 {
1393 tmp = tcg_temp_new();
1394 reg = DREG(insn, 0);
1395 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1396 tcg_gen_shri_i32(tmp, reg, 4);
1397 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1398 if (!ccr_only) {
1399 gen_helper_set_sr(cpu_env, reg);
1400 }
1401 }
1402 else if ((insn & 0x3f) == 0x3c)
1403 {
1404 uint16_t val;
1405 val = cpu_lduw_code(env, s->pc);
1406 s->pc += 2;
1407 gen_set_sr_im(s, val, ccr_only);
1408 }
1409 else
1410 disas_undef(env, s, insn);
1411 }
1412
1413 DISAS_INSN(move_to_ccr)
1414 {
1415 gen_set_sr(env, s, insn, 1);
1416 }
1417
1418 DISAS_INSN(not)
1419 {
1420 TCGv reg;
1421
1422 reg = DREG(insn, 0);
1423 tcg_gen_not_i32(reg, reg);
1424 gen_logic_cc(s, reg);
1425 }
1426
1427 DISAS_INSN(swap)
1428 {
1429 TCGv src1;
1430 TCGv src2;
1431 TCGv reg;
1432
1433 src1 = tcg_temp_new();
1434 src2 = tcg_temp_new();
1435 reg = DREG(insn, 0);
1436 tcg_gen_shli_i32(src1, reg, 16);
1437 tcg_gen_shri_i32(src2, reg, 16);
1438 tcg_gen_or_i32(reg, src1, src2);
1439 gen_logic_cc(s, reg);
1440 }
1441
1442 DISAS_INSN(pea)
1443 {
1444 TCGv tmp;
1445
1446 tmp = gen_lea(env, s, insn, OS_LONG);
1447 if (IS_NULL_QREG(tmp)) {
1448 gen_addr_fault(s);
1449 return;
1450 }
1451 gen_push(s, tmp);
1452 }
1453
1454 DISAS_INSN(ext)
1455 {
1456 int op;
1457 TCGv reg;
1458 TCGv tmp;
1459
1460 reg = DREG(insn, 0);
1461 op = (insn >> 6) & 7;
1462 tmp = tcg_temp_new();
1463 if (op == 3)
1464 tcg_gen_ext16s_i32(tmp, reg);
1465 else
1466 tcg_gen_ext8s_i32(tmp, reg);
1467 if (op == 2)
1468 gen_partset_reg(OS_WORD, reg, tmp);
1469 else
1470 tcg_gen_mov_i32(reg, tmp);
1471 gen_logic_cc(s, tmp);
1472 }
1473
1474 DISAS_INSN(tst)
1475 {
1476 int opsize;
1477 TCGv tmp;
1478
1479 switch ((insn >> 6) & 3) {
1480 case 0: /* tst.b */
1481 opsize = OS_BYTE;
1482 break;
1483 case 1: /* tst.w */
1484 opsize = OS_WORD;
1485 break;
1486 case 2: /* tst.l */
1487 opsize = OS_LONG;
1488 break;
1489 default:
1490 abort();
1491 }
1492 SRC_EA(env, tmp, opsize, 1, NULL);
1493 gen_logic_cc(s, tmp);
1494 }
1495
1496 DISAS_INSN(pulse)
1497 {
1498 /* Implemented as a NOP. */
1499 }
1500
1501 DISAS_INSN(illegal)
1502 {
1503 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1504 }
1505
1506 /* ??? This should be atomic. */
1507 DISAS_INSN(tas)
1508 {
1509 TCGv dest;
1510 TCGv src1;
1511 TCGv addr;
1512
1513 dest = tcg_temp_new();
1514 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1515 gen_logic_cc(s, src1);
1516 tcg_gen_ori_i32(dest, src1, 0x80);
1517 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1518 }
1519
1520 DISAS_INSN(mull)
1521 {
1522 uint16_t ext;
1523 TCGv reg;
1524 TCGv src1;
1525 TCGv dest;
1526
1527 /* The upper 32 bits of the product are discarded, so
1528 muls.l and mulu.l are functionally equivalent. */
1529 ext = cpu_lduw_code(env, s->pc);
1530 s->pc += 2;
1531 if (ext & 0x87ff) {
1532 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1533 return;
1534 }
1535 reg = DREG(ext, 12);
1536 SRC_EA(env, src1, OS_LONG, 0, NULL);
1537 dest = tcg_temp_new();
1538 tcg_gen_mul_i32(dest, src1, reg);
1539 tcg_gen_mov_i32(reg, dest);
1540 /* Unlike m68k, coldfire always clears the overflow bit. */
1541 gen_logic_cc(s, dest);
1542 }
1543
1544 DISAS_INSN(link)
1545 {
1546 int16_t offset;
1547 TCGv reg;
1548 TCGv tmp;
1549
1550 offset = cpu_ldsw_code(env, s->pc);
1551 s->pc += 2;
1552 reg = AREG(insn, 0);
1553 tmp = tcg_temp_new();
1554 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1555 gen_store(s, OS_LONG, tmp, reg);
1556 if ((insn & 7) != 7)
1557 tcg_gen_mov_i32(reg, tmp);
1558 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1559 }
1560
1561 DISAS_INSN(unlk)
1562 {
1563 TCGv src;
1564 TCGv reg;
1565 TCGv tmp;
1566
1567 src = tcg_temp_new();
1568 reg = AREG(insn, 0);
1569 tcg_gen_mov_i32(src, reg);
1570 tmp = gen_load(s, OS_LONG, src, 0);
1571 tcg_gen_mov_i32(reg, tmp);
1572 tcg_gen_addi_i32(QREG_SP, src, 4);
1573 }
1574
1575 DISAS_INSN(nop)
1576 {
1577 }
1578
1579 DISAS_INSN(rts)
1580 {
1581 TCGv tmp;
1582
1583 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1584 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1585 gen_jmp(s, tmp);
1586 }
1587
1588 DISAS_INSN(jump)
1589 {
1590 TCGv tmp;
1591
1592 /* Load the target address first to ensure correct exception
1593 behavior. */
1594 tmp = gen_lea(env, s, insn, OS_LONG);
1595 if (IS_NULL_QREG(tmp)) {
1596 gen_addr_fault(s);
1597 return;
1598 }
1599 if ((insn & 0x40) == 0) {
1600 /* jsr */
1601 gen_push(s, tcg_const_i32(s->pc));
1602 }
1603 gen_jmp(s, tmp);
1604 }
1605
1606 DISAS_INSN(addsubq)
1607 {
1608 TCGv src1;
1609 TCGv src2;
1610 TCGv dest;
1611 int val;
1612 TCGv addr;
1613
1614 SRC_EA(env, src1, OS_LONG, 0, &addr);
1615 val = (insn >> 9) & 7;
1616 if (val == 0)
1617 val = 8;
1618 dest = tcg_temp_new();
1619 tcg_gen_mov_i32(dest, src1);
1620 if ((insn & 0x38) == 0x08) {
1621 /* Don't update condition codes if the destination is an
1622 address register. */
1623 if (insn & 0x0100) {
1624 tcg_gen_subi_i32(dest, dest, val);
1625 } else {
1626 tcg_gen_addi_i32(dest, dest, val);
1627 }
1628 } else {
1629 src2 = tcg_const_i32(val);
1630 if (insn & 0x0100) {
1631 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1632 tcg_gen_subi_i32(dest, dest, val);
1633 s->cc_op = CC_OP_SUB;
1634 } else {
1635 tcg_gen_addi_i32(dest, dest, val);
1636 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1637 s->cc_op = CC_OP_ADD;
1638 }
1639 gen_update_cc_add(dest, src2);
1640 }
1641 DEST_EA(env, insn, OS_LONG, dest, &addr);
1642 }
1643
1644 DISAS_INSN(tpf)
1645 {
1646 switch (insn & 7) {
1647 case 2: /* One extension word. */
1648 s->pc += 2;
1649 break;
1650 case 3: /* Two extension words. */
1651 s->pc += 4;
1652 break;
1653 case 4: /* No extension words. */
1654 break;
1655 default:
1656 disas_undef(env, s, insn);
1657 }
1658 }
1659
1660 DISAS_INSN(branch)
1661 {
1662 int32_t offset;
1663 uint32_t base;
1664 int op;
1665 int l1;
1666
1667 base = s->pc;
1668 op = (insn >> 8) & 0xf;
1669 offset = (int8_t)insn;
1670 if (offset == 0) {
1671 offset = cpu_ldsw_code(env, s->pc);
1672 s->pc += 2;
1673 } else if (offset == -1) {
1674 offset = read_im32(env, s);
1675 }
1676 if (op == 1) {
1677 /* bsr */
1678 gen_push(s, tcg_const_i32(s->pc));
1679 }
1680 gen_flush_cc_op(s);
1681 if (op > 1) {
1682 /* Bcc */
1683 l1 = gen_new_label();
1684 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1685 gen_jmp_tb(s, 1, base + offset);
1686 gen_set_label(l1);
1687 gen_jmp_tb(s, 0, s->pc);
1688 } else {
1689 /* Unconditional branch. */
1690 gen_jmp_tb(s, 0, base + offset);
1691 }
1692 }
1693
1694 DISAS_INSN(moveq)
1695 {
1696 uint32_t val;
1697
1698 val = (int8_t)insn;
1699 tcg_gen_movi_i32(DREG(insn, 9), val);
1700 gen_logic_cc(s, tcg_const_i32(val));
1701 }
1702
1703 DISAS_INSN(mvzs)
1704 {
1705 int opsize;
1706 TCGv src;
1707 TCGv reg;
1708
1709 if (insn & 0x40)
1710 opsize = OS_WORD;
1711 else
1712 opsize = OS_BYTE;
1713 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1714 reg = DREG(insn, 9);
1715 tcg_gen_mov_i32(reg, src);
1716 gen_logic_cc(s, src);
1717 }
1718
1719 DISAS_INSN(or)
1720 {
1721 TCGv reg;
1722 TCGv dest;
1723 TCGv src;
1724 TCGv addr;
1725
1726 reg = DREG(insn, 9);
1727 dest = tcg_temp_new();
1728 if (insn & 0x100) {
1729 SRC_EA(env, src, OS_LONG, 0, &addr);
1730 tcg_gen_or_i32(dest, src, reg);
1731 DEST_EA(env, insn, OS_LONG, dest, &addr);
1732 } else {
1733 SRC_EA(env, src, OS_LONG, 0, NULL);
1734 tcg_gen_or_i32(dest, src, reg);
1735 tcg_gen_mov_i32(reg, dest);
1736 }
1737 gen_logic_cc(s, dest);
1738 }
1739
1740 DISAS_INSN(suba)
1741 {
1742 TCGv src;
1743 TCGv reg;
1744
1745 SRC_EA(env, src, OS_LONG, 0, NULL);
1746 reg = AREG(insn, 9);
1747 tcg_gen_sub_i32(reg, reg, src);
1748 }
1749
1750 DISAS_INSN(subx)
1751 {
1752 TCGv reg;
1753 TCGv src;
1754
1755 gen_flush_flags(s);
1756 reg = DREG(insn, 9);
1757 src = DREG(insn, 0);
1758 gen_helper_subx_cc(reg, cpu_env, reg, src);
1759 }
1760
1761 DISAS_INSN(mov3q)
1762 {
1763 TCGv src;
1764 int val;
1765
1766 val = (insn >> 9) & 7;
1767 if (val == 0)
1768 val = -1;
1769 src = tcg_const_i32(val);
1770 gen_logic_cc(s, src);
1771 DEST_EA(env, insn, OS_LONG, src, NULL);
1772 }
1773
1774 DISAS_INSN(cmp)
1775 {
1776 int op;
1777 TCGv src;
1778 TCGv reg;
1779 TCGv dest;
1780 int opsize;
1781
1782 op = (insn >> 6) & 3;
1783 switch (op) {
1784 case 0: /* cmp.b */
1785 opsize = OS_BYTE;
1786 s->cc_op = CC_OP_CMPB;
1787 break;
1788 case 1: /* cmp.w */
1789 opsize = OS_WORD;
1790 s->cc_op = CC_OP_CMPW;
1791 break;
1792 case 2: /* cmp.l */
1793 opsize = OS_LONG;
1794 s->cc_op = CC_OP_SUB;
1795 break;
1796 default:
1797 abort();
1798 }
1799 SRC_EA(env, src, opsize, 1, NULL);
1800 reg = DREG(insn, 9);
1801 dest = tcg_temp_new();
1802 tcg_gen_sub_i32(dest, reg, src);
1803 gen_update_cc_add(dest, src);
1804 }
1805
1806 DISAS_INSN(cmpa)
1807 {
1808 int opsize;
1809 TCGv src;
1810 TCGv reg;
1811 TCGv dest;
1812
1813 if (insn & 0x100) {
1814 opsize = OS_LONG;
1815 } else {
1816 opsize = OS_WORD;
1817 }
1818 SRC_EA(env, src, opsize, 1, NULL);
1819 reg = AREG(insn, 9);
1820 dest = tcg_temp_new();
1821 tcg_gen_sub_i32(dest, reg, src);
1822 gen_update_cc_add(dest, src);
1823 s->cc_op = CC_OP_SUB;
1824 }
1825
1826 DISAS_INSN(eor)
1827 {
1828 TCGv src;
1829 TCGv reg;
1830 TCGv dest;
1831 TCGv addr;
1832
1833 SRC_EA(env, src, OS_LONG, 0, &addr);
1834 reg = DREG(insn, 9);
1835 dest = tcg_temp_new();
1836 tcg_gen_xor_i32(dest, src, reg);
1837 gen_logic_cc(s, dest);
1838 DEST_EA(env, insn, OS_LONG, dest, &addr);
1839 }
1840
1841 DISAS_INSN(and)
1842 {
1843 TCGv src;
1844 TCGv reg;
1845 TCGv dest;
1846 TCGv addr;
1847
1848 reg = DREG(insn, 9);
1849 dest = tcg_temp_new();
1850 if (insn & 0x100) {
1851 SRC_EA(env, src, OS_LONG, 0, &addr);
1852 tcg_gen_and_i32(dest, src, reg);
1853 DEST_EA(env, insn, OS_LONG, dest, &addr);
1854 } else {
1855 SRC_EA(env, src, OS_LONG, 0, NULL);
1856 tcg_gen_and_i32(dest, src, reg);
1857 tcg_gen_mov_i32(reg, dest);
1858 }
1859 gen_logic_cc(s, dest);
1860 }
1861
1862 DISAS_INSN(adda)
1863 {
1864 TCGv src;
1865 TCGv reg;
1866
1867 SRC_EA(env, src, OS_LONG, 0, NULL);
1868 reg = AREG(insn, 9);
1869 tcg_gen_add_i32(reg, reg, src);
1870 }
1871
1872 DISAS_INSN(addx)
1873 {
1874 TCGv reg;
1875 TCGv src;
1876
1877 gen_flush_flags(s);
1878 reg = DREG(insn, 9);
1879 src = DREG(insn, 0);
1880 gen_helper_addx_cc(reg, cpu_env, reg, src);
1881 s->cc_op = CC_OP_FLAGS;
1882 }
1883
1884 /* TODO: This could be implemented without helper functions. */
1885 DISAS_INSN(shift_im)
1886 {
1887 TCGv reg;
1888 int tmp;
1889 TCGv shift;
1890
1891 reg = DREG(insn, 0);
1892 tmp = (insn >> 9) & 7;
1893 if (tmp == 0)
1894 tmp = 8;
1895 shift = tcg_const_i32(tmp);
1896 /* No need to flush flags becuse we know we will set C flag. */
1897 if (insn & 0x100) {
1898 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1899 } else {
1900 if (insn & 8) {
1901 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1902 } else {
1903 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1904 }
1905 }
1906 s->cc_op = CC_OP_SHIFT;
1907 }
1908
1909 DISAS_INSN(shift_reg)
1910 {
1911 TCGv reg;
1912 TCGv shift;
1913
1914 reg = DREG(insn, 0);
1915 shift = DREG(insn, 9);
1916 /* Shift by zero leaves C flag unmodified. */
1917 gen_flush_flags(s);
1918 if (insn & 0x100) {
1919 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1920 } else {
1921 if (insn & 8) {
1922 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1923 } else {
1924 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1925 }
1926 }
1927 s->cc_op = CC_OP_SHIFT;
1928 }
1929
1930 DISAS_INSN(ff1)
1931 {
1932 TCGv reg;
1933 reg = DREG(insn, 0);
1934 gen_logic_cc(s, reg);
1935 gen_helper_ff1(reg, reg);
1936 }
1937
1938 static TCGv gen_get_sr(DisasContext *s)
1939 {
1940 TCGv ccr;
1941 TCGv sr;
1942
1943 ccr = gen_get_ccr(s);
1944 sr = tcg_temp_new();
1945 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1946 tcg_gen_or_i32(sr, sr, ccr);
1947 return sr;
1948 }
1949
1950 DISAS_INSN(strldsr)
1951 {
1952 uint16_t ext;
1953 uint32_t addr;
1954
1955 addr = s->pc - 2;
1956 ext = cpu_lduw_code(env, s->pc);
1957 s->pc += 2;
1958 if (ext != 0x46FC) {
1959 gen_exception(s, addr, EXCP_UNSUPPORTED);
1960 return;
1961 }
1962 ext = cpu_lduw_code(env, s->pc);
1963 s->pc += 2;
1964 if (IS_USER(s) || (ext & SR_S) == 0) {
1965 gen_exception(s, addr, EXCP_PRIVILEGE);
1966 return;
1967 }
1968 gen_push(s, gen_get_sr(s));
1969 gen_set_sr_im(s, ext, 0);
1970 }
1971
1972 DISAS_INSN(move_from_sr)
1973 {
1974 TCGv reg;
1975 TCGv sr;
1976
1977 if (IS_USER(s)) {
1978 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1979 return;
1980 }
1981 sr = gen_get_sr(s);
1982 reg = DREG(insn, 0);
1983 gen_partset_reg(OS_WORD, reg, sr);
1984 }
1985
1986 DISAS_INSN(move_to_sr)
1987 {
1988 if (IS_USER(s)) {
1989 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1990 return;
1991 }
1992 gen_set_sr(env, s, insn, 0);
1993 gen_lookup_tb(s);
1994 }
1995
1996 DISAS_INSN(move_from_usp)
1997 {
1998 if (IS_USER(s)) {
1999 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2000 return;
2001 }
2002 /* TODO: Implement USP. */
2003 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2004 }
2005
2006 DISAS_INSN(move_to_usp)
2007 {
2008 if (IS_USER(s)) {
2009 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2010 return;
2011 }
2012 /* TODO: Implement USP. */
2013 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2014 }
2015
2016 DISAS_INSN(halt)
2017 {
2018 gen_exception(s, s->pc, EXCP_HALT_INSN);
2019 }
2020
2021 DISAS_INSN(stop)
2022 {
2023 uint16_t ext;
2024
2025 if (IS_USER(s)) {
2026 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2027 return;
2028 }
2029
2030 ext = cpu_lduw_code(env, s->pc);
2031 s->pc += 2;
2032
2033 gen_set_sr_im(s, ext, 0);
2034 tcg_gen_movi_i32(cpu_halted, 1);
2035 gen_exception(s, s->pc, EXCP_HLT);
2036 }
2037
2038 DISAS_INSN(rte)
2039 {
2040 if (IS_USER(s)) {
2041 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2042 return;
2043 }
2044 gen_exception(s, s->pc - 2, EXCP_RTE);
2045 }
2046
2047 DISAS_INSN(movec)
2048 {
2049 uint16_t ext;
2050 TCGv reg;
2051
2052 if (IS_USER(s)) {
2053 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2054 return;
2055 }
2056
2057 ext = cpu_lduw_code(env, s->pc);
2058 s->pc += 2;
2059
2060 if (ext & 0x8000) {
2061 reg = AREG(ext, 12);
2062 } else {
2063 reg = DREG(ext, 12);
2064 }
2065 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2066 gen_lookup_tb(s);
2067 }
2068
2069 DISAS_INSN(intouch)
2070 {
2071 if (IS_USER(s)) {
2072 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2073 return;
2074 }
2075 /* ICache fetch. Implement as no-op. */
2076 }
2077
2078 DISAS_INSN(cpushl)
2079 {
2080 if (IS_USER(s)) {
2081 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2082 return;
2083 }
2084 /* Cache push/invalidate. Implement as no-op. */
2085 }
2086
2087 DISAS_INSN(wddata)
2088 {
2089 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2090 }
2091
2092 DISAS_INSN(wdebug)
2093 {
2094 if (IS_USER(s)) {
2095 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2096 return;
2097 }
2098 /* TODO: Implement wdebug. */
2099 qemu_assert(0, "WDEBUG not implemented");
2100 }
2101
2102 DISAS_INSN(trap)
2103 {
2104 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2105 }
2106
2107 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2108 immediately before the next FP instruction is executed. */
2109 DISAS_INSN(fpu)
2110 {
2111 uint16_t ext;
2112 int32_t offset;
2113 int opmode;
2114 TCGv_i64 src;
2115 TCGv_i64 dest;
2116 TCGv_i64 res;
2117 TCGv tmp32;
2118 int round;
2119 int set_dest;
2120 int opsize;
2121
2122 ext = cpu_lduw_code(env, s->pc);
2123 s->pc += 2;
2124 opmode = ext & 0x7f;
2125 switch ((ext >> 13) & 7) {
2126 case 0: case 2:
2127 break;
2128 case 1:
2129 goto undef;
2130 case 3: /* fmove out */
2131 src = FREG(ext, 7);
2132 tmp32 = tcg_temp_new_i32();
2133 /* fmove */
2134 /* ??? TODO: Proper behavior on overflow. */
2135 switch ((ext >> 10) & 7) {
2136 case 0:
2137 opsize = OS_LONG;
2138 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2139 break;
2140 case 1:
2141 opsize = OS_SINGLE;
2142 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2143 break;
2144 case 4:
2145 opsize = OS_WORD;
2146 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2147 break;
2148 case 5: /* OS_DOUBLE */
2149 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2150 switch ((insn >> 3) & 7) {
2151 case 2:
2152 case 3:
2153 break;
2154 case 4:
2155 tcg_gen_addi_i32(tmp32, tmp32, -8);
2156 break;
2157 case 5:
2158 offset = cpu_ldsw_code(env, s->pc);
2159 s->pc += 2;
2160 tcg_gen_addi_i32(tmp32, tmp32, offset);
2161 break;
2162 default:
2163 goto undef;
2164 }
2165 gen_store64(s, tmp32, src);
2166 switch ((insn >> 3) & 7) {
2167 case 3:
2168 tcg_gen_addi_i32(tmp32, tmp32, 8);
2169 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2170 break;
2171 case 4:
2172 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2173 break;
2174 }
2175 tcg_temp_free_i32(tmp32);
2176 return;
2177 case 6:
2178 opsize = OS_BYTE;
2179 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2180 break;
2181 default:
2182 goto undef;
2183 }
2184 DEST_EA(env, insn, opsize, tmp32, NULL);
2185 tcg_temp_free_i32(tmp32);
2186 return;
2187 case 4: /* fmove to control register. */
2188 switch ((ext >> 10) & 7) {
2189 case 4: /* FPCR */
2190 /* Not implemented. Ignore writes. */
2191 break;
2192 case 1: /* FPIAR */
2193 case 2: /* FPSR */
2194 default:
2195 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2196 (ext >> 10) & 7);
2197 }
2198 break;
2199 case 5: /* fmove from control register. */
2200 switch ((ext >> 10) & 7) {
2201 case 4: /* FPCR */
2202 /* Not implemented. Always return zero. */
2203 tmp32 = tcg_const_i32(0);
2204 break;
2205 case 1: /* FPIAR */
2206 case 2: /* FPSR */
2207 default:
2208 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2209 (ext >> 10) & 7);
2210 goto undef;
2211 }
2212 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2213 break;
2214 case 6: /* fmovem */
2215 case 7:
2216 {
2217 TCGv addr;
2218 uint16_t mask;
2219 int i;
2220 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2221 goto undef;
2222 tmp32 = gen_lea(env, s, insn, OS_LONG);
2223 if (IS_NULL_QREG(tmp32)) {
2224 gen_addr_fault(s);
2225 return;
2226 }
2227 addr = tcg_temp_new_i32();
2228 tcg_gen_mov_i32(addr, tmp32);
2229 mask = 0x80;
2230 for (i = 0; i < 8; i++) {
2231 if (ext & mask) {
2232 s->is_mem = 1;
2233 dest = FREG(i, 0);
2234 if (ext & (1 << 13)) {
2235 /* store */
2236 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2237 } else {
2238 /* load */
2239 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2240 }
2241 if (ext & (mask - 1))
2242 tcg_gen_addi_i32(addr, addr, 8);
2243 }
2244 mask >>= 1;
2245 }
2246 tcg_temp_free_i32(addr);
2247 }
2248 return;
2249 }
2250 if (ext & (1 << 14)) {
2251 /* Source effective address. */
2252 switch ((ext >> 10) & 7) {
2253 case 0: opsize = OS_LONG; break;
2254 case 1: opsize = OS_SINGLE; break;
2255 case 4: opsize = OS_WORD; break;
2256 case 5: opsize = OS_DOUBLE; break;
2257 case 6: opsize = OS_BYTE; break;
2258 default:
2259 goto undef;
2260 }
2261 if (opsize == OS_DOUBLE) {
2262 tmp32 = tcg_temp_new_i32();
2263 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2264 switch ((insn >> 3) & 7) {
2265 case 2:
2266 case 3:
2267 break;
2268 case 4:
2269 tcg_gen_addi_i32(tmp32, tmp32, -8);
2270 break;
2271 case 5:
2272 offset = cpu_ldsw_code(env, s->pc);
2273 s->pc += 2;
2274 tcg_gen_addi_i32(tmp32, tmp32, offset);
2275 break;
2276 case 7:
2277 offset = cpu_ldsw_code(env, s->pc);
2278 offset += s->pc - 2;
2279 s->pc += 2;
2280 tcg_gen_addi_i32(tmp32, tmp32, offset);
2281 break;
2282 default:
2283 goto undef;
2284 }
2285 src = gen_load64(s, tmp32);
2286 switch ((insn >> 3) & 7) {
2287 case 3:
2288 tcg_gen_addi_i32(tmp32, tmp32, 8);
2289 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2290 break;
2291 case 4:
2292 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2293 break;
2294 }
2295 tcg_temp_free_i32(tmp32);
2296 } else {
2297 SRC_EA(env, tmp32, opsize, 1, NULL);
2298 src = tcg_temp_new_i64();
2299 switch (opsize) {
2300 case OS_LONG:
2301 case OS_WORD:
2302 case OS_BYTE:
2303 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2304 break;
2305 case OS_SINGLE:
2306 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2307 break;
2308 }
2309 }
2310 } else {
2311 /* Source register. */
2312 src = FREG(ext, 10);
2313 }
2314 dest = FREG(ext, 7);
2315 res = tcg_temp_new_i64();
2316 if (opmode != 0x3a)
2317 tcg_gen_mov_f64(res, dest);
2318 round = 1;
2319 set_dest = 1;
2320 switch (opmode) {
2321 case 0: case 0x40: case 0x44: /* fmove */
2322 tcg_gen_mov_f64(res, src);
2323 break;
2324 case 1: /* fint */
2325 gen_helper_iround_f64(res, cpu_env, src);
2326 round = 0;
2327 break;
2328 case 3: /* fintrz */
2329 gen_helper_itrunc_f64(res, cpu_env, src);
2330 round = 0;
2331 break;
2332 case 4: case 0x41: case 0x45: /* fsqrt */
2333 gen_helper_sqrt_f64(res, cpu_env, src);
2334 break;
2335 case 0x18: case 0x58: case 0x5c: /* fabs */
2336 gen_helper_abs_f64(res, src);
2337 break;
2338 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2339 gen_helper_chs_f64(res, src);
2340 break;
2341 case 0x20: case 0x60: case 0x64: /* fdiv */
2342 gen_helper_div_f64(res, cpu_env, res, src);
2343 break;
2344 case 0x22: case 0x62: case 0x66: /* fadd */
2345 gen_helper_add_f64(res, cpu_env, res, src);
2346 break;
2347 case 0x23: case 0x63: case 0x67: /* fmul */
2348 gen_helper_mul_f64(res, cpu_env, res, src);
2349 break;
2350 case 0x28: case 0x68: case 0x6c: /* fsub */
2351 gen_helper_sub_f64(res, cpu_env, res, src);
2352 break;
2353 case 0x38: /* fcmp */
2354 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2355 set_dest = 0;
2356 round = 0;
2357 break;
2358 case 0x3a: /* ftst */
2359 tcg_gen_mov_f64(res, src);
2360 set_dest = 0;
2361 round = 0;
2362 break;
2363 default:
2364 goto undef;
2365 }
2366 if (ext & (1 << 14)) {
2367 tcg_temp_free_i64(src);
2368 }
2369 if (round) {
2370 if (opmode & 0x40) {
2371 if ((opmode & 0x4) != 0)
2372 round = 0;
2373 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2374 round = 0;
2375 }
2376 }
2377 if (round) {
2378 TCGv tmp = tcg_temp_new_i32();
2379 gen_helper_f64_to_f32(tmp, cpu_env, res);
2380 gen_helper_f32_to_f64(res, cpu_env, tmp);
2381 tcg_temp_free_i32(tmp);
2382 }
2383 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2384 if (set_dest) {
2385 tcg_gen_mov_f64(dest, res);
2386 }
2387 tcg_temp_free_i64(res);
2388 return;
2389 undef:
2390 /* FIXME: Is this right for offset addressing modes? */
2391 s->pc -= 2;
2392 disas_undef_fpu(env, s, insn);
2393 }
2394
2395 DISAS_INSN(fbcc)
2396 {
2397 uint32_t offset;
2398 uint32_t addr;
2399 TCGv flag;
2400 int l1;
2401
2402 addr = s->pc;
2403 offset = cpu_ldsw_code(env, s->pc);
2404 s->pc += 2;
2405 if (insn & (1 << 6)) {
2406 offset = (offset << 16) | cpu_lduw_code(env, s->pc);
2407 s->pc += 2;
2408 }
2409
2410 l1 = gen_new_label();
2411 /* TODO: Raise BSUN exception. */
2412 flag = tcg_temp_new();
2413 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2414 /* Jump to l1 if condition is true. */
2415 switch (insn & 0xf) {
2416 case 0: /* f */
2417 break;
2418 case 1: /* eq (=0) */
2419 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2420 break;
2421 case 2: /* ogt (=1) */
2422 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2423 break;
2424 case 3: /* oge (=0 or =1) */
2425 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2426 break;
2427 case 4: /* olt (=-1) */
2428 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2429 break;
2430 case 5: /* ole (=-1 or =0) */
2431 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2432 break;
2433 case 6: /* ogl (=-1 or =1) */
2434 tcg_gen_andi_i32(flag, flag, 1);
2435 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2436 break;
2437 case 7: /* or (=2) */
2438 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2439 break;
2440 case 8: /* un (<2) */
2441 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2442 break;
2443 case 9: /* ueq (=0 or =2) */
2444 tcg_gen_andi_i32(flag, flag, 1);
2445 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2446 break;
2447 case 10: /* ugt (>0) */
2448 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2449 break;
2450 case 11: /* uge (>=0) */
2451 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2452 break;
2453 case 12: /* ult (=-1 or =2) */
2454 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2455 break;
2456 case 13: /* ule (!=1) */
2457 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2458 break;
2459 case 14: /* ne (!=0) */
2460 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2461 break;
2462 case 15: /* t */
2463 tcg_gen_br(l1);
2464 break;
2465 }
2466 gen_jmp_tb(s, 0, s->pc);
2467 gen_set_label(l1);
2468 gen_jmp_tb(s, 1, addr + offset);
2469 }
2470
2471 static void QEMU_NORETURN disas_frestore(CPUM68KState *env,
2472 DisasContext *s, uint16_t insn);
2473 DISAS_INSN(frestore)
2474 {
2475 /* TODO: Implement frestore. */
2476 qemu_assert(0, "FRESTORE not implemented");
2477 abort();
2478 }
2479
2480 static void QEMU_NORETURN disas_fsave(CPUM68KState *env,
2481 DisasContext *s, uint16_t insn);
2482 DISAS_INSN(fsave)
2483 {
2484 /* TODO: Implement fsave. */
2485 qemu_assert(0, "FSAVE not implemented");
2486 abort();
2487 }
2488
2489 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2490 {
2491 TCGv tmp = tcg_temp_new();
2492 if (s->env->macsr & MACSR_FI) {
2493 if (upper)
2494 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2495 else
2496 tcg_gen_shli_i32(tmp, val, 16);
2497 } else if (s->env->macsr & MACSR_SU) {
2498 if (upper)
2499 tcg_gen_sari_i32(tmp, val, 16);
2500 else
2501 tcg_gen_ext16s_i32(tmp, val);
2502 } else {
2503 if (upper)
2504 tcg_gen_shri_i32(tmp, val, 16);
2505 else
2506 tcg_gen_ext16u_i32(tmp, val);
2507 }
2508 return tmp;
2509 }
2510
2511 static void gen_mac_clear_flags(void)
2512 {
2513 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2514 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2515 }
2516
2517 DISAS_INSN(mac)
2518 {
2519 TCGv rx;
2520 TCGv ry;
2521 uint16_t ext;
2522 int acc;
2523 TCGv tmp;
2524 TCGv addr;
2525 TCGv loadval;
2526 int dual;
2527 TCGv saved_flags;
2528
2529 if (!s->done_mac) {
2530 s->mactmp = tcg_temp_new_i64();
2531 s->done_mac = 1;
2532 }
2533
2534 ext = cpu_lduw_code(env, s->pc);
2535 s->pc += 2;
2536
2537 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2538 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2539 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2540 disas_undef(env, s, insn);
2541 return;
2542 }
2543 if (insn & 0x30) {
2544 /* MAC with load. */
2545 tmp = gen_lea(env, s, insn, OS_LONG);
2546 addr = tcg_temp_new();
2547 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2548 /* Load the value now to ensure correct exception behavior.
2549 Perform writeback after reading the MAC inputs. */
2550 loadval = gen_load(s, OS_LONG, addr, 0);
2551
2552 acc ^= 1;
2553 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2554 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2555 } else {
2556 loadval = addr = NULL_QREG;
2557 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2558 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2559 }
2560
2561 gen_mac_clear_flags();
2562 #if 0
2563 l1 = -1;
2564 /* Disabled because conditional branches clobber temporary vars. */
2565 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2566 /* Skip the multiply if we know we will ignore it. */
2567 l1 = gen_new_label();
2568 tmp = tcg_temp_new();
2569 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2570 gen_op_jmp_nz32(tmp, l1);
2571 }
2572 #endif
2573
2574 if ((ext & 0x0800) == 0) {
2575 /* Word. */
2576 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2577 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2578 }
2579 if (s->env->macsr & MACSR_FI) {
2580 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2581 } else {
2582 if (s->env->macsr & MACSR_SU)
2583 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2584 else
2585 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2586 switch ((ext >> 9) & 3) {
2587 case 1:
2588 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2589 break;
2590 case 3:
2591 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2592 break;
2593 }
2594 }
2595
2596 if (dual) {
2597 /* Save the overflow flag from the multiply. */
2598 saved_flags = tcg_temp_new();
2599 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2600 } else {
2601 saved_flags = NULL_QREG;
2602 }
2603
2604 #if 0
2605 /* Disabled because conditional branches clobber temporary vars. */
2606 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2607 /* Skip the accumulate if the value is already saturated. */
2608 l1 = gen_new_label();
2609 tmp = tcg_temp_new();
2610 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2611 gen_op_jmp_nz32(tmp, l1);
2612 }
2613 #endif
2614
2615 if (insn & 0x100)
2616 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2617 else
2618 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2619
2620 if (s->env->macsr & MACSR_FI)
2621 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2622 else if (s->env->macsr & MACSR_SU)
2623 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2624 else
2625 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2626
2627 #if 0
2628 /* Disabled because conditional branches clobber temporary vars. */
2629 if (l1 != -1)
2630 gen_set_label(l1);
2631 #endif
2632
2633 if (dual) {
2634 /* Dual accumulate variant. */
2635 acc = (ext >> 2) & 3;
2636 /* Restore the overflow flag from the multiplier. */
2637 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2638 #if 0
2639 /* Disabled because conditional branches clobber temporary vars. */
2640 if ((s->env->macsr & MACSR_OMC) != 0) {
2641 /* Skip the accumulate if the value is already saturated. */
2642 l1 = gen_new_label();
2643 tmp = tcg_temp_new();
2644 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2645 gen_op_jmp_nz32(tmp, l1);
2646 }
2647 #endif
2648 if (ext & 2)
2649 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2650 else
2651 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2652 if (s->env->macsr & MACSR_FI)
2653 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2654 else if (s->env->macsr & MACSR_SU)
2655 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2656 else
2657 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2658 #if 0
2659 /* Disabled because conditional branches clobber temporary vars. */
2660 if (l1 != -1)
2661 gen_set_label(l1);
2662 #endif
2663 }
2664 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2665
2666 if (insn & 0x30) {
2667 TCGv rw;
2668 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2669 tcg_gen_mov_i32(rw, loadval);
2670 /* FIXME: Should address writeback happen with the masked or
2671 unmasked value? */
2672 switch ((insn >> 3) & 7) {
2673 case 3: /* Post-increment. */
2674 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2675 break;
2676 case 4: /* Pre-decrement. */
2677 tcg_gen_mov_i32(AREG(insn, 0), addr);
2678 }
2679 }
2680 }
2681
2682 DISAS_INSN(from_mac)
2683 {
2684 TCGv rx;
2685 TCGv_i64 acc;
2686 int accnum;
2687
2688 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2689 accnum = (insn >> 9) & 3;
2690 acc = MACREG(accnum);
2691 if (s->env->macsr & MACSR_FI) {
2692 gen_helper_get_macf(rx, cpu_env, acc);
2693 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2694 tcg_gen_trunc_i64_i32(rx, acc);
2695 } else if (s->env->macsr & MACSR_SU) {
2696 gen_helper_get_macs(rx, acc);
2697 } else {
2698 gen_helper_get_macu(rx, acc);
2699 }
2700 if (insn & 0x40) {
2701 tcg_gen_movi_i64(acc, 0);
2702 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2703 }
2704 }
2705
2706 DISAS_INSN(move_mac)
2707 {
2708 /* FIXME: This can be done without a helper. */
2709 int src;
2710 TCGv dest;
2711 src = insn & 3;
2712 dest = tcg_const_i32((insn >> 9) & 3);
2713 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2714 gen_mac_clear_flags();
2715 gen_helper_mac_set_flags(cpu_env, dest);
2716 }
2717
2718 DISAS_INSN(from_macsr)
2719 {
2720 TCGv reg;
2721
2722 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2723 tcg_gen_mov_i32(reg, QREG_MACSR);
2724 }
2725
2726 DISAS_INSN(from_mask)
2727 {
2728 TCGv reg;
2729 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2730 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2731 }
2732
2733 DISAS_INSN(from_mext)
2734 {
2735 TCGv reg;
2736 TCGv acc;
2737 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2738 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2739 if (s->env->macsr & MACSR_FI)
2740 gen_helper_get_mac_extf(reg, cpu_env, acc);
2741 else
2742 gen_helper_get_mac_exti(reg, cpu_env, acc);
2743 }
2744
2745 DISAS_INSN(macsr_to_ccr)
2746 {
2747 tcg_gen_movi_i32(QREG_CC_X, 0);
2748 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2749 s->cc_op = CC_OP_FLAGS;
2750 }
2751
2752 DISAS_INSN(to_mac)
2753 {
2754 TCGv_i64 acc;
2755 TCGv val;
2756 int accnum;
2757 accnum = (insn >> 9) & 3;
2758 acc = MACREG(accnum);
2759 SRC_EA(env, val, OS_LONG, 0, NULL);
2760 if (s->env->macsr & MACSR_FI) {
2761 tcg_gen_ext_i32_i64(acc, val);
2762 tcg_gen_shli_i64(acc, acc, 8);
2763 } else if (s->env->macsr & MACSR_SU) {
2764 tcg_gen_ext_i32_i64(acc, val);
2765 } else {
2766 tcg_gen_extu_i32_i64(acc, val);
2767 }
2768 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2769 gen_mac_clear_flags();
2770 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2771 }
2772
2773 DISAS_INSN(to_macsr)
2774 {
2775 TCGv val;
2776 SRC_EA(env, val, OS_LONG, 0, NULL);
2777 gen_helper_set_macsr(cpu_env, val);
2778 gen_lookup_tb(s);
2779 }
2780
2781 DISAS_INSN(to_mask)
2782 {
2783 TCGv val;
2784 SRC_EA(env, val, OS_LONG, 0, NULL);
2785 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2786 }
2787
2788 DISAS_INSN(to_mext)
2789 {
2790 TCGv val;
2791 TCGv acc;
2792 SRC_EA(env, val, OS_LONG, 0, NULL);
2793 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2794 if (s->env->macsr & MACSR_FI)
2795 gen_helper_set_mac_extf(cpu_env, val, acc);
2796 else if (s->env->macsr & MACSR_SU)
2797 gen_helper_set_mac_exts(cpu_env, val, acc);
2798 else
2799 gen_helper_set_mac_extu(cpu_env, val, acc);
2800 }
2801
2802 static disas_proc opcode_table[65536];
2803
2804 static void
2805 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2806 {
2807 int i;
2808 int from;
2809 int to;
2810
2811 /* Sanity check. All set bits must be included in the mask. */
2812 if (opcode & ~mask) {
2813 fprintf(stderr,
2814 "qemu internal error: bogus opcode definition %04x/%04x\n",
2815 opcode, mask);
2816 abort();
2817 }
2818 /* This could probably be cleverer. For now just optimize the case where
2819 the top bits are known. */
2820 /* Find the first zero bit in the mask. */
2821 i = 0x8000;
2822 while ((i & mask) != 0)
2823 i >>= 1;
2824 /* Iterate over all combinations of this and lower bits. */
2825 if (i == 0)
2826 i = 1;
2827 else
2828 i <<= 1;
2829 from = opcode & ~(i - 1);
2830 to = from + i;
2831 for (i = from; i < to; i++) {
2832 if ((i & mask) == opcode)
2833 opcode_table[i] = proc;
2834 }
2835 }
2836
2837 /* Register m68k opcode handlers. Order is important.
2838 Later insn override earlier ones. */
2839 void register_m68k_insns (CPUM68KState *env)
2840 {
2841 #define INSN(name, opcode, mask, feature) do { \
2842 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2843 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2844 } while(0)
2845 INSN(undef, 0000, 0000, CF_ISA_A);
2846 INSN(arith_im, 0080, fff8, CF_ISA_A);
2847 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2848 INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
2849 INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
2850 INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
2851 INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
2852 INSN(arith_im, 0280, fff8, CF_ISA_A);
2853 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2854 INSN(arith_im, 0480, fff8, CF_ISA_A);
2855 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2856 INSN(arith_im, 0680, fff8, CF_ISA_A);
2857 INSN(bitop_im, 0800, ffc0, CF_ISA_A);
2858 INSN(bitop_im, 0840, ffc0, CF_ISA_A);
2859 INSN(bitop_im, 0880, ffc0, CF_ISA_A);
2860 INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
2861 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2862 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2863 INSN(move, 1000, f000, CF_ISA_A);
2864 INSN(move, 2000, f000, CF_ISA_A);
2865 INSN(move, 3000, f000, CF_ISA_A);
2866 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2867 INSN(negx, 4080, fff8, CF_ISA_A);
2868 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2869 INSN(lea, 41c0, f1c0, CF_ISA_A);
2870 INSN(clr, 4200, ff00, CF_ISA_A);
2871 INSN(undef, 42c0, ffc0, CF_ISA_A);
2872 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2873 INSN(neg, 4480, fff8, CF_ISA_A);
2874 INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
2875 INSN(not, 4680, fff8, CF_ISA_A);
2876 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2877 INSN(pea, 4840, ffc0, CF_ISA_A);
2878 INSN(swap, 4840, fff8, CF_ISA_A);
2879 INSN(movem, 48c0, fbc0, CF_ISA_A);
2880 INSN(ext, 4880, fff8, CF_ISA_A);
2881 INSN(ext, 48c0, fff8, CF_ISA_A);
2882 INSN(ext, 49c0, fff8, CF_ISA_A);
2883 INSN(tst, 4a00, ff00, CF_ISA_A);
2884 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2885 INSN(halt, 4ac8, ffff, CF_ISA_A);
2886 INSN(pulse, 4acc, ffff, CF_ISA_A);
2887 INSN(illegal, 4afc, ffff, CF_ISA_A);
2888 INSN(mull, 4c00, ffc0, CF_ISA_A);
2889 INSN(divl, 4c40, ffc0, CF_ISA_A);
2890 INSN(sats, 4c80, fff8, CF_ISA_B);
2891 INSN(trap, 4e40, fff0, CF_ISA_A);
2892 INSN(link, 4e50, fff8, CF_ISA_A);
2893 INSN(unlk, 4e58, fff8, CF_ISA_A);
2894 INSN(move_to_usp, 4e60, fff8, USP);
2895 INSN(move_from_usp, 4e68, fff8, USP);
2896 INSN(nop, 4e71, ffff, CF_ISA_A);
2897 INSN(stop, 4e72, ffff, CF_ISA_A);
2898 INSN(rte, 4e73, ffff, CF_ISA_A);
2899 INSN(rts, 4e75, ffff, CF_ISA_A);
2900 INSN(movec, 4e7b, ffff, CF_ISA_A);
2901 INSN(jump, 4e80, ffc0, CF_ISA_A);
2902 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2903 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2904 INSN(scc, 50c0, f0f8, CF_ISA_A);
2905 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2906 INSN(tpf, 51f8, fff8, CF_ISA_A);
2907
2908 /* Branch instructions. */
2909 INSN(branch, 6000, f000, CF_ISA_A);
2910 /* Disable long branch instructions, then add back the ones we want. */
2911 INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
2912 INSN(branch, 60ff, f0ff, CF_ISA_B);
2913 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2914 INSN(branch, 60ff, ffff, BRAL);
2915
2916 INSN(moveq, 7000, f100, CF_ISA_A);
2917 INSN(mvzs, 7100, f100, CF_ISA_B);
2918 INSN(or, 8000, f000, CF_ISA_A);
2919 INSN(divw, 80c0, f0c0, CF_ISA_A);
2920 INSN(addsub, 9000, f000, CF_ISA_A);
2921 INSN(subx, 9180, f1f8, CF_ISA_A);
2922 INSN(suba, 91c0, f1c0, CF_ISA_A);
2923
2924 INSN(undef_mac, a000, f000, CF_ISA_A);
2925 INSN(mac, a000, f100, CF_EMAC);
2926 INSN(from_mac, a180, f9b0, CF_EMAC);
2927 INSN(move_mac, a110, f9fc, CF_EMAC);
2928 INSN(from_macsr,a980, f9f0, CF_EMAC);
2929 INSN(from_mask, ad80, fff0, CF_EMAC);
2930 INSN(from_mext, ab80, fbf0, CF_EMAC);
2931 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2932 INSN(to_mac, a100, f9c0, CF_EMAC);
2933 INSN(to_macsr, a900, ffc0, CF_EMAC);
2934 INSN(to_mext, ab00, fbc0, CF_EMAC);
2935 INSN(to_mask, ad00, ffc0, CF_EMAC);
2936
2937 INSN(mov3q, a140, f1c0, CF_ISA_B);
2938 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2939 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2940 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2941 INSN(cmp, b080, f1c0, CF_ISA_A);
2942 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2943 INSN(eor, b180, f1c0, CF_ISA_A);
2944 INSN(and, c000, f000, CF_ISA_A);
2945 INSN(mulw, c0c0, f0c0, CF_ISA_A);
2946 INSN(addsub, d000, f000, CF_ISA_A);
2947 INSN(addx, d180, f1f8, CF_ISA_A);
2948 INSN(adda, d1c0, f1c0, CF_ISA_A);
2949 INSN(shift_im, e080, f0f0, CF_ISA_A);
2950 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2951 INSN(undef_fpu, f000, f000, CF_ISA_A);
2952 INSN(fpu, f200, ffc0, CF_FPU);
2953 INSN(fbcc, f280, ffc0, CF_FPU);
2954 INSN(frestore, f340, ffc0, CF_FPU);
2955 INSN(fsave, f340, ffc0, CF_FPU);
2956 INSN(intouch, f340, ffc0, CF_ISA_A);
2957 INSN(cpushl, f428, ff38, CF_ISA_A);
2958 INSN(wddata, fb00, ff00, CF_ISA_A);
2959 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2960 #undef INSN
2961 }
2962
2963 /* ??? Some of this implementation is not exception safe. We should always
2964 write back the result to memory before setting the condition codes. */
2965 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2966 {
2967 uint16_t insn;
2968
2969 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
2970 tcg_gen_debug_insn_start(s->pc);
2971 }
2972
2973 insn = cpu_lduw_code(env, s->pc);
2974 s->pc += 2;
2975
2976 opcode_table[insn](env, s, insn);
2977 }
2978
2979 /* generate intermediate code for basic block 'tb'. */
2980 static inline void
2981 gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
2982 bool search_pc)
2983 {
2984 CPUState *cs = CPU(cpu);
2985 CPUM68KState *env = &cpu->env;
2986 DisasContext dc1, *dc = &dc1;
2987 uint16_t *gen_opc_end;
2988 CPUBreakpoint *bp;
2989 int j, lj;
2990 target_ulong pc_start;
2991 int pc_offset;
2992 int num_insns;
2993 int max_insns;
2994
2995 /* generate intermediate code */
2996 pc_start = tb->pc;
2997
2998 dc->tb = tb;
2999
3000 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3001
3002 dc->env = env;
3003 dc->is_jmp = DISAS_NEXT;
3004 dc->pc = pc_start;
3005 dc->cc_op = CC_OP_DYNAMIC;
3006 dc->singlestep_enabled = cs->singlestep_enabled;
3007 dc->fpcr = env->fpcr;
3008 dc->user = (env->sr & SR_S) == 0;
3009 dc->is_mem = 0;
3010 dc->done_mac = 0;
3011 lj = -1;
3012 num_insns = 0;
3013 max_insns = tb->cflags & CF_COUNT_MASK;
3014 if (max_insns == 0)
3015 max_insns = CF_COUNT_MASK;
3016
3017 gen_tb_start();
3018 do {
3019 pc_offset = dc->pc - pc_start;
3020 gen_throws_exception = NULL;
3021 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3022 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3023 if (bp->pc == dc->pc) {
3024 gen_exception(dc, dc->pc, EXCP_DEBUG);
3025 dc->is_jmp = DISAS_JUMP;
3026 break;
3027 }
3028 }
3029 if (dc->is_jmp)
3030 break;
3031 }
3032 if (search_pc) {
3033 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3034 if (lj < j) {
3035 lj++;
3036 while (lj < j)
3037 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3038 }
3039 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3040 tcg_ctx.gen_opc_instr_start[lj] = 1;
3041 tcg_ctx.gen_opc_icount[lj] = num_insns;
3042 }
3043 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3044 gen_io_start();
3045 dc->insn_pc = dc->pc;
3046 disas_m68k_insn(env, dc);
3047 num_insns++;
3048 } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
3049 !cs->singlestep_enabled &&
3050 !singlestep &&
3051 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3052 num_insns < max_insns);
3053
3054 if (tb->cflags & CF_LAST_IO)
3055 gen_io_end();
3056 if (unlikely(cs->singlestep_enabled)) {
3057 /* Make sure the pc is updated, and raise a debug exception. */
3058 if (!dc->is_jmp) {
3059 gen_flush_cc_op(dc);
3060 tcg_gen_movi_i32(QREG_PC, dc->pc);
3061 }
3062 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3063 } else {
3064 switch(dc->is_jmp) {
3065 case DISAS_NEXT:
3066 gen_flush_cc_op(dc);
3067 gen_jmp_tb(dc, 0, dc->pc);
3068 break;
3069 default:
3070 case DISAS_JUMP:
3071 case DISAS_UPDATE:
3072 gen_flush_cc_op(dc);
3073 /* indicate that the hash table must be used to find the next TB */
3074 tcg_gen_exit_tb(0);
3075 break;
3076 case DISAS_TB_JUMP:
3077 /* nothing more to generate */
3078 break;
3079 }
3080 }
3081 gen_tb_end(tb, num_insns);
3082 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3083
3084 #ifdef DEBUG_DISAS
3085 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3086 qemu_log("----------------\n");
3087 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3088 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
3089 qemu_log("\n");
3090 }
3091 #endif
3092 if (search_pc) {
3093 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3094 lj++;
3095 while (lj <= j)
3096 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3097 } else {
3098 tb->size = dc->pc - pc_start;
3099 tb->icount = num_insns;
3100 }
3101
3102 //optimize_flags();
3103 //expand_target_qops();
3104 }
3105
3106 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
3107 {
3108 gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, false);
3109 }
3110
3111 void gen_intermediate_code_pc(CPUM68KState *env, TranslationBlock *tb)
3112 {
3113 gen_intermediate_code_internal(m68k_env_get_cpu(env), tb, true);
3114 }
3115
3116 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3117 int flags)
3118 {
3119 M68kCPU *cpu = M68K_CPU(cs);
3120 CPUM68KState *env = &cpu->env;
3121 int i;
3122 uint16_t sr;
3123 CPU_DoubleU u;
3124 for (i = 0; i < 8; i++)
3125 {
3126 u.d = env->fregs[i];
3127 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3128 i, env->dregs[i], i, env->aregs[i],
3129 i, u.l.upper, u.l.lower, *(double *)&u.d);
3130 }
3131 cpu_fprintf (f, "PC = %08x ", env->pc);
3132 sr = env->sr;
3133 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3134 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3135 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3136 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3137 }
3138
3139 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos)
3140 {
3141 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3142 }
AR7 emulation for QEMU