4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "qemu/cutils.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "qemu/timer.h"
39 #include "qemu/config-file.h"
40 #include "qemu/error-report.h"
41 #include "qemu/qemu-print.h"
42 #if defined(CONFIG_USER_ONLY)
44 #else /* !CONFIG_USER_ONLY */
46 #include "exec/memory.h"
47 #include "exec/ioport.h"
48 #include "sysemu/dma.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/hw_accel.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/xen-mapcache.h"
53 #include "trace-root.h"
55 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
56 #include <linux/falloc.h>
60 #include "qemu/rcu_queue.h"
61 #include "qemu/main-loop.h"
62 #include "translate-all.h"
63 #include "sysemu/replay.h"
65 #include "exec/memory-internal.h"
66 #include "exec/ram_addr.h"
69 #include "migration/vmstate.h"
71 #include "qemu/range.h"
73 #include "qemu/mmap-alloc.h"
76 #include "monitor/monitor.h"
78 //#define DEBUG_SUBPAGE
80 #if !defined(CONFIG_USER_ONLY)
81 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
82 * are protected by the ramlist lock.
84 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
86 static MemoryRegion
*system_memory
;
87 static MemoryRegion
*system_io
;
89 AddressSpace address_space_io
;
90 AddressSpace address_space_memory
;
92 MemoryRegion io_mem_rom
, io_mem_notdirty
;
93 static MemoryRegion io_mem_unassigned
;
96 #ifdef TARGET_PAGE_BITS_VARY
98 bool target_page_bits_decided
;
101 CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
103 /* current CPU in the current thread. It is only valid inside
105 __thread CPUState
*current_cpu
;
106 /* 0 = Do not count executed instructions.
107 1 = Precise instruction counting.
108 2 = Adaptive rate instruction counting. */
111 uintptr_t qemu_host_page_size
;
112 intptr_t qemu_host_page_mask
;
114 bool set_preferred_target_page_bits(int bits
)
116 /* The target page size is the lowest common denominator for all
117 * the CPUs in the system, so we can only make it smaller, never
118 * larger. And we can't make it smaller once we've committed to
121 #ifdef TARGET_PAGE_BITS_VARY
122 assert(bits
>= TARGET_PAGE_BITS_MIN
);
123 if (target_page_bits
== 0 || target_page_bits
> bits
) {
124 if (target_page_bits_decided
) {
127 target_page_bits
= bits
;
133 #if !defined(CONFIG_USER_ONLY)
135 static void finalize_target_page_bits(void)
137 #ifdef TARGET_PAGE_BITS_VARY
138 if (target_page_bits
== 0) {
139 target_page_bits
= TARGET_PAGE_BITS_MIN
;
141 target_page_bits_decided
= true;
145 typedef struct PhysPageEntry PhysPageEntry
;
147 struct PhysPageEntry
{
148 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
150 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
154 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
156 /* Size of the L2 (and L3, etc) page tables. */
157 #define ADDR_SPACE_BITS 64
160 #define P_L2_SIZE (1 << P_L2_BITS)
162 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
164 typedef PhysPageEntry Node
[P_L2_SIZE
];
166 typedef struct PhysPageMap
{
169 unsigned sections_nb
;
170 unsigned sections_nb_alloc
;
172 unsigned nodes_nb_alloc
;
174 MemoryRegionSection
*sections
;
177 struct AddressSpaceDispatch
{
178 MemoryRegionSection
*mru_section
;
179 /* This is a multi-level map on the physical address space.
180 * The bottom level has pointers to MemoryRegionSections.
182 PhysPageEntry phys_map
;
186 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
187 typedef struct subpage_t
{
191 uint16_t sub_section
[];
194 #define PHYS_SECTION_UNASSIGNED 0
195 #define PHYS_SECTION_NOTDIRTY 1
196 #define PHYS_SECTION_ROM 2
197 #define PHYS_SECTION_WATCH 3
199 static void io_mem_init(void);
200 static void memory_map_init(void);
201 static void tcg_commit(MemoryListener
*listener
);
203 static MemoryRegion io_mem_watch
;
206 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
207 * @cpu: the CPU whose AddressSpace this is
208 * @as: the AddressSpace itself
209 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
210 * @tcg_as_listener: listener for tracking changes to the AddressSpace
212 struct CPUAddressSpace
{
215 struct AddressSpaceDispatch
*memory_dispatch
;
216 MemoryListener tcg_as_listener
;
219 struct DirtyBitmapSnapshot
{
222 unsigned long dirty
[];
227 #if !defined(CONFIG_USER_ONLY)
229 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
231 static unsigned alloc_hint
= 16;
232 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
233 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
234 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
235 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
236 alloc_hint
= map
->nodes_nb_alloc
;
240 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
247 ret
= map
->nodes_nb
++;
249 assert(ret
!= PHYS_MAP_NODE_NIL
);
250 assert(ret
!= map
->nodes_nb_alloc
);
252 e
.skip
= leaf
? 0 : 1;
253 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
254 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
255 memcpy(&p
[i
], &e
, sizeof(e
));
260 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
261 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
265 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
267 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
268 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
270 p
= map
->nodes
[lp
->ptr
];
271 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
273 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
274 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
280 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
286 static void phys_page_set(AddressSpaceDispatch
*d
,
287 hwaddr index
, hwaddr nb
,
290 /* Wildly overreserve - it doesn't matter much. */
291 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
293 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
296 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
297 * and update our entry so we can skip it and go directly to the destination.
299 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
301 unsigned valid_ptr
= P_L2_SIZE
;
306 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
311 for (i
= 0; i
< P_L2_SIZE
; i
++) {
312 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
319 phys_page_compact(&p
[i
], nodes
);
323 /* We can only compress if there's only one child. */
328 assert(valid_ptr
< P_L2_SIZE
);
330 /* Don't compress if it won't fit in the # of bits we have. */
331 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
335 lp
->ptr
= p
[valid_ptr
].ptr
;
336 if (!p
[valid_ptr
].skip
) {
337 /* If our only child is a leaf, make this a leaf. */
338 /* By design, we should have made this node a leaf to begin with so we
339 * should never reach here.
340 * But since it's so simple to handle this, let's do it just in case we
345 lp
->skip
+= p
[valid_ptr
].skip
;
349 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
351 if (d
->phys_map
.skip
) {
352 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
356 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
359 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
360 * the section must cover the entire address space.
362 return int128_gethi(section
->size
) ||
363 range_covers_byte(section
->offset_within_address_space
,
364 int128_getlo(section
->size
), addr
);
367 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
369 PhysPageEntry lp
= d
->phys_map
, *p
;
370 Node
*nodes
= d
->map
.nodes
;
371 MemoryRegionSection
*sections
= d
->map
.sections
;
372 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
375 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
376 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
377 return §ions
[PHYS_SECTION_UNASSIGNED
];
380 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
383 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
384 return §ions
[lp
.ptr
];
386 return §ions
[PHYS_SECTION_UNASSIGNED
];
390 /* Called from RCU critical section */
391 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
393 bool resolve_subpage
)
395 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
398 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
399 !section_covers_addr(section
, addr
)) {
400 section
= phys_page_find(d
, addr
);
401 atomic_set(&d
->mru_section
, section
);
403 if (resolve_subpage
&& section
->mr
->subpage
) {
404 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
405 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
410 /* Called from RCU critical section */
411 static MemoryRegionSection
*
412 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
413 hwaddr
*plen
, bool resolve_subpage
)
415 MemoryRegionSection
*section
;
419 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
420 /* Compute offset within MemoryRegionSection */
421 addr
-= section
->offset_within_address_space
;
423 /* Compute offset within MemoryRegion */
424 *xlat
= addr
+ section
->offset_within_region
;
428 /* MMIO registers can be expected to perform full-width accesses based only
429 * on their address, without considering adjacent registers that could
430 * decode to completely different MemoryRegions. When such registers
431 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
432 * regions overlap wildly. For this reason we cannot clamp the accesses
435 * If the length is small (as is the case for address_space_ldl/stl),
436 * everything works fine. If the incoming length is large, however,
437 * the caller really has to do the clamping through memory_access_size.
439 if (memory_region_is_ram(mr
)) {
440 diff
= int128_sub(section
->size
, int128_make64(addr
));
441 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
447 * address_space_translate_iommu - translate an address through an IOMMU
448 * memory region and then through the target address space.
450 * @iommu_mr: the IOMMU memory region that we start the translation from
451 * @addr: the address to be translated through the MMU
452 * @xlat: the translated address offset within the destination memory region.
453 * It cannot be %NULL.
454 * @plen_out: valid read/write length of the translated address. It
456 * @page_mask_out: page mask for the translated address. This
457 * should only be meaningful for IOMMU translated
458 * addresses, since there may be huge pages that this bit
459 * would tell. It can be %NULL if we don't care about it.
460 * @is_write: whether the translation operation is for write
461 * @is_mmio: whether this can be MMIO, set true if it can
462 * @target_as: the address space targeted by the IOMMU
463 * @attrs: transaction attributes
465 * This function is called from RCU critical section. It is the common
466 * part of flatview_do_translate and address_space_translate_cached.
468 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
471 hwaddr
*page_mask_out
,
474 AddressSpace
**target_as
,
477 MemoryRegionSection
*section
;
478 hwaddr page_mask
= (hwaddr
)-1;
482 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
486 if (imrc
->attrs_to_index
) {
487 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
490 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
491 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
493 if (!(iotlb
.perm
& (1 << is_write
))) {
497 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
498 | (addr
& iotlb
.addr_mask
));
499 page_mask
&= iotlb
.addr_mask
;
500 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
501 *target_as
= iotlb
.target_as
;
503 section
= address_space_translate_internal(
504 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
507 iommu_mr
= memory_region_get_iommu(section
->mr
);
508 } while (unlikely(iommu_mr
));
511 *page_mask_out
= page_mask
;
516 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
520 * flatview_do_translate - translate an address in FlatView
522 * @fv: the flat view that we want to translate on
523 * @addr: the address to be translated in above address space
524 * @xlat: the translated address offset within memory region. It
526 * @plen_out: valid read/write length of the translated address. It
527 * can be @NULL when we don't care about it.
528 * @page_mask_out: page mask for the translated address. This
529 * should only be meaningful for IOMMU translated
530 * addresses, since there may be huge pages that this bit
531 * would tell. It can be @NULL if we don't care about it.
532 * @is_write: whether the translation operation is for write
533 * @is_mmio: whether this can be MMIO, set true if it can
534 * @target_as: the address space targeted by the IOMMU
535 * @attrs: memory transaction attributes
537 * This function is called from RCU critical section
539 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
543 hwaddr
*page_mask_out
,
546 AddressSpace
**target_as
,
549 MemoryRegionSection
*section
;
550 IOMMUMemoryRegion
*iommu_mr
;
551 hwaddr plen
= (hwaddr
)(-1);
557 section
= address_space_translate_internal(
558 flatview_to_dispatch(fv
), addr
, xlat
,
561 iommu_mr
= memory_region_get_iommu(section
->mr
);
562 if (unlikely(iommu_mr
)) {
563 return address_space_translate_iommu(iommu_mr
, xlat
,
564 plen_out
, page_mask_out
,
569 /* Not behind an IOMMU, use default page size. */
570 *page_mask_out
= ~TARGET_PAGE_MASK
;
576 /* Called from RCU critical section */
577 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
578 bool is_write
, MemTxAttrs attrs
)
580 MemoryRegionSection section
;
581 hwaddr xlat
, page_mask
;
584 * This can never be MMIO, and we don't really care about plen,
587 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
588 NULL
, &page_mask
, is_write
, false, &as
,
591 /* Illegal translation */
592 if (section
.mr
== &io_mem_unassigned
) {
596 /* Convert memory region offset into address space offset */
597 xlat
+= section
.offset_within_address_space
-
598 section
.offset_within_region
;
600 return (IOMMUTLBEntry
) {
602 .iova
= addr
& ~page_mask
,
603 .translated_addr
= xlat
& ~page_mask
,
604 .addr_mask
= page_mask
,
605 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
610 return (IOMMUTLBEntry
) {0};
613 /* Called from RCU critical section */
614 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
615 hwaddr
*plen
, bool is_write
,
619 MemoryRegionSection section
;
620 AddressSpace
*as
= NULL
;
622 /* This can be MMIO, so setup MMIO bit. */
623 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
624 is_write
, true, &as
, attrs
);
627 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
628 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
629 *plen
= MIN(page
, *plen
);
635 typedef struct TCGIOMMUNotifier
{
643 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
645 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
647 if (!notifier
->active
) {
650 tlb_flush(notifier
->cpu
);
651 notifier
->active
= false;
652 /* We leave the notifier struct on the list to avoid reallocating it later.
653 * Generally the number of IOMMUs a CPU deals with will be small.
654 * In any case we can't unregister the iommu notifier from a notify
659 static void tcg_register_iommu_notifier(CPUState
*cpu
,
660 IOMMUMemoryRegion
*iommu_mr
,
663 /* Make sure this CPU has an IOMMU notifier registered for this
664 * IOMMU/IOMMU index combination, so that we can flush its TLB
665 * when the IOMMU tells us the mappings we've cached have changed.
667 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
668 TCGIOMMUNotifier
*notifier
;
671 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
672 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
673 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
677 if (i
== cpu
->iommu_notifiers
->len
) {
678 /* Not found, add a new entry at the end of the array */
679 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
680 notifier
= g_new0(TCGIOMMUNotifier
, 1);
681 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
684 notifier
->iommu_idx
= iommu_idx
;
686 /* Rather than trying to register interest in the specific part
687 * of the iommu's address space that we've accessed and then
688 * expand it later as subsequent accesses touch more of it, we
689 * just register interest in the whole thing, on the assumption
690 * that iommu reconfiguration will be rare.
692 iommu_notifier_init(¬ifier
->n
,
693 tcg_iommu_unmap_notify
,
694 IOMMU_NOTIFIER_UNMAP
,
698 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
701 if (!notifier
->active
) {
702 notifier
->active
= true;
706 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
708 /* Destroy the CPU's notifier list */
710 TCGIOMMUNotifier
*notifier
;
712 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
713 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
714 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
717 g_array_free(cpu
->iommu_notifiers
, true);
720 /* Called from RCU critical section */
721 MemoryRegionSection
*
722 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
723 hwaddr
*xlat
, hwaddr
*plen
,
724 MemTxAttrs attrs
, int *prot
)
726 MemoryRegionSection
*section
;
727 IOMMUMemoryRegion
*iommu_mr
;
728 IOMMUMemoryRegionClass
*imrc
;
731 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
734 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
736 iommu_mr
= memory_region_get_iommu(section
->mr
);
741 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
743 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
744 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
745 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
746 * doesn't short-cut its translation table walk.
748 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
749 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
750 | (addr
& iotlb
.addr_mask
));
751 /* Update the caller's prot bits to remove permissions the IOMMU
752 * is giving us a failure response for. If we get down to no
753 * permissions left at all we can give up now.
755 if (!(iotlb
.perm
& IOMMU_RO
)) {
756 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
758 if (!(iotlb
.perm
& IOMMU_WO
)) {
759 *prot
&= ~PAGE_WRITE
;
766 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
769 assert(!memory_region_is_iommu(section
->mr
));
774 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
778 #if !defined(CONFIG_USER_ONLY)
780 static int cpu_common_post_load(void *opaque
, int version_id
)
782 CPUState
*cpu
= opaque
;
784 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
785 version_id is increased. */
786 cpu
->interrupt_request
&= ~0x01;
789 /* loadvm has just updated the content of RAM, bypassing the
790 * usual mechanisms that ensure we flush TBs for writes to
791 * memory we've translated code from. So we must flush all TBs,
792 * which will now be stale.
799 static int cpu_common_pre_load(void *opaque
)
801 CPUState
*cpu
= opaque
;
803 cpu
->exception_index
= -1;
808 static bool cpu_common_exception_index_needed(void *opaque
)
810 CPUState
*cpu
= opaque
;
812 return tcg_enabled() && cpu
->exception_index
!= -1;
815 static const VMStateDescription vmstate_cpu_common_exception_index
= {
816 .name
= "cpu_common/exception_index",
818 .minimum_version_id
= 1,
819 .needed
= cpu_common_exception_index_needed
,
820 .fields
= (VMStateField
[]) {
821 VMSTATE_INT32(exception_index
, CPUState
),
822 VMSTATE_END_OF_LIST()
826 static bool cpu_common_crash_occurred_needed(void *opaque
)
828 CPUState
*cpu
= opaque
;
830 return cpu
->crash_occurred
;
833 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
834 .name
= "cpu_common/crash_occurred",
836 .minimum_version_id
= 1,
837 .needed
= cpu_common_crash_occurred_needed
,
838 .fields
= (VMStateField
[]) {
839 VMSTATE_BOOL(crash_occurred
, CPUState
),
840 VMSTATE_END_OF_LIST()
844 const VMStateDescription vmstate_cpu_common
= {
845 .name
= "cpu_common",
847 .minimum_version_id
= 1,
848 .pre_load
= cpu_common_pre_load
,
849 .post_load
= cpu_common_post_load
,
850 .fields
= (VMStateField
[]) {
851 VMSTATE_UINT32(halted
, CPUState
),
852 VMSTATE_UINT32(interrupt_request
, CPUState
),
853 VMSTATE_END_OF_LIST()
855 .subsections
= (const VMStateDescription
*[]) {
856 &vmstate_cpu_common_exception_index
,
857 &vmstate_cpu_common_crash_occurred
,
864 CPUState
*qemu_get_cpu(int index
)
869 if (cpu
->cpu_index
== index
) {
877 #if !defined(CONFIG_USER_ONLY)
878 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
879 const char *prefix
, MemoryRegion
*mr
)
881 CPUAddressSpace
*newas
;
882 AddressSpace
*as
= g_new0(AddressSpace
, 1);
886 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
887 address_space_init(as
, mr
, as_name
);
890 /* Target code should have set num_ases before calling us */
891 assert(asidx
< cpu
->num_ases
);
894 /* address space 0 gets the convenience alias */
898 /* KVM cannot currently support multiple address spaces. */
899 assert(asidx
== 0 || !kvm_enabled());
901 if (!cpu
->cpu_ases
) {
902 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
905 newas
= &cpu
->cpu_ases
[asidx
];
909 newas
->tcg_as_listener
.commit
= tcg_commit
;
910 memory_listener_register(&newas
->tcg_as_listener
, as
);
914 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
916 /* Return the AddressSpace corresponding to the specified index */
917 return cpu
->cpu_ases
[asidx
].as
;
921 void cpu_exec_unrealizefn(CPUState
*cpu
)
923 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
925 cpu_list_remove(cpu
);
927 if (cc
->vmsd
!= NULL
) {
928 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
930 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
931 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
933 #ifndef CONFIG_USER_ONLY
934 tcg_iommu_free_notifier_list(cpu
);
938 Property cpu_common_props
[] = {
939 #ifndef CONFIG_USER_ONLY
940 /* Create a memory property for softmmu CPU object,
941 * so users can wire up its memory. (This can't go in qom/cpu.c
942 * because that file is compiled only once for both user-mode
943 * and system builds.) The default if no link is set up is to use
944 * the system address space.
946 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
949 DEFINE_PROP_END_OF_LIST(),
952 void cpu_exec_initfn(CPUState
*cpu
)
957 #ifndef CONFIG_USER_ONLY
958 cpu
->thread_id
= qemu_get_thread_id();
959 cpu
->memory
= system_memory
;
960 object_ref(OBJECT(cpu
->memory
));
964 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
966 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
967 static bool tcg_target_initialized
;
971 if (tcg_enabled() && !tcg_target_initialized
) {
972 tcg_target_initialized
= true;
973 cc
->tcg_initialize();
977 #ifndef CONFIG_USER_ONLY
978 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
979 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
981 if (cc
->vmsd
!= NULL
) {
982 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
985 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
989 const char *parse_cpu_option(const char *cpu_option
)
993 gchar
**model_pieces
;
994 const char *cpu_type
;
996 model_pieces
= g_strsplit(cpu_option
, ",", 2);
997 if (!model_pieces
[0]) {
998 error_report("-cpu option cannot be empty");
1002 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
1004 error_report("unable to find CPU model '%s'", model_pieces
[0]);
1005 g_strfreev(model_pieces
);
1009 cpu_type
= object_class_get_name(oc
);
1011 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1012 g_strfreev(model_pieces
);
1016 #if defined(CONFIG_USER_ONLY)
1017 void tb_invalidate_phys_addr(target_ulong addr
)
1020 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1024 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1026 tb_invalidate_phys_addr(pc
);
1029 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1031 ram_addr_t ram_addr
;
1035 if (!tcg_enabled()) {
1040 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1041 if (!(memory_region_is_ram(mr
)
1042 || memory_region_is_romd(mr
))) {
1046 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1047 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1051 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1054 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1055 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1057 /* Locks grabbed by tb_invalidate_phys_addr */
1058 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1059 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1064 #if defined(CONFIG_USER_ONLY)
1065 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1070 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1076 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1080 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1081 int flags
, CPUWatchpoint
**watchpoint
)
1086 /* Add a watchpoint. */
1087 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1088 int flags
, CPUWatchpoint
**watchpoint
)
1092 /* forbid ranges which are empty or run off the end of the address space */
1093 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1094 error_report("tried to set invalid watchpoint at %"
1095 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1098 wp
= g_malloc(sizeof(*wp
));
1104 /* keep all GDB-injected watchpoints in front */
1105 if (flags
& BP_GDB
) {
1106 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1108 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1111 tlb_flush_page(cpu
, addr
);
1118 /* Remove a specific watchpoint. */
1119 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1124 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1125 if (addr
== wp
->vaddr
&& len
== wp
->len
1126 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1127 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1134 /* Remove a specific watchpoint by reference. */
1135 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1137 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1139 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1144 /* Remove all matching watchpoints. */
1145 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1147 CPUWatchpoint
*wp
, *next
;
1149 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1150 if (wp
->flags
& mask
) {
1151 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1156 /* Return true if this watchpoint address matches the specified
1157 * access (ie the address range covered by the watchpoint overlaps
1158 * partially or completely with the address range covered by the
1161 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1165 /* We know the lengths are non-zero, but a little caution is
1166 * required to avoid errors in the case where the range ends
1167 * exactly at the top of the address space and so addr + len
1168 * wraps round to zero.
1170 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1171 vaddr addrend
= addr
+ len
- 1;
1173 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1178 /* Add a breakpoint. */
1179 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1180 CPUBreakpoint
**breakpoint
)
1184 bp
= g_malloc(sizeof(*bp
));
1189 /* keep all GDB-injected breakpoints in front */
1190 if (flags
& BP_GDB
) {
1191 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1193 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1196 breakpoint_invalidate(cpu
, pc
);
1204 /* Remove a specific breakpoint. */
1205 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1209 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1210 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1211 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1218 /* Remove a specific breakpoint by reference. */
1219 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1221 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1223 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1228 /* Remove all matching breakpoints. */
1229 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1231 CPUBreakpoint
*bp
, *next
;
1233 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1234 if (bp
->flags
& mask
) {
1235 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1240 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1241 CPU loop after each instruction */
1242 void cpu_single_step(CPUState
*cpu
, int enabled
)
1244 if (cpu
->singlestep_enabled
!= enabled
) {
1245 cpu
->singlestep_enabled
= enabled
;
1246 if (kvm_enabled()) {
1247 kvm_update_guest_debug(cpu
, 0);
1249 /* must flush all the translated code to avoid inconsistencies */
1250 /* XXX: only flush what is necessary */
1256 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1263 fprintf(stderr
, "qemu: fatal: ");
1264 vfprintf(stderr
, fmt
, ap
);
1265 fprintf(stderr
, "\n");
1266 cpu_dump_state(cpu
, stderr
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1267 if (qemu_log_separate()) {
1269 qemu_log("qemu: fatal: ");
1270 qemu_log_vprintf(fmt
, ap2
);
1272 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1280 #if defined(CONFIG_USER_ONLY)
1282 struct sigaction act
;
1283 sigfillset(&act
.sa_mask
);
1284 act
.sa_handler
= SIG_DFL
;
1286 sigaction(SIGABRT
, &act
, NULL
);
1292 #if !defined(CONFIG_USER_ONLY)
1293 /* Called from RCU critical section */
1294 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1298 block
= atomic_rcu_read(&ram_list
.mru_block
);
1299 if (block
&& addr
- block
->offset
< block
->max_length
) {
1302 RAMBLOCK_FOREACH(block
) {
1303 if (addr
- block
->offset
< block
->max_length
) {
1308 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1312 /* It is safe to write mru_block outside the iothread lock. This
1317 * xxx removed from list
1321 * call_rcu(reclaim_ramblock, xxx);
1324 * atomic_rcu_set is not needed here. The block was already published
1325 * when it was placed into the list. Here we're just making an extra
1326 * copy of the pointer.
1328 ram_list
.mru_block
= block
;
1332 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1339 assert(tcg_enabled());
1340 end
= TARGET_PAGE_ALIGN(start
+ length
);
1341 start
&= TARGET_PAGE_MASK
;
1344 block
= qemu_get_ram_block(start
);
1345 assert(block
== qemu_get_ram_block(end
- 1));
1346 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1348 tlb_reset_dirty(cpu
, start1
, length
);
1353 /* Note: start and end must be within the same ram block. */
1354 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1358 DirtyMemoryBlocks
*blocks
;
1359 unsigned long end
, page
;
1366 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1367 page
= start
>> TARGET_PAGE_BITS
;
1371 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1373 while (page
< end
) {
1374 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1375 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1376 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1378 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1385 if (dirty
&& tcg_enabled()) {
1386 tlb_reset_dirty_range_all(start
, length
);
1392 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1393 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1395 DirtyMemoryBlocks
*blocks
;
1396 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1397 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1398 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1399 DirtyBitmapSnapshot
*snap
;
1400 unsigned long page
, end
, dest
;
1402 snap
= g_malloc0(sizeof(*snap
) +
1403 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1404 snap
->start
= first
;
1407 page
= first
>> TARGET_PAGE_BITS
;
1408 end
= last
>> TARGET_PAGE_BITS
;
1413 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1415 while (page
< end
) {
1416 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1417 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1418 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1420 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1421 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1422 offset
>>= BITS_PER_LEVEL
;
1424 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1425 blocks
->blocks
[idx
] + offset
,
1428 dest
+= num
>> BITS_PER_LEVEL
;
1433 if (tcg_enabled()) {
1434 tlb_reset_dirty_range_all(start
, length
);
1440 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1444 unsigned long page
, end
;
1446 assert(start
>= snap
->start
);
1447 assert(start
+ length
<= snap
->end
);
1449 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1450 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1452 while (page
< end
) {
1453 if (test_bit(page
, snap
->dirty
)) {
1461 /* Called from RCU critical section */
1462 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1463 MemoryRegionSection
*section
,
1465 hwaddr paddr
, hwaddr xlat
,
1467 target_ulong
*address
)
1472 if (memory_region_is_ram(section
->mr
)) {
1474 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1475 if (!section
->readonly
) {
1476 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1478 iotlb
|= PHYS_SECTION_ROM
;
1481 AddressSpaceDispatch
*d
;
1483 d
= flatview_to_dispatch(section
->fv
);
1484 iotlb
= section
- d
->map
.sections
;
1488 /* Make accesses to pages with watchpoints go via the
1489 watchpoint trap routines. */
1490 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1491 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1492 /* Avoid trapping reads of pages with a write breakpoint. */
1493 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1494 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1495 *address
|= TLB_MMIO
;
1503 #endif /* defined(CONFIG_USER_ONLY) */
1505 #if !defined(CONFIG_USER_ONLY)
1507 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1509 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1511 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1512 qemu_anon_ram_alloc
;
1515 * Set a custom physical guest memory alloator.
1516 * Accelerators with unusual needs may need this. Hopefully, we can
1517 * get rid of it eventually.
1519 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1521 phys_mem_alloc
= alloc
;
1524 static uint16_t phys_section_add(PhysPageMap
*map
,
1525 MemoryRegionSection
*section
)
1527 /* The physical section number is ORed with a page-aligned
1528 * pointer to produce the iotlb entries. Thus it should
1529 * never overflow into the page-aligned value.
1531 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1533 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1534 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1535 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1536 map
->sections_nb_alloc
);
1538 map
->sections
[map
->sections_nb
] = *section
;
1539 memory_region_ref(section
->mr
);
1540 return map
->sections_nb
++;
1543 static void phys_section_destroy(MemoryRegion
*mr
)
1545 bool have_sub_page
= mr
->subpage
;
1547 memory_region_unref(mr
);
1549 if (have_sub_page
) {
1550 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1551 object_unref(OBJECT(&subpage
->iomem
));
1556 static void phys_sections_free(PhysPageMap
*map
)
1558 while (map
->sections_nb
> 0) {
1559 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1560 phys_section_destroy(section
->mr
);
1562 g_free(map
->sections
);
1566 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1568 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1570 hwaddr base
= section
->offset_within_address_space
1572 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1573 MemoryRegionSection subsection
= {
1574 .offset_within_address_space
= base
,
1575 .size
= int128_make64(TARGET_PAGE_SIZE
),
1579 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1581 if (!(existing
->mr
->subpage
)) {
1582 subpage
= subpage_init(fv
, base
);
1584 subsection
.mr
= &subpage
->iomem
;
1585 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1586 phys_section_add(&d
->map
, &subsection
));
1588 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1590 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1591 end
= start
+ int128_get64(section
->size
) - 1;
1592 subpage_register(subpage
, start
, end
,
1593 phys_section_add(&d
->map
, section
));
1597 static void register_multipage(FlatView
*fv
,
1598 MemoryRegionSection
*section
)
1600 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1601 hwaddr start_addr
= section
->offset_within_address_space
;
1602 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1603 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1607 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1611 * The range in *section* may look like this:
1615 * where s stands for subpage and P for page.
1617 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1619 MemoryRegionSection remain
= *section
;
1620 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1622 /* register first subpage */
1623 if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1624 uint64_t left
= TARGET_PAGE_ALIGN(remain
.offset_within_address_space
)
1625 - remain
.offset_within_address_space
;
1627 MemoryRegionSection now
= remain
;
1628 now
.size
= int128_min(int128_make64(left
), now
.size
);
1629 register_subpage(fv
, &now
);
1630 if (int128_eq(remain
.size
, now
.size
)) {
1633 remain
.size
= int128_sub(remain
.size
, now
.size
);
1634 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1635 remain
.offset_within_region
+= int128_get64(now
.size
);
1638 /* register whole pages */
1639 if (int128_ge(remain
.size
, page_size
)) {
1640 MemoryRegionSection now
= remain
;
1641 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1642 register_multipage(fv
, &now
);
1643 if (int128_eq(remain
.size
, now
.size
)) {
1646 remain
.size
= int128_sub(remain
.size
, now
.size
);
1647 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1648 remain
.offset_within_region
+= int128_get64(now
.size
);
1651 /* register last subpage */
1652 register_subpage(fv
, &remain
);
1655 void qemu_flush_coalesced_mmio_buffer(void)
1658 kvm_flush_coalesced_mmio_buffer();
1661 void qemu_mutex_lock_ramlist(void)
1663 qemu_mutex_lock(&ram_list
.mutex
);
1666 void qemu_mutex_unlock_ramlist(void)
1668 qemu_mutex_unlock(&ram_list
.mutex
);
1671 void ram_block_dump(Monitor
*mon
)
1677 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1678 "Block Name", "PSize", "Offset", "Used", "Total");
1679 RAMBLOCK_FOREACH(block
) {
1680 psize
= size_to_str(block
->page_size
);
1681 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1682 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1683 (uint64_t)block
->offset
,
1684 (uint64_t)block
->used_length
,
1685 (uint64_t)block
->max_length
);
1693 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1694 * may or may not name the same files / on the same filesystem now as
1695 * when we actually open and map them. Iterate over the file
1696 * descriptors instead, and use qemu_fd_getpagesize().
1698 static int find_min_backend_pagesize(Object
*obj
, void *opaque
)
1700 long *hpsize_min
= opaque
;
1702 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1703 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1704 long hpsize
= host_memory_backend_pagesize(backend
);
1706 if (host_memory_backend_is_mapped(backend
) && (hpsize
< *hpsize_min
)) {
1707 *hpsize_min
= hpsize
;
1714 static int find_max_backend_pagesize(Object
*obj
, void *opaque
)
1716 long *hpsize_max
= opaque
;
1718 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1719 HostMemoryBackend
*backend
= MEMORY_BACKEND(obj
);
1720 long hpsize
= host_memory_backend_pagesize(backend
);
1722 if (host_memory_backend_is_mapped(backend
) && (hpsize
> *hpsize_max
)) {
1723 *hpsize_max
= hpsize
;
1731 * TODO: We assume right now that all mapped host memory backends are
1732 * used as RAM, however some might be used for different purposes.
1734 long qemu_minrampagesize(void)
1736 long hpsize
= LONG_MAX
;
1737 long mainrampagesize
;
1738 Object
*memdev_root
;
1740 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1742 /* it's possible we have memory-backend objects with
1743 * hugepage-backed RAM. these may get mapped into system
1744 * address space via -numa parameters or memory hotplug
1745 * hooks. we want to take these into account, but we
1746 * also want to make sure these supported hugepage
1747 * sizes are applicable across the entire range of memory
1748 * we may boot from, so we take the min across all
1749 * backends, and assume normal pages in cases where a
1750 * backend isn't backed by hugepages.
1752 memdev_root
= object_resolve_path("/objects", NULL
);
1754 object_child_foreach(memdev_root
, find_min_backend_pagesize
, &hpsize
);
1756 if (hpsize
== LONG_MAX
) {
1757 /* No additional memory regions found ==> Report main RAM page size */
1758 return mainrampagesize
;
1761 /* If NUMA is disabled or the NUMA nodes are not backed with a
1762 * memory-backend, then there is at least one node using "normal" RAM,
1763 * so if its page size is smaller we have got to report that size instead.
1765 if (hpsize
> mainrampagesize
&&
1766 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1769 error_report("Huge page support disabled (n/a for main memory).");
1772 return mainrampagesize
;
1778 long qemu_maxrampagesize(void)
1780 long pagesize
= qemu_mempath_getpagesize(mem_path
);
1781 Object
*memdev_root
= object_resolve_path("/objects", NULL
);
1784 object_child_foreach(memdev_root
, find_max_backend_pagesize
,
1790 long qemu_minrampagesize(void)
1792 return getpagesize();
1794 long qemu_maxrampagesize(void)
1796 return getpagesize();
1801 static int64_t get_file_size(int fd
)
1803 int64_t size
= lseek(fd
, 0, SEEK_END
);
1810 static int file_ram_open(const char *path
,
1811 const char *region_name
,
1816 char *sanitized_name
;
1822 fd
= open(path
, O_RDWR
);
1824 /* @path names an existing file, use it */
1827 if (errno
== ENOENT
) {
1828 /* @path names a file that doesn't exist, create it */
1829 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1834 } else if (errno
== EISDIR
) {
1835 /* @path names a directory, create a file there */
1836 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1837 sanitized_name
= g_strdup(region_name
);
1838 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1844 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1846 g_free(sanitized_name
);
1848 fd
= mkstemp(filename
);
1856 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1857 error_setg_errno(errp
, errno
,
1858 "can't open backing store %s for guest RAM",
1863 * Try again on EINTR and EEXIST. The latter happens when
1864 * something else creates the file between our two open().
1871 static void *file_ram_alloc(RAMBlock
*block
,
1877 MachineState
*ms
= MACHINE(qdev_get_machine());
1880 block
->page_size
= qemu_fd_getpagesize(fd
);
1881 if (block
->mr
->align
% block
->page_size
) {
1882 error_setg(errp
, "alignment 0x%" PRIx64
1883 " must be multiples of page size 0x%zx",
1884 block
->mr
->align
, block
->page_size
);
1886 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1887 error_setg(errp
, "alignment 0x%" PRIx64
1888 " must be a power of two", block
->mr
->align
);
1891 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1892 #if defined(__s390x__)
1893 if (kvm_enabled()) {
1894 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1898 if (memory
< block
->page_size
) {
1899 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1900 "or larger than page size 0x%zx",
1901 memory
, block
->page_size
);
1905 memory
= ROUND_UP(memory
, block
->page_size
);
1908 * ftruncate is not supported by hugetlbfs in older
1909 * hosts, so don't bother bailing out on errors.
1910 * If anything goes wrong with it under other filesystems,
1913 * Do not truncate the non-empty backend file to avoid corrupting
1914 * the existing data in the file. Disabling shrinking is not
1915 * enough. For example, the current vNVDIMM implementation stores
1916 * the guest NVDIMM labels at the end of the backend file. If the
1917 * backend file is later extended, QEMU will not be able to find
1918 * those labels. Therefore, extending the non-empty backend file
1919 * is disabled as well.
1921 if (truncate
&& ftruncate(fd
, memory
)) {
1922 perror("ftruncate");
1925 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1926 block
->flags
& RAM_SHARED
, block
->flags
& RAM_PMEM
);
1927 if (area
== MAP_FAILED
) {
1928 error_setg_errno(errp
, errno
,
1929 "unable to map backing store for guest RAM");
1934 os_mem_prealloc(fd
, area
, memory
, ms
->smp
.cpus
, errp
);
1935 if (errp
&& *errp
) {
1936 qemu_ram_munmap(fd
, area
, memory
);
1946 /* Allocate space within the ram_addr_t space that governs the
1948 * Called with the ramlist lock held.
1950 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1952 RAMBlock
*block
, *next_block
;
1953 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1955 assert(size
!= 0); /* it would hand out same offset multiple times */
1957 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1961 RAMBLOCK_FOREACH(block
) {
1962 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1964 /* Align blocks to start on a 'long' in the bitmap
1965 * which makes the bitmap sync'ing take the fast path.
1967 candidate
= block
->offset
+ block
->max_length
;
1968 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1970 /* Search for the closest following block
1973 RAMBLOCK_FOREACH(next_block
) {
1974 if (next_block
->offset
>= candidate
) {
1975 next
= MIN(next
, next_block
->offset
);
1979 /* If it fits remember our place and remember the size
1980 * of gap, but keep going so that we might find a smaller
1981 * gap to fill so avoiding fragmentation.
1983 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1985 mingap
= next
- candidate
;
1988 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1991 if (offset
== RAM_ADDR_MAX
) {
1992 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1997 trace_find_ram_offset(size
, offset
);
2002 static unsigned long last_ram_page(void)
2005 ram_addr_t last
= 0;
2008 RAMBLOCK_FOREACH(block
) {
2009 last
= MAX(last
, block
->offset
+ block
->max_length
);
2012 return last
>> TARGET_PAGE_BITS
;
2015 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
2019 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
2020 if (!machine_dump_guest_core(current_machine
)) {
2021 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
2023 perror("qemu_madvise");
2024 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
2025 "but dump_guest_core=off specified\n");
2030 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
2035 void *qemu_ram_get_host_addr(RAMBlock
*rb
)
2040 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
)
2045 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
)
2047 return rb
->used_length
;
2050 bool qemu_ram_is_shared(RAMBlock
*rb
)
2052 return rb
->flags
& RAM_SHARED
;
2055 /* Note: Only set at the start of postcopy */
2056 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
2058 return rb
->flags
& RAM_UF_ZEROPAGE
;
2061 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
2063 rb
->flags
|= RAM_UF_ZEROPAGE
;
2066 bool qemu_ram_is_migratable(RAMBlock
*rb
)
2068 return rb
->flags
& RAM_MIGRATABLE
;
2071 void qemu_ram_set_migratable(RAMBlock
*rb
)
2073 rb
->flags
|= RAM_MIGRATABLE
;
2076 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2078 rb
->flags
&= ~RAM_MIGRATABLE
;
2081 /* Called with iothread lock held. */
2082 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2087 assert(!new_block
->idstr
[0]);
2090 char *id
= qdev_get_dev_path(dev
);
2092 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2096 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2099 RAMBLOCK_FOREACH(block
) {
2100 if (block
!= new_block
&&
2101 !strcmp(block
->idstr
, new_block
->idstr
)) {
2102 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2110 /* Called with iothread lock held. */
2111 void qemu_ram_unset_idstr(RAMBlock
*block
)
2113 /* FIXME: arch_init.c assumes that this is not called throughout
2114 * migration. Ignore the problem since hot-unplug during migration
2115 * does not work anyway.
2118 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2122 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2124 return rb
->page_size
;
2127 /* Returns the largest size of page in use */
2128 size_t qemu_ram_pagesize_largest(void)
2133 RAMBLOCK_FOREACH(block
) {
2134 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2140 static int memory_try_enable_merging(void *addr
, size_t len
)
2142 if (!machine_mem_merge(current_machine
)) {
2143 /* disabled by the user */
2147 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2150 /* Only legal before guest might have detected the memory size: e.g. on
2151 * incoming migration, or right after reset.
2153 * As memory core doesn't know how is memory accessed, it is up to
2154 * resize callback to update device state and/or add assertions to detect
2155 * misuse, if necessary.
2157 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2161 newsize
= HOST_PAGE_ALIGN(newsize
);
2163 if (block
->used_length
== newsize
) {
2167 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2168 error_setg_errno(errp
, EINVAL
,
2169 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2170 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2171 newsize
, block
->used_length
);
2175 if (block
->max_length
< newsize
) {
2176 error_setg_errno(errp
, EINVAL
,
2177 "Length too large: %s: 0x" RAM_ADDR_FMT
2178 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2179 newsize
, block
->max_length
);
2183 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2184 block
->used_length
= newsize
;
2185 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2187 memory_region_set_size(block
->mr
, newsize
);
2188 if (block
->resized
) {
2189 block
->resized(block
->idstr
, newsize
, block
->host
);
2194 /* Called with ram_list.mutex held */
2195 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2196 ram_addr_t new_ram_size
)
2198 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2199 DIRTY_MEMORY_BLOCK_SIZE
);
2200 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2201 DIRTY_MEMORY_BLOCK_SIZE
);
2204 /* Only need to extend if block count increased */
2205 if (new_num_blocks
<= old_num_blocks
) {
2209 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2210 DirtyMemoryBlocks
*old_blocks
;
2211 DirtyMemoryBlocks
*new_blocks
;
2214 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2215 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2216 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2218 if (old_num_blocks
) {
2219 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2220 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2223 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2224 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2227 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2230 g_free_rcu(old_blocks
, rcu
);
2235 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2238 RAMBlock
*last_block
= NULL
;
2239 ram_addr_t old_ram_size
, new_ram_size
;
2242 old_ram_size
= last_ram_page();
2244 qemu_mutex_lock_ramlist();
2245 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2247 if (!new_block
->host
) {
2248 if (xen_enabled()) {
2249 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2250 new_block
->mr
, &err
);
2252 error_propagate(errp
, err
);
2253 qemu_mutex_unlock_ramlist();
2257 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2258 &new_block
->mr
->align
, shared
);
2259 if (!new_block
->host
) {
2260 error_setg_errno(errp
, errno
,
2261 "cannot set up guest memory '%s'",
2262 memory_region_name(new_block
->mr
));
2263 qemu_mutex_unlock_ramlist();
2266 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2270 new_ram_size
= MAX(old_ram_size
,
2271 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2272 if (new_ram_size
> old_ram_size
) {
2273 dirty_memory_extend(old_ram_size
, new_ram_size
);
2275 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2276 * QLIST (which has an RCU-friendly variant) does not have insertion at
2277 * tail, so save the last element in last_block.
2279 RAMBLOCK_FOREACH(block
) {
2281 if (block
->max_length
< new_block
->max_length
) {
2286 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2287 } else if (last_block
) {
2288 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2289 } else { /* list is empty */
2290 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2292 ram_list
.mru_block
= NULL
;
2294 /* Write list before version */
2297 qemu_mutex_unlock_ramlist();
2299 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2300 new_block
->used_length
,
2303 if (new_block
->host
) {
2304 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2305 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2306 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2307 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2308 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2313 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2314 uint32_t ram_flags
, int fd
,
2317 RAMBlock
*new_block
;
2318 Error
*local_err
= NULL
;
2321 /* Just support these ram flags by now. */
2322 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2324 if (xen_enabled()) {
2325 error_setg(errp
, "-mem-path not supported with Xen");
2329 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2331 "host lacks kvm mmu notifiers, -mem-path unsupported");
2335 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2337 * file_ram_alloc() needs to allocate just like
2338 * phys_mem_alloc, but we haven't bothered to provide
2342 "-mem-path not supported with this accelerator");
2346 size
= HOST_PAGE_ALIGN(size
);
2347 file_size
= get_file_size(fd
);
2348 if (file_size
> 0 && file_size
< size
) {
2349 error_setg(errp
, "backing store %s size 0x%" PRIx64
2350 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2351 mem_path
, file_size
, size
);
2355 new_block
= g_malloc0(sizeof(*new_block
));
2357 new_block
->used_length
= size
;
2358 new_block
->max_length
= size
;
2359 new_block
->flags
= ram_flags
;
2360 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2361 if (!new_block
->host
) {
2366 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2369 error_propagate(errp
, local_err
);
2377 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2378 uint32_t ram_flags
, const char *mem_path
,
2385 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2390 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2404 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2405 void (*resized
)(const char*,
2408 void *host
, bool resizeable
, bool share
,
2409 MemoryRegion
*mr
, Error
**errp
)
2411 RAMBlock
*new_block
;
2412 Error
*local_err
= NULL
;
2414 size
= HOST_PAGE_ALIGN(size
);
2415 max_size
= HOST_PAGE_ALIGN(max_size
);
2416 new_block
= g_malloc0(sizeof(*new_block
));
2418 new_block
->resized
= resized
;
2419 new_block
->used_length
= size
;
2420 new_block
->max_length
= max_size
;
2421 assert(max_size
>= size
);
2423 new_block
->page_size
= getpagesize();
2424 new_block
->host
= host
;
2426 new_block
->flags
|= RAM_PREALLOC
;
2429 new_block
->flags
|= RAM_RESIZEABLE
;
2431 ram_block_add(new_block
, &local_err
, share
);
2434 error_propagate(errp
, local_err
);
2440 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2441 MemoryRegion
*mr
, Error
**errp
)
2443 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2447 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2448 MemoryRegion
*mr
, Error
**errp
)
2450 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2454 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2455 void (*resized
)(const char*,
2458 MemoryRegion
*mr
, Error
**errp
)
2460 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2464 static void reclaim_ramblock(RAMBlock
*block
)
2466 if (block
->flags
& RAM_PREALLOC
) {
2468 } else if (xen_enabled()) {
2469 xen_invalidate_map_cache_entry(block
->host
);
2471 } else if (block
->fd
>= 0) {
2472 qemu_ram_munmap(block
->fd
, block
->host
, block
->max_length
);
2476 qemu_anon_ram_free(block
->host
, block
->max_length
);
2481 void qemu_ram_free(RAMBlock
*block
)
2488 ram_block_notify_remove(block
->host
, block
->max_length
);
2491 qemu_mutex_lock_ramlist();
2492 QLIST_REMOVE_RCU(block
, next
);
2493 ram_list
.mru_block
= NULL
;
2494 /* Write list before version */
2497 call_rcu(block
, reclaim_ramblock
, rcu
);
2498 qemu_mutex_unlock_ramlist();
2502 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2509 RAMBLOCK_FOREACH(block
) {
2510 offset
= addr
- block
->offset
;
2511 if (offset
< block
->max_length
) {
2512 vaddr
= ramblock_ptr(block
, offset
);
2513 if (block
->flags
& RAM_PREALLOC
) {
2515 } else if (xen_enabled()) {
2519 if (block
->fd
>= 0) {
2520 flags
|= (block
->flags
& RAM_SHARED
?
2521 MAP_SHARED
: MAP_PRIVATE
);
2522 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2523 flags
, block
->fd
, offset
);
2526 * Remap needs to match alloc. Accelerators that
2527 * set phys_mem_alloc never remap. If they did,
2528 * we'd need a remap hook here.
2530 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2532 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2533 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2536 if (area
!= vaddr
) {
2537 error_report("Could not remap addr: "
2538 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2542 memory_try_enable_merging(vaddr
, length
);
2543 qemu_ram_setup_dump(vaddr
, length
);
2548 #endif /* !_WIN32 */
2550 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2551 * This should not be used for general purpose DMA. Use address_space_map
2552 * or address_space_rw instead. For local memory (e.g. video ram) that the
2553 * device owns, use memory_region_get_ram_ptr.
2555 * Called within RCU critical section.
2557 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2559 RAMBlock
*block
= ram_block
;
2561 if (block
== NULL
) {
2562 block
= qemu_get_ram_block(addr
);
2563 addr
-= block
->offset
;
2566 if (xen_enabled() && block
->host
== NULL
) {
2567 /* We need to check if the requested address is in the RAM
2568 * because we don't want to map the entire memory in QEMU.
2569 * In that case just map until the end of the page.
2571 if (block
->offset
== 0) {
2572 return xen_map_cache(addr
, 0, 0, false);
2575 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2577 return ramblock_ptr(block
, addr
);
2580 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2581 * but takes a size argument.
2583 * Called within RCU critical section.
2585 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2586 hwaddr
*size
, bool lock
)
2588 RAMBlock
*block
= ram_block
;
2593 if (block
== NULL
) {
2594 block
= qemu_get_ram_block(addr
);
2595 addr
-= block
->offset
;
2597 *size
= MIN(*size
, block
->max_length
- addr
);
2599 if (xen_enabled() && block
->host
== NULL
) {
2600 /* We need to check if the requested address is in the RAM
2601 * because we don't want to map the entire memory in QEMU.
2602 * In that case just map the requested area.
2604 if (block
->offset
== 0) {
2605 return xen_map_cache(addr
, *size
, lock
, lock
);
2608 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2611 return ramblock_ptr(block
, addr
);
2614 /* Return the offset of a hostpointer within a ramblock */
2615 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2617 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2618 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2619 assert(res
< rb
->max_length
);
2625 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2628 * ptr: Host pointer to look up
2629 * round_offset: If true round the result offset down to a page boundary
2630 * *ram_addr: set to result ram_addr
2631 * *offset: set to result offset within the RAMBlock
2633 * Returns: RAMBlock (or NULL if not found)
2635 * By the time this function returns, the returned pointer is not protected
2636 * by RCU anymore. If the caller is not within an RCU critical section and
2637 * does not hold the iothread lock, it must have other means of protecting the
2638 * pointer, such as a reference to the region that includes the incoming
2641 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2645 uint8_t *host
= ptr
;
2647 if (xen_enabled()) {
2648 ram_addr_t ram_addr
;
2650 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2651 block
= qemu_get_ram_block(ram_addr
);
2653 *offset
= ram_addr
- block
->offset
;
2660 block
= atomic_rcu_read(&ram_list
.mru_block
);
2661 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2665 RAMBLOCK_FOREACH(block
) {
2666 /* This case append when the block is not mapped. */
2667 if (block
->host
== NULL
) {
2670 if (host
- block
->host
< block
->max_length
) {
2679 *offset
= (host
- block
->host
);
2681 *offset
&= TARGET_PAGE_MASK
;
2688 * Finds the named RAMBlock
2690 * name: The name of RAMBlock to find
2692 * Returns: RAMBlock (or NULL if not found)
2694 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2698 RAMBLOCK_FOREACH(block
) {
2699 if (!strcmp(name
, block
->idstr
)) {
2707 /* Some of the softmmu routines need to translate from a host pointer
2708 (typically a TLB entry) back to a ram offset. */
2709 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2714 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2716 return RAM_ADDR_INVALID
;
2719 return block
->offset
+ offset
;
2722 /* Called within RCU critical section. */
2723 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2726 ram_addr_t ram_addr
,
2730 ndi
->ram_addr
= ram_addr
;
2731 ndi
->mem_vaddr
= mem_vaddr
;
2735 assert(tcg_enabled());
2736 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2737 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2738 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2742 /* Called within RCU critical section. */
2743 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2746 assert(tcg_enabled());
2747 page_collection_unlock(ndi
->pages
);
2751 /* Set both VGA and migration bits for simplicity and to remove
2752 * the notdirty callback faster.
2754 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2755 DIRTY_CLIENTS_NOCODE
);
2756 /* we remove the notdirty callback only if the code has been
2758 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2759 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2763 /* Called within RCU critical section. */
2764 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2765 uint64_t val
, unsigned size
)
2769 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2772 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2773 memory_notdirty_write_complete(&ndi
);
2776 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2777 unsigned size
, bool is_write
,
2783 static const MemoryRegionOps notdirty_mem_ops
= {
2784 .write
= notdirty_mem_write
,
2785 .valid
.accepts
= notdirty_mem_accepts
,
2786 .endianness
= DEVICE_NATIVE_ENDIAN
,
2788 .min_access_size
= 1,
2789 .max_access_size
= 8,
2793 .min_access_size
= 1,
2794 .max_access_size
= 8,
2799 /* Generate a debug exception if a watchpoint has been hit. */
2800 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2802 CPUState
*cpu
= current_cpu
;
2803 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2807 assert(tcg_enabled());
2808 if (cpu
->watchpoint_hit
) {
2809 /* We re-entered the check after replacing the TB. Now raise
2810 * the debug interrupt so that is will trigger after the
2811 * current instruction. */
2812 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2815 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2816 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2817 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2818 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2819 && (wp
->flags
& flags
)) {
2820 if (flags
== BP_MEM_READ
) {
2821 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2823 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2825 wp
->hitaddr
= vaddr
;
2826 wp
->hitattrs
= attrs
;
2827 if (!cpu
->watchpoint_hit
) {
2828 if (wp
->flags
& BP_CPU
&&
2829 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2830 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2833 cpu
->watchpoint_hit
= wp
;
2836 tb_check_watchpoint(cpu
);
2837 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2838 cpu
->exception_index
= EXCP_DEBUG
;
2842 /* Force execution of one insn next time. */
2843 cpu
->cflags_next_tb
= 1 | curr_cflags();
2845 cpu_loop_exit_noexc(cpu
);
2849 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2854 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2855 so these check for a hit then pass through to the normal out-of-line
2857 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2858 unsigned size
, MemTxAttrs attrs
)
2862 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2863 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2865 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2868 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2871 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2874 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2877 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2885 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2886 uint64_t val
, unsigned size
,
2890 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2891 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2893 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2896 address_space_stb(as
, addr
, val
, attrs
, &res
);
2899 address_space_stw(as
, addr
, val
, attrs
, &res
);
2902 address_space_stl(as
, addr
, val
, attrs
, &res
);
2905 address_space_stq(as
, addr
, val
, attrs
, &res
);
2912 static const MemoryRegionOps watch_mem_ops
= {
2913 .read_with_attrs
= watch_mem_read
,
2914 .write_with_attrs
= watch_mem_write
,
2915 .endianness
= DEVICE_NATIVE_ENDIAN
,
2917 .min_access_size
= 1,
2918 .max_access_size
= 8,
2922 .min_access_size
= 1,
2923 .max_access_size
= 8,
2928 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2929 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
);
2930 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2931 const uint8_t *buf
, hwaddr len
);
2932 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
2933 bool is_write
, MemTxAttrs attrs
);
2935 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2936 unsigned len
, MemTxAttrs attrs
)
2938 subpage_t
*subpage
= opaque
;
2942 #if defined(DEBUG_SUBPAGE)
2943 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2944 subpage
, len
, addr
);
2946 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2950 *data
= ldn_p(buf
, len
);
2954 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2955 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2957 subpage_t
*subpage
= opaque
;
2960 #if defined(DEBUG_SUBPAGE)
2961 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2962 " value %"PRIx64
"\n",
2963 __func__
, subpage
, len
, addr
, value
);
2965 stn_p(buf
, len
, value
);
2966 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2969 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2970 unsigned len
, bool is_write
,
2973 subpage_t
*subpage
= opaque
;
2974 #if defined(DEBUG_SUBPAGE)
2975 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2976 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2979 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2980 len
, is_write
, attrs
);
2983 static const MemoryRegionOps subpage_ops
= {
2984 .read_with_attrs
= subpage_read
,
2985 .write_with_attrs
= subpage_write
,
2986 .impl
.min_access_size
= 1,
2987 .impl
.max_access_size
= 8,
2988 .valid
.min_access_size
= 1,
2989 .valid
.max_access_size
= 8,
2990 .valid
.accepts
= subpage_accepts
,
2991 .endianness
= DEVICE_NATIVE_ENDIAN
,
2994 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2999 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
3001 idx
= SUBPAGE_IDX(start
);
3002 eidx
= SUBPAGE_IDX(end
);
3003 #if defined(DEBUG_SUBPAGE)
3004 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
3005 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
3007 for (; idx
<= eidx
; idx
++) {
3008 mmio
->sub_section
[idx
] = section
;
3014 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
3018 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
3021 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
3022 NULL
, TARGET_PAGE_SIZE
);
3023 mmio
->iomem
.subpage
= true;
3024 #if defined(DEBUG_SUBPAGE)
3025 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
3026 mmio
, base
, TARGET_PAGE_SIZE
);
3028 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
3033 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
3036 MemoryRegionSection section
= {
3039 .offset_within_address_space
= 0,
3040 .offset_within_region
= 0,
3041 .size
= int128_2_64(),
3044 return phys_section_add(map
, §ion
);
3047 static void readonly_mem_write(void *opaque
, hwaddr addr
,
3048 uint64_t val
, unsigned size
)
3050 /* Ignore any write to ROM. */
3053 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
3054 unsigned size
, bool is_write
,
3060 /* This will only be used for writes, because reads are special cased
3061 * to directly access the underlying host ram.
3063 static const MemoryRegionOps readonly_mem_ops
= {
3064 .write
= readonly_mem_write
,
3065 .valid
.accepts
= readonly_mem_accepts
,
3066 .endianness
= DEVICE_NATIVE_ENDIAN
,
3068 .min_access_size
= 1,
3069 .max_access_size
= 8,
3073 .min_access_size
= 1,
3074 .max_access_size
= 8,
3079 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3080 hwaddr index
, MemTxAttrs attrs
)
3082 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3083 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3084 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3085 MemoryRegionSection
*sections
= d
->map
.sections
;
3087 return §ions
[index
& ~TARGET_PAGE_MASK
];
3090 static void io_mem_init(void)
3092 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3093 NULL
, NULL
, UINT64_MAX
);
3094 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3097 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3098 * which can be called without the iothread mutex.
3100 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3102 memory_region_clear_global_locking(&io_mem_notdirty
);
3104 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3108 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3110 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3113 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3114 assert(n
== PHYS_SECTION_UNASSIGNED
);
3115 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3116 assert(n
== PHYS_SECTION_NOTDIRTY
);
3117 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3118 assert(n
== PHYS_SECTION_ROM
);
3119 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3120 assert(n
== PHYS_SECTION_WATCH
);
3122 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3127 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3129 phys_sections_free(&d
->map
);
3133 static void tcg_commit(MemoryListener
*listener
)
3135 CPUAddressSpace
*cpuas
;
3136 AddressSpaceDispatch
*d
;
3138 assert(tcg_enabled());
3139 /* since each CPU stores ram addresses in its TLB cache, we must
3140 reset the modified entries */
3141 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3142 cpu_reloading_memory_map();
3143 /* The CPU and TLB are protected by the iothread lock.
3144 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3145 * may have split the RCU critical section.
3147 d
= address_space_to_dispatch(cpuas
->as
);
3148 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3149 tlb_flush(cpuas
->cpu
);
3152 static void memory_map_init(void)
3154 system_memory
= g_malloc(sizeof(*system_memory
));
3156 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3157 address_space_init(&address_space_memory
, system_memory
, "memory");
3159 system_io
= g_malloc(sizeof(*system_io
));
3160 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3162 address_space_init(&address_space_io
, system_io
, "I/O");
3165 MemoryRegion
*get_system_memory(void)
3167 return system_memory
;
3170 MemoryRegion
*get_system_io(void)
3175 #endif /* !defined(CONFIG_USER_ONLY) */
3177 /* physical memory access (slow version, mainly for debug) */
3178 #if defined(CONFIG_USER_ONLY)
3179 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3180 uint8_t *buf
, target_ulong len
, int is_write
)
3183 target_ulong l
, page
;
3187 page
= addr
& TARGET_PAGE_MASK
;
3188 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3191 flags
= page_get_flags(page
);
3192 if (!(flags
& PAGE_VALID
))
3195 if (!(flags
& PAGE_WRITE
))
3197 /* XXX: this code should not depend on lock_user */
3198 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3201 unlock_user(p
, addr
, l
);
3203 if (!(flags
& PAGE_READ
))
3205 /* XXX: this code should not depend on lock_user */
3206 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3209 unlock_user(p
, addr
, 0);
3220 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3223 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3224 addr
+= memory_region_get_ram_addr(mr
);
3226 /* No early return if dirty_log_mask is or becomes 0, because
3227 * cpu_physical_memory_set_dirty_range will still call
3228 * xen_modified_memory.
3230 if (dirty_log_mask
) {
3232 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3234 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3235 assert(tcg_enabled());
3236 tb_invalidate_phys_range(addr
, addr
+ length
);
3237 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3239 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3242 void memory_region_flush_rom_device(MemoryRegion
*mr
, hwaddr addr
, hwaddr size
)
3245 * In principle this function would work on other memory region types too,
3246 * but the ROM device use case is the only one where this operation is
3247 * necessary. Other memory regions should use the
3248 * address_space_read/write() APIs.
3250 assert(memory_region_is_romd(mr
));
3252 invalidate_and_set_dirty(mr
, addr
, size
);
3255 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3257 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3259 /* Regions are assumed to support 1-4 byte accesses unless
3260 otherwise specified. */
3261 if (access_size_max
== 0) {
3262 access_size_max
= 4;
3265 /* Bound the maximum access by the alignment of the address. */
3266 if (!mr
->ops
->impl
.unaligned
) {
3267 unsigned align_size_max
= addr
& -addr
;
3268 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3269 access_size_max
= align_size_max
;
3273 /* Don't attempt accesses larger than the maximum. */
3274 if (l
> access_size_max
) {
3275 l
= access_size_max
;
3282 static bool prepare_mmio_access(MemoryRegion
*mr
)
3284 bool unlocked
= !qemu_mutex_iothread_locked();
3285 bool release_lock
= false;
3287 if (unlocked
&& mr
->global_locking
) {
3288 qemu_mutex_lock_iothread();
3290 release_lock
= true;
3292 if (mr
->flush_coalesced_mmio
) {
3294 qemu_mutex_lock_iothread();
3296 qemu_flush_coalesced_mmio_buffer();
3298 qemu_mutex_unlock_iothread();
3302 return release_lock
;
3305 /* Called within RCU critical section. */
3306 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3309 hwaddr len
, hwaddr addr1
,
3310 hwaddr l
, MemoryRegion
*mr
)
3314 MemTxResult result
= MEMTX_OK
;
3315 bool release_lock
= false;
3318 if (!memory_access_is_direct(mr
, true)) {
3319 release_lock
|= prepare_mmio_access(mr
);
3320 l
= memory_access_size(mr
, l
, addr1
);
3321 /* XXX: could force current_cpu to NULL to avoid
3323 val
= ldn_p(buf
, l
);
3324 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3327 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3328 memcpy(ptr
, buf
, l
);
3329 invalidate_and_set_dirty(mr
, addr1
, l
);
3333 qemu_mutex_unlock_iothread();
3334 release_lock
= false;
3346 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3352 /* Called from RCU critical section. */
3353 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3354 const uint8_t *buf
, hwaddr len
)
3359 MemTxResult result
= MEMTX_OK
;
3362 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3363 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3369 /* Called within RCU critical section. */
3370 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3371 MemTxAttrs attrs
, uint8_t *buf
,
3372 hwaddr len
, hwaddr addr1
, hwaddr l
,
3377 MemTxResult result
= MEMTX_OK
;
3378 bool release_lock
= false;
3381 if (!memory_access_is_direct(mr
, false)) {
3383 release_lock
|= prepare_mmio_access(mr
);
3384 l
= memory_access_size(mr
, l
, addr1
);
3385 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3389 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3390 memcpy(buf
, ptr
, l
);
3394 qemu_mutex_unlock_iothread();
3395 release_lock
= false;
3407 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3413 /* Called from RCU critical section. */
3414 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3415 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3422 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3423 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3427 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3428 MemTxAttrs attrs
, uint8_t *buf
, hwaddr len
)
3430 MemTxResult result
= MEMTX_OK
;
3435 fv
= address_space_to_flatview(as
);
3436 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3443 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3445 const uint8_t *buf
, hwaddr len
)
3447 MemTxResult result
= MEMTX_OK
;
3452 fv
= address_space_to_flatview(as
);
3453 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3460 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3461 uint8_t *buf
, hwaddr len
, bool is_write
)
3464 return address_space_write(as
, addr
, attrs
, buf
, len
);
3466 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3470 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3471 hwaddr len
, int is_write
)
3473 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3474 buf
, len
, is_write
);
3477 enum write_rom_type
{
3482 static inline MemTxResult
address_space_write_rom_internal(AddressSpace
*as
,
3487 enum write_rom_type type
)
3497 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true, attrs
);
3499 if (!(memory_region_is_ram(mr
) ||
3500 memory_region_is_romd(mr
))) {
3501 l
= memory_access_size(mr
, l
, addr1
);
3504 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3507 memcpy(ptr
, buf
, l
);
3508 invalidate_and_set_dirty(mr
, addr1
, l
);
3511 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3523 /* used for ROM loading : can write in RAM and ROM */
3524 MemTxResult
address_space_write_rom(AddressSpace
*as
, hwaddr addr
,
3526 const uint8_t *buf
, hwaddr len
)
3528 return address_space_write_rom_internal(as
, addr
, attrs
,
3529 buf
, len
, WRITE_DATA
);
3532 void cpu_flush_icache_range(hwaddr start
, hwaddr len
)
3535 * This function should do the same thing as an icache flush that was
3536 * triggered from within the guest. For TCG we are always cache coherent,
3537 * so there is no need to flush anything. For KVM / Xen we need to flush
3538 * the host's instruction cache at least.
3540 if (tcg_enabled()) {
3544 address_space_write_rom_internal(&address_space_memory
,
3545 start
, MEMTXATTRS_UNSPECIFIED
,
3546 NULL
, len
, FLUSH_CACHE
);
3557 static BounceBuffer bounce
;
3559 typedef struct MapClient
{
3561 QLIST_ENTRY(MapClient
) link
;
3564 QemuMutex map_client_list_lock
;
3565 static QLIST_HEAD(, MapClient
) map_client_list
3566 = QLIST_HEAD_INITIALIZER(map_client_list
);
3568 static void cpu_unregister_map_client_do(MapClient
*client
)
3570 QLIST_REMOVE(client
, link
);
3574 static void cpu_notify_map_clients_locked(void)
3578 while (!QLIST_EMPTY(&map_client_list
)) {
3579 client
= QLIST_FIRST(&map_client_list
);
3580 qemu_bh_schedule(client
->bh
);
3581 cpu_unregister_map_client_do(client
);
3585 void cpu_register_map_client(QEMUBH
*bh
)
3587 MapClient
*client
= g_malloc(sizeof(*client
));
3589 qemu_mutex_lock(&map_client_list_lock
);
3591 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3592 if (!atomic_read(&bounce
.in_use
)) {
3593 cpu_notify_map_clients_locked();
3595 qemu_mutex_unlock(&map_client_list_lock
);
3598 void cpu_exec_init_all(void)
3600 qemu_mutex_init(&ram_list
.mutex
);
3601 /* The data structures we set up here depend on knowing the page size,
3602 * so no more changes can be made after this point.
3603 * In an ideal world, nothing we did before we had finished the
3604 * machine setup would care about the target page size, and we could
3605 * do this much later, rather than requiring board models to state
3606 * up front what their requirements are.
3608 finalize_target_page_bits();
3611 qemu_mutex_init(&map_client_list_lock
);
3614 void cpu_unregister_map_client(QEMUBH
*bh
)
3618 qemu_mutex_lock(&map_client_list_lock
);
3619 QLIST_FOREACH(client
, &map_client_list
, link
) {
3620 if (client
->bh
== bh
) {
3621 cpu_unregister_map_client_do(client
);
3625 qemu_mutex_unlock(&map_client_list_lock
);
3628 static void cpu_notify_map_clients(void)
3630 qemu_mutex_lock(&map_client_list_lock
);
3631 cpu_notify_map_clients_locked();
3632 qemu_mutex_unlock(&map_client_list_lock
);
3635 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, hwaddr len
,
3636 bool is_write
, MemTxAttrs attrs
)
3643 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3644 if (!memory_access_is_direct(mr
, is_write
)) {
3645 l
= memory_access_size(mr
, l
, addr
);
3646 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3657 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3658 hwaddr len
, bool is_write
,
3665 fv
= address_space_to_flatview(as
);
3666 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3672 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3674 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3675 bool is_write
, MemTxAttrs attrs
)
3679 MemoryRegion
*this_mr
;
3685 if (target_len
== 0) {
3690 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3691 &len
, is_write
, attrs
);
3692 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3698 /* Map a physical memory region into a host virtual address.
3699 * May map a subset of the requested range, given by and returned in *plen.
3700 * May return NULL if resources needed to perform the mapping are exhausted.
3701 * Use only for reads OR writes - not for read-modify-write operations.
3702 * Use cpu_register_map_client() to know when retrying the map operation is
3703 * likely to succeed.
3705 void *address_space_map(AddressSpace
*as
,
3723 fv
= address_space_to_flatview(as
);
3724 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3726 if (!memory_access_is_direct(mr
, is_write
)) {
3727 if (atomic_xchg(&bounce
.in_use
, true)) {
3731 /* Avoid unbounded allocations */
3732 l
= MIN(l
, TARGET_PAGE_SIZE
);
3733 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3737 memory_region_ref(mr
);
3740 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3746 return bounce
.buffer
;
3750 memory_region_ref(mr
);
3751 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3752 l
, is_write
, attrs
);
3753 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3759 /* Unmaps a memory region previously mapped by address_space_map().
3760 * Will also mark the memory as dirty if is_write == 1. access_len gives
3761 * the amount of memory that was actually read or written by the caller.
3763 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3764 int is_write
, hwaddr access_len
)
3766 if (buffer
!= bounce
.buffer
) {
3770 mr
= memory_region_from_host(buffer
, &addr1
);
3773 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3775 if (xen_enabled()) {
3776 xen_invalidate_map_cache_entry(buffer
);
3778 memory_region_unref(mr
);
3782 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3783 bounce
.buffer
, access_len
);
3785 qemu_vfree(bounce
.buffer
);
3786 bounce
.buffer
= NULL
;
3787 memory_region_unref(bounce
.mr
);
3788 atomic_mb_set(&bounce
.in_use
, false);
3789 cpu_notify_map_clients();
3792 void *cpu_physical_memory_map(hwaddr addr
,
3796 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3797 MEMTXATTRS_UNSPECIFIED
);
3800 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3801 int is_write
, hwaddr access_len
)
3803 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3806 #define ARG1_DECL AddressSpace *as
3809 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3810 #define RCU_READ_LOCK(...) rcu_read_lock()
3811 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3812 #include "memory_ldst.inc.c"
3814 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3820 AddressSpaceDispatch
*d
;
3827 cache
->fv
= address_space_get_flatview(as
);
3828 d
= flatview_to_dispatch(cache
->fv
);
3829 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3832 memory_region_ref(mr
);
3833 if (memory_access_is_direct(mr
, is_write
)) {
3834 /* We don't care about the memory attributes here as we're only
3835 * doing this if we found actual RAM, which behaves the same
3836 * regardless of attributes; so UNSPECIFIED is fine.
3838 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3839 cache
->xlat
, l
, is_write
,
3840 MEMTXATTRS_UNSPECIFIED
);
3841 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3847 cache
->is_write
= is_write
;
3851 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3855 assert(cache
->is_write
);
3856 if (likely(cache
->ptr
)) {
3857 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3861 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3863 if (!cache
->mrs
.mr
) {
3867 if (xen_enabled()) {
3868 xen_invalidate_map_cache_entry(cache
->ptr
);
3870 memory_region_unref(cache
->mrs
.mr
);
3871 flatview_unref(cache
->fv
);
3872 cache
->mrs
.mr
= NULL
;
3876 /* Called from RCU critical section. This function has the same
3877 * semantics as address_space_translate, but it only works on a
3878 * predefined range of a MemoryRegion that was mapped with
3879 * address_space_cache_init.
3881 static inline MemoryRegion
*address_space_translate_cached(
3882 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3883 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3885 MemoryRegionSection section
;
3887 IOMMUMemoryRegion
*iommu_mr
;
3888 AddressSpace
*target_as
;
3890 assert(!cache
->ptr
);
3891 *xlat
= addr
+ cache
->xlat
;
3894 iommu_mr
= memory_region_get_iommu(mr
);
3900 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3901 NULL
, is_write
, true,
3906 /* Called from RCU critical section. address_space_read_cached uses this
3907 * out of line function when the target is an MMIO or IOMMU region.
3910 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3911 void *buf
, hwaddr len
)
3917 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3918 MEMTXATTRS_UNSPECIFIED
);
3919 flatview_read_continue(cache
->fv
,
3920 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3924 /* Called from RCU critical section. address_space_write_cached uses this
3925 * out of line function when the target is an MMIO or IOMMU region.
3928 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3929 const void *buf
, hwaddr len
)
3935 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3936 MEMTXATTRS_UNSPECIFIED
);
3937 flatview_write_continue(cache
->fv
,
3938 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3942 #define ARG1_DECL MemoryRegionCache *cache
3944 #define SUFFIX _cached_slow
3945 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3946 #define RCU_READ_LOCK() ((void)0)
3947 #define RCU_READ_UNLOCK() ((void)0)
3948 #include "memory_ldst.inc.c"
3950 /* virtual memory access for debug (includes writing to ROM) */
3951 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3952 uint8_t *buf
, target_ulong len
, int is_write
)
3955 target_ulong l
, page
;
3957 cpu_synchronize_state(cpu
);
3962 page
= addr
& TARGET_PAGE_MASK
;
3963 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3964 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3965 /* if no physical page mapped, return an error */
3966 if (phys_addr
== -1)
3968 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3971 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3973 address_space_write_rom(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3976 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3987 * Allows code that needs to deal with migration bitmaps etc to still be built
3988 * target independent.
3990 size_t qemu_target_page_size(void)
3992 return TARGET_PAGE_SIZE
;
3995 int qemu_target_page_bits(void)
3997 return TARGET_PAGE_BITS
;
4000 int qemu_target_page_bits_min(void)
4002 return TARGET_PAGE_BITS_MIN
;
4006 bool target_words_bigendian(void)
4008 #if defined(TARGET_WORDS_BIGENDIAN)
4015 #ifndef CONFIG_USER_ONLY
4016 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
4023 mr
= address_space_translate(&address_space_memory
,
4024 phys_addr
, &phys_addr
, &l
, false,
4025 MEMTXATTRS_UNSPECIFIED
);
4027 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
4032 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
4038 RAMBLOCK_FOREACH(block
) {
4039 ret
= func(block
, opaque
);
4049 * Unmap pages of memory from start to start+length such that
4050 * they a) read as 0, b) Trigger whatever fault mechanism
4051 * the OS provides for postcopy.
4052 * The pages must be unmapped by the end of the function.
4053 * Returns: 0 on success, none-0 on failure
4056 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
4060 uint8_t *host_startaddr
= rb
->host
+ start
;
4062 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
4063 error_report("ram_block_discard_range: Unaligned start address: %p",
4068 if ((start
+ length
) <= rb
->used_length
) {
4069 bool need_madvise
, need_fallocate
;
4070 uint8_t *host_endaddr
= host_startaddr
+ length
;
4071 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
4072 error_report("ram_block_discard_range: Unaligned end address: %p",
4077 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4079 /* The logic here is messy;
4080 * madvise DONTNEED fails for hugepages
4081 * fallocate works on hugepages and shmem
4083 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4084 need_fallocate
= rb
->fd
!= -1;
4085 if (need_fallocate
) {
4086 /* For a file, this causes the area of the file to be zero'd
4087 * if read, and for hugetlbfs also causes it to be unmapped
4088 * so a userfault will trigger.
4090 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4091 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4095 error_report("ram_block_discard_range: Failed to fallocate "
4096 "%s:%" PRIx64
" +%zx (%d)",
4097 rb
->idstr
, start
, length
, ret
);
4102 error_report("ram_block_discard_range: fallocate not available/file"
4103 "%s:%" PRIx64
" +%zx (%d)",
4104 rb
->idstr
, start
, length
, ret
);
4109 /* For normal RAM this causes it to be unmapped,
4110 * for shared memory it causes the local mapping to disappear
4111 * and to fall back on the file contents (which we just
4112 * fallocate'd away).
4114 #if defined(CONFIG_MADVISE)
4115 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4118 error_report("ram_block_discard_range: Failed to discard range "
4119 "%s:%" PRIx64
" +%zx (%d)",
4120 rb
->idstr
, start
, length
, ret
);
4125 error_report("ram_block_discard_range: MADVISE not available"
4126 "%s:%" PRIx64
" +%zx (%d)",
4127 rb
->idstr
, start
, length
, ret
);
4131 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4132 need_madvise
, need_fallocate
, ret
);
4134 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4135 "/%zx/" RAM_ADDR_FMT
")",
4136 rb
->idstr
, start
, length
, rb
->used_length
);
4143 bool ramblock_is_pmem(RAMBlock
*rb
)
4145 return rb
->flags
& RAM_PMEM
;
4150 void page_size_init(void)
4152 /* NOTE: we can always suppose that qemu_host_page_size >=
4154 if (qemu_host_page_size
== 0) {
4155 qemu_host_page_size
= qemu_real_host_page_size
;
4157 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4158 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4160 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4163 #if !defined(CONFIG_USER_ONLY)
4165 static void mtree_print_phys_entries(int start
, int end
, int skip
, int ptr
)
4167 if (start
== end
- 1) {
4168 qemu_printf("\t%3d ", start
);
4170 qemu_printf("\t%3d..%-3d ", start
, end
- 1);
4172 qemu_printf(" skip=%d ", skip
);
4173 if (ptr
== PHYS_MAP_NODE_NIL
) {
4174 qemu_printf(" ptr=NIL");
4176 qemu_printf(" ptr=#%d", ptr
);
4178 qemu_printf(" ptr=[%d]", ptr
);
4183 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4184 int128_sub((size), int128_one())) : 0)
4186 void mtree_print_dispatch(AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4190 qemu_printf(" Dispatch\n");
4191 qemu_printf(" Physical sections\n");
4193 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4194 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4195 const char *names
[] = { " [unassigned]", " [not dirty]",
4196 " [ROM]", " [watch]" };
4198 qemu_printf(" #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
4201 s
->offset_within_address_space
,
4202 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4203 s
->mr
->name
? s
->mr
->name
: "(noname)",
4204 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4205 s
->mr
== root
? " [ROOT]" : "",
4206 s
== d
->mru_section
? " [MRU]" : "",
4207 s
->mr
->is_iommu
? " [iommu]" : "");
4210 qemu_printf(" alias=%s", s
->mr
->alias
->name
?
4211 s
->mr
->alias
->name
: "noname");
4216 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4217 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4218 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4221 Node
*n
= d
->map
.nodes
+ i
;
4223 qemu_printf(" [%d]\n", i
);
4225 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4226 PhysPageEntry
*pe
= *n
+ j
;
4228 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4232 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);
4238 if (jprev
!= ARRAY_SIZE(*n
)) {
4239 mtree_print_phys_entries(jprev
, j
, prev
.skip
, prev
.ptr
);