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libqos/ahci: allow nondata commands for ahci_io variants
[qemu/ar7.git] / tests / libqos / ahci.c
bloba9a745eef5d85b8ef372670b6dca7a17f418d8ef
1 /*
2 * libqos AHCI functions
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include <glib.h>
26
27 #include "libqtest.h"
28 #include "libqos/ahci.h"
29 #include "libqos/pci-pc.h"
30
31 #include "qemu-common.h"
32 #include "qemu/host-utils.h"
33
34 #include "hw/pci/pci_ids.h"
35 #include "hw/pci/pci_regs.h"
36
37 typedef struct AHCICommandProp {
38 uint8_t cmd; /* Command Code */
39 bool data; /* Data transfer command? */
40 bool pio;
41 bool dma;
42 bool lba28;
43 bool lba48;
44 bool read;
45 bool write;
46 bool atapi;
47 bool ncq;
48 uint64_t size; /* Static transfer size, for commands like IDENTIFY. */
49 uint32_t interrupts; /* Expected interrupts for this command. */
50 } AHCICommandProp;
51
52 AHCICommandProp ahci_command_properties[] = {
53 { .cmd = CMD_READ_PIO, .data = true, .pio = true,
54 .lba28 = true, .read = true },
55 { .cmd = CMD_WRITE_PIO, .data = true, .pio = true,
56 .lba28 = true, .write = true },
57 { .cmd = CMD_READ_PIO_EXT, .data = true, .pio = true,
58 .lba48 = true, .read = true },
59 { .cmd = CMD_WRITE_PIO_EXT, .data = true, .pio = true,
60 .lba48 = true, .write = true },
61 { .cmd = CMD_READ_DMA, .data = true, .dma = true,
62 .lba28 = true, .read = true },
63 { .cmd = CMD_WRITE_DMA, .data = true, .dma = true,
64 .lba28 = true, .write = true },
65 { .cmd = CMD_READ_DMA_EXT, .data = true, .dma = true,
66 .lba48 = true, .read = true },
67 { .cmd = CMD_WRITE_DMA_EXT, .data = true, .dma = true,
68 .lba48 = true, .write = true },
69 { .cmd = CMD_IDENTIFY, .data = true, .pio = true,
70 .size = 512, .read = true },
71 { .cmd = READ_FPDMA_QUEUED, .data = true, .dma = true,
72 .lba48 = true, .read = true, .ncq = true },
73 { .cmd = WRITE_FPDMA_QUEUED, .data = true, .dma = true,
74 .lba48 = true, .write = true, .ncq = true },
75 { .cmd = CMD_READ_MAX, .lba28 = true },
76 { .cmd = CMD_READ_MAX_EXT, .lba48 = true },
77 { .cmd = CMD_FLUSH_CACHE, .data = false },
78 { .cmd = CMD_PACKET, .data = true, .size = 16,
79 .atapi = true, .pio = true },
80 { .cmd = CMD_PACKET_ID, .data = true, .pio = true,
81 .size = 512, .read = true }
82 };
83
84 struct AHCICommand {
85 /* Test Management Data */
86 uint8_t name;
87 uint8_t port;
88 uint8_t slot;
89 uint32_t interrupts;
90 uint64_t xbytes;
91 uint32_t prd_size;
92 uint64_t buffer;
93 AHCICommandProp *props;
94 /* Data to be transferred to the guest */
95 AHCICommandHeader header;
96 RegH2DFIS fis;
97 unsigned char *atapi_cmd;
98 };
99
100 /**
101 * Allocate space in the guest using information in the AHCIQState object.
102 */
103 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
104 {
105 g_assert(ahci);
106 g_assert(ahci->parent);
107 return qmalloc(ahci->parent, bytes);
108 }
109
110 void ahci_free(AHCIQState *ahci, uint64_t addr)
111 {
112 g_assert(ahci);
113 g_assert(ahci->parent);
114 qfree(ahci->parent, addr);
115 }
116
117 bool is_atapi(AHCIQState *ahci, uint8_t port)
118 {
119 return ahci_px_rreg(ahci, port, AHCI_PX_SIG) == AHCI_SIGNATURE_CDROM;
120 }
121
122 /**
123 * Locate, verify, and return a handle to the AHCI device.
124 */
125 QPCIDevice *get_ahci_device(uint32_t *fingerprint)
126 {
127 QPCIDevice *ahci;
128 uint32_t ahci_fingerprint;
129 QPCIBus *pcibus;
130
131 pcibus = qpci_init_pc();
132
133 /* Find the AHCI PCI device and verify it's the right one. */
134 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
135 g_assert(ahci != NULL);
136
137 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
138
139 switch (ahci_fingerprint) {
140 case AHCI_INTEL_ICH9:
141 break;
142 default:
143 /* Unknown device. */
144 g_assert_not_reached();
145 }
146
147 if (fingerprint) {
148 *fingerprint = ahci_fingerprint;
149 }
150 return ahci;
151 }
152
153 void free_ahci_device(QPCIDevice *dev)
154 {
155 QPCIBus *pcibus = dev ? dev->bus : NULL;
156
157 /* libqos doesn't have a function for this, so free it manually */
158 g_free(dev);
159 qpci_free_pc(pcibus);
160 }
161
162 /* Free all memory in-use by the AHCI device. */
163 void ahci_clean_mem(AHCIQState *ahci)
164 {
165 uint8_t port, slot;
166
167 for (port = 0; port < 32; ++port) {
168 if (ahci->port[port].fb) {
169 ahci_free(ahci, ahci->port[port].fb);
170 ahci->port[port].fb = 0;
171 }
172 if (ahci->port[port].clb) {
173 for (slot = 0; slot < 32; slot++) {
174 ahci_destroy_command(ahci, port, slot);
175 }
176 ahci_free(ahci, ahci->port[port].clb);
177 ahci->port[port].clb = 0;
178 }
179 }
180 }
181
182 /*** Logical Device Initialization ***/
183
184 /**
185 * Start the PCI device and sanity-check default operation.
186 */
187 void ahci_pci_enable(AHCIQState *ahci)
188 {
189 uint8_t reg;
190
191 start_ahci_device(ahci);
192
193 switch (ahci->fingerprint) {
194 case AHCI_INTEL_ICH9:
195 /* ICH9 has a register at PCI 0x92 that
196 * acts as a master port enabler mask. */
197 reg = qpci_config_readb(ahci->dev, 0x92);
198 reg |= 0x3F;
199 qpci_config_writeb(ahci->dev, 0x92, reg);
200 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
201 ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
202 break;
203 }
204
205 }
206
207 /**
208 * Map BAR5/ABAR, and engage the PCI device.
209 */
210 void start_ahci_device(AHCIQState *ahci)
211 {
212 /* Map AHCI's ABAR (BAR5) */
213 ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
214 g_assert(ahci->hba_base);
215
216 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
217 qpci_device_enable(ahci->dev);
218 }
219
220 /**
221 * Test and initialize the AHCI's HBA memory areas.
222 * Initialize and start any ports with devices attached.
223 * Bring the HBA into the idle state.
224 */
225 void ahci_hba_enable(AHCIQState *ahci)
226 {
227 /* Bits of interest in this section:
228 * GHC.AE Global Host Control / AHCI Enable
229 * PxCMD.ST Port Command: Start
230 * PxCMD.SUD "Spin Up Device"
231 * PxCMD.POD "Power On Device"
232 * PxCMD.FRE "FIS Receive Enable"
233 * PxCMD.FR "FIS Receive Running"
234 * PxCMD.CR "Command List Running"
235 */
236 uint32_t reg, ports_impl;
237 uint16_t i;
238 uint8_t num_cmd_slots;
239
240 g_assert(ahci != NULL);
241
242 /* Set GHC.AE to 1 */
243 ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
244 reg = ahci_rreg(ahci, AHCI_GHC);
245 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
246
247 /* Cache CAP and CAP2. */
248 ahci->cap = ahci_rreg(ahci, AHCI_CAP);
249 ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
250
251 /* Read CAP.NCS, how many command slots do we have? */
252 num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
253 g_test_message("Number of Command Slots: %u", num_cmd_slots);
254
255 /* Determine which ports are implemented. */
256 ports_impl = ahci_rreg(ahci, AHCI_PI);
257
258 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
259 if (!(ports_impl & 0x01)) {
260 continue;
261 }
262
263 g_test_message("Initializing port %u", i);
264
265 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
266 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
267 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
268 g_test_message("port is idle");
269 } else {
270 g_test_message("port needs to be idled");
271 ahci_px_clr(ahci, i, AHCI_PX_CMD,
272 (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
273 /* The port has 500ms to disengage. */
274 usleep(500000);
275 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
276 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
277 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
278 g_test_message("port is now idle");
279 /* The spec does allow for possibly needing a PORT RESET
280 * or HBA reset if we fail to idle the port. */
281 }
282
283 /* Allocate Memory for the Command List Buffer & FIS Buffer */
284 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
285 ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
286 qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);
287 g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
288 ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
289 g_assert_cmphex(ahci->port[i].clb, ==,
290 ahci_px_rreg(ahci, i, AHCI_PX_CLB));
291
292 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
293 ahci->port[i].fb = ahci_alloc(ahci, 0x100);
294 qmemset(ahci->port[i].fb, 0x00, 0x100);
295 g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
296 ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
297 g_assert_cmphex(ahci->port[i].fb, ==,
298 ahci_px_rreg(ahci, i, AHCI_PX_FB));
299
300 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
301 ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
302 ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
303 ahci_wreg(ahci, AHCI_IS, (1 << i));
304
305 /* Verify Interrupts Cleared */
306 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
307 g_assert_cmphex(reg, ==, 0);
308
309 reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
310 g_assert_cmphex(reg, ==, 0);
311
312 reg = ahci_rreg(ahci, AHCI_IS);
313 ASSERT_BIT_CLEAR(reg, (1 << i));
314
315 /* Enable All Interrupts: */
316 ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
317 reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
318 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
319
320 /* Enable the FIS Receive Engine. */
321 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
322 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
323 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
324
325 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
326 * physical presence, a device is present and may be started. However,
327 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
328 reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
329 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
330 ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
331 }
332
333 reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
334 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
335 reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
336 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
337 /* Device Found: set PxCMD.ST := 1 */
338 ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
339 ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
340 AHCI_PX_CMD_CR);
341 g_test_message("Started Device %u", i);
342 } else if ((reg & AHCI_PX_SSTS_DET)) {
343 /* Device present, but in some unknown state. */
344 g_assert_not_reached();
345 }
346 }
347 }
348
349 /* Enable GHC.IE */
350 ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
351 reg = ahci_rreg(ahci, AHCI_GHC);
352 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
353
354 /* TODO: The device should now be idling and waiting for commands.
355 * In the future, a small test-case to inspect the Register D2H FIS
356 * and clear the initial interrupts might be good. */
357 }
358
359 /**
360 * Pick the first implemented and running port
361 */
362 unsigned ahci_port_select(AHCIQState *ahci)
363 {
364 uint32_t ports, reg;
365 unsigned i;
366
367 ports = ahci_rreg(ahci, AHCI_PI);
368 for (i = 0; i < 32; ports >>= 1, ++i) {
369 if (ports == 0) {
370 i = 32;
371 }
372
373 if (!(ports & 0x01)) {
374 continue;
375 }
376
377 reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
378 if (BITSET(reg, AHCI_PX_CMD_ST)) {
379 break;
380 }
381 }
382 g_assert(i < 32);
383 return i;
384 }
385
386 /**
387 * Clear a port's interrupts and status information prior to a test.
388 */
389 void ahci_port_clear(AHCIQState *ahci, uint8_t port)
390 {
391 uint32_t reg;
392
393 /* Clear out this port's interrupts (ignore the init register d2h fis) */
394 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
395 ahci_px_wreg(ahci, port, AHCI_PX_IS, reg);
396 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
397
398 /* Wipe the FIS-Receive Buffer */
399 qmemset(ahci->port[port].fb, 0x00, 0x100);
400 }
401
402 /**
403 * Check a port for errors.
404 */
405 void ahci_port_check_error(AHCIQState *ahci, uint8_t port)
406 {
407 uint32_t reg;
408
409 /* The upper 9 bits of the IS register all indicate errors. */
410 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
411 reg >>= 23;
412 g_assert_cmphex(reg, ==, 0);
413
414 /* The Sata Error Register should be empty. */
415 reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
416 g_assert_cmphex(reg, ==, 0);
417
418 /* The TFD also has two error sections. */
419 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
420 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
421 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
422 }
423
424 void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port,
425 uint32_t intr_mask)
426 {
427 uint32_t reg;
428
429 /* Check for expected interrupts */
430 reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
431 ASSERT_BIT_SET(reg, intr_mask);
432
433 /* Clear expected interrupts and assert all interrupts now cleared. */
434 ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask);
435 g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
436 }
437
438 void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot)
439 {
440 uint32_t reg;
441
442 /* Assert that the command slot is no longer busy (NCQ) */
443 reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
444 ASSERT_BIT_CLEAR(reg, (1 << slot));
445
446 /* Non-NCQ */
447 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
448 ASSERT_BIT_CLEAR(reg, (1 << slot));
449
450 /* And assert that we are generally not busy. */
451 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
452 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
453 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_DRQ);
454 }
455
456 void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
457 {
458 RegD2HFIS *d2h = g_malloc0(0x20);
459 uint32_t reg;
460
461 memread(ahci->port[port].fb + 0x40, d2h, 0x20);
462 g_assert_cmphex(d2h->fis_type, ==, 0x34);
463
464 reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
465 g_assert_cmphex((reg & AHCI_PX_TFD_ERR) >> 8, ==, d2h->error);
466 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, d2h->status);
467
468 g_free(d2h);
469 }
470
471 void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
472 uint8_t slot, size_t buffsize)
473 {
474 PIOSetupFIS *pio = g_malloc0(0x20);
475
476 /* We cannot check the Status or E_Status registers, because
477 * the status may have again changed between the PIO Setup FIS
478 * and the conclusion of the command with the D2H Register FIS. */
479 memread(ahci->port[port].fb + 0x20, pio, 0x20);
480 g_assert_cmphex(pio->fis_type, ==, 0x5f);
481
482 /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
483 * transfer size in a uint16_t field. The maximum transfer size can
484 * eclipse this; the field is meant to convey the size of data per
485 * each Data FIS, not the entire operation as a whole. For now,
486 * we will sanity check the broken case where applicable. */
487 if (buffsize <= UINT16_MAX) {
488 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, buffsize);
489 }
490
491 g_free(pio);
492 }
493
494 void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd)
495 {
496 AHCICommandHeader cmdh;
497
498 ahci_get_command_header(ahci, cmd->port, cmd->slot, &cmdh);
499 /* Physical Region Descriptor Byte Count is not required to work for NCQ. */
500 if (!cmd->props->ncq) {
501 g_assert_cmphex(cmd->xbytes, ==, cmdh.prdbc);
502 }
503 }
504
505 /* Get the command in #slot of port #port. */
506 void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
507 uint8_t slot, AHCICommandHeader *cmd)
508 {
509 uint64_t ba = ahci->port[port].clb;
510 ba += slot * sizeof(AHCICommandHeader);
511 memread(ba, cmd, sizeof(AHCICommandHeader));
512
513 cmd->flags = le16_to_cpu(cmd->flags);
514 cmd->prdtl = le16_to_cpu(cmd->prdtl);
515 cmd->prdbc = le32_to_cpu(cmd->prdbc);
516 cmd->ctba = le64_to_cpu(cmd->ctba);
517 }
518
519 /* Set the command in #slot of port #port. */
520 void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
521 uint8_t slot, AHCICommandHeader *cmd)
522 {
523 AHCICommandHeader tmp = { .flags = 0 };
524 uint64_t ba = ahci->port[port].clb;
525 ba += slot * sizeof(AHCICommandHeader);
526
527 tmp.flags = cpu_to_le16(cmd->flags);
528 tmp.prdtl = cpu_to_le16(cmd->prdtl);
529 tmp.prdbc = cpu_to_le32(cmd->prdbc);
530 tmp.ctba = cpu_to_le64(cmd->ctba);
531
532 memwrite(ba, &tmp, sizeof(AHCICommandHeader));
533 }
534
535 void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
536 {
537 AHCICommandHeader cmd;
538
539 /* Obtain the Nth Command Header */
540 ahci_get_command_header(ahci, port, slot, &cmd);
541 if (cmd.ctba == 0) {
542 /* No address in it, so just return -- it's empty. */
543 goto tidy;
544 }
545
546 /* Free the Table */
547 ahci_free(ahci, cmd.ctba);
548
549 tidy:
550 /* NULL the header. */
551 memset(&cmd, 0x00, sizeof(cmd));
552 ahci_set_command_header(ahci, port, slot, &cmd);
553 ahci->port[port].ctba[slot] = 0;
554 ahci->port[port].prdtl[slot] = 0;
555 }
556
557 void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
558 {
559 RegH2DFIS tmp = cmd->fis;
560 uint64_t addr = cmd->header.ctba;
561
562 /* NCQ commands use exclusively 8 bit fields and needs no adjustment.
563 * Only the count field needs to be adjusted for non-NCQ commands.
564 * The auxiliary FIS fields are defined per-command and are not currently
565 * implemented in libqos/ahci.o, but may or may not need to be flipped. */
566 if (!cmd->props->ncq) {
567 tmp.count = cpu_to_le16(tmp.count);
568 }
569
570 memwrite(addr, &tmp, sizeof(tmp));
571 }
572
573 unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
574 {
575 unsigned i;
576 unsigned j;
577 uint32_t reg;
578
579 reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
580
581 /* Pick the least recently used command slot that's available */
582 for (i = 0; i < 32; ++i) {
583 j = ((ahci->port[port].next + i) % 32);
584 if (reg & (1 << j)) {
585 continue;
586 }
587 ahci_destroy_command(ahci, port, j);
588 ahci->port[port].next = (j + 1) % 32;
589 return j;
590 }
591
592 g_test_message("All command slots were busy.");
593 g_assert_not_reached();
594 }
595
596 inline unsigned size_to_prdtl(unsigned bytes, unsigned bytes_per_prd)
597 {
598 /* Each PRD can describe up to 4MiB */
599 g_assert_cmphex(bytes_per_prd, <=, 4096 * 1024);
600 g_assert_cmphex(bytes_per_prd & 0x01, ==, 0x00);
601 return (bytes + bytes_per_prd - 1) / bytes_per_prd;
602 }
603
604 /* Issue a command, expecting it to fail and STOP the VM */
605 AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
606 uint8_t ide_cmd, uint64_t buffer,
607 size_t bufsize, uint64_t sector)
608 {
609 AHCICommand *cmd;
610
611 cmd = ahci_command_create(ide_cmd);
612 ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
613 ahci_command_commit(ahci, cmd, port);
614 ahci_command_issue_async(ahci, cmd);
615 qmp_eventwait("STOP");
616
617 return cmd;
618 }
619
620 /* Resume a previously failed command and verify/finalize */
621 void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
622 {
623 /* Complete the command */
624 qmp_async("{'execute':'cont' }");
625 qmp_eventwait("RESUME");
626 ahci_command_wait(ahci, cmd);
627 ahci_command_verify(ahci, cmd);
628 ahci_command_free(cmd);
629 }
630
631 /* Given a guest buffer address, perform an IO operation */
632 void ahci_guest_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
633 uint64_t buffer, size_t bufsize, uint64_t sector)
634 {
635 AHCICommand *cmd;
636 cmd = ahci_command_create(ide_cmd);
637 ahci_command_set_buffer(cmd, buffer);
638 ahci_command_set_size(cmd, bufsize);
639 if (sector) {
640 ahci_command_set_offset(cmd, sector);
641 }
642 ahci_command_commit(ahci, cmd, port);
643 ahci_command_issue(ahci, cmd);
644 ahci_command_verify(ahci, cmd);
645 ahci_command_free(cmd);
646 }
647
648 static AHCICommandProp *ahci_command_find(uint8_t command_name)
649 {
650 int i;
651
652 for (i = 0; i < ARRAY_SIZE(ahci_command_properties); i++) {
653 if (ahci_command_properties[i].cmd == command_name) {
654 return &ahci_command_properties[i];
655 }
656 }
657
658 return NULL;
659 }
660
661 /* Given a HOST buffer, create a buffer address and perform an IO operation. */
662 void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
663 void *buffer, size_t bufsize, uint64_t sector)
664 {
665 uint64_t ptr;
666 AHCICommandProp *props;
667
668 props = ahci_command_find(ide_cmd);
669 g_assert(props);
670 ptr = ahci_alloc(ahci, bufsize);
671 g_assert(!bufsize || ptr);
672 qmemset(ptr, 0x00, bufsize);
673
674 if (bufsize && props->write) {
675 bufwrite(ptr, buffer, bufsize);
676 }
677
678 ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
679
680 if (bufsize && props->read) {
681 bufread(ptr, buffer, bufsize);
682 }
683
684 ahci_free(ahci, ptr);
685 }
686
687 /**
688 * Initializes a basic command header in memory.
689 * We assume that this is for an ATA command using RegH2DFIS.
690 */
691 static void command_header_init(AHCICommand *cmd)
692 {
693 AHCICommandHeader *hdr = &cmd->header;
694 AHCICommandProp *props = cmd->props;
695
696 hdr->flags = 5; /* RegH2DFIS is 5 DW long. Must be < 32 */
697 hdr->flags |= CMDH_CLR_BSY; /* Clear the BSY bit when done */
698 if (props->write) {
699 hdr->flags |= CMDH_WRITE;
700 }
701 if (props->atapi) {
702 hdr->flags |= CMDH_ATAPI;
703 }
704 /* Other flags: PREFETCH, RESET, and BIST */
705 hdr->prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
706 hdr->prdbc = 0;
707 hdr->ctba = 0;
708 }
709
710 static void command_table_init(AHCICommand *cmd)
711 {
712 RegH2DFIS *fis = &(cmd->fis);
713 uint16_t sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
714
715 fis->fis_type = REG_H2D_FIS;
716 fis->flags = REG_H2D_FIS_CMD; /* "Command" bit */
717 fis->command = cmd->name;
718
719 if (cmd->props->ncq) {
720 NCQFIS *ncqfis = (NCQFIS *)fis;
721 /* NCQ is weird and re-uses FIS frames for unrelated data.
722 * See SATA 3.2, 13.6.4.1 READ FPDMA QUEUED for an example. */
723 ncqfis->sector_low = sect_count & 0xFF;
724 ncqfis->sector_hi = (sect_count >> 8) & 0xFF;
725 ncqfis->device = NCQ_DEVICE_MAGIC;
726 /* Force Unit Access is bit 7 in the device register */
727 ncqfis->tag = 0; /* bits 3-7 are the NCQ tag */
728 ncqfis->prio = 0; /* bits 6,7 are a prio tag */
729 /* RARC bit is bit 0 of TAG field */
730 } else {
731 fis->feature_low = 0x00;
732 fis->feature_high = 0x00;
733 if (cmd->props->lba28 || cmd->props->lba48) {
734 fis->device = ATA_DEVICE_LBA;
735 }
736 fis->count = (cmd->xbytes / AHCI_SECTOR_SIZE);
737 }
738 fis->icc = 0x00;
739 fis->control = 0x00;
740 memset(fis->aux, 0x00, ARRAY_SIZE(fis->aux));
741 }
742
743 void ahci_command_enable_atapi_dma(AHCICommand *cmd)
744 {
745 RegH2DFIS *fis = &(cmd->fis);
746 g_assert(cmd->props->atapi);
747 fis->feature_low |= 0x01;
748 cmd->interrupts &= ~AHCI_PX_IS_PSS;
749 cmd->props->dma = true;
750 cmd->props->pio = false;
751 /* BUG: We expect the DMA Setup interrupt for DMA commands */
752 /* cmd->interrupts |= AHCI_PX_IS_DSS; */
753 }
754
755 AHCICommand *ahci_command_create(uint8_t command_name)
756 {
757 AHCICommandProp *props = ahci_command_find(command_name);
758 AHCICommand *cmd;
759
760 g_assert(props);
761 cmd = g_malloc0(sizeof(AHCICommand));
762 g_assert(!(props->dma && props->pio));
763 g_assert(!(props->lba28 && props->lba48));
764 g_assert(!(props->read && props->write));
765 g_assert(!props->size || props->data);
766 g_assert(!props->ncq || props->lba48);
767
768 /* Defaults and book-keeping */
769 cmd->props = g_memdup(props, sizeof(AHCICommandProp));
770 cmd->name = command_name;
771 cmd->xbytes = props->size;
772 cmd->prd_size = 4096;
773 cmd->buffer = 0xabad1dea;
774
775 if (!cmd->props->ncq) {
776 cmd->interrupts = AHCI_PX_IS_DHRS;
777 }
778 /* BUG: We expect the DPS interrupt for data commands */
779 /* cmd->interrupts |= props->data ? AHCI_PX_IS_DPS : 0; */
780 /* BUG: We expect the DMA Setup interrupt for DMA commands */
781 /* cmd->interrupts |= props->dma ? AHCI_PX_IS_DSS : 0; */
782 cmd->interrupts |= props->pio ? AHCI_PX_IS_PSS : 0;
783 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;
784
785 command_header_init(cmd);
786 command_table_init(cmd);
787
788 return cmd;
789 }
790
791 AHCICommand *ahci_atapi_command_create(uint8_t scsi_cmd)
792 {
793 AHCICommand *cmd = ahci_command_create(CMD_PACKET);
794 cmd->atapi_cmd = g_malloc0(16);
795 cmd->atapi_cmd[0] = scsi_cmd;
796 /* ATAPI needs a PIO transfer chunk size set inside of the LBA registers.
797 * The block/sector size is a natural default. */
798 cmd->fis.lba_lo[1] = ATAPI_SECTOR_SIZE >> 8 & 0xFF;
799 cmd->fis.lba_lo[2] = ATAPI_SECTOR_SIZE & 0xFF;
800
801 return cmd;
802 }
803
804 void ahci_command_free(AHCICommand *cmd)
805 {
806 g_free(cmd->atapi_cmd);
807 g_free(cmd->props);
808 g_free(cmd);
809 }
810
811 void ahci_command_set_flags(AHCICommand *cmd, uint16_t cmdh_flags)
812 {
813 cmd->header.flags |= cmdh_flags;
814 }
815
816 void ahci_command_clr_flags(AHCICommand *cmd, uint16_t cmdh_flags)
817 {
818 cmd->header.flags &= ~cmdh_flags;
819 }
820
821 static void ahci_atapi_command_set_offset(AHCICommand *cmd, uint64_t lba)
822 {
823 unsigned char *cbd = cmd->atapi_cmd;
824 g_assert(cbd);
825
826 switch (cbd[0]) {
827 case CMD_ATAPI_READ_10:
828 g_assert_cmpuint(lba, <=, UINT32_MAX);
829 stl_be_p(&cbd[2], lba);
830 break;
831 default:
832 /* SCSI doesn't have uniform packet formats,
833 * so you have to add support for it manually. Sorry! */
834 g_assert_not_reached();
835 }
836 }
837
838 void ahci_command_set_offset(AHCICommand *cmd, uint64_t lba_sect)
839 {
840 RegH2DFIS *fis = &(cmd->fis);
841
842 if (cmd->props->atapi) {
843 ahci_atapi_command_set_offset(cmd, lba_sect);
844 return;
845 } else if (!cmd->props->data && !lba_sect) {
846 /* Not meaningful, ignore. */
847 return;
848 } else if (cmd->props->lba28) {
849 g_assert_cmphex(lba_sect, <=, 0xFFFFFFF);
850 } else if (cmd->props->lba48 || cmd->props->ncq) {
851 g_assert_cmphex(lba_sect, <=, 0xFFFFFFFFFFFF);
852 } else {
853 /* Can't set offset if we don't know the format. */
854 g_assert_not_reached();
855 }
856
857 /* LBA28 uses the low nibble of the device/control register for LBA24:27 */
858 fis->lba_lo[0] = (lba_sect & 0xFF);
859 fis->lba_lo[1] = (lba_sect >> 8) & 0xFF;
860 fis->lba_lo[2] = (lba_sect >> 16) & 0xFF;
861 if (cmd->props->lba28) {
862 fis->device = (fis->device & 0xF0) | ((lba_sect >> 24) & 0x0F);
863 }
864 fis->lba_hi[0] = (lba_sect >> 24) & 0xFF;
865 fis->lba_hi[1] = (lba_sect >> 32) & 0xFF;
866 fis->lba_hi[2] = (lba_sect >> 40) & 0xFF;
867 }
868
869 void ahci_command_set_buffer(AHCICommand *cmd, uint64_t buffer)
870 {
871 cmd->buffer = buffer;
872 }
873
874 static void ahci_atapi_set_size(AHCICommand *cmd, uint64_t xbytes)
875 {
876 unsigned char *cbd = cmd->atapi_cmd;
877 uint64_t nsectors = xbytes / 2048;
878 g_assert(cbd);
879
880 switch (cbd[0]) {
881 case CMD_ATAPI_READ_10:
882 g_assert_cmpuint(nsectors, <=, UINT16_MAX);
883 stw_be_p(&cbd[7], nsectors);
884 break;
885 default:
886 /* SCSI doesn't have uniform packet formats,
887 * so you have to add support for it manually. Sorry! */
888 g_assert_not_reached();
889 }
890 }
891
892 void ahci_command_set_sizes(AHCICommand *cmd, uint64_t xbytes,
893 unsigned prd_size)
894 {
895 uint16_t sect_count;
896
897 /* Each PRD can describe up to 4MiB, and must not be odd. */
898 g_assert_cmphex(prd_size, <=, 4096 * 1024);
899 g_assert_cmphex(prd_size & 0x01, ==, 0x00);
900 if (prd_size) {
901 cmd->prd_size = prd_size;
902 }
903 cmd->xbytes = xbytes;
904 sect_count = (cmd->xbytes / AHCI_SECTOR_SIZE);
905
906 if (cmd->props->ncq) {
907 NCQFIS *nfis = (NCQFIS *)&(cmd->fis);
908 nfis->sector_low = sect_count & 0xFF;
909 nfis->sector_hi = (sect_count >> 8) & 0xFF;
910 } else if (cmd->props->atapi) {
911 ahci_atapi_set_size(cmd, xbytes);
912 } else {
913 cmd->fis.count = sect_count;
914 }
915 cmd->header.prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
916 }
917
918 void ahci_command_set_size(AHCICommand *cmd, uint64_t xbytes)
919 {
920 ahci_command_set_sizes(cmd, xbytes, cmd->prd_size);
921 }
922
923 void ahci_command_set_prd_size(AHCICommand *cmd, unsigned prd_size)
924 {
925 ahci_command_set_sizes(cmd, cmd->xbytes, prd_size);
926 }
927
928 void ahci_command_adjust(AHCICommand *cmd, uint64_t offset, uint64_t buffer,
929 uint64_t xbytes, unsigned prd_size)
930 {
931 ahci_command_set_sizes(cmd, xbytes, prd_size);
932 ahci_command_set_buffer(cmd, buffer);
933 ahci_command_set_offset(cmd, offset);
934 }
935
936 void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
937 {
938 uint16_t i, prdtl;
939 uint64_t table_size, table_ptr, remaining;
940 PRD prd;
941
942 /* This command is now tied to this port/command slot */
943 cmd->port = port;
944 cmd->slot = ahci_pick_cmd(ahci, port);
945
946 if (cmd->props->ncq) {
947 NCQFIS *nfis = (NCQFIS *)&cmd->fis;
948 nfis->tag = (cmd->slot << 3) & 0xFC;
949 }
950
951 /* Create a buffer for the command table */
952 prdtl = size_to_prdtl(cmd->xbytes, cmd->prd_size);
953 table_size = CMD_TBL_SIZ(prdtl);
954 table_ptr = ahci_alloc(ahci, table_size);
955 g_assert(table_ptr);
956 /* AHCI 1.3: Must be aligned to 0x80 */
957 g_assert((table_ptr & 0x7F) == 0x00);
958 cmd->header.ctba = table_ptr;
959
960 /* Commit the command header (part of the Command List Buffer) */
961 ahci_set_command_header(ahci, port, cmd->slot, &(cmd->header));
962 /* Now, write the command table (FIS, ACMD, and PRDT) -- FIS first, */
963 ahci_write_fis(ahci, cmd);
964 /* Then ATAPI CMD, if needed */
965 if (cmd->props->atapi) {
966 memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);
967 }
968
969 /* Construct and write the PRDs to the command table */
970 g_assert_cmphex(prdtl, ==, cmd->header.prdtl);
971 remaining = cmd->xbytes;
972 for (i = 0; i < prdtl; ++i) {
973 prd.dba = cpu_to_le64(cmd->buffer + (cmd->prd_size * i));
974 prd.res = 0;
975 if (remaining > cmd->prd_size) {
976 /* Note that byte count is 0-based. */
977 prd.dbc = cpu_to_le32(cmd->prd_size - 1);
978 remaining -= cmd->prd_size;
979 } else {
980 /* Again, dbc is 0-based. */
981 prd.dbc = cpu_to_le32(remaining - 1);
982 remaining = 0;
983 }
984 prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
985
986 /* Commit the PRD entry to the Command Table */
987 memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
988 &prd, sizeof(PRD));
989 }
990
991 /* Bookmark the PRDTL and CTBA values */
992 ahci->port[port].ctba[cmd->slot] = table_ptr;
993 ahci->port[port].prdtl[cmd->slot] = prdtl;
994 }
995
996 void ahci_command_issue_async(AHCIQState *ahci, AHCICommand *cmd)
997 {
998 if (cmd->props->ncq) {
999 ahci_px_wreg(ahci, cmd->port, AHCI_PX_SACT, (1 << cmd->slot));
1000 }
1001
1002 ahci_px_wreg(ahci, cmd->port, AHCI_PX_CI, (1 << cmd->slot));
1003 }
1004
1005 void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd)
1006 {
1007 /* We can't rely on STS_BSY until the command has started processing.
1008 * Therefore, we also use the Command Issue bit as indication of
1009 * a command in-flight. */
1010
1011 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK)))
1012
1013 while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) ||
1014 RSET(AHCI_PX_CI, 1 << cmd->slot) ||
1015 (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) {
1016 usleep(50);
1017 }
1018
1019 }
1020
1021 void ahci_command_issue(AHCIQState *ahci, AHCICommand *cmd)
1022 {
1023 ahci_command_issue_async(ahci, cmd);
1024 ahci_command_wait(ahci, cmd);
1025 }
1026
1027 void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd)
1028 {
1029 uint8_t slot = cmd->slot;
1030 uint8_t port = cmd->port;
1031
1032 ahci_port_check_error(ahci, port);
1033 ahci_port_check_interrupts(ahci, port, cmd->interrupts);
1034 ahci_port_check_nonbusy(ahci, port, slot);
1035 ahci_port_check_cmd_sanity(ahci, cmd);
1036 if (cmd->interrupts & AHCI_PX_IS_DHRS) {
1037 ahci_port_check_d2h_sanity(ahci, port, slot);
1038 }
1039 if (cmd->props->pio) {
1040 ahci_port_check_pio_sanity(ahci, port, slot, cmd->xbytes);
1041 }
1042 }
1043
1044 uint8_t ahci_command_slot(AHCICommand *cmd)
1045 {
1046 return cmd->slot;
1047 }
AR7 emulation for QEMU