apci: switch piix4 gpe to memory api
[qemu/ar7.git] / hw / nvram.h
blob59337faaadd796e190cb49aba8b4d272efc881fd
1 #ifndef NVRAM_H
2 #define NVRAM_H
4 /* NVRAM helpers */
5 typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
6 typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
7 typedef struct nvram_t {
8 void *opaque;
9 nvram_read_t read_fn;
10 nvram_write_t write_fn;
11 } nvram_t;
13 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
14 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
16 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
17 const char *arch,
18 uint32_t RAM_size, int boot_device,
19 uint32_t kernel_image, uint32_t kernel_size,
20 const char *cmdline,
21 uint32_t initrd_image, uint32_t initrd_size,
22 uint32_t NVRAM_image,
23 int width, int height, int depth);
24 typedef struct M48t59State M48t59State;
26 void m48t59_write (void *private, uint32_t addr, uint32_t val);
27 uint32_t m48t59_read (void *private, uint32_t addr);
28 void m48t59_toggle_lock (void *private, int lock);
29 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
30 int type);
31 M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
32 uint32_t io_base, uint16_t size, int type);
34 #endif /* !NVRAM_H */