target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7 #define TARGET_HAS_ICE 1
   8
   9 #define ELF_MACHINE     EM_MIPS
  10
  11 #define CPUArchState struct CPUMIPSState
  12
  13 #include "config.h"
  14 #include "qemu-common.h"
  15 #include "mips-defs.h"
  16 #include "exec/cpu-defs.h"
  17 #include "fpu/softfloat.h"
  18
  19 struct CPUMIPSState;
  20
  21 typedef struct r4k_tlb_t r4k_tlb_t;
  22 struct r4k_tlb_t {
  23     target_ulong VPN;
  24     uint32_t PageMask;
  25     uint_fast8_t ASID;
  26     uint_fast16_t G:1;
  27     uint_fast16_t C0:3;
  28     uint_fast16_t C1:3;
  29     uint_fast16_t V0:1;
  30     uint_fast16_t V1:1;
  31     uint_fast16_t D0:1;
  32     uint_fast16_t D1:1;
  33     uint_fast16_t XI0:1;
  34     uint_fast16_t XI1:1;
  35     uint_fast16_t RI0:1;
  36     uint_fast16_t RI1:1;
  37     uint_fast16_t EHINV:1;
  38     target_ulong PFN[2];
  39 };
  40
  41 #if !defined(CONFIG_USER_ONLY)
  42 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  43 struct CPUMIPSTLBContext {
  44     uint32_t nb_tlb;
  45     uint32_t tlb_in_use;
  46     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  47     void (*helper_tlbwi)(struct CPUMIPSState *env);
  48     void (*helper_tlbwr)(struct CPUMIPSState *env);
  49     void (*helper_tlbp)(struct CPUMIPSState *env);
  50     void (*helper_tlbr)(struct CPUMIPSState *env);
  51     void (*helper_tlbinv)(struct CPUMIPSState *env);
  52     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  53     union {
  54         struct {
  55             r4k_tlb_t tlb[MIPS_TLB_MAX];
  56         } r4k;
  57     } mmu;
  58 };
  59 #endif
  60
  61 /* MSA Context */
  62 #define MSA_WRLEN (128)
  63
  64 enum CPUMIPSMSADataFormat {
  65     DF_BYTE = 0,
  66     DF_HALF,
  67     DF_WORD,
  68     DF_DOUBLE
  69 };
  70
  71 typedef union wr_t wr_t;
  72 union wr_t {
  73     int8_t  b[MSA_WRLEN/8];
  74     int16_t h[MSA_WRLEN/16];
  75     int32_t w[MSA_WRLEN/32];
  76     int64_t d[MSA_WRLEN/64];
  77 };
  78
  79 typedef union fpr_t fpr_t;
  80 union fpr_t {
  81     float64  fd;   /* ieee double precision */
  82     float32  fs[2];/* ieee single precision */
  83     uint64_t d;    /* binary double fixed-point */
  84     uint32_t w[2]; /* binary single fixed-point */
  85 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  86     wr_t     wr;   /* vector data */
  87 };
  88 /* define FP_ENDIAN_IDX to access the same location
  89  * in the fpr_t union regardless of the host endianness
  90  */
  91 #if defined(HOST_WORDS_BIGENDIAN)
  92 #  define FP_ENDIAN_IDX 1
  93 #else
  94 #  define FP_ENDIAN_IDX 0
  95 #endif
  96
  97 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  98 struct CPUMIPSFPUContext {
  99     /* Floating point registers */
 100     fpr_t fpr[32];
 101     float_status fp_status;
 102     /* fpu implementation/revision register (fir) */
 103     uint32_t fcr0;
 104 #define FCR0_UFRP 28
 105 #define FCR0_F64 22
 106 #define FCR0_L 21
 107 #define FCR0_W 20
 108 #define FCR0_3D 19
 109 #define FCR0_PS 18
 110 #define FCR0_D 17
 111 #define FCR0_S 16
 112 #define FCR0_PRID 8
 113 #define FCR0_REV 0
 114     /* fcsr */
 115     uint32_t fcr31;
 116 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 117 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 118 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 119 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 120 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 121 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 122 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 123 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 124 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 125 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 126 #define FP_INEXACT        1
 127 #define FP_UNDERFLOW      2
 128 #define FP_OVERFLOW       4
 129 #define FP_DIV0           8
 130 #define FP_INVALID        16
 131 #define FP_UNIMPLEMENTED  32
 132 };
 133
 134 #define NB_MMU_MODES 3
 135
 136 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 137 struct CPUMIPSMVPContext {
 138     int32_t CP0_MVPControl;
 139 #define CP0MVPCo_CPA    3
 140 #define CP0MVPCo_STLB   2
 141 #define CP0MVPCo_VPC    1
 142 #define CP0MVPCo_EVP    0
 143     int32_t CP0_MVPConf0;
 144 #define CP0MVPC0_M      31
 145 #define CP0MVPC0_TLBS   29
 146 #define CP0MVPC0_GS     28
 147 #define CP0MVPC0_PCP    27
 148 #define CP0MVPC0_PTLBE  16
 149 #define CP0MVPC0_TCA    15
 150 #define CP0MVPC0_PVPE   10
 151 #define CP0MVPC0_PTC    0
 152     int32_t CP0_MVPConf1;
 153 #define CP0MVPC1_CIM    31
 154 #define CP0MVPC1_CIF    30
 155 #define CP0MVPC1_PCX    20
 156 #define CP0MVPC1_PCP2   10
 157 #define CP0MVPC1_PCP1   0
 158 };
 159
 160 typedef struct mips_def_t mips_def_t;
 161
 162 #define MIPS_SHADOW_SET_MAX 16
 163 #define MIPS_TC_MAX 5
 164 #define MIPS_FPU_MAX 1
 165 #define MIPS_DSP_ACC 4
 166 #define MIPS_KSCRATCH_NUM 6
 167
 168 typedef struct TCState TCState;
 169 struct TCState {
 170     target_ulong gpr[32];
 171     target_ulong PC;
 172     target_ulong HI[MIPS_DSP_ACC];
 173     target_ulong LO[MIPS_DSP_ACC];
 174     target_ulong ACX[MIPS_DSP_ACC];
 175     target_ulong DSPControl;
 176     int32_t CP0_TCStatus;
 177 #define CP0TCSt_TCU3    31
 178 #define CP0TCSt_TCU2    30
 179 #define CP0TCSt_TCU1    29
 180 #define CP0TCSt_TCU0    28
 181 #define CP0TCSt_TMX     27
 182 #define CP0TCSt_RNST    23
 183 #define CP0TCSt_TDS     21
 184 #define CP0TCSt_DT      20
 185 #define CP0TCSt_DA      15
 186 #define CP0TCSt_A       13
 187 #define CP0TCSt_TKSU    11
 188 #define CP0TCSt_IXMT    10
 189 #define CP0TCSt_TASID   0
 190     int32_t CP0_TCBind;
 191 #define CP0TCBd_CurTC   21
 192 #define CP0TCBd_TBE     17
 193 #define CP0TCBd_CurVPE  0
 194     target_ulong CP0_TCHalt;
 195     target_ulong CP0_TCContext;
 196     target_ulong CP0_TCSchedule;
 197     target_ulong CP0_TCScheFBack;
 198     int32_t CP0_Debug_tcstatus;
 199     target_ulong CP0_UserLocal;
 200
 201     int32_t msacsr;
 202
 203 #define MSACSR_FS       24
 204 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 205 #define MSACSR_NX       18
 206 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 207 #define MSACSR_CEF      2
 208 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 209 #define MSACSR_RM       0
 210 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 211 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 212         MSACSR_FS_MASK)
 213
 214     float_status msa_fp_status;
 215 };
 216
 217 typedef struct CPUMIPSState CPUMIPSState;
 218 struct CPUMIPSState {
 219     TCState active_tc;
 220     CPUMIPSFPUContext active_fpu;
 221
 222     uint32_t current_tc;
 223     uint32_t current_fpu;
 224
 225     uint32_t SEGBITS;
 226     uint32_t PABITS;
 227     target_ulong SEGMask;
 228     target_ulong PAMask;
 229
 230     int32_t msair;
 231 #define MSAIR_ProcID    8
 232 #define MSAIR_Rev       0
 233
 234     int32_t CP0_Index;
 235     /* CP0_MVP* are per MVP registers. */
 236     int32_t CP0_Random;
 237     int32_t CP0_VPEControl;
 238 #define CP0VPECo_YSI    21
 239 #define CP0VPECo_GSI    20
 240 #define CP0VPECo_EXCPT  16
 241 #define CP0VPECo_TE     15
 242 #define CP0VPECo_TargTC 0
 243     int32_t CP0_VPEConf0;
 244 #define CP0VPEC0_M      31
 245 #define CP0VPEC0_XTC    21
 246 #define CP0VPEC0_TCS    19
 247 #define CP0VPEC0_SCS    18
 248 #define CP0VPEC0_DSC    17
 249 #define CP0VPEC0_ICS    16
 250 #define CP0VPEC0_MVP    1
 251 #define CP0VPEC0_VPA    0
 252     int32_t CP0_VPEConf1;
 253 #define CP0VPEC1_NCX    20
 254 #define CP0VPEC1_NCP2   10
 255 #define CP0VPEC1_NCP1   0
 256     target_ulong CP0_YQMask;
 257     target_ulong CP0_VPESchedule;
 258     target_ulong CP0_VPEScheFBack;
 259     int32_t CP0_VPEOpt;
 260 #define CP0VPEOpt_IWX7  15
 261 #define CP0VPEOpt_IWX6  14
 262 #define CP0VPEOpt_IWX5  13
 263 #define CP0VPEOpt_IWX4  12
 264 #define CP0VPEOpt_IWX3  11
 265 #define CP0VPEOpt_IWX2  10
 266 #define CP0VPEOpt_IWX1  9
 267 #define CP0VPEOpt_IWX0  8
 268 #define CP0VPEOpt_DWX7  7
 269 #define CP0VPEOpt_DWX6  6
 270 #define CP0VPEOpt_DWX5  5
 271 #define CP0VPEOpt_DWX4  4
 272 #define CP0VPEOpt_DWX3  3
 273 #define CP0VPEOpt_DWX2  2
 274 #define CP0VPEOpt_DWX1  1
 275 #define CP0VPEOpt_DWX0  0
 276     target_ulong CP0_EntryLo0;
 277     target_ulong CP0_EntryLo1;
 278 #if defined(TARGET_MIPS64)
 279 # define CP0EnLo_RI 63
 280 # define CP0EnLo_XI 62
 281 #else
 282 # define CP0EnLo_RI 31
 283 # define CP0EnLo_XI 30
 284 #endif
 285     target_ulong CP0_Context;
 286     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 287     int32_t CP0_PageMask;
 288     int32_t CP0_PageGrain_rw_bitmask;
 289     int32_t CP0_PageGrain;
 290 #define CP0PG_RIE 31
 291 #define CP0PG_XIE 30
 292 #define CP0PG_IEC 27
 293     int32_t CP0_Wired;
 294     int32_t CP0_SRSConf0_rw_bitmask;
 295     int32_t CP0_SRSConf0;
 296 #define CP0SRSC0_M      31
 297 #define CP0SRSC0_SRS3   20
 298 #define CP0SRSC0_SRS2   10
 299 #define CP0SRSC0_SRS1   0
 300     int32_t CP0_SRSConf1_rw_bitmask;
 301     int32_t CP0_SRSConf1;
 302 #define CP0SRSC1_M      31
 303 #define CP0SRSC1_SRS6   20
 304 #define CP0SRSC1_SRS5   10
 305 #define CP0SRSC1_SRS4   0
 306     int32_t CP0_SRSConf2_rw_bitmask;
 307     int32_t CP0_SRSConf2;
 308 #define CP0SRSC2_M      31
 309 #define CP0SRSC2_SRS9   20
 310 #define CP0SRSC2_SRS8   10
 311 #define CP0SRSC2_SRS7   0
 312     int32_t CP0_SRSConf3_rw_bitmask;
 313     int32_t CP0_SRSConf3;
 314 #define CP0SRSC3_M      31
 315 #define CP0SRSC3_SRS12  20
 316 #define CP0SRSC3_SRS11  10
 317 #define CP0SRSC3_SRS10  0
 318     int32_t CP0_SRSConf4_rw_bitmask;
 319     int32_t CP0_SRSConf4;
 320 #define CP0SRSC4_SRS15  20
 321 #define CP0SRSC4_SRS14  10
 322 #define CP0SRSC4_SRS13  0
 323     int32_t CP0_HWREna;
 324     target_ulong CP0_BadVAddr;
 325     uint32_t CP0_BadInstr;
 326     uint32_t CP0_BadInstrP;
 327     int32_t CP0_Count;
 328     target_ulong CP0_EntryHi;
 329 #define CP0EnHi_EHINV 10
 330     int32_t CP0_Compare;
 331     int32_t CP0_Status;
 332 #define CP0St_CU3   31
 333 #define CP0St_CU2   30
 334 #define CP0St_CU1   29
 335 #define CP0St_CU0   28
 336 #define CP0St_RP    27
 337 #define CP0St_FR    26
 338 #define CP0St_RE    25
 339 #define CP0St_MX    24
 340 #define CP0St_PX    23
 341 #define CP0St_BEV   22
 342 #define CP0St_TS    21
 343 #define CP0St_SR    20
 344 #define CP0St_NMI   19
 345 #define CP0St_IM    8
 346 #define CP0St_KX    7
 347 #define CP0St_SX    6
 348 #define CP0St_UX    5
 349 #define CP0St_KSU   3
 350 #define CP0St_ERL   2
 351 #define CP0St_EXL   1
 352 #define CP0St_IE    0
 353     int32_t CP0_IntCtl;
 354 #define CP0IntCtl_IPTI 29
 355 #define CP0IntCtl_IPPC1 26
 356 #define CP0IntCtl_VS 5
 357     int32_t CP0_SRSCtl;
 358 #define CP0SRSCtl_HSS 26
 359 #define CP0SRSCtl_EICSS 18
 360 #define CP0SRSCtl_ESS 12
 361 #define CP0SRSCtl_PSS 6
 362 #define CP0SRSCtl_CSS 0
 363     int32_t CP0_SRSMap;
 364 #define CP0SRSMap_SSV7 28
 365 #define CP0SRSMap_SSV6 24
 366 #define CP0SRSMap_SSV5 20
 367 #define CP0SRSMap_SSV4 16
 368 #define CP0SRSMap_SSV3 12
 369 #define CP0SRSMap_SSV2 8
 370 #define CP0SRSMap_SSV1 4
 371 #define CP0SRSMap_SSV0 0
 372     int32_t CP0_Cause;
 373 #define CP0Ca_BD   31
 374 #define CP0Ca_TI   30
 375 #define CP0Ca_CE   28
 376 #define CP0Ca_DC   27
 377 #define CP0Ca_PCI  26
 378 #define CP0Ca_IV   23
 379 #define CP0Ca_WP   22
 380 #define CP0Ca_IP    8
 381 #define CP0Ca_IP_mask 0x0000FF00
 382 #define CP0Ca_EC    2
 383     target_ulong CP0_EPC;
 384     int32_t CP0_PRid;
 385     int32_t CP0_EBase;
 386     int32_t CP0_Config0;
 387 #define CP0C0_M    31
 388 #define CP0C0_K23  28
 389 #define CP0C0_KU   25
 390 #define CP0C0_MDU  20
 391 #define CP0C0_MM   17
 392 #define CP0C0_BM   16
 393 #define CP0C0_BE   15
 394 #define CP0C0_AT   13
 395 #define CP0C0_AR   10
 396 #define CP0C0_MT   7
 397 #define CP0C0_VI   3
 398 #define CP0C0_K0   0
 399     int32_t CP0_Config1;
 400 #define CP0C1_M    31
 401 #define CP0C1_MMU  25
 402 #define CP0C1_IS   22
 403 #define CP0C1_IL   19
 404 #define CP0C1_IA   16
 405 #define CP0C1_DS   13
 406 #define CP0C1_DL   10
 407 #define CP0C1_DA   7
 408 #define CP0C1_C2   6
 409 #define CP0C1_MD   5
 410 #define CP0C1_PC   4
 411 #define CP0C1_WR   3
 412 #define CP0C1_CA   2
 413 #define CP0C1_EP   1
 414 #define CP0C1_FP   0
 415     int32_t CP0_Config2;
 416 #define CP0C2_M    31
 417 #define CP0C2_TU   28
 418 #define CP0C2_TS   24
 419 #define CP0C2_TL   20
 420 #define CP0C2_TA   16
 421 #define CP0C2_SU   12
 422 #define CP0C2_SS   8
 423 #define CP0C2_SL   4
 424 #define CP0C2_SA   0
 425     int32_t CP0_Config3;
 426 #define CP0C3_M    31
 427 #define CP0C3_BPG  30
 428 #define CP0C3_CMCGR 29
 429 #define CP0C3_MSAP  28
 430 #define CP0C3_BP 27
 431 #define CP0C3_BI 26
 432 #define CP0C3_IPLW 21
 433 #define CP0C3_MMAR 18
 434 #define CP0C3_MCU  17
 435 #define CP0C3_ISA_ON_EXC 16
 436 #define CP0C3_ISA  14
 437 #define CP0C3_ULRI 13
 438 #define CP0C3_RXI  12
 439 #define CP0C3_DSP2P 11
 440 #define CP0C3_DSPP 10
 441 #define CP0C3_LPA  7
 442 #define CP0C3_VEIC 6
 443 #define CP0C3_VInt 5
 444 #define CP0C3_SP   4
 445 #define CP0C3_CDMM 3
 446 #define CP0C3_MT   2
 447 #define CP0C3_SM   1
 448 #define CP0C3_TL   0
 449     int32_t CP0_Config4;
 450     int32_t CP0_Config4_rw_bitmask;
 451 #define CP0C4_M    31
 452 #define CP0C4_IE   29
 453 #define CP0C4_KScrExist 16
 454 #define CP0C4_MMUExtDef 14
 455 #define CP0C4_FTLBPageSize 8
 456 #define CP0C4_FTLBWays 4
 457 #define CP0C4_FTLBSets 0
 458 #define CP0C4_MMUSizeExt 0
 459     int32_t CP0_Config5;
 460     int32_t CP0_Config5_rw_bitmask;
 461 #define CP0C5_M          31
 462 #define CP0C5_K          30
 463 #define CP0C5_CV         29
 464 #define CP0C5_EVA        28
 465 #define CP0C5_MSAEn      27
 466 #define CP0C5_SBRI       6
 467 #define CP0C5_UFR        2
 468 #define CP0C5_NFExists   0
 469     int32_t CP0_Config6;
 470     int32_t CP0_Config7;
 471     /* XXX: Maybe make LLAddr per-TC? */
 472     target_ulong lladdr;
 473     target_ulong llval;
 474     target_ulong llnewval;
 475     target_ulong llreg;
 476     target_ulong CP0_LLAddr_rw_bitmask;
 477     int CP0_LLAddr_shift;
 478     target_ulong CP0_WatchLo[8];
 479     int32_t CP0_WatchHi[8];
 480     target_ulong CP0_XContext;
 481     int32_t CP0_Framemask;
 482     int32_t CP0_Debug;
 483 #define CP0DB_DBD  31
 484 #define CP0DB_DM   30
 485 #define CP0DB_LSNM 28
 486 #define CP0DB_Doze 27
 487 #define CP0DB_Halt 26
 488 #define CP0DB_CNT  25
 489 #define CP0DB_IBEP 24
 490 #define CP0DB_DBEP 21
 491 #define CP0DB_IEXI 20
 492 #define CP0DB_VER  15
 493 #define CP0DB_DEC  10
 494 #define CP0DB_SSt  8
 495 #define CP0DB_DINT 5
 496 #define CP0DB_DIB  4
 497 #define CP0DB_DDBS 3
 498 #define CP0DB_DDBL 2
 499 #define CP0DB_DBp  1
 500 #define CP0DB_DSS  0
 501     target_ulong CP0_DEPC;
 502     int32_t CP0_Performance0;
 503     int32_t CP0_TagLo;
 504     int32_t CP0_DataLo;
 505     int32_t CP0_TagHi;
 506     int32_t CP0_DataHi;
 507     target_ulong CP0_ErrorEPC;
 508     int32_t CP0_DESAVE;
 509     /* We waste some space so we can handle shadow registers like TCs. */
 510     TCState tcs[MIPS_SHADOW_SET_MAX];
 511     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 512     /* QEMU */
 513     int error_code;
 514 #define EXCP_TLB_NOMATCH   0x1
 515 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 516     uint32_t hflags;    /* CPU State */
 517     /* TMASK defines different execution modes */
 518 #define MIPS_HFLAG_TMASK  0x15807FF
 519 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 520     /* The KSU flags must be the lowest bits in hflags. The flag order
 521        must be the same as defined for CP0 Status. This allows to use
 522        the bits as the value of mmu_idx. */
 523 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 524 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 525 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 526 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 527 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 528 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 529 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 530 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 531 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 532     /* True if the MIPS IV COP1X instructions can be used.  This also
 533        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 534        and RSQRT.D.  */
 535 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 536 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 537 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 538 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 539 #define MIPS_HFLAG_M16_SHIFT 10
 540     /* If translation is interrupted between the branch instruction and
 541      * the delay slot, record what type of branch it is so that we can
 542      * resume translation properly.  It might be possible to reduce
 543      * this from three bits to two.  */
 544 #define MIPS_HFLAG_BMASK_BASE  0x803800
 545 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 546 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 547 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 548 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 549     /* Extra flags about the current pending branch.  */
 550 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 551 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 552 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 553 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 554 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 555 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 556 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 557     /* MIPS DSP resources access. */
 558 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 559 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 560     /* Extra flag about HWREna register. */
 561 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 562 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 563 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 564 #define MIPS_HFLAG_MSA   0x1000000
 565     target_ulong btarget;        /* Jump / branch target               */
 566     target_ulong bcond;          /* Branch condition (if needed)       */
 567
 568     int SYNCI_Step; /* Address step size for SYNCI */
 569     int CCRes; /* Cycle count resolution/divisor */
 570     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 571     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 572     int insn_flags; /* Supported instruction set */
 573
 574     CPU_COMMON
 575
 576     /* Fields from here on are preserved across CPU reset. */
 577     CPUMIPSMVPContext *mvp;
 578 #if !defined(CONFIG_USER_ONLY)
 579     CPUMIPSTLBContext *tlb;
 580 #endif
 581
 582     const mips_def_t *cpu_model;
 583     void *irq[8];
 584     QEMUTimer *timer; /* Internal timer */
 585 };
 586
 587 #include "cpu-qom.h"
 588
 589 #if !defined(CONFIG_USER_ONLY)
 590 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 591                         target_ulong address, int rw, int access_type);
 592 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 593                            target_ulong address, int rw, int access_type);
 594 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 595                      target_ulong address, int rw, int access_type);
 596 void r4k_helper_tlbwi(CPUMIPSState *env);
 597 void r4k_helper_tlbwr(CPUMIPSState *env);
 598 void r4k_helper_tlbp(CPUMIPSState *env);
 599 void r4k_helper_tlbr(CPUMIPSState *env);
 600 void r4k_helper_tlbinv(CPUMIPSState *env);
 601 void r4k_helper_tlbinvf(CPUMIPSState *env);
 602
 603 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 604                                 bool is_write, bool is_exec, int unused,
 605                                 unsigned size);
 606 #endif
 607
 608 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 609
 610 #define cpu_exec cpu_mips_exec
 611 #define cpu_gen_code cpu_mips_gen_code
 612 #define cpu_signal_handler cpu_mips_signal_handler
 613 #define cpu_list mips_cpu_list
 614
 615 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 616 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 617
 618 #define CPU_SAVE_VERSION 5
 619
 620 /* MMU modes definitions. We carefully match the indices with our
 621    hflags layout. */
 622 #define MMU_MODE0_SUFFIX _kernel
 623 #define MMU_MODE1_SUFFIX _super
 624 #define MMU_MODE2_SUFFIX _user
 625 #define MMU_USER_IDX 2
 626 static inline int cpu_mmu_index (CPUMIPSState *env)
 627 {
 628     return env->hflags & MIPS_HFLAG_KSU;
 629 }
 630
 631 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 632 {
 633     int32_t pending;
 634     int32_t status;
 635     int r;
 636
 637     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 638         (env->CP0_Status & (1 << CP0St_EXL)) ||
 639         (env->CP0_Status & (1 << CP0St_ERL)) ||
 640         /* Note that the TCStatus IXMT field is initialized to zero,
 641            and only MT capable cores can set it to one. So we don't
 642            need to check for MT capabilities here.  */
 643         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 644         (env->hflags & MIPS_HFLAG_DM)) {
 645         /* Interrupts are disabled */
 646         return 0;
 647     }
 648
 649     pending = env->CP0_Cause & CP0Ca_IP_mask;
 650     status = env->CP0_Status & CP0Ca_IP_mask;
 651
 652     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 653         /* A MIPS configured with a vectorizing external interrupt controller
 654            will feed a vector into the Cause pending lines. The core treats
 655            the status lines as a vector level, not as indiviual masks.  */
 656         r = pending > status;
 657     } else {
 658         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 659            treats the pending lines as individual interrupt lines, the status
 660            lines are individual masks.  */
 661         r = pending & status;
 662     }
 663     return r;
 664 }
 665
 666 #include "exec/cpu-all.h"
 667
 668 /* Memory access type :
 669  * may be needed for precise access rights control and precise exceptions.
 670  */
 671 enum {
 672     /* 1 bit to define user level / supervisor access */
 673     ACCESS_USER  = 0x00,
 674     ACCESS_SUPER = 0x01,
 675     /* 1 bit to indicate direction */
 676     ACCESS_STORE = 0x02,
 677     /* Type of instruction that generated the access */
 678     ACCESS_CODE  = 0x10, /* Code fetch access                */
 679     ACCESS_INT   = 0x20, /* Integer load/store access        */
 680     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 681 };
 682
 683 /* Exceptions */
 684 enum {
 685     EXCP_NONE          = -1,
 686     EXCP_RESET         = 0,
 687     EXCP_SRESET,
 688     EXCP_DSS,
 689     EXCP_DINT,
 690     EXCP_DDBL,
 691     EXCP_DDBS,
 692     EXCP_NMI,
 693     EXCP_MCHECK,
 694     EXCP_EXT_INTERRUPT, /* 8 */
 695     EXCP_DFWATCH,
 696     EXCP_DIB,
 697     EXCP_IWATCH,
 698     EXCP_AdEL,
 699     EXCP_AdES,
 700     EXCP_TLBF,
 701     EXCP_IBE,
 702     EXCP_DBp, /* 16 */
 703     EXCP_SYSCALL,
 704     EXCP_BREAK,
 705     EXCP_CpU,
 706     EXCP_RI,
 707     EXCP_OVERFLOW,
 708     EXCP_TRAP,
 709     EXCP_FPE,
 710     EXCP_DWATCH, /* 24 */
 711     EXCP_LTLBL,
 712     EXCP_TLBL,
 713     EXCP_TLBS,
 714     EXCP_DBE,
 715     EXCP_THREAD,
 716     EXCP_MDMX,
 717     EXCP_C2E,
 718     EXCP_CACHE, /* 32 */
 719     EXCP_DSPDIS,
 720     EXCP_MSADIS,
 721     EXCP_MSAFPE,
 722     EXCP_TLBXI,
 723     EXCP_TLBRI,
 724
 725     EXCP_LAST = EXCP_TLBRI,
 726 };
 727 /* Dummy exception for conditional stores.  */
 728 #define EXCP_SC 0x100
 729
 730 /*
 731  * This is an interrnally generated WAKE request line.
 732  * It is driven by the CPU itself. Raised when the MT
 733  * block wants to wake a VPE from an inactive state and
 734  * cleared when VPE goes from active to inactive.
 735  */
 736 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 737
 738 int cpu_mips_exec(CPUMIPSState *s);
 739 void mips_tcg_init(void);
 740 MIPSCPU *cpu_mips_init(const char *cpu_model);
 741 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 742
 743 static inline CPUMIPSState *cpu_init(const char *cpu_model)
 744 {
 745     MIPSCPU *cpu = cpu_mips_init(cpu_model);
 746     if (cpu == NULL) {
 747         return NULL;
 748     }
 749     return &cpu->env;
 750 }
 751
 752 /* TODO QOM'ify CPU reset and remove */
 753 void cpu_state_reset(CPUMIPSState *s);
 754
 755 /* mips_timer.c */
 756 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 757 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 758 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 759 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 760 void cpu_mips_start_count(CPUMIPSState *env);
 761 void cpu_mips_stop_count(CPUMIPSState *env);
 762
 763 /* mips_int.c */
 764 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 765
 766 /* helper.c */
 767 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 768                               int mmu_idx);
 769 #if !defined(CONFIG_USER_ONLY)
 770 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 771 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 772                                                int rw);
 773 #endif
 774 target_ulong exception_resume_pc (CPUMIPSState *env);
 775
 776 /* op_helper.c */
 777 extern unsigned int ieee_rm[];
 778 int ieee_ex_to_mips(int xcpt);
 779
 780 static inline void restore_rounding_mode(CPUMIPSState *env)
 781 {
 782     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 783                             &env->active_fpu.fp_status);
 784 }
 785
 786 static inline void restore_flush_mode(CPUMIPSState *env)
 787 {
 788     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 789                       &env->active_fpu.fp_status);
 790 }
 791
 792 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 793                                         target_ulong *cs_base, int *flags)
 794 {
 795     *pc = env->active_tc.PC;
 796     *cs_base = 0;
 797     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 798                             MIPS_HFLAG_HWRENA_ULR);
 799 }
 800
 801 static inline int mips_vpe_active(CPUMIPSState *env)
 802 {
 803     int active = 1;
 804
 805     /* Check that the VPE is enabled.  */
 806     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 807         active = 0;
 808     }
 809     /* Check that the VPE is activated.  */
 810     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 811         active = 0;
 812     }
 813
 814     /* Now verify that there are active thread contexts in the VPE.
 815
 816        This assumes the CPU model will internally reschedule threads
 817        if the active one goes to sleep. If there are no threads available
 818        the active one will be in a sleeping state, and we can turn off
 819        the entire VPE.  */
 820     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 821         /* TC is not activated.  */
 822         active = 0;
 823     }
 824     if (env->active_tc.CP0_TCHalt & 1) {
 825         /* TC is in halt state.  */
 826         active = 0;
 827     }
 828
 829     return active;
 830 }
 831
 832 #include "exec/exec-all.h"
 833
 834 static inline void compute_hflags(CPUMIPSState *env)
 835 {
 836     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 837                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 838                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 839                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA);
 840     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 841         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 842         !(env->hflags & MIPS_HFLAG_DM)) {
 843         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 844     }
 845 #if defined(TARGET_MIPS64)
 846     if ((env->insn_flags & ISA_MIPS3) &&
 847         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 848          (env->CP0_Status & (1 << CP0St_PX)) ||
 849          (env->CP0_Status & (1 << CP0St_UX)))) {
 850         env->hflags |= MIPS_HFLAG_64;
 851     }
 852
 853     if (!(env->insn_flags & ISA_MIPS3)) {
 854         env->hflags |= MIPS_HFLAG_AWRAP;
 855     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 856                !(env->CP0_Status & (1 << CP0St_UX))) {
 857         env->hflags |= MIPS_HFLAG_AWRAP;
 858     } else if (env->insn_flags & ISA_MIPS64R6) {
 859         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 860         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 861              !(env->CP0_Status & (1 << CP0St_SX))) ||
 862             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 863              !(env->CP0_Status & (1 << CP0St_KX)))) {
 864             env->hflags |= MIPS_HFLAG_AWRAP;
 865         }
 866     }
 867 #endif
 868     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 869          !(env->insn_flags & ISA_MIPS32R6)) ||
 870         !(env->hflags & MIPS_HFLAG_KSU)) {
 871         env->hflags |= MIPS_HFLAG_CP0;
 872     }
 873     if (env->CP0_Status & (1 << CP0St_CU1)) {
 874         env->hflags |= MIPS_HFLAG_FPU;
 875     }
 876     if (env->CP0_Status & (1 << CP0St_FR)) {
 877         env->hflags |= MIPS_HFLAG_F64;
 878     }
 879     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 880         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 881         env->hflags |= MIPS_HFLAG_SBRI;
 882     }
 883     if (env->insn_flags & ASE_DSPR2) {
 884         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 885            so enable to access DSPR2 resources. */
 886         if (env->CP0_Status & (1 << CP0St_MX)) {
 887             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 888         }
 889
 890     } else if (env->insn_flags & ASE_DSP) {
 891         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 892            so enable to access DSP resources. */
 893         if (env->CP0_Status & (1 << CP0St_MX)) {
 894             env->hflags |= MIPS_HFLAG_DSP;
 895         }
 896
 897     }
 898     if (env->insn_flags & ISA_MIPS32R2) {
 899         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 900             env->hflags |= MIPS_HFLAG_COP1X;
 901         }
 902     } else if (env->insn_flags & ISA_MIPS32) {
 903         if (env->hflags & MIPS_HFLAG_64) {
 904             env->hflags |= MIPS_HFLAG_COP1X;
 905         }
 906     } else if (env->insn_flags & ISA_MIPS4) {
 907         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 908            and disable the MIPS IV extensions to the MIPS III ISA.
 909            Some other MIPS IV CPUs ignore the bit, so the check here
 910            would be too restrictive for them.  */
 911         if (env->CP0_Status & (1U << CP0St_CU3)) {
 912             env->hflags |= MIPS_HFLAG_COP1X;
 913         }
 914     }
 915     if (env->insn_flags & ASE_MSA) {
 916         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 917             env->hflags |= MIPS_HFLAG_MSA;
 918         }
 919     }
 920 }
 921
 922 #ifndef CONFIG_USER_ONLY
 923 /* Called for updates to CP0_Status.  */
 924 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 925 {
 926     int32_t tcstatus, *tcst;
 927     uint32_t v = cpu->CP0_Status;
 928     uint32_t cu, mx, asid, ksu;
 929     uint32_t mask = ((1 << CP0TCSt_TCU3)
 930                        | (1 << CP0TCSt_TCU2)
 931                        | (1 << CP0TCSt_TCU1)
 932                        | (1 << CP0TCSt_TCU0)
 933                        | (1 << CP0TCSt_TMX)
 934                        | (3 << CP0TCSt_TKSU)
 935                        | (0xff << CP0TCSt_TASID));
 936
 937     cu = (v >> CP0St_CU0) & 0xf;
 938     mx = (v >> CP0St_MX) & 0x1;
 939     ksu = (v >> CP0St_KSU) & 0x3;
 940     asid = env->CP0_EntryHi & 0xff;
 941
 942     tcstatus = cu << CP0TCSt_TCU0;
 943     tcstatus |= mx << CP0TCSt_TMX;
 944     tcstatus |= ksu << CP0TCSt_TKSU;
 945     tcstatus |= asid;
 946
 947     if (tc == cpu->current_tc) {
 948         tcst = &cpu->active_tc.CP0_TCStatus;
 949     } else {
 950         tcst = &cpu->tcs[tc].CP0_TCStatus;
 951     }
 952
 953     *tcst &= ~mask;
 954     *tcst |= tcstatus;
 955     compute_hflags(cpu);
 956 }
 957
 958 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 959 {
 960     uint32_t mask = env->CP0_Status_rw_bitmask;
 961
 962     if (env->insn_flags & ISA_MIPS32R6) {
 963         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
 964
 965         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
 966             mask &= ~(3 << CP0St_KSU);
 967         }
 968         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
 969     }
 970
 971     env->CP0_Status = (env->CP0_Status & ~mask) | (val & mask);
 972     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
 973         sync_c0_status(env, env, env->current_tc);
 974     } else {
 975         compute_hflags(env);
 976     }
 977 }
 978
 979 static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 980 {
 981     uint32_t mask = 0x00C00300;
 982     uint32_t old = env->CP0_Cause;
 983     int i;
 984
 985     if (env->insn_flags & ISA_MIPS32R2) {
 986         mask |= 1 << CP0Ca_DC;
 987     }
 988     if (env->insn_flags & ISA_MIPS32R6) {
 989         mask &= ~((1 << CP0Ca_WP) & val);
 990     }
 991
 992     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 993
 994     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 995         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 996             cpu_mips_stop_count(env);
 997         } else {
 998             cpu_mips_start_count(env);
 999         }
1000     }
1001
1002     /* Set/reset software interrupts */
1003     for (i = 0 ; i < 2 ; i++) {
1004         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1005             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
1006         }
1007     }
1008 }
1009 #endif
1010
1011 #endif /* !defined (__MIPS_CPU_H__) */