4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_bridge.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/pci/pci_host.h"
31 #include "monitor/monitor.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/loader.h"
35 #include "qemu/error-report.h"
36 #include "qemu/range.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qapi/error.h"
44 #include "qapi/qapi-commands-misc.h"
45 #include "qemu/cutils.h"
49 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
51 # define PCI_DPRINTF(format, ...) do { } while (0)
54 bool pci_available
= true;
56 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
57 static char *pcibus_get_dev_path(DeviceState
*dev
);
58 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
59 static void pcibus_reset(BusState
*qbus
);
61 static Property pci_props
[] = {
62 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
63 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
64 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
65 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
66 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
67 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
68 QEMU_PCI_CAP_SERR_BITNR
, true),
69 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
70 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
71 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
72 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
73 DEFINE_PROP_END_OF_LIST()
76 static const VMStateDescription vmstate_pcibus
= {
79 .minimum_version_id
= 1,
80 .fields
= (VMStateField
[]) {
81 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
82 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
83 nirq
, 0, vmstate_info_int32
,
89 static void pci_init_bus_master(PCIDevice
*pci_dev
)
91 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
93 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
94 OBJECT(pci_dev
), "bus master",
95 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
96 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
97 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
98 &pci_dev
->bus_master_enable_region
);
101 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
103 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
106 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
107 if (bus
->devices
[i
]) {
108 pci_init_bus_master(bus
->devices
[i
]);
113 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
115 PCIBus
*bus
= PCI_BUS(qbus
);
117 bus
->machine_done
.notify
= pcibus_machine_done
;
118 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
120 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
123 static void pci_bus_unrealize(BusState
*qbus
, Error
**errp
)
125 PCIBus
*bus
= PCI_BUS(qbus
);
127 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
129 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
132 static bool pcibus_is_root(PCIBus
*bus
)
134 return !bus
->parent_dev
;
137 static int pcibus_num(PCIBus
*bus
)
139 if (pcibus_is_root(bus
)) {
140 return 0; /* pci host bridge */
142 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
145 static uint16_t pcibus_numa_node(PCIBus
*bus
)
147 return NUMA_NODE_UNASSIGNED
;
150 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
152 BusClass
*k
= BUS_CLASS(klass
);
153 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
155 k
->print_dev
= pcibus_dev_print
;
156 k
->get_dev_path
= pcibus_get_dev_path
;
157 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
158 k
->realize
= pci_bus_realize
;
159 k
->unrealize
= pci_bus_unrealize
;
160 k
->reset
= pcibus_reset
;
162 pbc
->is_root
= pcibus_is_root
;
163 pbc
->bus_num
= pcibus_num
;
164 pbc
->numa_node
= pcibus_numa_node
;
167 static const TypeInfo pci_bus_info
= {
168 .name
= TYPE_PCI_BUS
,
170 .instance_size
= sizeof(PCIBus
),
171 .class_size
= sizeof(PCIBusClass
),
172 .class_init
= pci_bus_class_init
,
175 static const TypeInfo pcie_interface_info
= {
176 .name
= INTERFACE_PCIE_DEVICE
,
177 .parent
= TYPE_INTERFACE
,
180 static const TypeInfo conventional_pci_interface_info
= {
181 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
182 .parent
= TYPE_INTERFACE
,
185 static const TypeInfo pcie_bus_info
= {
186 .name
= TYPE_PCIE_BUS
,
187 .parent
= TYPE_PCI_BUS
,
190 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
191 static void pci_update_mappings(PCIDevice
*d
);
192 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
193 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
194 static void pci_del_option_rom(PCIDevice
*pdev
);
196 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
197 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
199 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
201 int pci_bar(PCIDevice
*d
, int reg
)
205 if (reg
!= PCI_ROM_SLOT
)
206 return PCI_BASE_ADDRESS_0
+ reg
* 4;
208 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
209 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
212 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
214 return (d
->irq_state
>> irq_num
) & 0x1;
217 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
219 d
->irq_state
&= ~(0x1 << irq_num
);
220 d
->irq_state
|= level
<< irq_num
;
223 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
227 bus
= pci_get_bus(pci_dev
);
228 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
231 pci_dev
= bus
->parent_dev
;
233 bus
->irq_count
[irq_num
] += change
;
234 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
237 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
239 assert(irq_num
>= 0);
240 assert(irq_num
< bus
->nirq
);
241 return !!bus
->irq_count
[irq_num
];
244 /* Update interrupt status bit in config space on interrupt
246 static void pci_update_irq_status(PCIDevice
*dev
)
248 if (dev
->irq_state
) {
249 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
251 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
255 void pci_device_deassert_intx(PCIDevice
*dev
)
258 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
259 pci_irq_handler(dev
, i
, 0);
263 static void pci_do_device_reset(PCIDevice
*dev
)
267 pci_device_deassert_intx(dev
);
268 assert(dev
->irq_state
== 0);
270 /* Clear all writable bits */
271 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
272 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
273 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
274 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
275 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
276 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
277 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
278 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
279 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
280 PCIIORegion
*region
= &dev
->io_regions
[r
];
285 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
286 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
287 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
289 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
292 pci_update_mappings(dev
);
299 * This function is called on #RST and FLR.
300 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
302 void pci_device_reset(PCIDevice
*dev
)
304 qdev_reset_all(&dev
->qdev
);
305 pci_do_device_reset(dev
);
309 * Trigger pci bus reset under a given bus.
310 * Called via qbus_reset_all on RST# assert, after the devices
311 * have been reset qdev_reset_all-ed already.
313 static void pcibus_reset(BusState
*qbus
)
315 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
318 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
319 if (bus
->devices
[i
]) {
320 pci_do_device_reset(bus
->devices
[i
]);
324 for (i
= 0; i
< bus
->nirq
; i
++) {
325 assert(bus
->irq_count
[i
] == 0);
329 static void pci_host_bus_register(DeviceState
*host
)
331 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
333 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
336 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
338 PCIBus
*bus
= pci_get_bus(d
);
340 while (!pci_bus_is_root(bus
)) {
344 bus
= pci_get_bus(d
);
350 const char *pci_root_bus_path(PCIDevice
*dev
)
352 PCIBus
*rootbus
= pci_device_root_bus(dev
);
353 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
354 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
356 assert(host_bridge
->bus
== rootbus
);
358 if (hc
->root_bus_path
) {
359 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
362 return rootbus
->qbus
.name
;
365 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
366 MemoryRegion
*address_space_mem
,
367 MemoryRegion
*address_space_io
,
370 assert(PCI_FUNC(devfn_min
) == 0);
371 bus
->devfn_min
= devfn_min
;
372 bus
->slot_reserved_mask
= 0x0;
373 bus
->address_space_mem
= address_space_mem
;
374 bus
->address_space_io
= address_space_io
;
377 QLIST_INIT(&bus
->child
);
379 pci_host_bus_register(parent
);
382 bool pci_bus_is_express(PCIBus
*bus
)
384 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
387 bool pci_bus_is_root(PCIBus
*bus
)
389 return PCI_BUS_GET_CLASS(bus
)->is_root(bus
);
392 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
394 MemoryRegion
*address_space_mem
,
395 MemoryRegion
*address_space_io
,
396 uint8_t devfn_min
, const char *typename
)
398 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
399 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
403 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
404 MemoryRegion
*address_space_mem
,
405 MemoryRegion
*address_space_io
,
406 uint8_t devfn_min
, const char *typename
)
410 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
411 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
416 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
417 void *irq_opaque
, int nirq
)
419 bus
->set_irq
= set_irq
;
420 bus
->map_irq
= map_irq
;
421 bus
->irq_opaque
= irq_opaque
;
423 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
426 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
427 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
429 MemoryRegion
*address_space_mem
,
430 MemoryRegion
*address_space_io
,
431 uint8_t devfn_min
, int nirq
,
432 const char *typename
)
436 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
437 address_space_io
, devfn_min
, typename
);
438 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
442 int pci_bus_num(PCIBus
*s
)
444 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
447 int pci_bus_numa_node(PCIBus
*bus
)
449 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
452 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
455 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
456 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
460 assert(size
== pci_config_size(s
));
461 config
= g_malloc(size
);
463 qemu_get_buffer(f
, config
, size
);
464 for (i
= 0; i
< size
; ++i
) {
465 if ((config
[i
] ^ s
->config
[i
]) &
466 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
467 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
468 "cmask: %x wmask: %x w1cmask:%x", __func__
,
469 i
, config
[i
], s
->config
[i
],
470 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
475 memcpy(s
->config
, config
, size
);
477 pci_update_mappings(s
);
479 PCIBridge
*b
= PCI_BRIDGE(s
);
480 pci_bridge_update_mappings(b
);
483 memory_region_set_enabled(&s
->bus_master_enable_region
,
484 pci_get_word(s
->config
+ PCI_COMMAND
)
485 & PCI_COMMAND_MASTER
);
491 /* just put buffer */
492 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
493 VMStateField
*field
, QJSON
*vmdesc
)
495 const uint8_t **v
= pv
;
496 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
497 qemu_put_buffer(f
, *v
, size
);
502 static VMStateInfo vmstate_info_pci_config
= {
503 .name
= "pci config",
504 .get
= get_pci_config_device
,
505 .put
= put_pci_config_device
,
508 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
511 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
512 uint32_t irq_state
[PCI_NUM_PINS
];
514 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
515 irq_state
[i
] = qemu_get_be32(f
);
516 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
517 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
523 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
524 pci_set_irq_state(s
, i
, irq_state
[i
]);
530 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
531 VMStateField
*field
, QJSON
*vmdesc
)
534 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
536 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
537 qemu_put_be32(f
, pci_irq_state(s
, i
));
543 static VMStateInfo vmstate_info_pci_irq_state
= {
544 .name
= "pci irq state",
545 .get
= get_pci_irq_state
,
546 .put
= put_pci_irq_state
,
549 static bool migrate_is_pcie(void *opaque
, int version_id
)
551 return pci_is_express((PCIDevice
*)opaque
);
554 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
556 return !pci_is_express((PCIDevice
*)opaque
);
559 const VMStateDescription vmstate_pci_device
= {
562 .minimum_version_id
= 1,
563 .fields
= (VMStateField
[]) {
564 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
565 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
567 0, vmstate_info_pci_config
,
568 PCI_CONFIG_SPACE_SIZE
),
569 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
571 0, vmstate_info_pci_config
,
572 PCIE_CONFIG_SPACE_SIZE
),
573 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
574 vmstate_info_pci_irq_state
,
575 PCI_NUM_PINS
* sizeof(int32_t)),
576 VMSTATE_END_OF_LIST()
581 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
583 /* Clear interrupt status bit: it is implicit
584 * in irq_state which we are saving.
585 * This makes us compatible with old devices
586 * which never set or clear this bit. */
587 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
588 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
589 /* Restore the interrupt status bit. */
590 pci_update_irq_status(s
);
593 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
596 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
597 /* Restore the interrupt status bit. */
598 pci_update_irq_status(s
);
602 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
604 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
605 pci_default_sub_vendor_id
);
606 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
607 pci_default_sub_device_id
);
611 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
612 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
614 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
615 unsigned int *slotp
, unsigned int *funcp
)
620 unsigned long dom
= 0, bus
= 0;
621 unsigned int slot
= 0;
622 unsigned int func
= 0;
625 val
= strtoul(p
, &e
, 16);
631 val
= strtoul(p
, &e
, 16);
638 val
= strtoul(p
, &e
, 16);
651 val
= strtoul(p
, &e
, 16);
658 /* if funcp == NULL func is 0 */
659 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
673 static PCIBus
*pci_get_bus_devfn(int *devfnp
, PCIBus
*root
,
680 fprintf(stderr
, "No primary PCI bus\n");
684 assert(!root
->parent_dev
);
688 return pci_find_bus_nr(root
, 0);
691 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
696 fprintf(stderr
, "No support for non-zero PCI domains\n");
700 *devfnp
= PCI_DEVFN(slot
, 0);
701 return pci_find_bus_nr(root
, bus
);
704 static void pci_init_cmask(PCIDevice
*dev
)
706 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
707 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
708 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
709 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
710 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
711 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
712 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
713 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
716 static void pci_init_wmask(PCIDevice
*dev
)
718 int config_size
= pci_config_size(dev
);
720 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
721 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
722 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
723 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
724 PCI_COMMAND_INTX_DISABLE
);
725 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
726 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
729 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
730 config_size
- PCI_CONFIG_HEADER_SIZE
);
733 static void pci_init_w1cmask(PCIDevice
*dev
)
736 * Note: It's okay to set w1cmask even for readonly bits as
737 * long as their value is hardwired to 0.
739 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
740 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
741 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
742 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
745 static void pci_init_mask_bridge(PCIDevice
*d
)
747 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
748 PCI_SEC_LETENCY_TIMER */
749 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
752 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
753 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
754 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
755 PCI_MEMORY_RANGE_MASK
& 0xffff);
756 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
757 PCI_MEMORY_RANGE_MASK
& 0xffff);
758 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
759 PCI_PREF_RANGE_MASK
& 0xffff);
760 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
761 PCI_PREF_RANGE_MASK
& 0xffff);
763 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
764 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
766 /* Supported memory and i/o types */
767 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
768 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
769 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
770 PCI_PREF_RANGE_TYPE_64
);
771 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
772 PCI_PREF_RANGE_TYPE_64
);
775 * TODO: Bridges default to 10-bit VGA decoding but we currently only
776 * implement 16-bit decoding (no alias support).
778 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
779 PCI_BRIDGE_CTL_PARITY
|
780 PCI_BRIDGE_CTL_SERR
|
783 PCI_BRIDGE_CTL_VGA_16BIT
|
784 PCI_BRIDGE_CTL_MASTER_ABORT
|
785 PCI_BRIDGE_CTL_BUS_RESET
|
786 PCI_BRIDGE_CTL_FAST_BACK
|
787 PCI_BRIDGE_CTL_DISCARD
|
788 PCI_BRIDGE_CTL_SEC_DISCARD
|
789 PCI_BRIDGE_CTL_DISCARD_SERR
);
790 /* Below does not do anything as we never set this bit, put here for
792 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
793 PCI_BRIDGE_CTL_DISCARD_STATUS
);
794 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
795 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
796 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
797 PCI_PREF_RANGE_TYPE_MASK
);
798 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
799 PCI_PREF_RANGE_TYPE_MASK
);
802 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
804 uint8_t slot
= PCI_SLOT(dev
->devfn
);
807 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
808 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
812 * multifunction bit is interpreted in two ways as follows.
813 * - all functions must set the bit to 1.
815 * - function 0 must set the bit, but the rest function (> 0)
816 * is allowed to leave the bit to 0.
817 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
819 * So OS (at least Linux) checks the bit of only function 0,
820 * and doesn't see the bit of function > 0.
822 * The below check allows both interpretation.
824 if (PCI_FUNC(dev
->devfn
)) {
825 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
826 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
827 /* function 0 should set multifunction bit */
828 error_setg(errp
, "PCI: single function device can't be populated "
829 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
835 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
838 /* function 0 indicates single function, so function > 0 must be NULL */
839 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
840 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
841 error_setg(errp
, "PCI: %x.0 indicates single function, "
842 "but %x.%x is already populated.",
849 static void pci_config_alloc(PCIDevice
*pci_dev
)
851 int config_size
= pci_config_size(pci_dev
);
853 pci_dev
->config
= g_malloc0(config_size
);
854 pci_dev
->cmask
= g_malloc0(config_size
);
855 pci_dev
->wmask
= g_malloc0(config_size
);
856 pci_dev
->w1cmask
= g_malloc0(config_size
);
857 pci_dev
->used
= g_malloc0(config_size
);
860 static void pci_config_free(PCIDevice
*pci_dev
)
862 g_free(pci_dev
->config
);
863 g_free(pci_dev
->cmask
);
864 g_free(pci_dev
->wmask
);
865 g_free(pci_dev
->w1cmask
);
866 g_free(pci_dev
->used
);
869 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
871 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
872 pci_config_free(pci_dev
);
874 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
875 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
876 &pci_dev
->bus_master_enable_region
);
878 address_space_destroy(&pci_dev
->bus_master_as
);
881 /* Extract PCIReqIDCache into BDF format */
882 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
887 switch (cache
->type
) {
889 result
= pci_get_bdf(cache
->dev
);
891 case PCI_REQ_ID_SECONDARY_BUS
:
892 bus_n
= pci_dev_bus_num(cache
->dev
);
893 result
= PCI_BUILD_BDF(bus_n
, 0);
896 error_printf("Invalid PCI requester ID cache type: %d\n",
905 /* Parse bridges up to the root complex and return requester ID
906 * cache for specific device. For full PCIe topology, the cache
907 * result would be exactly the same as getting BDF of the device.
908 * However, several tricks are required when system mixed up with
909 * legacy PCI devices and PCIe-to-PCI bridges.
911 * Here we cache the proxy device (and type) not requester ID since
912 * bus number might change from time to time.
914 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
917 PCIReqIDCache cache
= {
919 .type
= PCI_REQ_ID_BDF
,
922 while (!pci_bus_is_root(pci_get_bus(dev
))) {
923 /* We are under PCI/PCIe bridges */
924 parent
= pci_get_bus(dev
)->parent_dev
;
925 if (pci_is_express(parent
)) {
926 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
927 /* When we pass through PCIe-to-PCI/PCIX bridges, we
928 * override the requester ID using secondary bus
929 * number of parent bridge with zeroed devfn
930 * (pcie-to-pci bridge spec chap 2.3). */
931 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
935 /* Legacy PCI, override requester ID with the bridge's
936 * BDF upstream. When the root complex connects to
937 * legacy PCI devices (including buses), it can only
938 * obtain requester ID info from directly attached
939 * devices. If devices are attached under bridges, only
940 * the requester ID of the bridge that is directly
941 * attached to the root complex can be recognized. */
942 cache
.type
= PCI_REQ_ID_BDF
;
951 uint16_t pci_requester_id(PCIDevice
*dev
)
953 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
956 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
958 return !(bus
->devices
[devfn
]);
961 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
963 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
966 /* -1 for devfn means auto assign */
967 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
968 const char *name
, int devfn
,
971 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
972 PCIConfigReadFunc
*config_read
= pc
->config_read
;
973 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
974 Error
*local_err
= NULL
;
975 DeviceState
*dev
= DEVICE(pci_dev
);
976 PCIBus
*bus
= pci_get_bus(pci_dev
);
978 /* Only pci bridges can be attached to extra PCI root buses */
979 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
981 "PCI: Only PCI/PCIe bridges can be plugged into %s",
982 bus
->parent_dev
->name
);
987 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
988 devfn
+= PCI_FUNC_MAX
) {
989 if (pci_bus_devfn_available(bus
, devfn
) &&
990 !pci_bus_devfn_reserved(bus
, devfn
)) {
994 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
995 "or reserved", name
);
998 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
999 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1001 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1003 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1004 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1006 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1007 bus
->devices
[devfn
]->name
);
1009 } else if (dev
->hotplugged
&&
1010 pci_get_function_0(pci_dev
)) {
1011 error_setg(errp
, "PCI: slot %d function 0 already ocuppied by %s,"
1012 " new func %s cannot be exposed to guest.",
1013 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1014 pci_get_function_0(pci_dev
)->name
,
1020 pci_dev
->devfn
= devfn
;
1021 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1022 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1024 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1025 "bus master container", UINT64_MAX
);
1026 address_space_init(&pci_dev
->bus_master_as
,
1027 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1030 pci_init_bus_master(pci_dev
);
1032 pci_dev
->irq_state
= 0;
1033 pci_config_alloc(pci_dev
);
1035 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1036 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1037 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1038 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1040 if (!pc
->is_bridge
) {
1041 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1042 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1043 pc
->subsystem_vendor_id
);
1044 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1047 pci_set_default_subsystem_id(pci_dev
);
1050 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1051 assert(!pc
->subsystem_vendor_id
);
1052 assert(!pc
->subsystem_id
);
1054 pci_init_cmask(pci_dev
);
1055 pci_init_wmask(pci_dev
);
1056 pci_init_w1cmask(pci_dev
);
1057 if (pc
->is_bridge
) {
1058 pci_init_mask_bridge(pci_dev
);
1060 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1062 error_propagate(errp
, local_err
);
1063 do_pci_unregister_device(pci_dev
);
1068 config_read
= pci_default_read_config
;
1070 config_write
= pci_default_write_config
;
1071 pci_dev
->config_read
= config_read
;
1072 pci_dev
->config_write
= config_write
;
1073 bus
->devices
[devfn
] = pci_dev
;
1074 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1078 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1083 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1084 r
= &pci_dev
->io_regions
[i
];
1085 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1087 memory_region_del_subregion(r
->address_space
, r
->memory
);
1090 pci_unregister_vga(pci_dev
);
1093 static void pci_qdev_unrealize(DeviceState
*dev
, Error
**errp
)
1095 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1096 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1098 pci_unregister_io_regions(pci_dev
);
1099 pci_del_option_rom(pci_dev
);
1105 pci_device_deassert_intx(pci_dev
);
1106 do_pci_unregister_device(pci_dev
);
1109 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1110 uint8_t type
, MemoryRegion
*memory
)
1113 uint32_t addr
; /* offset in pci config space */
1115 pcibus_t size
= memory_region_size(memory
);
1117 assert(region_num
>= 0);
1118 assert(region_num
< PCI_NUM_REGIONS
);
1119 if (size
& (size
-1)) {
1120 error_report("ERROR: PCI region size must be pow2 "
1121 "type=0x%x, size=0x%"FMT_PCIBUS
"", type
, size
);
1125 r
= &pci_dev
->io_regions
[region_num
];
1126 r
->addr
= PCI_BAR_UNMAPPED
;
1130 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1131 ? pci_get_bus(pci_dev
)->address_space_io
1132 : pci_get_bus(pci_dev
)->address_space_mem
;
1134 wmask
= ~(size
- 1);
1135 if (region_num
== PCI_ROM_SLOT
) {
1136 /* ROM enable bit is writable */
1137 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1140 addr
= pci_bar(pci_dev
, region_num
);
1141 pci_set_long(pci_dev
->config
+ addr
, type
);
1143 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1144 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1145 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1146 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1148 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1149 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1153 static void pci_update_vga(PCIDevice
*pci_dev
)
1157 if (!pci_dev
->has_vga
) {
1161 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1163 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1164 cmd
& PCI_COMMAND_MEMORY
);
1165 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1166 cmd
& PCI_COMMAND_IO
);
1167 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1168 cmd
& PCI_COMMAND_IO
);
1171 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1172 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1174 PCIBus
*bus
= pci_get_bus(pci_dev
);
1176 assert(!pci_dev
->has_vga
);
1178 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1179 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1180 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1181 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1183 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1184 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1185 memory_region_add_subregion_overlap(bus
->address_space_io
,
1186 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1188 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1189 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1190 memory_region_add_subregion_overlap(bus
->address_space_io
,
1191 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1192 pci_dev
->has_vga
= true;
1194 pci_update_vga(pci_dev
);
1197 void pci_unregister_vga(PCIDevice
*pci_dev
)
1199 PCIBus
*bus
= pci_get_bus(pci_dev
);
1201 if (!pci_dev
->has_vga
) {
1205 memory_region_del_subregion(bus
->address_space_mem
,
1206 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1207 memory_region_del_subregion(bus
->address_space_io
,
1208 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1209 memory_region_del_subregion(bus
->address_space_io
,
1210 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1211 pci_dev
->has_vga
= false;
1214 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1216 return pci_dev
->io_regions
[region_num
].addr
;
1219 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1220 int reg
, uint8_t type
, pcibus_t size
)
1222 pcibus_t new_addr
, last_addr
;
1223 int bar
= pci_bar(d
, reg
);
1224 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1225 Object
*machine
= qdev_get_machine();
1226 ObjectClass
*oc
= object_get_class(machine
);
1227 MachineClass
*mc
= MACHINE_CLASS(oc
);
1228 bool allow_0_address
= mc
->pci_allow_0_address
;
1230 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1231 if (!(cmd
& PCI_COMMAND_IO
)) {
1232 return PCI_BAR_UNMAPPED
;
1234 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1235 last_addr
= new_addr
+ size
- 1;
1236 /* Check if 32 bit BAR wraps around explicitly.
1237 * TODO: make priorities correct and remove this work around.
1239 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1240 (!allow_0_address
&& new_addr
== 0)) {
1241 return PCI_BAR_UNMAPPED
;
1246 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1247 return PCI_BAR_UNMAPPED
;
1249 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1250 new_addr
= pci_get_quad(d
->config
+ bar
);
1252 new_addr
= pci_get_long(d
->config
+ bar
);
1254 /* the ROM slot has a specific enable bit */
1255 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1256 return PCI_BAR_UNMAPPED
;
1258 new_addr
&= ~(size
- 1);
1259 last_addr
= new_addr
+ size
- 1;
1260 /* NOTE: we do not support wrapping */
1261 /* XXX: as we cannot support really dynamic
1262 mappings, we handle specific values as invalid
1264 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1265 (!allow_0_address
&& new_addr
== 0)) {
1266 return PCI_BAR_UNMAPPED
;
1269 /* Now pcibus_t is 64bit.
1270 * Check if 32 bit BAR wraps around explicitly.
1271 * Without this, PC ide doesn't work well.
1272 * TODO: remove this work around.
1274 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1275 return PCI_BAR_UNMAPPED
;
1279 * OS is allowed to set BAR beyond its addressable
1280 * bits. For example, 32 bit OS can set 64bit bar
1281 * to >4G. Check it. TODO: we might need to support
1282 * it in the future for e.g. PAE.
1284 if (last_addr
>= HWADDR_MAX
) {
1285 return PCI_BAR_UNMAPPED
;
1291 static void pci_update_mappings(PCIDevice
*d
)
1297 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1298 r
= &d
->io_regions
[i
];
1300 /* this region isn't registered */
1304 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1306 /* This bar isn't changed */
1307 if (new_addr
== r
->addr
)
1310 /* now do the real mapping */
1311 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1312 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1315 i
, r
->addr
, r
->size
);
1316 memory_region_del_subregion(r
->address_space
, r
->memory
);
1319 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1320 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1323 i
, r
->addr
, r
->size
);
1324 memory_region_add_subregion_overlap(r
->address_space
,
1325 r
->addr
, r
->memory
, 1);
1332 static inline int pci_irq_disabled(PCIDevice
*d
)
1334 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1337 /* Called after interrupt disabled field update in config space,
1338 * assert/deassert interrupts if necessary.
1339 * Gets original interrupt disable bit value (before update). */
1340 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1342 int i
, disabled
= pci_irq_disabled(d
);
1343 if (disabled
== was_irq_disabled
)
1345 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1346 int state
= pci_irq_state(d
, i
);
1347 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1351 uint32_t pci_default_read_config(PCIDevice
*d
,
1352 uint32_t address
, int len
)
1356 memcpy(&val
, d
->config
+ address
, len
);
1357 return le32_to_cpu(val
);
1360 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1362 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1363 uint32_t val
= val_in
;
1365 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1366 uint8_t wmask
= d
->wmask
[addr
+ i
];
1367 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1368 assert(!(wmask
& w1cmask
));
1369 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1370 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1372 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1373 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1374 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1375 range_covers_byte(addr
, l
, PCI_COMMAND
))
1376 pci_update_mappings(d
);
1378 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1379 pci_update_irq_disabled(d
, was_irq_disabled
);
1380 memory_region_set_enabled(&d
->bus_master_enable_region
,
1381 pci_get_word(d
->config
+ PCI_COMMAND
)
1382 & PCI_COMMAND_MASTER
);
1385 msi_write_config(d
, addr
, val_in
, l
);
1386 msix_write_config(d
, addr
, val_in
, l
);
1389 /***********************************************************/
1390 /* generic PCI irq support */
1392 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1393 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1395 PCIDevice
*pci_dev
= opaque
;
1398 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1402 pci_set_irq_state(pci_dev
, irq_num
, level
);
1403 pci_update_irq_status(pci_dev
);
1404 if (pci_irq_disabled(pci_dev
))
1406 pci_change_irq_level(pci_dev
, irq_num
, change
);
1409 static inline int pci_intx(PCIDevice
*pci_dev
)
1411 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1414 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1416 int intx
= pci_intx(pci_dev
);
1418 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1421 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1423 int intx
= pci_intx(pci_dev
);
1424 pci_irq_handler(pci_dev
, intx
, level
);
1427 /* Special hooks used by device assignment */
1428 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1430 assert(pci_bus_is_root(bus
));
1431 bus
->route_intx_to_irq
= route_intx_to_irq
;
1434 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1439 bus
= pci_get_bus(dev
);
1440 pin
= bus
->map_irq(dev
, pin
);
1441 dev
= bus
->parent_dev
;
1444 if (!bus
->route_intx_to_irq
) {
1445 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1446 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1447 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1450 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1453 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1455 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1458 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1464 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1465 dev
= bus
->devices
[i
];
1466 if (dev
&& dev
->intx_routing_notifier
) {
1467 dev
->intx_routing_notifier(dev
);
1471 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1472 pci_bus_fire_intx_routing_notifier(sec
);
1476 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1477 PCIINTxRoutingNotifier notifier
)
1479 dev
->intx_routing_notifier
= notifier
;
1483 * PCI-to-PCI bridge specification
1484 * 9.1: Interrupt routing. Table 9-1
1486 * the PCI Express Base Specification, Revision 2.1
1487 * 2.2.8.1: INTx interrutp signaling - Rules
1488 * the Implementation Note
1492 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1493 * 0-origin unlike PCI interrupt pin register.
1495 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1497 return (pin
+ PCI_SLOT(pci_dev
->devfn
)) % PCI_NUM_PINS
;
1500 /***********************************************************/
1501 /* monitor info on PCI */
1506 const char *fw_name
;
1507 uint16_t fw_ign_bits
;
1510 static const pci_class_desc pci_class_descriptions
[] =
1512 { 0x0001, "VGA controller", "display"},
1513 { 0x0100, "SCSI controller", "scsi"},
1514 { 0x0101, "IDE controller", "ide"},
1515 { 0x0102, "Floppy controller", "fdc"},
1516 { 0x0103, "IPI controller", "ipi"},
1517 { 0x0104, "RAID controller", "raid"},
1518 { 0x0106, "SATA controller"},
1519 { 0x0107, "SAS controller"},
1520 { 0x0180, "Storage controller"},
1521 { 0x0200, "Ethernet controller", "ethernet"},
1522 { 0x0201, "Token Ring controller", "token-ring"},
1523 { 0x0202, "FDDI controller", "fddi"},
1524 { 0x0203, "ATM controller", "atm"},
1525 { 0x0280, "Network controller"},
1526 { 0x0300, "VGA controller", "display", 0x00ff},
1527 { 0x0301, "XGA controller"},
1528 { 0x0302, "3D controller"},
1529 { 0x0380, "Display controller"},
1530 { 0x0400, "Video controller", "video"},
1531 { 0x0401, "Audio controller", "sound"},
1533 { 0x0403, "Audio controller", "sound"},
1534 { 0x0480, "Multimedia controller"},
1535 { 0x0500, "RAM controller", "memory"},
1536 { 0x0501, "Flash controller", "flash"},
1537 { 0x0580, "Memory controller"},
1538 { 0x0600, "Host bridge", "host"},
1539 { 0x0601, "ISA bridge", "isa"},
1540 { 0x0602, "EISA bridge", "eisa"},
1541 { 0x0603, "MC bridge", "mca"},
1542 { 0x0604, "PCI bridge", "pci-bridge"},
1543 { 0x0605, "PCMCIA bridge", "pcmcia"},
1544 { 0x0606, "NUBUS bridge", "nubus"},
1545 { 0x0607, "CARDBUS bridge", "cardbus"},
1546 { 0x0608, "RACEWAY bridge"},
1547 { 0x0680, "Bridge"},
1548 { 0x0700, "Serial port", "serial"},
1549 { 0x0701, "Parallel port", "parallel"},
1550 { 0x0800, "Interrupt controller", "interrupt-controller"},
1551 { 0x0801, "DMA controller", "dma-controller"},
1552 { 0x0802, "Timer", "timer"},
1553 { 0x0803, "RTC", "rtc"},
1554 { 0x0900, "Keyboard", "keyboard"},
1555 { 0x0901, "Pen", "pen"},
1556 { 0x0902, "Mouse", "mouse"},
1557 { 0x0A00, "Dock station", "dock", 0x00ff},
1558 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1559 { 0x0c00, "Fireware contorller", "fireware"},
1560 { 0x0c01, "Access bus controller", "access-bus"},
1561 { 0x0c02, "SSA controller", "ssa"},
1562 { 0x0c03, "USB controller", "usb"},
1563 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1568 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1569 void (*fn
)(PCIBus
*b
,
1577 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1578 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1585 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1586 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1589 bus
= pci_find_bus_nr(bus
, bus_num
);
1592 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1596 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1597 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1604 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1605 d
= bus
->devices
[devfn
];
1612 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1613 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1616 bus
= pci_find_bus_nr(bus
, bus_num
);
1619 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1623 static const pci_class_desc
*get_class_desc(int class)
1625 const pci_class_desc
*desc
;
1627 desc
= pci_class_descriptions
;
1628 while (desc
->desc
&& class != desc
->class) {
1635 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1637 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1639 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1642 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1643 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1644 PciMemoryRegionList
*region
;
1650 region
= g_malloc0(sizeof(*region
));
1651 region
->value
= g_malloc0(sizeof(*region
->value
));
1653 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1654 region
->value
->type
= g_strdup("io");
1656 region
->value
->type
= g_strdup("memory");
1657 region
->value
->has_prefetch
= true;
1658 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1659 region
->value
->has_mem_type_64
= true;
1660 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1663 region
->value
->bar
= i
;
1664 region
->value
->address
= r
->addr
;
1665 region
->value
->size
= r
->size
;
1667 /* XXX: waiting for the qapi to support GSList */
1669 head
= cur_item
= region
;
1671 cur_item
->next
= region
;
1679 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1682 PciBridgeInfo
*info
;
1683 PciMemoryRange
*range
;
1685 info
= g_new0(PciBridgeInfo
, 1);
1687 info
->bus
= g_new0(PciBusInfo
, 1);
1688 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1689 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1690 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1692 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1693 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1694 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1696 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1697 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1698 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1700 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1701 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1702 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1704 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1705 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1707 info
->has_devices
= true;
1708 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1715 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1718 const pci_class_desc
*desc
;
1719 PciDeviceInfo
*info
;
1723 info
= g_new0(PciDeviceInfo
, 1);
1724 info
->bus
= bus_num
;
1725 info
->slot
= PCI_SLOT(dev
->devfn
);
1726 info
->function
= PCI_FUNC(dev
->devfn
);
1728 info
->class_info
= g_new0(PciDeviceClass
, 1);
1729 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1730 info
->class_info
->q_class
= class;
1731 desc
= get_class_desc(class);
1733 info
->class_info
->has_desc
= true;
1734 info
->class_info
->desc
= g_strdup(desc
->desc
);
1737 info
->id
= g_new0(PciDeviceId
, 1);
1738 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1739 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1740 info
->regions
= qmp_query_pci_regions(dev
);
1741 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1743 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1744 info
->has_irq
= true;
1745 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1748 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1749 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1750 info
->has_pci_bridge
= true;
1751 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1757 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1759 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1763 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1764 dev
= bus
->devices
[devfn
];
1766 info
= g_malloc0(sizeof(*info
));
1767 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1769 /* XXX: waiting for the qapi to support GSList */
1771 head
= cur_item
= info
;
1773 cur_item
->next
= info
;
1782 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1784 PciInfo
*info
= NULL
;
1786 bus
= pci_find_bus_nr(bus
, bus_num
);
1788 info
= g_malloc0(sizeof(*info
));
1789 info
->bus
= bus_num
;
1790 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1796 PciInfoList
*qmp_query_pci(Error
**errp
)
1798 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1799 PCIHostState
*host_bridge
;
1801 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1802 info
= g_malloc0(sizeof(*info
));
1803 info
->value
= qmp_query_pci_bus(host_bridge
->bus
,
1804 pci_bus_num(host_bridge
->bus
));
1806 /* XXX: waiting for the qapi to support GSList */
1808 head
= cur_item
= info
;
1810 cur_item
->next
= info
;
1818 /* Initialize a PCI NIC. */
1819 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1820 const char *default_model
,
1821 const char *default_devaddr
)
1823 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1825 GPtrArray
*pci_nic_models
;
1832 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1834 nd
->model
= g_strdup("virtio-net-pci");
1837 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1838 pci_nic_models
= g_ptr_array_new();
1840 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1843 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1844 dc
->user_creatable
) {
1845 const char *name
= object_class_get_name(list
->data
);
1846 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1849 g_slist_free_1(list
);
1852 g_ptr_array_add(pci_nic_models
, NULL
);
1854 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1858 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1864 bus
= pci_get_bus_devfn(&devfn
, rootbus
, devaddr
);
1866 error_report("Invalid PCI device address %s for device %s",
1867 devaddr
, nd
->model
);
1871 pci_dev
= pci_create(bus
, devfn
, nd
->model
);
1872 dev
= &pci_dev
->qdev
;
1873 qdev_set_nic_properties(dev
, nd
);
1874 qdev_init_nofail(dev
);
1875 g_ptr_array_free(pci_nic_models
, true);
1879 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1881 switch (vga_interface_type
) {
1883 return pci_create_simple(bus
, -1, "cirrus-vga");
1885 return pci_create_simple(bus
, -1, "qxl-vga");
1887 return pci_create_simple(bus
, -1, "VGA");
1889 return pci_create_simple(bus
, -1, "vmware-svga");
1891 return pci_create_simple(bus
, -1, "virtio-vga");
1893 default: /* Other non-PCI types. Checking for unsupported types is already
1899 /* Whether a given bus number is in range of the secondary
1900 * bus of the given bridge device. */
1901 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1903 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1904 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1905 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1906 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1909 /* Whether a given bus number is in a range of a root bus */
1910 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
1914 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1915 PCIDevice
*dev
= bus
->devices
[i
];
1917 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
1918 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
1927 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1935 if (pci_bus_num(bus
) == bus_num
) {
1939 /* Consider all bus numbers in range for the host pci bridge. */
1940 if (!pci_bus_is_root(bus
) &&
1941 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1946 for (; bus
; bus
= sec
) {
1947 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1948 if (pci_bus_num(sec
) == bus_num
) {
1951 /* PXB buses assumed to be children of bus 0 */
1952 if (pci_bus_is_root(sec
)) {
1953 if (pci_root_bus_in_range(sec
, bus_num
)) {
1957 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1967 void pci_for_each_bus_depth_first(PCIBus
*bus
,
1968 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
1969 void (*end
)(PCIBus
*bus
, void *state
),
1980 state
= begin(bus
, parent_state
);
1982 state
= parent_state
;
1985 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1986 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
1995 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1997 bus
= pci_find_bus_nr(bus
, bus_num
);
2002 return bus
->devices
[devfn
];
2005 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2007 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2008 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2009 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2010 Error
*local_err
= NULL
;
2011 bool is_default_rom
;
2013 /* initialize cap_present for pci_is_express() and pci_config_size(),
2014 * Note that hybrid PCIs are not set automatically and need to manage
2015 * QEMU_PCI_CAP_EXPRESS manually */
2016 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2017 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2018 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2021 pci_dev
= do_pci_register_device(pci_dev
,
2022 object_get_typename(OBJECT(qdev
)),
2023 pci_dev
->devfn
, errp
);
2024 if (pci_dev
== NULL
)
2028 pc
->realize(pci_dev
, &local_err
);
2030 error_propagate(errp
, local_err
);
2031 do_pci_unregister_device(pci_dev
);
2037 is_default_rom
= false;
2038 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2039 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2040 is_default_rom
= true;
2043 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2045 error_propagate(errp
, local_err
);
2046 pci_qdev_unrealize(DEVICE(pci_dev
), NULL
);
2051 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
2056 dev
= qdev_create(&bus
->qbus
, name
);
2057 qdev_prop_set_int32(dev
, "addr", devfn
);
2058 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2059 return PCI_DEVICE(dev
);
2062 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2066 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
2067 qdev_init_nofail(&dev
->qdev
);
2071 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
2073 return pci_create_multifunction(bus
, devfn
, false, name
);
2076 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2078 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2081 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2083 int offset
= PCI_CONFIG_HEADER_SIZE
;
2085 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2088 else if (i
- offset
+ 1 == size
)
2094 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2099 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2102 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2103 prev
= next
+ PCI_CAP_LIST_NEXT
)
2104 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2112 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2114 uint8_t next
, prev
, found
= 0;
2116 if (!(pdev
->used
[offset
])) {
2120 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2122 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2123 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2124 if (next
<= offset
&& next
> found
) {
2131 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2132 This is needed for an option rom which is used for more than one device. */
2133 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
2137 uint16_t rom_vendor_id
;
2138 uint16_t rom_device_id
;
2140 uint16_t pcir_offset
;
2143 /* Words in rom data are little endian (like in PCI configuration),
2144 so they can be read / written with pci_get_word / pci_set_word. */
2146 /* Only a valid rom will be patched. */
2147 rom_magic
= pci_get_word(ptr
);
2148 if (rom_magic
!= 0xaa55) {
2149 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2152 pcir_offset
= pci_get_word(ptr
+ 0x18);
2153 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2154 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2158 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2159 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2160 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2161 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2163 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2164 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2168 if (vendor_id
!= rom_vendor_id
) {
2169 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2170 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2171 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2172 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2174 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2177 if (device_id
!= rom_device_id
) {
2178 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2179 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2180 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2181 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2183 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2187 /* Add an option rom for the device */
2188 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2195 const VMStateDescription
*vmsd
;
2199 if (strlen(pdev
->romfile
) == 0)
2202 if (!pdev
->rom_bar
) {
2204 * Load rom via fw_cfg instead of creating a rom bar,
2205 * for 0.11 compatibility.
2207 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2210 * Hot-plugged devices can't use the option ROM
2211 * if the rom bar is disabled.
2213 if (DEVICE(pdev
)->hotplugged
) {
2214 error_setg(errp
, "Hot-plugged device without ROM bar"
2215 " can't have an option ROM");
2219 if (class == 0x0300) {
2220 rom_add_vga(pdev
->romfile
);
2222 rom_add_option(pdev
->romfile
, -1);
2227 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2229 path
= g_strdup(pdev
->romfile
);
2232 size
= get_image_size(path
);
2234 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2237 } else if (size
== 0) {
2238 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2242 size
= pow2ceil(size
);
2244 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2247 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2249 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2251 pdev
->has_rom
= true;
2252 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, size
, &error_fatal
);
2253 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2254 load_image(path
, ptr
);
2257 if (is_default_rom
) {
2258 /* Only the default rom images will be patched (if needed). */
2259 pci_patch_ids(pdev
, ptr
, size
);
2262 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2265 static void pci_del_option_rom(PCIDevice
*pdev
)
2270 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2271 pdev
->has_rom
= false;
2275 * On success, pci_add_capability() returns a positive value
2276 * that the offset of the pci capability.
2277 * On failure, it sets an error and returns a negative error
2280 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2281 uint8_t offset
, uint8_t size
,
2285 int i
, overlapping_cap
;
2288 offset
= pci_find_space(pdev
, size
);
2289 /* out of PCI config space is programming error */
2292 /* Verify that capabilities don't overlap. Note: device assignment
2293 * depends on this check to verify that the device is not broken.
2294 * Should never trigger for emulated devices, but it's helpful
2295 * for debugging these. */
2296 for (i
= offset
; i
< offset
+ size
; i
++) {
2297 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2298 if (overlapping_cap
) {
2299 error_setg(errp
, "%s:%02x:%02x.%x "
2300 "Attempt to add PCI capability %x at offset "
2301 "%x overlaps existing capability %x at offset %x",
2302 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2303 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2304 cap_id
, offset
, overlapping_cap
, i
);
2310 config
= pdev
->config
+ offset
;
2311 config
[PCI_CAP_LIST_ID
] = cap_id
;
2312 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2313 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2314 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2315 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2316 /* Make capability read-only by default */
2317 memset(pdev
->wmask
+ offset
, 0, size
);
2318 /* Check capability by default */
2319 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2323 /* Unlink capability from the pci config space. */
2324 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2326 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2329 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2330 /* Make capability writable again */
2331 memset(pdev
->wmask
+ offset
, 0xff, size
);
2332 memset(pdev
->w1cmask
+ offset
, 0, size
);
2333 /* Clear cmask as device-specific registers can't be checked */
2334 memset(pdev
->cmask
+ offset
, 0, size
);
2335 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2337 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2338 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2341 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2343 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2346 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2348 PCIDevice
*d
= (PCIDevice
*)dev
;
2349 const pci_class_desc
*desc
;
2354 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2355 desc
= pci_class_descriptions
;
2356 while (desc
->desc
&& class != desc
->class)
2359 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2361 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2364 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2365 "pci id %04x:%04x (sub %04x:%04x)\n",
2366 indent
, "", ctxt
, pci_dev_bus_num(d
),
2367 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2368 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2369 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2370 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2371 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2372 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2373 r
= &d
->io_regions
[i
];
2376 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2377 " [0x%"FMT_PCIBUS
"]\n",
2379 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2380 r
->addr
, r
->addr
+ r
->size
- 1);
2384 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2386 PCIDevice
*d
= (PCIDevice
*)dev
;
2387 const char *name
= NULL
;
2388 const pci_class_desc
*desc
= pci_class_descriptions
;
2389 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2391 while (desc
->desc
&&
2392 (class & ~desc
->fw_ign_bits
) !=
2393 (desc
->class & ~desc
->fw_ign_bits
)) {
2398 name
= desc
->fw_name
;
2402 pstrcpy(buf
, len
, name
);
2404 snprintf(buf
, len
, "pci%04x,%04x",
2405 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2406 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2412 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2414 PCIDevice
*d
= (PCIDevice
*)dev
;
2415 char path
[50], name
[33];
2418 off
= snprintf(path
, sizeof(path
), "%s@%x",
2419 pci_dev_fw_name(dev
, name
, sizeof name
),
2420 PCI_SLOT(d
->devfn
));
2421 if (PCI_FUNC(d
->devfn
))
2422 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2423 return g_strdup(path
);
2426 static char *pcibus_get_dev_path(DeviceState
*dev
)
2428 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2431 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2432 * 00 is added here to make this format compatible with
2433 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2434 * Slot.Function list specifies the slot and function numbers for all
2435 * devices on the path from root to the specific device. */
2436 const char *root_bus_path
;
2438 char slot
[] = ":SS.F";
2439 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2444 root_bus_path
= pci_root_bus_path(d
);
2445 root_bus_len
= strlen(root_bus_path
);
2447 /* Calculate # of slots on path between device and root. */;
2449 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2453 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2455 /* Allocate memory, fill in the terminating null byte. */
2456 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2457 path
[path_len
] = '\0';
2459 memcpy(path
, root_bus_path
, root_bus_len
);
2461 /* Fill in slot numbers. We walk up from device to root, so need to print
2462 * them in the reverse order, last to first. */
2463 p
= path
+ path_len
;
2464 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2466 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2467 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2468 assert(s
== slot_len
);
2469 memcpy(p
, slot
, slot_len
);
2475 static int pci_qdev_find_recursive(PCIBus
*bus
,
2476 const char *id
, PCIDevice
**pdev
)
2478 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2483 /* roughly check if given qdev is pci device */
2484 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2485 *pdev
= PCI_DEVICE(qdev
);
2491 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2493 PCIHostState
*host_bridge
;
2496 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2497 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2502 if (tmp
!= -ENODEV
) {
2510 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2512 return pci_get_bus(dev
)->address_space_mem
;
2515 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2517 return pci_get_bus(dev
)->address_space_io
;
2520 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2522 DeviceClass
*k
= DEVICE_CLASS(klass
);
2524 k
->realize
= pci_qdev_realize
;
2525 k
->unrealize
= pci_qdev_unrealize
;
2526 k
->bus_type
= TYPE_PCI_BUS
;
2527 k
->props
= pci_props
;
2530 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2532 if (!object_class_is_abstract(klass
)) {
2533 ObjectClass
*conventional
=
2534 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2536 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2537 assert(conventional
|| pcie
);
2541 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2543 PCIBus
*bus
= pci_get_bus(dev
);
2544 PCIBus
*iommu_bus
= bus
;
2546 while(iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2547 iommu_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2549 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2550 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, dev
->devfn
);
2552 return &address_space_memory
;
2555 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2558 bus
->iommu_opaque
= opaque
;
2561 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2563 Range
*range
= opaque
;
2564 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2565 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2568 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2572 if (pc
->is_bridge
) {
2573 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2574 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2576 base
= MAX(base
, 0x1ULL
<< 32);
2578 if (limit
>= base
) {
2580 range_set_bounds(&pref_range
, base
, limit
);
2581 range_extend(range
, &pref_range
);
2584 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2585 PCIIORegion
*r
= &dev
->io_regions
[i
];
2590 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2591 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2595 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2596 upb
= lob
+ r
->size
- 1;
2597 if (lob
== PCI_BAR_UNMAPPED
) {
2601 lob
= MAX(lob
, 0x1ULL
<< 32);
2604 range_set_bounds(®ion_range
, lob
, upb
);
2605 range_extend(range
, ®ion_range
);
2610 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2612 range_make_empty(range
);
2613 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2616 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2618 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2620 /* Device associated with an upstream port.
2621 * As there are several types of these, it's easier to check the
2622 * parent device: upstream ports are always connected to
2623 * root or downstream ports.
2625 return parent_dev
&&
2626 pci_is_express(parent_dev
) &&
2627 parent_dev
->exp
.exp_cap
&&
2628 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2629 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2632 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2634 PCIBus
*bus
= pci_get_bus(pci_dev
);
2636 if(pcie_has_upstream_port(pci_dev
)) {
2637 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2638 return bus
->devices
[0];
2640 /* Other bus types might support multiple devices at slots 0-31 */
2641 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2645 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2648 if (msix_enabled(dev
)) {
2649 msg
= msix_get_message(dev
, vector
);
2650 } else if (msi_enabled(dev
)) {
2651 msg
= msi_get_message(dev
, vector
);
2653 /* Should never happen */
2654 error_report("%s: unknown interrupt type", __func__
);
2660 static const TypeInfo pci_device_type_info
= {
2661 .name
= TYPE_PCI_DEVICE
,
2662 .parent
= TYPE_DEVICE
,
2663 .instance_size
= sizeof(PCIDevice
),
2665 .class_size
= sizeof(PCIDeviceClass
),
2666 .class_init
= pci_device_class_init
,
2667 .class_base_init
= pci_device_class_base_init
,
2670 static void pci_register_types(void)
2672 type_register_static(&pci_bus_info
);
2673 type_register_static(&pcie_bus_info
);
2674 type_register_static(&conventional_pci_interface_info
);
2675 type_register_static(&pcie_interface_info
);
2676 type_register_static(&pci_device_type_info
);
2679 type_init(pci_register_types
)