block: Ignore generated job QAPI files
[qemu/ar7.git] / hw / nvram / fw_cfg.c
blobb23e7f64a873a046dea81cbe51e9eeeea43495d4
1 /*
2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/dma.h"
29 #include "hw/boards.h"
30 #include "hw/isa/isa.h"
31 #include "hw/nvram/fw_cfg.h"
32 #include "hw/sysbus.h"
33 #include "trace.h"
34 #include "qemu/error-report.h"
35 #include "qemu/option.h"
36 #include "qemu/config-file.h"
37 #include "qemu/cutils.h"
38 #include "qapi/error.h"
40 #define FW_CFG_FILE_SLOTS_DFLT 0x20
42 /* FW_CFG_VERSION bits */
43 #define FW_CFG_VERSION 0x01
44 #define FW_CFG_VERSION_DMA 0x02
46 /* FW_CFG_DMA_CONTROL bits */
47 #define FW_CFG_DMA_CTL_ERROR 0x01
48 #define FW_CFG_DMA_CTL_READ 0x02
49 #define FW_CFG_DMA_CTL_SKIP 0x04
50 #define FW_CFG_DMA_CTL_SELECT 0x08
51 #define FW_CFG_DMA_CTL_WRITE 0x10
53 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
55 struct FWCfgEntry {
56 uint32_t len;
57 bool allow_write;
58 uint8_t *data;
59 void *callback_opaque;
60 FWCfgCallback select_cb;
61 FWCfgWriteCallback write_cb;
64 #define JPG_FILE 0
65 #define BMP_FILE 1
67 static char *read_splashfile(char *filename, gsize *file_sizep,
68 int *file_typep)
70 GError *err = NULL;
71 gboolean res;
72 gchar *content;
73 int file_type;
74 unsigned int filehead;
75 int bmp_bpp;
77 res = g_file_get_contents(filename, &content, file_sizep, &err);
78 if (res == FALSE) {
79 error_report("failed to read splash file '%s'", filename);
80 g_error_free(err);
81 return NULL;
84 /* check file size */
85 if (*file_sizep < 30) {
86 goto error;
89 /* check magic ID */
90 filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
91 if (filehead == 0xd8ff) {
92 file_type = JPG_FILE;
93 } else if (filehead == 0x4d42) {
94 file_type = BMP_FILE;
95 } else {
96 goto error;
99 /* check BMP bpp */
100 if (file_type == BMP_FILE) {
101 bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
102 if (bmp_bpp != 24) {
103 goto error;
107 /* return values */
108 *file_typep = file_type;
110 return content;
112 error:
113 error_report("splash file '%s' format not recognized; must be JPEG "
114 "or 24 bit BMP", filename);
115 g_free(content);
116 return NULL;
119 static void fw_cfg_bootsplash(FWCfgState *s)
121 int boot_splash_time = -1;
122 const char *boot_splash_filename = NULL;
123 char *p;
124 char *filename, *file_data;
125 gsize file_size;
126 int file_type;
127 const char *temp;
129 /* get user configuration */
130 QemuOptsList *plist = qemu_find_opts("boot-opts");
131 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
132 if (opts != NULL) {
133 temp = qemu_opt_get(opts, "splash");
134 if (temp != NULL) {
135 boot_splash_filename = temp;
137 temp = qemu_opt_get(opts, "splash-time");
138 if (temp != NULL) {
139 p = (char *)temp;
140 boot_splash_time = strtol(p, &p, 10);
144 /* insert splash time if user configurated */
145 if (boot_splash_time >= 0) {
146 /* validate the input */
147 if (boot_splash_time > 0xffff) {
148 error_report("splash time is big than 65535, force it to 65535.");
149 boot_splash_time = 0xffff;
151 /* use little endian format */
152 qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
153 qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
154 fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
157 /* insert splash file if user configurated */
158 if (boot_splash_filename != NULL) {
159 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
160 if (filename == NULL) {
161 error_report("failed to find file '%s'.", boot_splash_filename);
162 return;
165 /* loading file data */
166 file_data = read_splashfile(filename, &file_size, &file_type);
167 if (file_data == NULL) {
168 g_free(filename);
169 return;
171 g_free(boot_splash_filedata);
172 boot_splash_filedata = (uint8_t *)file_data;
173 boot_splash_filedata_size = file_size;
175 /* insert data */
176 if (file_type == JPG_FILE) {
177 fw_cfg_add_file(s, "bootsplash.jpg",
178 boot_splash_filedata, boot_splash_filedata_size);
179 } else {
180 fw_cfg_add_file(s, "bootsplash.bmp",
181 boot_splash_filedata, boot_splash_filedata_size);
183 g_free(filename);
187 static void fw_cfg_reboot(FWCfgState *s)
189 int reboot_timeout = -1;
190 char *p;
191 const char *temp;
193 /* get user configuration */
194 QemuOptsList *plist = qemu_find_opts("boot-opts");
195 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
196 if (opts != NULL) {
197 temp = qemu_opt_get(opts, "reboot-timeout");
198 if (temp != NULL) {
199 p = (char *)temp;
200 reboot_timeout = strtol(p, &p, 10);
203 /* validate the input */
204 if (reboot_timeout > 0xffff) {
205 error_report("reboot timeout is larger than 65535, force it to 65535.");
206 reboot_timeout = 0xffff;
208 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
211 static void fw_cfg_write(FWCfgState *s, uint8_t value)
213 /* nothing, write support removed in QEMU v2.4+ */
216 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
218 return s->file_slots;
221 /* Note: this function returns an exclusive limit. */
222 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
224 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
227 static int fw_cfg_select(FWCfgState *s, uint16_t key)
229 int arch, ret;
230 FWCfgEntry *e;
232 s->cur_offset = 0;
233 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
234 s->cur_entry = FW_CFG_INVALID;
235 ret = 0;
236 } else {
237 s->cur_entry = key;
238 ret = 1;
239 /* entry successfully selected, now run callback if present */
240 arch = !!(key & FW_CFG_ARCH_LOCAL);
241 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
242 if (e->select_cb) {
243 e->select_cb(e->callback_opaque);
247 trace_fw_cfg_select(s, key, ret);
248 return ret;
251 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
253 FWCfgState *s = opaque;
254 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
255 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
256 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
257 uint64_t value = 0;
259 assert(size > 0 && size <= sizeof(value));
260 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
261 /* The least significant 'size' bytes of the return value are
262 * expected to contain a string preserving portion of the item
263 * data, padded with zeros on the right in case we run out early.
264 * In technical terms, we're composing the host-endian representation
265 * of the big endian interpretation of the fw_cfg string.
267 do {
268 value = (value << 8) | e->data[s->cur_offset++];
269 } while (--size && s->cur_offset < e->len);
270 /* If size is still not zero, we *did* run out early, so continue
271 * left-shifting, to add the appropriate number of padding zeros
272 * on the right.
274 value <<= 8 * size;
277 trace_fw_cfg_read(s, value);
278 return value;
281 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
282 uint64_t value, unsigned size)
284 FWCfgState *s = opaque;
285 unsigned i = size;
287 do {
288 fw_cfg_write(s, value >> (8 * --i));
289 } while (i);
292 static void fw_cfg_dma_transfer(FWCfgState *s)
294 dma_addr_t len;
295 FWCfgDmaAccess dma;
296 int arch;
297 FWCfgEntry *e;
298 int read = 0, write = 0;
299 dma_addr_t dma_addr;
301 /* Reset the address before the next access */
302 dma_addr = s->dma_addr;
303 s->dma_addr = 0;
305 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
306 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
307 FW_CFG_DMA_CTL_ERROR);
308 return;
311 dma.address = be64_to_cpu(dma.address);
312 dma.length = be32_to_cpu(dma.length);
313 dma.control = be32_to_cpu(dma.control);
315 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
316 fw_cfg_select(s, dma.control >> 16);
319 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
320 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
321 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
323 if (dma.control & FW_CFG_DMA_CTL_READ) {
324 read = 1;
325 write = 0;
326 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
327 read = 0;
328 write = 1;
329 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
330 read = 0;
331 write = 0;
332 } else {
333 dma.length = 0;
336 dma.control = 0;
338 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
339 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
340 s->cur_offset >= e->len) {
341 len = dma.length;
343 /* If the access is not a read access, it will be a skip access,
344 * tested before.
346 if (read) {
347 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
348 dma.control |= FW_CFG_DMA_CTL_ERROR;
351 if (write) {
352 dma.control |= FW_CFG_DMA_CTL_ERROR;
354 } else {
355 if (dma.length <= (e->len - s->cur_offset)) {
356 len = dma.length;
357 } else {
358 len = (e->len - s->cur_offset);
361 /* If the access is not a read access, it will be a skip access,
362 * tested before.
364 if (read) {
365 if (dma_memory_write(s->dma_as, dma.address,
366 &e->data[s->cur_offset], len)) {
367 dma.control |= FW_CFG_DMA_CTL_ERROR;
370 if (write) {
371 if (!e->allow_write ||
372 len != dma.length ||
373 dma_memory_read(s->dma_as, dma.address,
374 &e->data[s->cur_offset], len)) {
375 dma.control |= FW_CFG_DMA_CTL_ERROR;
376 } else if (e->write_cb) {
377 e->write_cb(e->callback_opaque, s->cur_offset, len);
381 s->cur_offset += len;
384 dma.address += len;
385 dma.length -= len;
389 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
390 dma.control);
392 trace_fw_cfg_read(s, 0);
395 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
396 unsigned size)
398 /* Return a signature value (and handle various read sizes) */
399 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
402 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
403 uint64_t value, unsigned size)
405 FWCfgState *s = opaque;
407 if (size == 4) {
408 if (addr == 0) {
409 /* FWCfgDmaAccess high address */
410 s->dma_addr = value << 32;
411 } else if (addr == 4) {
412 /* FWCfgDmaAccess low address */
413 s->dma_addr |= value;
414 fw_cfg_dma_transfer(s);
416 } else if (size == 8 && addr == 0) {
417 s->dma_addr = value;
418 fw_cfg_dma_transfer(s);
422 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
423 unsigned size, bool is_write,
424 MemTxAttrs attrs)
426 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
427 (size == 8 && addr == 0));
430 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
431 unsigned size, bool is_write,
432 MemTxAttrs attrs)
434 return addr == 0;
437 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
438 uint64_t value, unsigned size)
440 fw_cfg_select(opaque, (uint16_t)value);
443 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
444 unsigned size, bool is_write,
445 MemTxAttrs attrs)
447 return is_write && size == 2;
450 static void fw_cfg_comb_write(void *opaque, hwaddr addr,
451 uint64_t value, unsigned size)
453 switch (size) {
454 case 1:
455 fw_cfg_write(opaque, (uint8_t)value);
456 break;
457 case 2:
458 fw_cfg_select(opaque, (uint16_t)value);
459 break;
463 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
464 unsigned size, bool is_write,
465 MemTxAttrs attrs)
467 return (size == 1) || (is_write && size == 2);
470 static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
471 .write = fw_cfg_ctl_mem_write,
472 .endianness = DEVICE_BIG_ENDIAN,
473 .valid.accepts = fw_cfg_ctl_mem_valid,
476 static const MemoryRegionOps fw_cfg_data_mem_ops = {
477 .read = fw_cfg_data_read,
478 .write = fw_cfg_data_mem_write,
479 .endianness = DEVICE_BIG_ENDIAN,
480 .valid = {
481 .min_access_size = 1,
482 .max_access_size = 1,
483 .accepts = fw_cfg_data_mem_valid,
487 static const MemoryRegionOps fw_cfg_comb_mem_ops = {
488 .read = fw_cfg_data_read,
489 .write = fw_cfg_comb_write,
490 .endianness = DEVICE_LITTLE_ENDIAN,
491 .valid.accepts = fw_cfg_comb_valid,
494 static const MemoryRegionOps fw_cfg_dma_mem_ops = {
495 .read = fw_cfg_dma_mem_read,
496 .write = fw_cfg_dma_mem_write,
497 .endianness = DEVICE_BIG_ENDIAN,
498 .valid.accepts = fw_cfg_dma_mem_valid,
499 .valid.max_access_size = 8,
500 .impl.max_access_size = 8,
503 static void fw_cfg_reset(DeviceState *d)
505 FWCfgState *s = FW_CFG(d);
507 /* we never register a read callback for FW_CFG_SIGNATURE */
508 fw_cfg_select(s, FW_CFG_SIGNATURE);
511 /* Save restore 32 bit int as uint16_t
512 This is a Big hack, but it is how the old state did it.
513 Or we broke compatibility in the state, or we can't use struct tm
516 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
517 VMStateField *field)
519 uint32_t *v = pv;
520 *v = qemu_get_be16(f);
521 return 0;
524 static int put_unused(QEMUFile *f, void *pv, size_t size, VMStateField *field,
525 QJSON *vmdesc)
527 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
528 fprintf(stderr, "This functions shouldn't be called.\n");
530 return 0;
533 static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
534 .name = "int32_as_uint16",
535 .get = get_uint32_as_uint16,
536 .put = put_unused,
539 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
540 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
543 static bool is_version_1(void *opaque, int version_id)
545 return version_id == 1;
548 bool fw_cfg_dma_enabled(void *opaque)
550 FWCfgState *s = opaque;
552 return s->dma_enabled;
555 static const VMStateDescription vmstate_fw_cfg_dma = {
556 .name = "fw_cfg/dma",
557 .needed = fw_cfg_dma_enabled,
558 .fields = (VMStateField[]) {
559 VMSTATE_UINT64(dma_addr, FWCfgState),
560 VMSTATE_END_OF_LIST()
564 static const VMStateDescription vmstate_fw_cfg = {
565 .name = "fw_cfg",
566 .version_id = 2,
567 .minimum_version_id = 1,
568 .fields = (VMStateField[]) {
569 VMSTATE_UINT16(cur_entry, FWCfgState),
570 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
571 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
572 VMSTATE_END_OF_LIST()
574 .subsections = (const VMStateDescription*[]) {
575 &vmstate_fw_cfg_dma,
576 NULL,
580 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key,
581 FWCfgCallback select_cb,
582 FWCfgWriteCallback write_cb,
583 void *callback_opaque,
584 void *data, size_t len,
585 bool read_only)
587 int arch = !!(key & FW_CFG_ARCH_LOCAL);
589 key &= FW_CFG_ENTRY_MASK;
591 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
592 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
594 s->entries[arch][key].data = data;
595 s->entries[arch][key].len = (uint32_t)len;
596 s->entries[arch][key].select_cb = select_cb;
597 s->entries[arch][key].write_cb = write_cb;
598 s->entries[arch][key].callback_opaque = callback_opaque;
599 s->entries[arch][key].allow_write = !read_only;
602 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
603 void *data, size_t len)
605 void *ptr;
606 int arch = !!(key & FW_CFG_ARCH_LOCAL);
608 key &= FW_CFG_ENTRY_MASK;
610 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
612 /* return the old data to the function caller, avoid memory leak */
613 ptr = s->entries[arch][key].data;
614 s->entries[arch][key].data = data;
615 s->entries[arch][key].len = len;
616 s->entries[arch][key].callback_opaque = NULL;
617 s->entries[arch][key].allow_write = false;
619 return ptr;
622 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
624 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true);
627 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
629 size_t sz = strlen(value) + 1;
631 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
634 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
636 uint16_t *copy;
638 copy = g_malloc(sizeof(value));
639 *copy = cpu_to_le16(value);
640 fw_cfg_add_bytes(s, key, copy, sizeof(value));
643 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
645 uint16_t *copy, *old;
647 copy = g_malloc(sizeof(value));
648 *copy = cpu_to_le16(value);
649 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
650 g_free(old);
653 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
655 uint32_t *copy;
657 copy = g_malloc(sizeof(value));
658 *copy = cpu_to_le32(value);
659 fw_cfg_add_bytes(s, key, copy, sizeof(value));
662 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
664 uint64_t *copy;
666 copy = g_malloc(sizeof(value));
667 *copy = cpu_to_le64(value);
668 fw_cfg_add_bytes(s, key, copy, sizeof(value));
671 void fw_cfg_set_order_override(FWCfgState *s, int order)
673 assert(s->fw_cfg_order_override == 0);
674 s->fw_cfg_order_override = order;
677 void fw_cfg_reset_order_override(FWCfgState *s)
679 assert(s->fw_cfg_order_override != 0);
680 s->fw_cfg_order_override = 0;
684 * This is the legacy order list. For legacy systems, files are in
685 * the fw_cfg in the order defined below, by the "order" value. Note
686 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
687 * specific area, but there may be more than one and they occur in the
688 * order that the user specifies them on the command line. Those are
689 * handled in a special manner, using the order override above.
691 * For non-legacy, the files are sorted by filename to avoid this kind
692 * of complexity in the future.
694 * This is only for x86, other arches don't implement versioning so
695 * they won't set legacy mode.
697 static struct {
698 const char *name;
699 int order;
700 } fw_cfg_order[] = {
701 { "etc/boot-menu-wait", 10 },
702 { "bootsplash.jpg", 11 },
703 { "bootsplash.bmp", 12 },
704 { "etc/boot-fail-wait", 15 },
705 { "etc/smbios/smbios-tables", 20 },
706 { "etc/smbios/smbios-anchor", 30 },
707 { "etc/e820", 40 },
708 { "etc/reserved-memory-end", 50 },
709 { "genroms/kvmvapic.bin", 55 },
710 { "genroms/linuxboot.bin", 60 },
711 { }, /* VGA ROMs from pc_vga_init come here, 70. */
712 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
713 { "etc/system-states", 90 },
714 { }, /* User ROMs come here, 100. */
715 { }, /* Device FW comes here, 110. */
716 { "etc/extra-pci-roots", 120 },
717 { "etc/acpi/tables", 130 },
718 { "etc/table-loader", 140 },
719 { "etc/tpm/log", 150 },
720 { "etc/acpi/rsdp", 160 },
721 { "bootorder", 170 },
723 #define FW_CFG_ORDER_OVERRIDE_LAST 200
726 static int get_fw_cfg_order(FWCfgState *s, const char *name)
728 int i;
730 if (s->fw_cfg_order_override > 0) {
731 return s->fw_cfg_order_override;
734 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
735 if (fw_cfg_order[i].name == NULL) {
736 continue;
739 if (strcmp(name, fw_cfg_order[i].name) == 0) {
740 return fw_cfg_order[i].order;
744 /* Stick unknown stuff at the end. */
745 warn_report("Unknown firmware file in legacy mode: %s", name);
746 return FW_CFG_ORDER_OVERRIDE_LAST;
749 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
750 FWCfgCallback select_cb,
751 FWCfgWriteCallback write_cb,
752 void *callback_opaque,
753 void *data, size_t len, bool read_only)
755 int i, index, count;
756 size_t dsize;
757 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
758 int order = 0;
760 if (!s->files) {
761 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
762 s->files = g_malloc0(dsize);
763 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
766 count = be32_to_cpu(s->files->count);
767 assert(count < fw_cfg_file_slots(s));
769 /* Find the insertion point. */
770 if (mc->legacy_fw_cfg_order) {
772 * Sort by order. For files with the same order, we keep them
773 * in the sequence in which they were added.
775 order = get_fw_cfg_order(s, filename);
776 for (index = count;
777 index > 0 && order < s->entry_order[index - 1];
778 index--);
779 } else {
780 /* Sort by file name. */
781 for (index = count;
782 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
783 index--);
787 * Move all the entries from the index point and after down one
788 * to create a slot for the new entry. Because calculations are
789 * being done with the index, make it so that "i" is the current
790 * index and "i - 1" is the one being copied from, thus the
791 * unusual start and end in the for statement.
793 for (i = count; i > index; i--) {
794 s->files->f[i] = s->files->f[i - 1];
795 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
796 s->entries[0][FW_CFG_FILE_FIRST + i] =
797 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
798 s->entry_order[i] = s->entry_order[i - 1];
801 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
802 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
804 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
805 for (i = 0; i <= count; i++) {
806 if (i != index &&
807 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
808 error_report("duplicate fw_cfg file name: %s",
809 s->files->f[index].name);
810 exit(1);
814 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index,
815 select_cb, write_cb,
816 callback_opaque, data, len,
817 read_only);
819 s->files->f[index].size = cpu_to_be32(len);
820 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
821 s->entry_order[index] = order;
822 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
824 s->files->count = cpu_to_be32(count+1);
827 void fw_cfg_add_file(FWCfgState *s, const char *filename,
828 void *data, size_t len)
830 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
833 void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
834 void *data, size_t len)
836 int i, index;
837 void *ptr = NULL;
839 assert(s->files);
841 index = be32_to_cpu(s->files->count);
843 for (i = 0; i < index; i++) {
844 if (strcmp(filename, s->files->f[i].name) == 0) {
845 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
846 data, len);
847 s->files->f[i].size = cpu_to_be32(len);
848 return ptr;
852 assert(index < fw_cfg_file_slots(s));
854 /* add new one */
855 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
856 return NULL;
859 static void fw_cfg_machine_reset(void *opaque)
861 void *ptr;
862 size_t len;
863 FWCfgState *s = opaque;
864 char *bootindex = get_boot_devices_list(&len, false);
866 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len);
867 g_free(ptr);
870 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
872 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
873 qemu_register_reset(fw_cfg_machine_reset, s);
878 static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
880 FWCfgState *s = FW_CFG(dev);
881 MachineState *machine = MACHINE(qdev_get_machine());
882 uint32_t version = FW_CFG_VERSION;
884 if (!fw_cfg_find()) {
885 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
886 return;
889 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
890 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
891 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
892 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
893 fw_cfg_bootsplash(s);
894 fw_cfg_reboot(s);
896 if (s->dma_enabled) {
897 version |= FW_CFG_VERSION_DMA;
900 fw_cfg_add_i32(s, FW_CFG_ID, version);
902 s->machine_ready.notify = fw_cfg_machine_ready;
903 qemu_add_machine_init_done_notifier(&s->machine_ready);
906 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
907 AddressSpace *dma_as)
909 DeviceState *dev;
910 SysBusDevice *sbd;
911 FWCfgIoState *ios;
912 FWCfgState *s;
913 bool dma_requested = dma_iobase && dma_as;
915 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
916 if (!dma_requested) {
917 qdev_prop_set_bit(dev, "dma_enabled", false);
920 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
921 OBJECT(dev), NULL);
922 qdev_init_nofail(dev);
924 sbd = SYS_BUS_DEVICE(dev);
925 ios = FW_CFG_IO(dev);
926 sysbus_add_io(sbd, iobase, &ios->comb_iomem);
928 s = FW_CFG(dev);
930 if (s->dma_enabled) {
931 /* 64 bits for the address field */
932 s->dma_as = dma_as;
933 s->dma_addr = 0;
934 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem);
937 return s;
940 FWCfgState *fw_cfg_init_io(uint32_t iobase)
942 return fw_cfg_init_io_dma(iobase, 0, NULL);
945 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
946 hwaddr data_addr, uint32_t data_width,
947 hwaddr dma_addr, AddressSpace *dma_as)
949 DeviceState *dev;
950 SysBusDevice *sbd;
951 FWCfgState *s;
952 bool dma_requested = dma_addr && dma_as;
954 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
955 qdev_prop_set_uint32(dev, "data_width", data_width);
956 if (!dma_requested) {
957 qdev_prop_set_bit(dev, "dma_enabled", false);
960 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
961 OBJECT(dev), NULL);
962 qdev_init_nofail(dev);
964 sbd = SYS_BUS_DEVICE(dev);
965 sysbus_mmio_map(sbd, 0, ctl_addr);
966 sysbus_mmio_map(sbd, 1, data_addr);
968 s = FW_CFG(dev);
970 if (s->dma_enabled) {
971 s->dma_as = dma_as;
972 s->dma_addr = 0;
973 sysbus_mmio_map(sbd, 2, dma_addr);
976 return s;
979 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
981 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
982 fw_cfg_data_mem_ops.valid.max_access_size,
983 0, NULL);
987 FWCfgState *fw_cfg_find(void)
989 /* Returns NULL unless there is exactly one fw_cfg device */
990 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
994 static void fw_cfg_class_init(ObjectClass *klass, void *data)
996 DeviceClass *dc = DEVICE_CLASS(klass);
998 dc->reset = fw_cfg_reset;
999 dc->vmsd = &vmstate_fw_cfg;
1002 static const TypeInfo fw_cfg_info = {
1003 .name = TYPE_FW_CFG,
1004 .parent = TYPE_SYS_BUS_DEVICE,
1005 .abstract = true,
1006 .instance_size = sizeof(FWCfgState),
1007 .class_init = fw_cfg_class_init,
1010 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1012 uint16_t file_slots_max;
1014 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1015 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1016 FW_CFG_FILE_SLOTS_MIN);
1017 return;
1020 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1021 * that we permit. The actual (exclusive) value coming from the
1022 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1023 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1024 if (fw_cfg_file_slots(s) > file_slots_max) {
1025 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1026 file_slots_max);
1027 return;
1030 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1031 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1032 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1035 static Property fw_cfg_io_properties[] = {
1036 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1037 true),
1038 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1039 FW_CFG_FILE_SLOTS_DFLT),
1040 DEFINE_PROP_END_OF_LIST(),
1043 static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1045 FWCfgIoState *s = FW_CFG_IO(dev);
1046 Error *local_err = NULL;
1048 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1049 if (local_err) {
1050 error_propagate(errp, local_err);
1051 return;
1054 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1055 * with half of the 16-bit control register. Hence, the total size
1056 * of the i/o region used is FW_CFG_CTL_SIZE */
1057 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1058 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1060 if (FW_CFG(s)->dma_enabled) {
1061 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1062 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1063 sizeof(dma_addr_t));
1066 fw_cfg_common_realize(dev, errp);
1069 static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1071 DeviceClass *dc = DEVICE_CLASS(klass);
1073 dc->realize = fw_cfg_io_realize;
1074 dc->props = fw_cfg_io_properties;
1077 static const TypeInfo fw_cfg_io_info = {
1078 .name = TYPE_FW_CFG_IO,
1079 .parent = TYPE_FW_CFG,
1080 .instance_size = sizeof(FWCfgIoState),
1081 .class_init = fw_cfg_io_class_init,
1085 static Property fw_cfg_mem_properties[] = {
1086 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1087 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1088 true),
1089 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1090 FW_CFG_FILE_SLOTS_DFLT),
1091 DEFINE_PROP_END_OF_LIST(),
1094 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1096 FWCfgMemState *s = FW_CFG_MEM(dev);
1097 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1098 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1099 Error *local_err = NULL;
1101 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1102 if (local_err) {
1103 error_propagate(errp, local_err);
1104 return;
1107 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1108 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1109 sysbus_init_mmio(sbd, &s->ctl_iomem);
1111 if (s->data_width > data_ops->valid.max_access_size) {
1112 /* memberwise copy because the "old_mmio" member is const */
1113 s->wide_data_ops.read = data_ops->read;
1114 s->wide_data_ops.write = data_ops->write;
1115 s->wide_data_ops.endianness = data_ops->endianness;
1116 s->wide_data_ops.valid = data_ops->valid;
1117 s->wide_data_ops.impl = data_ops->impl;
1119 s->wide_data_ops.valid.max_access_size = s->data_width;
1120 s->wide_data_ops.impl.max_access_size = s->data_width;
1121 data_ops = &s->wide_data_ops;
1123 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1124 "fwcfg.data", data_ops->valid.max_access_size);
1125 sysbus_init_mmio(sbd, &s->data_iomem);
1127 if (FW_CFG(s)->dma_enabled) {
1128 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1129 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1130 sizeof(dma_addr_t));
1131 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1134 fw_cfg_common_realize(dev, errp);
1137 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1139 DeviceClass *dc = DEVICE_CLASS(klass);
1141 dc->realize = fw_cfg_mem_realize;
1142 dc->props = fw_cfg_mem_properties;
1145 static const TypeInfo fw_cfg_mem_info = {
1146 .name = TYPE_FW_CFG_MEM,
1147 .parent = TYPE_FW_CFG,
1148 .instance_size = sizeof(FWCfgMemState),
1149 .class_init = fw_cfg_mem_class_init,
1153 static void fw_cfg_register_types(void)
1155 type_register_static(&fw_cfg_info);
1156 type_register_static(&fw_cfg_io_info);
1157 type_register_static(&fw_cfg_mem_info);
1160 type_init(fw_cfg_register_types)