hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/error-report.h"
  25 #include "monitor/monitor.h"
  26 #include "hw/hw.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/i386/apic.h"
  29 #include "hw/i386/ioapic.h"
  30 #include "hw/i386/ioapic_internal.h"
  31 #include "hw/pci/msi.h"
  32 #include "sysemu/kvm.h"
  33 #include "hw/i386/apic-msidef.h"
  34 #include "hw/i386/x86-iommu.h"
  35 #include "trace.h"
  36
  37 #define APIC_DELIVERY_MODE_SHIFT 8
  38 #define APIC_POLARITY_SHIFT 14
  39 #define APIC_TRIG_MODE_SHIFT 15
  40
  41 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  42
  43 /* global variable from ioapic_common.c */
  44 extern int ioapic_no;
  45
  46 struct ioapic_entry_info {
  47     /* fields parsed from IOAPIC entries */
  48     uint8_t masked;
  49     uint8_t trig_mode;
  50     uint16_t dest_idx;
  51     uint8_t dest_mode;
  52     uint8_t delivery_mode;
  53     uint8_t vector;
  54
  55     /* MSI message generated from above parsed fields */
  56     uint32_t addr;
  57     uint32_t data;
  58 };
  59
  60 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
  61 {
  62     memset(info, 0, sizeof(*info));
  63     info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
  64     info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
  65     /*
  66      * By default, this would be dest_id[8] + reserved[8]. When IR
  67      * is enabled, this would be interrupt_index[15] +
  68      * interrupt_format[1]. This field never means anything, but
  69      * only used to generate corresponding MSI.
  70      */
  71     info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
  72     info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  73     info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
  74         & IOAPIC_DM_MASK;
  75     if (info->delivery_mode == IOAPIC_DM_EXTINT) {
  76         info->vector = pic_read_irq(isa_pic);
  77     } else {
  78         info->vector = entry & IOAPIC_VECTOR_MASK;
  79     }
  80
  81     info->addr = APIC_DEFAULT_ADDRESS | \
  82         (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
  83         (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
  84     info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
  85         (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
  86         (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
  87 }
  88
  89 static void ioapic_service(IOAPICCommonState *s)
  90 {
  91     AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
  92     struct ioapic_entry_info info;
  93     uint8_t i;
  94     uint32_t mask;
  95     uint64_t entry;
  96
  97     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  98         mask = 1 << i;
  99         if (s->irr & mask) {
 100             int coalesce = 0;
 101
 102             entry = s->ioredtbl[i];
 103             ioapic_entry_parse(entry, &info);
 104             if (!info.masked) {
 105                 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 106                     s->irr &= ~mask;
 107                 } else {
 108                     coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
 109                     trace_ioapic_set_remote_irr(i);
 110                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 111                 }
 112
 113                 if (coalesce) {
 114                     /* We are level triggered interrupts, and the
 115                      * guest should be still working on previous one,
 116                      * so skip it. */
 117                     continue;
 118                 }
 119
 120 #ifdef CONFIG_KVM
 121                 if (kvm_irqchip_is_split()) {
 122                     if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 123                         kvm_set_irq(kvm_state, i, 1);
 124                         kvm_set_irq(kvm_state, i, 0);
 125                     } else {
 126                         kvm_set_irq(kvm_state, i, 1);
 127                     }
 128                     continue;
 129                 }
 130 #endif
 131
 132                 /* No matter whether IR is enabled, we translate
 133                  * the IOAPIC message into a MSI one, and its
 134                  * address space will decide whether we need a
 135                  * translation. */
 136                 stl_le_phys(ioapic_as, info.addr, info.data);
 137             }
 138         }
 139     }
 140 }
 141
 142 static void ioapic_set_irq(void *opaque, int vector, int level)
 143 {
 144     IOAPICCommonState *s = opaque;
 145
 146     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 147      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 148      * the cleanest way of doing it but it should work. */
 149
 150     trace_ioapic_set_irq(vector, level);
 151     if (vector == 0) {
 152         vector = 2;
 153     }
 154     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 155         uint32_t mask = 1 << vector;
 156         uint64_t entry = s->ioredtbl[vector];
 157
 158         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 159             IOAPIC_TRIGGER_LEVEL) {
 160             /* level triggered */
 161             if (level) {
 162                 s->irr |= mask;
 163                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 164                     ioapic_service(s);
 165                 }
 166             } else {
 167                 s->irr &= ~mask;
 168             }
 169         } else {
 170             /* According to the 82093AA manual, we must ignore edge requests
 171              * if the input pin is masked. */
 172             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 173                 s->irr |= mask;
 174                 ioapic_service(s);
 175             }
 176         }
 177     }
 178 }
 179
 180 static void ioapic_update_kvm_routes(IOAPICCommonState *s)
 181 {
 182 #ifdef CONFIG_KVM
 183     int i;
 184
 185     if (kvm_irqchip_is_split()) {
 186         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 187             MSIMessage msg;
 188             struct ioapic_entry_info info;
 189             ioapic_entry_parse(s->ioredtbl[i], &info);
 190             msg.address = info.addr;
 191             msg.data = info.data;
 192             kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
 193         }
 194         kvm_irqchip_commit_routes(kvm_state);
 195     }
 196 #endif
 197 }
 198
 199 #ifdef CONFIG_KVM
 200 static void ioapic_iec_notifier(void *private, bool global,
 201                                 uint32_t index, uint32_t mask)
 202 {
 203     IOAPICCommonState *s = (IOAPICCommonState *)private;
 204     /* For simplicity, we just update all the routes */
 205     ioapic_update_kvm_routes(s);
 206 }
 207 #endif
 208
 209 void ioapic_eoi_broadcast(int vector)
 210 {
 211     IOAPICCommonState *s;
 212     uint64_t entry;
 213     int i, n;
 214
 215     trace_ioapic_eoi_broadcast(vector);
 216
 217     for (i = 0; i < MAX_IOAPICS; i++) {
 218         s = ioapics[i];
 219         if (!s) {
 220             continue;
 221         }
 222         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 223             entry = s->ioredtbl[n];
 224             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 225                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 226                 trace_ioapic_clear_remote_irr(n, vector);
 227                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 228                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 229                     ioapic_service(s);
 230                 }
 231             }
 232         }
 233     }
 234 }
 235
 236 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 237 {
 238     int i;
 239
 240     for (i = 0; i < MAX_IOAPICS; i++) {
 241         if (ioapics[i] != 0) {
 242             ioapic_print_redtbl(mon, ioapics[i]);
 243         }
 244     }
 245 }
 246
 247 static uint64_t
 248 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 249 {
 250     IOAPICCommonState *s = opaque;
 251     int index;
 252     uint32_t val = 0;
 253
 254     addr &= 0xff;
 255
 256     switch (addr) {
 257     case IOAPIC_IOREGSEL:
 258         val = s->ioregsel;
 259         break;
 260     case IOAPIC_IOWIN:
 261         if (size != 4) {
 262             break;
 263         }
 264         switch (s->ioregsel) {
 265         case IOAPIC_REG_ID:
 266         case IOAPIC_REG_ARB:
 267             val = s->id << IOAPIC_ID_SHIFT;
 268             break;
 269         case IOAPIC_REG_VER:
 270             val = s->version |
 271                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 272             break;
 273         default:
 274             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 275             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 276                 if (s->ioregsel & 1) {
 277                     val = s->ioredtbl[index] >> 32;
 278                 } else {
 279                     val = s->ioredtbl[index] & 0xffffffff;
 280                 }
 281             }
 282         }
 283         break;
 284     }
 285
 286     trace_ioapic_mem_read(addr, s->ioregsel, size, val);
 287
 288     return val;
 289 }
 290
 291 /*
 292  * This is to satisfy the hack in Linux kernel. One hack of it is to
 293  * simulate clearing the Remote IRR bit of IOAPIC entry using the
 294  * following:
 295  *
 296  * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
 297  * Otherwise, we simulate the EOI message manually by changing the trigger
 298  * mode to edge and then back to level, with RTE being masked during
 299  * this."
 300  *
 301  * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
 302  *
 303  * This is based on the assumption that, Remote IRR bit will be
 304  * cleared by IOAPIC hardware when configured as edge-triggered
 305  * interrupts.
 306  *
 307  * Without this, level-triggered interrupts in IR mode might fail to
 308  * work correctly.
 309  */
 310 static inline void
 311 ioapic_fix_edge_remote_irr(uint64_t *entry)
 312 {
 313     if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
 314         /* Edge-triggered interrupts, make sure remote IRR is zero */
 315         *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
 316     }
 317 }
 318
 319 static void
 320 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 321                  unsigned int size)
 322 {
 323     IOAPICCommonState *s = opaque;
 324     int index;
 325
 326     addr &= 0xff;
 327     trace_ioapic_mem_write(addr, s->ioregsel, size, val);
 328
 329     switch (addr) {
 330     case IOAPIC_IOREGSEL:
 331         s->ioregsel = val;
 332         break;
 333     case IOAPIC_IOWIN:
 334         if (size != 4) {
 335             break;
 336         }
 337         switch (s->ioregsel) {
 338         case IOAPIC_REG_ID:
 339             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 340             break;
 341         case IOAPIC_REG_VER:
 342         case IOAPIC_REG_ARB:
 343             break;
 344         default:
 345             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 346             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 347                 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
 348                 if (s->ioregsel & 1) {
 349                     s->ioredtbl[index] &= 0xffffffff;
 350                     s->ioredtbl[index] |= (uint64_t)val << 32;
 351                 } else {
 352                     s->ioredtbl[index] &= ~0xffffffffULL;
 353                     s->ioredtbl[index] |= val;
 354                 }
 355                 /* restore RO bits */
 356                 s->ioredtbl[index] &= IOAPIC_RW_BITS;
 357                 s->ioredtbl[index] |= ro_bits;
 358                 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
 359                 ioapic_service(s);
 360             }
 361         }
 362         break;
 363     case IOAPIC_EOI:
 364         /* Explicit EOI is only supported for IOAPIC version 0x20 */
 365         if (size != 4 || s->version != 0x20) {
 366             break;
 367         }
 368         ioapic_eoi_broadcast(val);
 369         break;
 370     }
 371
 372     ioapic_update_kvm_routes(s);
 373 }
 374
 375 static const MemoryRegionOps ioapic_io_ops = {
 376     .read = ioapic_mem_read,
 377     .write = ioapic_mem_write,
 378     .endianness = DEVICE_NATIVE_ENDIAN,
 379 };
 380
 381 static void ioapic_machine_done_notify(Notifier *notifier, void *data)
 382 {
 383 #ifdef CONFIG_KVM
 384     IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
 385                                         machine_done);
 386
 387     if (kvm_irqchip_is_split()) {
 388         X86IOMMUState *iommu = x86_iommu_get_default();
 389         if (iommu) {
 390             /* Register this IOAPIC with IOMMU IEC notifier, so that
 391              * when there are IR invalidates, we can be notified to
 392              * update kernel IR cache. */
 393             x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
 394         }
 395     }
 396 #endif
 397 }
 398
 399 #define IOAPIC_VER_DEF 0x20
 400
 401 static void ioapic_realize(DeviceState *dev, Error **errp)
 402 {
 403     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 404
 405     if (s->version != 0x11 && s->version != 0x20) {
 406         error_report("IOAPIC only supports version 0x11 or 0x20 "
 407                      "(default: 0x%x).", IOAPIC_VER_DEF);
 408         exit(1);
 409     }
 410
 411     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 412                           "ioapic", 0x1000);
 413
 414     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 415
 416     ioapics[ioapic_no] = s;
 417     s->machine_done.notify = ioapic_machine_done_notify;
 418     qemu_add_machine_init_done_notifier(&s->machine_done);
 419 }
 420
 421 static Property ioapic_properties[] = {
 422     DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF),
 423     DEFINE_PROP_END_OF_LIST(),
 424 };
 425
 426 static void ioapic_class_init(ObjectClass *klass, void *data)
 427 {
 428     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 429     DeviceClass *dc = DEVICE_CLASS(klass);
 430
 431     k->realize = ioapic_realize;
 432     /*
 433      * If APIC is in kernel, we need to update the kernel cache after
 434      * migration, otherwise first 24 gsi routes will be invalid.
 435      */
 436     k->post_load = ioapic_update_kvm_routes;
 437     dc->reset = ioapic_reset_common;
 438     dc->props = ioapic_properties;
 439 }
 440
 441 static const TypeInfo ioapic_info = {
 442     .name          = "ioapic",
 443     .parent        = TYPE_IOAPIC_COMMON,
 444     .instance_size = sizeof(IOAPICCommonState),
 445     .class_init    = ioapic_class_init,
 446 };
 447
 448 static void ioapic_register_types(void)
 449 {
 450     type_register_static(&ioapic_info);
 451 }
 452
 453 type_init(ioapic_register_types)