hw/intc/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "qemu/thread.h"
  23 #include "hw/i386/apic_internal.h"
  24 #include "hw/i386/apic.h"
  25 #include "hw/i386/ioapic.h"
  26 #include "hw/pci/msi.h"
  27 #include "qemu/host-utils.h"
  28 #include "trace.h"
  29 #include "hw/i386/pc.h"
  30 #include "hw/i386/apic-msidef.h"
  31 #include "qapi/error.h"
  32
  33 #define MAX_APICS 255
  34 #define MAX_APIC_WORDS 8
  35
  36 #define SYNC_FROM_VAPIC                 0x1
  37 #define SYNC_TO_VAPIC                   0x2
  38 #define SYNC_ISR_IRR_TO_VAPIC           0x4
  39
  40 static APICCommonState *local_apics[MAX_APICS + 1];
  41
  42 #define TYPE_APIC "apic"
  43 #define APIC(obj) \
  44     OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC)
  45
  46 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
  47 static void apic_update_irq(APICCommonState *s);
  48 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  49                                       uint8_t dest, uint8_t dest_mode);
  50
  51 /* Find first bit starting from msb */
  52 static int apic_fls_bit(uint32_t value)
  53 {
  54     return 31 - clz32(value);
  55 }
  56
  57 /* Find first bit starting from lsb */
  58 static int apic_ffs_bit(uint32_t value)
  59 {
  60     return ctz32(value);
  61 }
  62
  63 static inline void apic_reset_bit(uint32_t *tab, int index)
  64 {
  65     int i, mask;
  66     i = index >> 5;
  67     mask = 1 << (index & 0x1f);
  68     tab[i] &= ~mask;
  69 }
  70
  71 /* return -1 if no bit is set */
  72 static int get_highest_priority_int(uint32_t *tab)
  73 {
  74     int i;
  75     for (i = 7; i >= 0; i--) {
  76         if (tab[i] != 0) {
  77             return i * 32 + apic_fls_bit(tab[i]);
  78         }
  79     }
  80     return -1;
  81 }
  82
  83 static void apic_sync_vapic(APICCommonState *s, int sync_type)
  84 {
  85     VAPICState vapic_state;
  86     size_t length;
  87     off_t start;
  88     int vector;
  89
  90     if (!s->vapic_paddr) {
  91         return;
  92     }
  93     if (sync_type & SYNC_FROM_VAPIC) {
  94         cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
  95                                  sizeof(vapic_state));
  96         s->tpr = vapic_state.tpr;
  97     }
  98     if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
  99         start = offsetof(VAPICState, isr);
 100         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
 101
 102         if (sync_type & SYNC_TO_VAPIC) {
 103             assert(qemu_cpu_is_self(CPU(s->cpu)));
 104
 105             vapic_state.tpr = s->tpr;
 106             vapic_state.enabled = 1;
 107             start = 0;
 108             length = sizeof(VAPICState);
 109         }
 110
 111         vector = get_highest_priority_int(s->isr);
 112         if (vector < 0) {
 113             vector = 0;
 114         }
 115         vapic_state.isr = vector & 0xf0;
 116
 117         vapic_state.zero = 0;
 118
 119         vector = get_highest_priority_int(s->irr);
 120         if (vector < 0) {
 121             vector = 0;
 122         }
 123         vapic_state.irr = vector & 0xff;
 124
 125         cpu_physical_memory_write_rom(&address_space_memory,
 126                                       s->vapic_paddr + start,
 127                                       ((void *)&vapic_state) + start, length);
 128     }
 129 }
 130
 131 static void apic_vapic_base_update(APICCommonState *s)
 132 {
 133     apic_sync_vapic(s, SYNC_TO_VAPIC);
 134 }
 135
 136 static void apic_local_deliver(APICCommonState *s, int vector)
 137 {
 138     uint32_t lvt = s->lvt[vector];
 139     int trigger_mode;
 140
 141     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 142
 143     if (lvt & APIC_LVT_MASKED)
 144         return;
 145
 146     switch ((lvt >> 8) & 7) {
 147     case APIC_DM_SMI:
 148         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
 149         break;
 150
 151     case APIC_DM_NMI:
 152         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
 153         break;
 154
 155     case APIC_DM_EXTINT:
 156         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
 157         break;
 158
 159     case APIC_DM_FIXED:
 160         trigger_mode = APIC_TRIGGER_EDGE;
 161         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 162             (lvt & APIC_LVT_LEVEL_TRIGGER))
 163             trigger_mode = APIC_TRIGGER_LEVEL;
 164         apic_set_irq(s, lvt & 0xff, trigger_mode);
 165     }
 166 }
 167
 168 void apic_deliver_pic_intr(DeviceState *dev, int level)
 169 {
 170     APICCommonState *s = APIC(dev);
 171
 172     if (level) {
 173         apic_local_deliver(s, APIC_LVT_LINT0);
 174     } else {
 175         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 176
 177         switch ((lvt >> 8) & 7) {
 178         case APIC_DM_FIXED:
 179             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 180                 break;
 181             apic_reset_bit(s->irr, lvt & 0xff);
 182             /* fall through */
 183         case APIC_DM_EXTINT:
 184             apic_update_irq(s);
 185             break;
 186         }
 187     }
 188 }
 189
 190 static void apic_external_nmi(APICCommonState *s)
 191 {
 192     apic_local_deliver(s, APIC_LVT_LINT1);
 193 }
 194
 195 #define foreach_apic(apic, deliver_bitmask, code) \
 196 {\
 197     int __i, __j;\
 198     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 199         uint32_t __mask = deliver_bitmask[__i];\
 200         if (__mask) {\
 201             for(__j = 0; __j < 32; __j++) {\
 202                 if (__mask & (1U << __j)) {\
 203                     apic = local_apics[__i * 32 + __j];\
 204                     if (apic) {\
 205                         code;\
 206                     }\
 207                 }\
 208             }\
 209         }\
 210     }\
 211 }
 212
 213 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 214                              uint8_t delivery_mode, uint8_t vector_num,
 215                              uint8_t trigger_mode)
 216 {
 217     APICCommonState *apic_iter;
 218
 219     switch (delivery_mode) {
 220         case APIC_DM_LOWPRI:
 221             /* XXX: search for focus processor, arbitration */
 222             {
 223                 int i, d;
 224                 d = -1;
 225                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 226                     if (deliver_bitmask[i]) {
 227                         d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
 228                         break;
 229                     }
 230                 }
 231                 if (d >= 0) {
 232                     apic_iter = local_apics[d];
 233                     if (apic_iter) {
 234                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 235                     }
 236                 }
 237             }
 238             return;
 239
 240         case APIC_DM_FIXED:
 241             break;
 242
 243         case APIC_DM_SMI:
 244             foreach_apic(apic_iter, deliver_bitmask,
 245                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
 246             );
 247             return;
 248
 249         case APIC_DM_NMI:
 250             foreach_apic(apic_iter, deliver_bitmask,
 251                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
 252             );
 253             return;
 254
 255         case APIC_DM_INIT:
 256             /* normal INIT IPI sent to processors */
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                          cpu_interrupt(CPU(apic_iter->cpu),
 259                                        CPU_INTERRUPT_INIT)
 260             );
 261             return;
 262
 263         case APIC_DM_EXTINT:
 264             /* handled in I/O APIC code */
 265             break;
 266
 267         default:
 268             return;
 269     }
 270
 271     foreach_apic(apic_iter, deliver_bitmask,
 272                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 273 }
 274
 275 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 276                       uint8_t vector_num, uint8_t trigger_mode)
 277 {
 278     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 279
 280     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 281                            trigger_mode);
 282
 283     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 284     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 285 }
 286
 287 static void apic_set_base(APICCommonState *s, uint64_t val)
 288 {
 289     s->apicbase = (val & 0xfffff000) |
 290         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 291     /* if disabled, cannot be enabled again */
 292     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 293         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 294         cpu_clear_apic_feature(&s->cpu->env);
 295         s->spurious_vec &= ~APIC_SV_ENABLE;
 296     }
 297 }
 298
 299 static void apic_set_tpr(APICCommonState *s, uint8_t val)
 300 {
 301     /* Updates from cr8 are ignored while the VAPIC is active */
 302     if (!s->vapic_paddr) {
 303         s->tpr = val << 4;
 304         apic_update_irq(s);
 305     }
 306 }
 307
 308 int apic_get_highest_priority_irr(DeviceState *dev)
 309 {
 310     APICCommonState *s;
 311
 312     if (!dev) {
 313         /* no interrupts */
 314         return -1;
 315     }
 316     s = APIC_COMMON(dev);
 317     return get_highest_priority_int(s->irr);
 318 }
 319
 320 static uint8_t apic_get_tpr(APICCommonState *s)
 321 {
 322     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 323     return s->tpr >> 4;
 324 }
 325
 326 int apic_get_ppr(APICCommonState *s)
 327 {
 328     int tpr, isrv, ppr;
 329
 330     tpr = (s->tpr >> 4);
 331     isrv = get_highest_priority_int(s->isr);
 332     if (isrv < 0)
 333         isrv = 0;
 334     isrv >>= 4;
 335     if (tpr >= isrv)
 336         ppr = s->tpr;
 337     else
 338         ppr = isrv << 4;
 339     return ppr;
 340 }
 341
 342 static int apic_get_arb_pri(APICCommonState *s)
 343 {
 344     /* XXX: arbitration */
 345     return 0;
 346 }
 347
 348
 349 /*
 350  * <0 - low prio interrupt,
 351  * 0  - no interrupt,
 352  * >0 - interrupt number
 353  */
 354 static int apic_irq_pending(APICCommonState *s)
 355 {
 356     int irrv, ppr;
 357
 358     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 359         return 0;
 360     }
 361
 362     irrv = get_highest_priority_int(s->irr);
 363     if (irrv < 0) {
 364         return 0;
 365     }
 366     ppr = apic_get_ppr(s);
 367     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 368         return -1;
 369     }
 370
 371     return irrv;
 372 }
 373
 374 /* signal the CPU if an irq is pending */
 375 static void apic_update_irq(APICCommonState *s)
 376 {
 377     CPUState *cpu;
 378     DeviceState *dev = (DeviceState *)s;
 379
 380     cpu = CPU(s->cpu);
 381     if (!qemu_cpu_is_self(cpu)) {
 382         cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
 383     } else if (apic_irq_pending(s) > 0) {
 384         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
 385     } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 386         cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
 387     }
 388 }
 389
 390 void apic_poll_irq(DeviceState *dev)
 391 {
 392     APICCommonState *s = APIC(dev);
 393
 394     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 395     apic_update_irq(s);
 396 }
 397
 398 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
 399 {
 400     apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
 401
 402     apic_set_bit(s->irr, vector_num);
 403     if (trigger_mode)
 404         apic_set_bit(s->tmr, vector_num);
 405     else
 406         apic_reset_bit(s->tmr, vector_num);
 407     if (s->vapic_paddr) {
 408         apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
 409         /*
 410          * The vcpu thread needs to see the new IRR before we pull its current
 411          * TPR value. That way, if we miss a lowering of the TRP, the guest
 412          * has the chance to notice the new IRR and poll for IRQs on its own.
 413          */
 414         smp_wmb();
 415         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 416     }
 417     apic_update_irq(s);
 418 }
 419
 420 static void apic_eoi(APICCommonState *s)
 421 {
 422     int isrv;
 423     isrv = get_highest_priority_int(s->isr);
 424     if (isrv < 0)
 425         return;
 426     apic_reset_bit(s->isr, isrv);
 427     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
 428         ioapic_eoi_broadcast(isrv);
 429     }
 430     apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
 431     apic_update_irq(s);
 432 }
 433
 434 static int apic_find_dest(uint8_t dest)
 435 {
 436     APICCommonState *apic = local_apics[dest];
 437     int i;
 438
 439     if (apic && apic->id == dest)
 440         return dest;  /* shortcut in case apic->id == local_apics[dest]->id */
 441
 442     for (i = 0; i < MAX_APICS; i++) {
 443         apic = local_apics[i];
 444         if (apic && apic->id == dest)
 445             return i;
 446         if (!apic)
 447             break;
 448     }
 449
 450     return -1;
 451 }
 452
 453 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 454                                       uint8_t dest, uint8_t dest_mode)
 455 {
 456     APICCommonState *apic_iter;
 457     int i;
 458
 459     if (dest_mode == 0) {
 460         if (dest == 0xff) {
 461             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 462         } else {
 463             int idx = apic_find_dest(dest);
 464             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 465             if (idx >= 0)
 466                 apic_set_bit(deliver_bitmask, idx);
 467         }
 468     } else {
 469         /* XXX: cluster mode */
 470         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 471         for(i = 0; i < MAX_APICS; i++) {
 472             apic_iter = local_apics[i];
 473             if (apic_iter) {
 474                 if (apic_iter->dest_mode == 0xf) {
 475                     if (dest & apic_iter->log_dest)
 476                         apic_set_bit(deliver_bitmask, i);
 477                 } else if (apic_iter->dest_mode == 0x0) {
 478                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 479                         (dest & apic_iter->log_dest & 0x0f)) {
 480                         apic_set_bit(deliver_bitmask, i);
 481                     }
 482                 }
 483             } else {
 484                 break;
 485             }
 486         }
 487     }
 488 }
 489
 490 static void apic_startup(APICCommonState *s, int vector_num)
 491 {
 492     s->sipi_vector = vector_num;
 493     cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 494 }
 495
 496 void apic_sipi(DeviceState *dev)
 497 {
 498     APICCommonState *s = APIC(dev);
 499
 500     cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 501
 502     if (!s->wait_for_sipi)
 503         return;
 504     cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
 505     s->wait_for_sipi = 0;
 506 }
 507
 508 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
 509                          uint8_t delivery_mode, uint8_t vector_num,
 510                          uint8_t trigger_mode)
 511 {
 512     APICCommonState *s = APIC(dev);
 513     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 514     int dest_shorthand = (s->icr[0] >> 18) & 3;
 515     APICCommonState *apic_iter;
 516
 517     switch (dest_shorthand) {
 518     case 0:
 519         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 520         break;
 521     case 1:
 522         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 523         apic_set_bit(deliver_bitmask, s->id);
 524         break;
 525     case 2:
 526         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 527         break;
 528     case 3:
 529         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 530         apic_reset_bit(deliver_bitmask, s->id);
 531         break;
 532     }
 533
 534     switch (delivery_mode) {
 535         case APIC_DM_INIT:
 536             {
 537                 int trig_mode = (s->icr[0] >> 15) & 1;
 538                 int level = (s->icr[0] >> 14) & 1;
 539                 if (level == 0 && trig_mode == 1) {
 540                     foreach_apic(apic_iter, deliver_bitmask,
 541                                  apic_iter->arb_id = apic_iter->id );
 542                     return;
 543                 }
 544             }
 545             break;
 546
 547         case APIC_DM_SIPI:
 548             foreach_apic(apic_iter, deliver_bitmask,
 549                          apic_startup(apic_iter, vector_num) );
 550             return;
 551     }
 552
 553     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 554 }
 555
 556 static bool apic_check_pic(APICCommonState *s)
 557 {
 558     DeviceState *dev = (DeviceState *)s;
 559
 560     if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
 561         return false;
 562     }
 563     apic_deliver_pic_intr(dev, 1);
 564     return true;
 565 }
 566
 567 int apic_get_interrupt(DeviceState *dev)
 568 {
 569     APICCommonState *s = APIC(dev);
 570     int intno;
 571
 572     /* if the APIC is installed or enabled, we let the 8259 handle the
 573        IRQs */
 574     if (!s)
 575         return -1;
 576     if (!(s->spurious_vec & APIC_SV_ENABLE))
 577         return -1;
 578
 579     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 580     intno = apic_irq_pending(s);
 581
 582     /* if there is an interrupt from the 8259, let the caller handle
 583      * that first since ExtINT interrupts ignore the priority.
 584      */
 585     if (intno == 0 || apic_check_pic(s)) {
 586         apic_sync_vapic(s, SYNC_TO_VAPIC);
 587         return -1;
 588     } else if (intno < 0) {
 589         apic_sync_vapic(s, SYNC_TO_VAPIC);
 590         return s->spurious_vec & 0xff;
 591     }
 592     apic_reset_bit(s->irr, intno);
 593     apic_set_bit(s->isr, intno);
 594     apic_sync_vapic(s, SYNC_TO_VAPIC);
 595
 596     apic_update_irq(s);
 597
 598     return intno;
 599 }
 600
 601 int apic_accept_pic_intr(DeviceState *dev)
 602 {
 603     APICCommonState *s = APIC(dev);
 604     uint32_t lvt0;
 605
 606     if (!s)
 607         return -1;
 608
 609     lvt0 = s->lvt[APIC_LVT_LINT0];
 610
 611     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 612         (lvt0 & APIC_LVT_MASKED) == 0)
 613         return 1;
 614
 615     return 0;
 616 }
 617
 618 static uint32_t apic_get_current_count(APICCommonState *s)
 619 {
 620     int64_t d;
 621     uint32_t val;
 622     d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
 623         s->count_shift;
 624     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 625         /* periodic */
 626         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 627     } else {
 628         if (d >= s->initial_count)
 629             val = 0;
 630         else
 631             val = s->initial_count - d;
 632     }
 633     return val;
 634 }
 635
 636 static void apic_timer_update(APICCommonState *s, int64_t current_time)
 637 {
 638     if (apic_next_timer(s, current_time)) {
 639         timer_mod(s->timer, s->next_time);
 640     } else {
 641         timer_del(s->timer);
 642     }
 643 }
 644
 645 static void apic_timer(void *opaque)
 646 {
 647     APICCommonState *s = opaque;
 648
 649     apic_local_deliver(s, APIC_LVT_TIMER);
 650     apic_timer_update(s, s->next_time);
 651 }
 652
 653 static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
 654 {
 655     return 0;
 656 }
 657
 658 static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
 659 {
 660     return 0;
 661 }
 662
 663 static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
 664 {
 665 }
 666
 667 static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
 668 {
 669 }
 670
 671 static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
 672 {
 673     DeviceState *dev;
 674     APICCommonState *s;
 675     uint32_t val;
 676     int index;
 677
 678     dev = cpu_get_current_apic();
 679     if (!dev) {
 680         return 0;
 681     }
 682     s = APIC(dev);
 683
 684     index = (addr >> 4) & 0xff;
 685     switch(index) {
 686     case 0x02: /* id */
 687         val = s->id << 24;
 688         break;
 689     case 0x03: /* version */
 690         val = s->version | ((APIC_LVT_NB - 1) << 16);
 691         break;
 692     case 0x08:
 693         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 694         if (apic_report_tpr_access) {
 695             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
 696         }
 697         val = s->tpr;
 698         break;
 699     case 0x09:
 700         val = apic_get_arb_pri(s);
 701         break;
 702     case 0x0a:
 703         /* ppr */
 704         val = apic_get_ppr(s);
 705         break;
 706     case 0x0b:
 707         val = 0;
 708         break;
 709     case 0x0d:
 710         val = s->log_dest << 24;
 711         break;
 712     case 0x0e:
 713         val = (s->dest_mode << 28) | 0xfffffff;
 714         break;
 715     case 0x0f:
 716         val = s->spurious_vec;
 717         break;
 718     case 0x10 ... 0x17:
 719         val = s->isr[index & 7];
 720         break;
 721     case 0x18 ... 0x1f:
 722         val = s->tmr[index & 7];
 723         break;
 724     case 0x20 ... 0x27:
 725         val = s->irr[index & 7];
 726         break;
 727     case 0x28:
 728         val = s->esr;
 729         break;
 730     case 0x30:
 731     case 0x31:
 732         val = s->icr[index & 1];
 733         break;
 734     case 0x32 ... 0x37:
 735         val = s->lvt[index - 0x32];
 736         break;
 737     case 0x38:
 738         val = s->initial_count;
 739         break;
 740     case 0x39:
 741         val = apic_get_current_count(s);
 742         break;
 743     case 0x3e:
 744         val = s->divide_conf;
 745         break;
 746     default:
 747         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 748         val = 0;
 749         break;
 750     }
 751     trace_apic_mem_readl(addr, val);
 752     return val;
 753 }
 754
 755 static void apic_send_msi(MSIMessage *msi)
 756 {
 757     uint64_t addr = msi->address;
 758     uint32_t data = msi->data;
 759     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 760     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 761     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 762     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 763     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 764     /* XXX: Ignore redirection hint. */
 765     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 766 }
 767
 768 static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
 769 {
 770     DeviceState *dev;
 771     APICCommonState *s;
 772     int index = (addr >> 4) & 0xff;
 773     if (addr > 0xfff || !index) {
 774         /* MSI and MMIO APIC are at the same memory location,
 775          * but actually not on the global bus: MSI is on PCI bus
 776          * APIC is connected directly to the CPU.
 777          * Mapping them on the global bus happens to work because
 778          * MSI registers are reserved in APIC MMIO and vice versa. */
 779         MSIMessage msi = { .address = addr, .data = val };
 780         apic_send_msi(&msi);
 781         return;
 782     }
 783
 784     dev = cpu_get_current_apic();
 785     if (!dev) {
 786         return;
 787     }
 788     s = APIC(dev);
 789
 790     trace_apic_mem_writel(addr, val);
 791
 792     switch(index) {
 793     case 0x02:
 794         s->id = (val >> 24);
 795         break;
 796     case 0x03:
 797         break;
 798     case 0x08:
 799         if (apic_report_tpr_access) {
 800             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
 801         }
 802         s->tpr = val;
 803         apic_sync_vapic(s, SYNC_TO_VAPIC);
 804         apic_update_irq(s);
 805         break;
 806     case 0x09:
 807     case 0x0a:
 808         break;
 809     case 0x0b: /* EOI */
 810         apic_eoi(s);
 811         break;
 812     case 0x0d:
 813         s->log_dest = val >> 24;
 814         break;
 815     case 0x0e:
 816         s->dest_mode = val >> 28;
 817         break;
 818     case 0x0f:
 819         s->spurious_vec = val & 0x1ff;
 820         apic_update_irq(s);
 821         break;
 822     case 0x10 ... 0x17:
 823     case 0x18 ... 0x1f:
 824     case 0x20 ... 0x27:
 825     case 0x28:
 826         break;
 827     case 0x30:
 828         s->icr[0] = val;
 829         apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 830                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 831                      (s->icr[0] >> 15) & 1);
 832         break;
 833     case 0x31:
 834         s->icr[1] = val;
 835         break;
 836     case 0x32 ... 0x37:
 837         {
 838             int n = index - 0x32;
 839             s->lvt[n] = val;
 840             if (n == APIC_LVT_TIMER) {
 841                 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 842             } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
 843                 apic_update_irq(s);
 844             }
 845         }
 846         break;
 847     case 0x38:
 848         s->initial_count = val;
 849         s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 850         apic_timer_update(s, s->initial_count_load_time);
 851         break;
 852     case 0x39:
 853         break;
 854     case 0x3e:
 855         {
 856             int v;
 857             s->divide_conf = val & 0xb;
 858             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 859             s->count_shift = (v + 1) & 7;
 860         }
 861         break;
 862     default:
 863         s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
 864         break;
 865     }
 866 }
 867
 868 static void apic_pre_save(APICCommonState *s)
 869 {
 870     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 871 }
 872
 873 static void apic_post_load(APICCommonState *s)
 874 {
 875     if (s->timer_expiry != -1) {
 876         timer_mod(s->timer, s->timer_expiry);
 877     } else {
 878         timer_del(s->timer);
 879     }
 880 }
 881
 882 static const MemoryRegionOps apic_io_ops = {
 883     .old_mmio = {
 884         .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
 885         .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
 886     },
 887     .endianness = DEVICE_NATIVE_ENDIAN,
 888 };
 889
 890 static void apic_realize(DeviceState *dev, Error **errp)
 891 {
 892     APICCommonState *s = APIC(dev);
 893
 894     if (s->id >= MAX_APICS) {
 895         error_setg(errp, "%s initialization failed. APIC ID %d is invalid",
 896                    object_get_typename(OBJECT(dev)), s->id);
 897         return;
 898     }
 899
 900     memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
 901                           APIC_SPACE_SIZE);
 902
 903     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
 904     local_apics[s->id] = s;
 905
 906     msi_nonbroken = true;
 907 }
 908
 909 static void apic_unrealize(DeviceState *dev, Error **errp)
 910 {
 911     APICCommonState *s = APIC(dev);
 912
 913     timer_del(s->timer);
 914     timer_free(s->timer);
 915     local_apics[s->id] = NULL;
 916 }
 917
 918 static void apic_class_init(ObjectClass *klass, void *data)
 919 {
 920     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 921
 922     k->realize = apic_realize;
 923     k->unrealize = apic_unrealize;
 924     k->set_base = apic_set_base;
 925     k->set_tpr = apic_set_tpr;
 926     k->get_tpr = apic_get_tpr;
 927     k->vapic_base_update = apic_vapic_base_update;
 928     k->external_nmi = apic_external_nmi;
 929     k->pre_save = apic_pre_save;
 930     k->post_load = apic_post_load;
 931     k->send_msi = apic_send_msi;
 932 }
 933
 934 static const TypeInfo apic_info = {
 935     .name          = TYPE_APIC,
 936     .instance_size = sizeof(APICCommonState),
 937     .parent        = TYPE_APIC_COMMON,
 938     .class_init    = apic_class_init,
 939 };
 940
 941 static void apic_register_types(void)
 942 {
 943     type_register_static(&apic_info);
 944 }
 945
 946 type_init(apic_register_types)