2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
22 * Supported commands/modes are:
28 * - unlock bypass command
31 * It does not support flash interleaving.
32 * It does not implement boot blocs with reduced size
33 * It does not implement software data protection as found in many real chips
34 * It does not implement erase suspend/resume commands
35 * It does not implement multiple sectors erase
38 #include "qemu/osdep.h"
40 #include "hw/block/flash.h"
41 #include "qapi/error.h"
42 #include "qemu/timer.h"
43 #include "sysemu/block-backend.h"
44 #include "qemu/host-utils.h"
45 #include "hw/sysbus.h"
47 //#define PFLASH_DEBUG
49 #define DPRINTF(fmt, ...) \
51 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
54 #define DPRINTF(fmt, ...) do { } while (0)
57 #define PFLASH_LAZY_ROMD_THRESHOLD 42
59 #define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
63 SysBusDevice parent_obj
;
73 int wcycle
; /* if 0, the flash is read normally */
78 /* FIXME: implement array device properties */
83 uint16_t unlock_addr0
;
84 uint16_t unlock_addr1
;
85 uint8_t cfi_table
[0x52];
87 /* The device replicates the flash memory across its memory space. Emulate
88 * that by having a container (.mem) filled with an array of aliases
89 * (.mem_mappings) pointing to the flash memory (.orig_mem).
92 MemoryRegion
*mem_mappings
; /* array; one per mapping */
93 MemoryRegion orig_mem
;
95 int read_counter
; /* used for lazy switch-back to rom mode */
101 * Set up replicated mappings of the same region.
103 static void pflash_setup_mappings(pflash_t
*pfl
)
106 hwaddr size
= memory_region_size(&pfl
->orig_mem
);
108 memory_region_init(&pfl
->mem
, OBJECT(pfl
), "pflash", pfl
->mappings
* size
);
109 pfl
->mem_mappings
= g_new(MemoryRegion
, pfl
->mappings
);
110 for (i
= 0; i
< pfl
->mappings
; ++i
) {
111 memory_region_init_alias(&pfl
->mem_mappings
[i
], OBJECT(pfl
),
112 "pflash-alias", &pfl
->orig_mem
, 0, size
);
113 memory_region_add_subregion(&pfl
->mem
, i
* size
, &pfl
->mem_mappings
[i
]);
117 static void pflash_register_memory(pflash_t
*pfl
, int rom_mode
)
119 memory_region_rom_device_set_romd(&pfl
->orig_mem
, rom_mode
);
120 pfl
->rom_mode
= rom_mode
;
123 static void pflash_timer (void *opaque
)
125 pflash_t
*pfl
= opaque
;
127 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
133 pflash_register_memory(pfl
, 1);
139 static uint32_t pflash_read (pflash_t
*pfl
, hwaddr offset
,
146 DPRINTF("%s: offset " TARGET_FMT_plx
"\n", __func__
, offset
);
148 /* Lazy reset to ROMD mode after a certain amount of read accesses */
149 if (!pfl
->rom_mode
&& pfl
->wcycle
== 0 &&
150 ++pfl
->read_counter
> PFLASH_LAZY_ROMD_THRESHOLD
) {
151 pflash_register_memory(pfl
, 1);
153 offset
&= pfl
->chip_len
- 1;
154 boff
= offset
& 0xFF;
157 else if (pfl
->width
== 4)
161 /* This should never happen : reset state & treat it as a read*/
162 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
165 /* fall through to the read code */
167 /* We accept reads during second unlock sequence... */
170 /* Flash area read */
175 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
179 ret
= p
[offset
] << 8;
180 ret
|= p
[offset
+ 1];
183 ret
|= p
[offset
+ 1] << 8;
185 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
189 ret
= p
[offset
] << 24;
190 ret
|= p
[offset
+ 1] << 16;
191 ret
|= p
[offset
+ 2] << 8;
192 ret
|= p
[offset
+ 3];
195 ret
|= p
[offset
+ 1] << 8;
196 ret
|= p
[offset
+ 2] << 16;
197 ret
|= p
[offset
+ 3] << 24;
199 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
208 ret
= boff
& 0x01 ? pfl
->ident1
: pfl
->ident0
;
211 ret
= 0x00; /* Pretend all sectors are unprotected */
215 ret
= boff
& 0x01 ? pfl
->ident3
: pfl
->ident2
;
216 if (ret
== (uint8_t)-1) {
223 DPRINTF("%s: ID " TARGET_FMT_plx
" %x\n", __func__
, boff
, ret
);
228 /* Status register read */
230 DPRINTF("%s: status %x\n", __func__
, ret
);
236 if (boff
< sizeof(pfl
->cfi_table
)) {
237 ret
= pfl
->cfi_table
[boff
];
247 /* update flash content on disk */
248 static void pflash_update(pflash_t
*pfl
, int offset
,
253 offset_end
= offset
+ size
;
254 /* widen to sector boundaries */
255 offset
= QEMU_ALIGN_DOWN(offset
, BDRV_SECTOR_SIZE
);
256 offset_end
= QEMU_ALIGN_UP(offset_end
, BDRV_SECTOR_SIZE
);
257 blk_pwrite(pfl
->blk
, offset
, pfl
->storage
+ offset
,
258 offset_end
- offset
, 0);
262 static void pflash_write (pflash_t
*pfl
, hwaddr offset
,
263 uint32_t value
, int width
, int be
)
270 if (pfl
->cmd
!= 0xA0 && cmd
== 0xF0) {
272 DPRINTF("%s: flash reset asked (%02x %02x)\n",
273 __func__
, pfl
->cmd
, cmd
);
277 DPRINTF("%s: offset " TARGET_FMT_plx
" %08x %d %d\n", __func__
,
278 offset
, value
, width
, pfl
->wcycle
);
279 offset
&= pfl
->chip_len
- 1;
281 DPRINTF("%s: offset " TARGET_FMT_plx
" %08x %d\n", __func__
,
282 offset
, value
, width
);
283 boff
= offset
& (pfl
->sector_len
- 1);
286 else if (pfl
->width
== 4)
288 switch (pfl
->wcycle
) {
290 /* Set the device in I/O access mode if required */
292 pflash_register_memory(pfl
, 0);
293 pfl
->read_counter
= 0;
294 /* We're in read mode */
296 if (boff
== 0x55 && cmd
== 0x98) {
298 /* Enter CFI query mode */
303 if (boff
!= pfl
->unlock_addr0
|| cmd
!= 0xAA) {
304 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx
" %02x %04x\n",
305 __func__
, boff
, cmd
, pfl
->unlock_addr0
);
308 DPRINTF("%s: unlock sequence started\n", __func__
);
311 /* We started an unlock sequence */
313 if (boff
!= pfl
->unlock_addr1
|| cmd
!= 0x55) {
314 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx
" %02x\n", __func__
,
318 DPRINTF("%s: unlock sequence done\n", __func__
);
321 /* We finished an unlock sequence */
322 if (!pfl
->bypass
&& boff
!= pfl
->unlock_addr0
) {
323 DPRINTF("%s: command failed " TARGET_FMT_plx
" %02x\n", __func__
,
335 DPRINTF("%s: starting command %02x\n", __func__
, cmd
);
338 DPRINTF("%s: unknown command %02x\n", __func__
, cmd
);
345 /* We need another unlock sequence */
348 DPRINTF("%s: write data offset " TARGET_FMT_plx
" %08x %d\n",
349 __func__
, offset
, value
, width
);
355 pflash_update(pfl
, offset
, 1);
359 p
[offset
] &= value
>> 8;
360 p
[offset
+ 1] &= value
;
363 p
[offset
+ 1] &= value
>> 8;
365 pflash_update(pfl
, offset
, 2);
369 p
[offset
] &= value
>> 24;
370 p
[offset
+ 1] &= value
>> 16;
371 p
[offset
+ 2] &= value
>> 8;
372 p
[offset
+ 3] &= value
;
375 p
[offset
+ 1] &= value
>> 8;
376 p
[offset
+ 2] &= value
>> 16;
377 p
[offset
+ 3] &= value
>> 24;
379 pflash_update(pfl
, offset
, 4);
383 pfl
->status
= 0x00 | ~(value
& 0x80);
384 /* Let's pretend write is immediate */
389 if (pfl
->bypass
&& cmd
== 0x00) {
390 /* Unlock bypass reset */
393 /* We can enter CFI query mode from autoselect mode */
394 if (boff
== 0x55 && cmd
== 0x98)
398 DPRINTF("%s: invalid write for command %02x\n",
405 /* Ignore writes while flash data write is occurring */
406 /* As we suppose write is immediate, this should never happen */
411 /* Should never happen */
412 DPRINTF("%s: invalid command state %02x (wc 4)\n",
420 if (boff
!= pfl
->unlock_addr0
) {
421 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx
"\n",
426 DPRINTF("%s: start chip erase\n", __func__
);
428 memset(pfl
->storage
, 0xFF, pfl
->chip_len
);
429 pflash_update(pfl
, 0, pfl
->chip_len
);
432 /* Let's wait 5 seconds before chip erase is done */
433 timer_mod(pfl
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
434 (NANOSECONDS_PER_SECOND
* 5));
439 offset
&= ~(pfl
->sector_len
- 1);
440 DPRINTF("%s: start sector erase at " TARGET_FMT_plx
"\n", __func__
,
443 memset(p
+ offset
, 0xFF, pfl
->sector_len
);
444 pflash_update(pfl
, offset
, pfl
->sector_len
);
447 /* Let's wait 1/2 second before sector erase is done */
448 timer_mod(pfl
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
449 (NANOSECONDS_PER_SECOND
/ 2));
452 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__
, cmd
);
460 /* Ignore writes during chip erase */
463 /* Ignore writes during sector erase */
466 /* Should never happen */
467 DPRINTF("%s: invalid command state %02x (wc 6)\n",
472 case 7: /* Special value for CFI queries */
473 DPRINTF("%s: invalid write in CFI query mode\n", __func__
);
476 /* Should never happen */
477 DPRINTF("%s: invalid write state (wc 7)\n", __func__
);
497 static uint32_t pflash_readb_be(void *opaque
, hwaddr addr
)
499 return pflash_read(opaque
, addr
, 1, 1);
502 static uint32_t pflash_readb_le(void *opaque
, hwaddr addr
)
504 return pflash_read(opaque
, addr
, 1, 0);
507 static uint32_t pflash_readw_be(void *opaque
, hwaddr addr
)
509 pflash_t
*pfl
= opaque
;
511 return pflash_read(pfl
, addr
, 2, 1);
514 static uint32_t pflash_readw_le(void *opaque
, hwaddr addr
)
516 pflash_t
*pfl
= opaque
;
518 return pflash_read(pfl
, addr
, 2, 0);
521 static uint32_t pflash_readl_be(void *opaque
, hwaddr addr
)
523 pflash_t
*pfl
= opaque
;
525 return pflash_read(pfl
, addr
, 4, 1);
528 static uint32_t pflash_readl_le(void *opaque
, hwaddr addr
)
530 pflash_t
*pfl
= opaque
;
532 return pflash_read(pfl
, addr
, 4, 0);
535 static void pflash_writeb_be(void *opaque
, hwaddr addr
,
538 pflash_write(opaque
, addr
, value
, 1, 1);
541 static void pflash_writeb_le(void *opaque
, hwaddr addr
,
544 pflash_write(opaque
, addr
, value
, 1, 0);
547 static void pflash_writew_be(void *opaque
, hwaddr addr
,
550 pflash_t
*pfl
= opaque
;
552 pflash_write(pfl
, addr
, value
, 2, 1);
555 static void pflash_writew_le(void *opaque
, hwaddr addr
,
558 pflash_t
*pfl
= opaque
;
560 pflash_write(pfl
, addr
, value
, 2, 0);
563 static void pflash_writel_be(void *opaque
, hwaddr addr
,
566 pflash_t
*pfl
= opaque
;
568 pflash_write(pfl
, addr
, value
, 4, 1);
571 static void pflash_writel_le(void *opaque
, hwaddr addr
,
574 pflash_t
*pfl
= opaque
;
576 pflash_write(pfl
, addr
, value
, 4, 0);
579 static const MemoryRegionOps pflash_cfi02_ops_be
= {
581 .read
= { pflash_readb_be
, pflash_readw_be
, pflash_readl_be
, },
582 .write
= { pflash_writeb_be
, pflash_writew_be
, pflash_writel_be
, },
584 .endianness
= DEVICE_NATIVE_ENDIAN
,
587 static const MemoryRegionOps pflash_cfi02_ops_le
= {
589 .read
= { pflash_readb_le
, pflash_readw_le
, pflash_readl_le
, },
590 .write
= { pflash_writeb_le
, pflash_writew_le
, pflash_writel_le
, },
592 .endianness
= DEVICE_NATIVE_ENDIAN
,
595 static void pflash_cfi02_realize(DeviceState
*dev
, Error
**errp
)
597 pflash_t
*pfl
= CFI_PFLASH02(dev
);
600 Error
*local_err
= NULL
;
602 if (pfl
->sector_len
== 0) {
603 error_setg(errp
, "attribute \"sector-length\" not specified or zero.");
606 if (pfl
->nb_blocs
== 0) {
607 error_setg(errp
, "attribute \"num-blocks\" not specified or zero.");
610 if (pfl
->name
== NULL
) {
611 error_setg(errp
, "attribute \"name\" not specified.");
615 chip_len
= pfl
->sector_len
* pfl
->nb_blocs
;
616 /* XXX: to be fixed */
618 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
619 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
623 memory_region_init_rom_device(&pfl
->orig_mem
, OBJECT(pfl
), pfl
->be
?
624 &pflash_cfi02_ops_be
: &pflash_cfi02_ops_le
,
625 pfl
, pfl
->name
, chip_len
, &local_err
);
627 error_propagate(errp
, local_err
);
631 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->orig_mem
);
632 pfl
->chip_len
= chip_len
;
636 pfl
->ro
= blk_is_read_only(pfl
->blk
);
637 perm
= BLK_PERM_CONSISTENT_READ
| (pfl
->ro
? 0 : BLK_PERM_WRITE
);
638 ret
= blk_set_perm(pfl
->blk
, perm
, BLK_PERM_ALL
, errp
);
647 /* read the initial flash content */
648 ret
= blk_pread(pfl
->blk
, 0, pfl
->storage
, chip_len
);
650 vmstate_unregister_ram(&pfl
->orig_mem
, DEVICE(pfl
));
651 error_setg(errp
, "failed to read the initial flash content");
656 pflash_setup_mappings(pfl
);
658 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
660 pfl
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, pflash_timer
, pfl
);
664 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
665 /* Standard "QRY" string */
666 pfl
->cfi_table
[0x10] = 'Q';
667 pfl
->cfi_table
[0x11] = 'R';
668 pfl
->cfi_table
[0x12] = 'Y';
669 /* Command set (AMD/Fujitsu) */
670 pfl
->cfi_table
[0x13] = 0x02;
671 pfl
->cfi_table
[0x14] = 0x00;
672 /* Primary extended table address */
673 pfl
->cfi_table
[0x15] = 0x31;
674 pfl
->cfi_table
[0x16] = 0x00;
675 /* Alternate command set (none) */
676 pfl
->cfi_table
[0x17] = 0x00;
677 pfl
->cfi_table
[0x18] = 0x00;
678 /* Alternate extended table (none) */
679 pfl
->cfi_table
[0x19] = 0x00;
680 pfl
->cfi_table
[0x1A] = 0x00;
682 pfl
->cfi_table
[0x1B] = 0x27;
684 pfl
->cfi_table
[0x1C] = 0x36;
685 /* Vpp min (no Vpp pin) */
686 pfl
->cfi_table
[0x1D] = 0x00;
687 /* Vpp max (no Vpp pin) */
688 pfl
->cfi_table
[0x1E] = 0x00;
690 pfl
->cfi_table
[0x1F] = 0x07;
691 /* Timeout for min size buffer write (NA) */
692 pfl
->cfi_table
[0x20] = 0x00;
693 /* Typical timeout for block erase (512 ms) */
694 pfl
->cfi_table
[0x21] = 0x09;
695 /* Typical timeout for full chip erase (4096 ms) */
696 pfl
->cfi_table
[0x22] = 0x0C;
698 pfl
->cfi_table
[0x23] = 0x01;
699 /* Max timeout for buffer write (NA) */
700 pfl
->cfi_table
[0x24] = 0x00;
701 /* Max timeout for block erase */
702 pfl
->cfi_table
[0x25] = 0x0A;
703 /* Max timeout for chip erase */
704 pfl
->cfi_table
[0x26] = 0x0D;
706 pfl
->cfi_table
[0x27] = ctz32(chip_len
);
707 /* Flash device interface (8 & 16 bits) */
708 pfl
->cfi_table
[0x28] = 0x02;
709 pfl
->cfi_table
[0x29] = 0x00;
710 /* Max number of bytes in multi-bytes write */
711 /* XXX: disable buffered write as it's not supported */
712 // pfl->cfi_table[0x2A] = 0x05;
713 pfl
->cfi_table
[0x2A] = 0x00;
714 pfl
->cfi_table
[0x2B] = 0x00;
715 /* Number of erase block regions (uniform) */
716 pfl
->cfi_table
[0x2C] = 0x01;
717 /* Erase block region 1 */
718 pfl
->cfi_table
[0x2D] = pfl
->nb_blocs
- 1;
719 pfl
->cfi_table
[0x2E] = (pfl
->nb_blocs
- 1) >> 8;
720 pfl
->cfi_table
[0x2F] = pfl
->sector_len
>> 8;
721 pfl
->cfi_table
[0x30] = pfl
->sector_len
>> 16;
724 pfl
->cfi_table
[0x31] = 'P';
725 pfl
->cfi_table
[0x32] = 'R';
726 pfl
->cfi_table
[0x33] = 'I';
728 pfl
->cfi_table
[0x34] = '1';
729 pfl
->cfi_table
[0x35] = '0';
731 pfl
->cfi_table
[0x36] = 0x00;
732 pfl
->cfi_table
[0x37] = 0x00;
733 pfl
->cfi_table
[0x38] = 0x00;
734 pfl
->cfi_table
[0x39] = 0x00;
736 pfl
->cfi_table
[0x3a] = 0x00;
738 pfl
->cfi_table
[0x3b] = 0x00;
739 pfl
->cfi_table
[0x3c] = 0x00;
742 static Property pflash_cfi02_properties
[] = {
743 DEFINE_PROP_DRIVE("drive", struct pflash_t
, blk
),
744 DEFINE_PROP_UINT32("num-blocks", struct pflash_t
, nb_blocs
, 0),
745 DEFINE_PROP_UINT32("sector-length", struct pflash_t
, sector_len
, 0),
746 DEFINE_PROP_UINT8("width", struct pflash_t
, width
, 0),
747 DEFINE_PROP_UINT8("mappings", struct pflash_t
, mappings
, 0),
748 DEFINE_PROP_UINT8("big-endian", struct pflash_t
, be
, 0),
749 DEFINE_PROP_UINT16("id0", struct pflash_t
, ident0
, 0),
750 DEFINE_PROP_UINT16("id1", struct pflash_t
, ident1
, 0),
751 DEFINE_PROP_UINT16("id2", struct pflash_t
, ident2
, 0),
752 DEFINE_PROP_UINT16("id3", struct pflash_t
, ident3
, 0),
753 DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t
, unlock_addr0
, 0),
754 DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t
, unlock_addr1
, 0),
755 DEFINE_PROP_STRING("name", struct pflash_t
, name
),
756 DEFINE_PROP_END_OF_LIST(),
759 static void pflash_cfi02_class_init(ObjectClass
*klass
, void *data
)
761 DeviceClass
*dc
= DEVICE_CLASS(klass
);
763 dc
->realize
= pflash_cfi02_realize
;
764 dc
->props
= pflash_cfi02_properties
;
765 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
768 static const TypeInfo pflash_cfi02_info
= {
769 .name
= TYPE_CFI_PFLASH02
,
770 .parent
= TYPE_SYS_BUS_DEVICE
,
771 .instance_size
= sizeof(struct pflash_t
),
772 .class_init
= pflash_cfi02_class_init
,
775 static void pflash_cfi02_register_types(void)
777 type_register_static(&pflash_cfi02_info
);
780 type_init(pflash_cfi02_register_types
)
782 pflash_t
*pflash_cfi02_register(hwaddr base
,
783 DeviceState
*qdev
, const char *name
,
785 BlockBackend
*blk
, uint32_t sector_len
,
786 int nb_blocs
, int nb_mappings
, int width
,
787 uint16_t id0
, uint16_t id1
,
788 uint16_t id2
, uint16_t id3
,
789 uint16_t unlock_addr0
, uint16_t unlock_addr1
,
792 DeviceState
*dev
= qdev_create(NULL
, TYPE_CFI_PFLASH02
);
795 qdev_prop_set_drive(dev
, "drive", blk
, &error_abort
);
797 qdev_prop_set_uint32(dev
, "num-blocks", nb_blocs
);
798 qdev_prop_set_uint32(dev
, "sector-length", sector_len
);
799 qdev_prop_set_uint8(dev
, "width", width
);
800 qdev_prop_set_uint8(dev
, "mappings", nb_mappings
);
801 qdev_prop_set_uint8(dev
, "big-endian", !!be
);
802 qdev_prop_set_uint16(dev
, "id0", id0
);
803 qdev_prop_set_uint16(dev
, "id1", id1
);
804 qdev_prop_set_uint16(dev
, "id2", id2
);
805 qdev_prop_set_uint16(dev
, "id3", id3
);
806 qdev_prop_set_uint16(dev
, "unlock-addr0", unlock_addr0
);
807 qdev_prop_set_uint16(dev
, "unlock-addr1", unlock_addr1
);
808 qdev_prop_set_string(dev
, "name", name
);
809 qdev_init_nofail(dev
);
811 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
812 return CFI_PFLASH02(dev
);