2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "exec/cpu-common.h"
23 #include "exec/memory.h"
24 #include "qemu/thread.h"
25 #include "hw/core/cpu.h"
28 #define EXCP_INTERRUPT 0x10000 /* async interruption */
29 #define EXCP_HLT 0x10001 /* hlt instruction reached */
30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
35 /* some important defines:
37 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
38 * otherwise little endian.
40 * TARGET_WORDS_BIGENDIAN : same for target cpu
43 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
49 static inline uint16_t tswap16(uint16_t s
)
54 static inline uint32_t tswap32(uint32_t s
)
59 static inline uint64_t tswap64(uint64_t s
)
64 static inline void tswap16s(uint16_t *s
)
69 static inline void tswap32s(uint32_t *s
)
74 static inline void tswap64s(uint64_t *s
)
81 static inline uint16_t tswap16(uint16_t s
)
86 static inline uint32_t tswap32(uint32_t s
)
91 static inline uint64_t tswap64(uint64_t s
)
96 static inline void tswap16s(uint16_t *s
)
100 static inline void tswap32s(uint32_t *s
)
104 static inline void tswap64s(uint64_t *s
)
110 #if TARGET_LONG_SIZE == 4
111 #define tswapl(s) tswap32(s)
112 #define tswapls(s) tswap32s((uint32_t *)(s))
113 #define bswaptls(s) bswap32s(s)
115 #define tswapl(s) tswap64(s)
116 #define tswapls(s) tswap64s((uint64_t *)(s))
117 #define bswaptls(s) bswap64s(s)
120 /* Target-endianness CPU memory access functions. These fit into the
121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
123 #if defined(TARGET_WORDS_BIGENDIAN)
124 #define lduw_p(p) lduw_be_p(p)
125 #define ldsw_p(p) ldsw_be_p(p)
126 #define ldl_p(p) ldl_be_p(p)
127 #define ldq_p(p) ldq_be_p(p)
128 #define ldfl_p(p) ldfl_be_p(p)
129 #define ldfq_p(p) ldfq_be_p(p)
130 #define stw_p(p, v) stw_be_p(p, v)
131 #define stl_p(p, v) stl_be_p(p, v)
132 #define stq_p(p, v) stq_be_p(p, v)
133 #define stfl_p(p, v) stfl_be_p(p, v)
134 #define stfq_p(p, v) stfq_be_p(p, v)
135 #define ldn_p(p, sz) ldn_be_p(p, sz)
136 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
138 #define lduw_p(p) lduw_le_p(p)
139 #define ldsw_p(p) ldsw_le_p(p)
140 #define ldl_p(p) ldl_le_p(p)
141 #define ldq_p(p) ldq_le_p(p)
142 #define ldfl_p(p) ldfl_le_p(p)
143 #define ldfq_p(p) ldfq_le_p(p)
144 #define stw_p(p, v) stw_le_p(p, v)
145 #define stl_p(p, v) stl_le_p(p, v)
146 #define stq_p(p, v) stq_le_p(p, v)
147 #define stfl_p(p, v) stfl_le_p(p, v)
148 #define stfq_p(p, v) stfq_le_p(p, v)
149 #define ldn_p(p, sz) ldn_le_p(p, sz)
150 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
153 /* MMU memory access macros */
155 #if defined(CONFIG_USER_ONLY)
156 #include "exec/user/abitypes.h"
158 /* On some host systems the guest address space is reserved on the host.
159 * This allows the guest address space to be offset to a convenient location.
161 extern unsigned long guest_base
;
162 extern int have_guest_base
;
163 extern unsigned long reserved_va
;
165 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
166 #define GUEST_ADDR_MAX (~0ul)
168 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : \
169 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
173 #include "exec/hwaddr.h"
177 #define ARG1_DECL AddressSpace *as
178 #define TARGET_ENDIANNESS
179 #include "exec/memory_ldst.inc.h"
181 #define SUFFIX _cached_slow
183 #define ARG1_DECL MemoryRegionCache *cache
184 #define TARGET_ENDIANNESS
185 #include "exec/memory_ldst.inc.h"
187 static inline void stl_phys_notdirty(AddressSpace
*as
, hwaddr addr
, uint32_t val
)
189 address_space_stl_notdirty(as
, addr
, val
,
190 MEMTXATTRS_UNSPECIFIED
, NULL
);
195 #define ARG1_DECL AddressSpace *as
196 #define TARGET_ENDIANNESS
197 #include "exec/memory_ldst_phys.inc.h"
199 /* Inline fast path for direct RAM access. */
201 #include "exec/memory_ldst_cached.inc.h"
203 #define SUFFIX _cached
205 #define ARG1_DECL MemoryRegionCache *cache
206 #define TARGET_ENDIANNESS
207 #include "exec/memory_ldst_phys.inc.h"
210 /* page related stuff */
212 #ifdef TARGET_PAGE_BITS_VARY
213 extern bool target_page_bits_decided
;
214 extern int target_page_bits
;
215 #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \
218 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
221 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
222 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
223 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
225 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
226 * when intptr_t is 32-bit and we are aligning a long long.
228 extern uintptr_t qemu_host_page_size
;
229 extern intptr_t qemu_host_page_mask
;
231 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
232 #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
233 qemu_real_host_page_mask)
235 /* same as PROT_xxx */
236 #define PAGE_READ 0x0001
237 #define PAGE_WRITE 0x0002
238 #define PAGE_EXEC 0x0004
239 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
240 #define PAGE_VALID 0x0008
241 /* original state of the write flag (used when tracking self-modifying
243 #define PAGE_WRITE_ORG 0x0010
244 /* Invalidate the TLB entry immediately, helpful for s390x
245 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */
246 #define PAGE_WRITE_INV 0x0040
247 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
248 /* FIXME: Code that sets/uses this is broken and needs to go away. */
249 #define PAGE_RESERVED 0x0020
252 #if defined(CONFIG_USER_ONLY)
253 void page_dump(FILE *f
);
255 typedef int (*walk_memory_regions_fn
)(void *, target_ulong
,
256 target_ulong
, unsigned long);
257 int walk_memory_regions(void *, walk_memory_regions_fn
);
259 int page_get_flags(target_ulong address
);
260 void page_set_flags(target_ulong start
, target_ulong end
, int flags
);
261 int page_check_range(target_ulong start
, target_ulong len
, int flags
);
264 CPUArchState
*cpu_copy(CPUArchState
*env
);
266 /* Flags for use in ENV->INTERRUPT_PENDING.
268 The numbers assigned here are non-sequential in order to preserve
269 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
270 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
273 /* External hardware interrupt pending. This is typically used for
274 interrupts from devices. */
275 #define CPU_INTERRUPT_HARD 0x0002
277 /* Exit the current TB. This is typically used when some system-level device
278 makes some change to the memory mapping. E.g. the a20 line change. */
279 #define CPU_INTERRUPT_EXITTB 0x0004
282 #define CPU_INTERRUPT_HALT 0x0020
284 /* Debug event pending. */
285 #define CPU_INTERRUPT_DEBUG 0x0080
288 #define CPU_INTERRUPT_RESET 0x0400
290 /* Several target-specific external hardware interrupts. Each target/cpu.h
291 should define proper names based on these defines. */
292 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
293 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
294 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
295 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
296 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
298 /* Several target-specific internal interrupts. These differ from the
299 preceding target-specific interrupts in that they are intended to
300 originate from within the cpu itself, typically in response to some
301 instruction being executed. These, therefore, are not masked while
302 single-stepping within the debugger. */
303 #define CPU_INTERRUPT_TGT_INT_0 0x0100
304 #define CPU_INTERRUPT_TGT_INT_1 0x0800
305 #define CPU_INTERRUPT_TGT_INT_2 0x2000
307 /* First unused bit: 0x4000. */
309 /* The set of all bits that should be masked when single-stepping. */
310 #define CPU_INTERRUPT_SSTEP_MASK \
311 (CPU_INTERRUPT_HARD \
312 | CPU_INTERRUPT_TGT_EXT_0 \
313 | CPU_INTERRUPT_TGT_EXT_1 \
314 | CPU_INTERRUPT_TGT_EXT_2 \
315 | CPU_INTERRUPT_TGT_EXT_3 \
316 | CPU_INTERRUPT_TGT_EXT_4)
318 #if !defined(CONFIG_USER_ONLY)
321 * Flags stored in the low bits of the TLB virtual address.
322 * These are defined so that fast path ram access is all zeros.
323 * The flags all must be between TARGET_PAGE_BITS and
324 * maximum address alignment bit.
326 * Use TARGET_PAGE_BITS_MIN so that these bits are constant
327 * when TARGET_PAGE_BITS_VARY is in effect.
329 /* Zero if TLB entry is valid. */
330 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
331 /* Set if TLB entry references a clean RAM page. The iotlb entry will
332 contain the page physical address. */
333 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
334 /* Set if TLB entry is an IO callback. */
335 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
336 /* Set if TLB entry contains a watchpoint. */
337 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
338 /* Set if TLB entry requires byte swap. */
339 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5))
340 /* Set if TLB entry writes ignored. */
341 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
343 /* Use this mask to check interception with an alignment mask
346 #define TLB_FLAGS_MASK \
347 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
348 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE)
351 * tlb_hit_page: return true if page aligned @addr is a hit against the
352 * TLB entry @tlb_addr
354 * @addr: virtual address to test (must be page aligned)
355 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
357 static inline bool tlb_hit_page(target_ulong tlb_addr
, target_ulong addr
)
359 return addr
== (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
));
363 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
365 * @addr: virtual address to test (need not be page aligned)
366 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
368 static inline bool tlb_hit(target_ulong tlb_addr
, target_ulong addr
)
370 return tlb_hit_page(tlb_addr
, addr
& TARGET_PAGE_MASK
);
373 void dump_exec_info(void);
374 void dump_opcount_info(void);
375 #endif /* !CONFIG_USER_ONLY */
377 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
378 uint8_t *buf
, target_ulong len
, int is_write
);
380 int cpu_exec(CPUState
*cpu
);
383 * cpu_set_cpustate_pointers(cpu)
384 * @cpu: The cpu object
386 * Set the generic pointers in CPUState into the outer object.
388 static inline void cpu_set_cpustate_pointers(ArchCPU
*cpu
)
390 cpu
->parent_obj
.env_ptr
= &cpu
->env
;
391 cpu
->parent_obj
.icount_decr_ptr
= &cpu
->neg
.icount_decr
;
396 * @env: The architecture environment
398 * Return the ArchCPU associated with the environment.
400 static inline ArchCPU
*env_archcpu(CPUArchState
*env
)
402 return container_of(env
, ArchCPU
, env
);
407 * @env: The architecture environment
409 * Return the CPUState associated with the environment.
411 static inline CPUState
*env_cpu(CPUArchState
*env
)
413 return &env_archcpu(env
)->parent_obj
;
418 * @env: The architecture environment
420 * Return the CPUNegativeOffsetState associated with the environment.
422 static inline CPUNegativeOffsetState
*env_neg(CPUArchState
*env
)
424 ArchCPU
*arch_cpu
= container_of(env
, ArchCPU
, env
);
425 return &arch_cpu
->neg
;
430 * @cpu: The generic CPUState
432 * Return the CPUNegativeOffsetState associated with the cpu.
434 static inline CPUNegativeOffsetState
*cpu_neg(CPUState
*cpu
)
436 ArchCPU
*arch_cpu
= container_of(cpu
, ArchCPU
, parent_obj
);
437 return &arch_cpu
->neg
;
442 * @env: The architecture environment
444 * Return the CPUTLB state associated with the environment.
446 static inline CPUTLB
*env_tlb(CPUArchState
*env
)
448 return &env_neg(env
)->tlb
;
451 #endif /* CPU_ALL_H */