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vfio: Enable sparse mmap capability
[qemu/ar7.git] / target-ppc / translate.c
blob745f4de98f18d12ff6d2cf1362b6a9cc7e4806f5
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 int mem_idx;
197 int access_type;
198 /* Translation flags */
199 int le_mode;
200 TCGMemOp default_tcg_memop_mask;
201 #if defined(TARGET_PPC64)
202 int sf_mode;
203 int has_cfar;
204 #endif
205 int fpu_enabled;
206 int altivec_enabled;
207 int vsx_enabled;
208 int spe_enabled;
209 int tm_enabled;
210 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
211 int singlestep_enabled;
212 uint64_t insns_flags;
213 uint64_t insns_flags2;
214 };
215
216 /* Return true iff byteswap is needed in a scalar memop */
217 static inline bool need_byteswap(const DisasContext *ctx)
218 {
219 #if defined(TARGET_WORDS_BIGENDIAN)
220 return ctx->le_mode;
221 #else
222 return !ctx->le_mode;
223 #endif
224 }
225
226 /* True when active word size < size of target_long. */
227 #ifdef TARGET_PPC64
228 # define NARROW_MODE(C) (!(C)->sf_mode)
229 #else
230 # define NARROW_MODE(C) 0
231 #endif
232
233 struct opc_handler_t {
234 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
235 uint32_t inval1;
236 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
237 uint32_t inval2;
238 /* instruction type */
239 uint64_t type;
240 /* extended instruction type */
241 uint64_t type2;
242 /* handler */
243 void (*handler)(DisasContext *ctx);
244 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
245 const char *oname;
246 #endif
247 #if defined(DO_PPC_STATISTICS)
248 uint64_t count;
249 #endif
250 };
251
252 static inline void gen_reset_fpstatus(void)
253 {
254 gen_helper_reset_fpstatus(cpu_env);
255 }
256
257 static inline void gen_compute_fprf(TCGv_i64 arg)
258 {
259 gen_helper_compute_fprf(cpu_env, arg);
260 gen_helper_float_check_status(cpu_env);
261 }
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 void gen_update_current_nip(void *opaque)
280 {
281 DisasContext *ctx = opaque;
282
283 tcg_gen_movi_tl(cpu_nip, ctx->nip);
284 }
285
286 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
287 {
288 TCGv_i32 t0, t1;
289 if (ctx->exception == POWERPC_EXCP_NONE) {
290 gen_update_nip(ctx, ctx->nip);
291 }
292 t0 = tcg_const_i32(excp);
293 t1 = tcg_const_i32(error);
294 gen_helper_raise_exception_err(cpu_env, t0, t1);
295 tcg_temp_free_i32(t0);
296 tcg_temp_free_i32(t1);
297 ctx->exception = (excp);
298 }
299
300 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
301 {
302 TCGv_i32 t0;
303 if (ctx->exception == POWERPC_EXCP_NONE) {
304 gen_update_nip(ctx, ctx->nip);
305 }
306 t0 = tcg_const_i32(excp);
307 gen_helper_raise_exception(cpu_env, t0);
308 tcg_temp_free_i32(t0);
309 ctx->exception = (excp);
310 }
311
312 static inline void gen_debug_exception(DisasContext *ctx)
313 {
314 TCGv_i32 t0;
315
316 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
317 (ctx->exception != POWERPC_EXCP_SYNC)) {
318 gen_update_nip(ctx, ctx->nip);
319 }
320 t0 = tcg_const_i32(EXCP_DEBUG);
321 gen_helper_raise_exception(cpu_env, t0);
322 tcg_temp_free_i32(t0);
323 }
324
325 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
326 {
327 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
328 }
329
330 /* Stop translation */
331 static inline void gen_stop_exception(DisasContext *ctx)
332 {
333 gen_update_nip(ctx, ctx->nip);
334 ctx->exception = POWERPC_EXCP_STOP;
335 }
336
337 #ifndef CONFIG_USER_ONLY
338 /* No need to update nip here, as execution flow will change */
339 static inline void gen_sync_exception(DisasContext *ctx)
340 {
341 ctx->exception = POWERPC_EXCP_SYNC;
342 }
343 #endif
344
345 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
350
351 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
356
357 typedef struct opcode_t {
358 unsigned char opc1, opc2, opc3;
359 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
360 unsigned char pad[5];
361 #else
362 unsigned char pad[1];
363 #endif
364 opc_handler_t handler;
365 const char *oname;
366 } opcode_t;
367
368 /*****************************************************************************/
369 /*** Instruction decoding ***/
370 #define EXTRACT_HELPER(name, shift, nb) \
371 static inline uint32_t name(uint32_t opcode) \
372 { \
373 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
374 }
375
376 #define EXTRACT_SHELPER(name, shift, nb) \
377 static inline int32_t name(uint32_t opcode) \
378 { \
379 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
380 }
381
382 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
383 static inline uint32_t name(uint32_t opcode) \
384 { \
385 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
386 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
387 }
388 /* Opcode part 1 */
389 EXTRACT_HELPER(opc1, 26, 6);
390 /* Opcode part 2 */
391 EXTRACT_HELPER(opc2, 1, 5);
392 /* Opcode part 3 */
393 EXTRACT_HELPER(opc3, 6, 5);
394 /* Update Cr0 flags */
395 EXTRACT_HELPER(Rc, 0, 1);
396 /* Update Cr6 flags (Altivec) */
397 EXTRACT_HELPER(Rc21, 10, 1);
398 /* Destination */
399 EXTRACT_HELPER(rD, 21, 5);
400 /* Source */
401 EXTRACT_HELPER(rS, 21, 5);
402 /* First operand */
403 EXTRACT_HELPER(rA, 16, 5);
404 /* Second operand */
405 EXTRACT_HELPER(rB, 11, 5);
406 /* Third operand */
407 EXTRACT_HELPER(rC, 6, 5);
408 /*** Get CRn ***/
409 EXTRACT_HELPER(crfD, 23, 3);
410 EXTRACT_HELPER(crfS, 18, 3);
411 EXTRACT_HELPER(crbD, 21, 5);
412 EXTRACT_HELPER(crbA, 16, 5);
413 EXTRACT_HELPER(crbB, 11, 5);
414 /* SPR / TBL */
415 EXTRACT_HELPER(_SPR, 11, 10);
416 static inline uint32_t SPR(uint32_t opcode)
417 {
418 uint32_t sprn = _SPR(opcode);
419
420 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
421 }
422 /*** Get constants ***/
423 /* 16 bits signed immediate value */
424 EXTRACT_SHELPER(SIMM, 0, 16);
425 /* 16 bits unsigned immediate value */
426 EXTRACT_HELPER(UIMM, 0, 16);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(SIMM5, 16, 5);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(UIMM5, 16, 5);
431 /* Bit count */
432 EXTRACT_HELPER(NB, 11, 5);
433 /* Shift count */
434 EXTRACT_HELPER(SH, 11, 5);
435 /* Vector shift count */
436 EXTRACT_HELPER(VSH, 6, 4);
437 /* Mask start */
438 EXTRACT_HELPER(MB, 6, 5);
439 /* Mask end */
440 EXTRACT_HELPER(ME, 1, 5);
441 /* Trap operand */
442 EXTRACT_HELPER(TO, 21, 5);
443
444 EXTRACT_HELPER(CRM, 12, 8);
445
446 #ifndef CONFIG_USER_ONLY
447 EXTRACT_HELPER(SR, 16, 4);
448 #endif
449
450 /* mtfsf/mtfsfi */
451 EXTRACT_HELPER(FPBF, 23, 3);
452 EXTRACT_HELPER(FPIMM, 12, 4);
453 EXTRACT_HELPER(FPL, 25, 1);
454 EXTRACT_HELPER(FPFLM, 17, 8);
455 EXTRACT_HELPER(FPW, 16, 1);
456
457 /*** Jump target decoding ***/
458 /* Immediate address */
459 static inline target_ulong LI(uint32_t opcode)
460 {
461 return (opcode >> 0) & 0x03FFFFFC;
462 }
463
464 static inline uint32_t BD(uint32_t opcode)
465 {
466 return (opcode >> 0) & 0xFFFC;
467 }
468
469 EXTRACT_HELPER(BO, 21, 5);
470 EXTRACT_HELPER(BI, 16, 5);
471 /* Absolute/relative address */
472 EXTRACT_HELPER(AA, 1, 1);
473 /* Link */
474 EXTRACT_HELPER(LK, 0, 1);
475
476 /* DFP Z22-form */
477 EXTRACT_HELPER(DCM, 10, 6)
478
479 /* DFP Z23-form */
480 EXTRACT_HELPER(RMC, 9, 2)
481
482 /* Create a mask between <start> and <end> bits */
483 static inline target_ulong MASK(uint32_t start, uint32_t end)
484 {
485 target_ulong ret;
486
487 #if defined(TARGET_PPC64)
488 if (likely(start == 0)) {
489 ret = UINT64_MAX << (63 - end);
490 } else if (likely(end == 63)) {
491 ret = UINT64_MAX >> start;
492 }
493 #else
494 if (likely(start == 0)) {
495 ret = UINT32_MAX << (31 - end);
496 } else if (likely(end == 31)) {
497 ret = UINT32_MAX >> start;
498 }
499 #endif
500 else {
501 ret = (((target_ulong)(-1ULL)) >> (start)) ^
502 (((target_ulong)(-1ULL) >> (end)) >> 1);
503 if (unlikely(start > end))
504 return ~ret;
505 }
506
507 return ret;
508 }
509
510 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
511 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
513 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
514 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
515 EXTRACT_HELPER(DM, 8, 2);
516 EXTRACT_HELPER(UIM, 16, 2);
517 EXTRACT_HELPER(SHW, 8, 2);
518 EXTRACT_HELPER(SP, 19, 2);
519 /*****************************************************************************/
520 /* PowerPC instructions table */
521
522 #if defined(DO_PPC_STATISTICS)
523 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl, \
531 .type = _typ, \
532 .type2 = _typ2, \
533 .handler = &gen_##name, \
534 .oname = stringify(name), \
535 }, \
536 .oname = stringify(name), \
537 }
538 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
539 { \
540 .opc1 = op1, \
541 .opc2 = op2, \
542 .opc3 = op3, \
543 .pad = { 0, }, \
544 .handler = { \
545 .inval1 = invl1, \
546 .inval2 = invl2, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = stringify(name), \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 .oname = onam, \
566 }, \
567 .oname = onam, \
568 }
569 #else
570 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .pad = { 0, }, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl1, \
592 .inval2 = invl2, \
593 .type = _typ, \
594 .type2 = _typ2, \
595 .handler = &gen_##name, \
596 }, \
597 .oname = stringify(name), \
598 }
599 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
600 { \
601 .opc1 = op1, \
602 .opc2 = op2, \
603 .opc3 = op3, \
604 .pad = { 0, }, \
605 .handler = { \
606 .inval1 = invl, \
607 .type = _typ, \
608 .type2 = _typ2, \
609 .handler = &gen_##name, \
610 }, \
611 .oname = onam, \
612 }
613 #endif
614
615 /* SPR load/store helpers */
616 static inline void gen_load_spr(TCGv t, int reg)
617 {
618 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
619 }
620
621 static inline void gen_store_spr(int reg, TCGv t)
622 {
623 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
624 }
625
626 /* Invalid instruction */
627 static void gen_invalid(DisasContext *ctx)
628 {
629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
630 }
631
632 static opc_handler_t invalid_handler = {
633 .inval1 = 0xFFFFFFFF,
634 .inval2 = 0xFFFFFFFF,
635 .type = PPC_NONE,
636 .type2 = PPC_NONE,
637 .handler = gen_invalid,
638 };
639
640 /*** Integer comparison ***/
641
642 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
643 {
644 TCGv t0 = tcg_temp_new();
645 TCGv_i32 t1 = tcg_temp_new_i32();
646
647 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
648
649 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
650 tcg_gen_trunc_tl_i32(t1, t0);
651 tcg_gen_shli_i32(t1, t1, CRF_LT);
652 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
653
654 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
655 tcg_gen_trunc_tl_i32(t1, t0);
656 tcg_gen_shli_i32(t1, t1, CRF_GT);
657 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
658
659 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
660 tcg_gen_trunc_tl_i32(t1, t0);
661 tcg_gen_shli_i32(t1, t1, CRF_EQ);
662 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
663
664 tcg_temp_free(t0);
665 tcg_temp_free_i32(t1);
666 }
667
668 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
669 {
670 TCGv t0 = tcg_const_tl(arg1);
671 gen_op_cmp(arg0, t0, s, crf);
672 tcg_temp_free(t0);
673 }
674
675 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
676 {
677 TCGv t0, t1;
678 t0 = tcg_temp_new();
679 t1 = tcg_temp_new();
680 if (s) {
681 tcg_gen_ext32s_tl(t0, arg0);
682 tcg_gen_ext32s_tl(t1, arg1);
683 } else {
684 tcg_gen_ext32u_tl(t0, arg0);
685 tcg_gen_ext32u_tl(t1, arg1);
686 }
687 gen_op_cmp(t0, t1, s, crf);
688 tcg_temp_free(t1);
689 tcg_temp_free(t0);
690 }
691
692 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
693 {
694 TCGv t0 = tcg_const_tl(arg1);
695 gen_op_cmp32(arg0, t0, s, crf);
696 tcg_temp_free(t0);
697 }
698
699 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
700 {
701 if (NARROW_MODE(ctx)) {
702 gen_op_cmpi32(reg, 0, 1, 0);
703 } else {
704 gen_op_cmpi(reg, 0, 1, 0);
705 }
706 }
707
708 /* cmp */
709 static void gen_cmp(DisasContext *ctx)
710 {
711 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
714 } else {
715 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
716 1, crfD(ctx->opcode));
717 }
718 }
719
720 /* cmpi */
721 static void gen_cmpi(DisasContext *ctx)
722 {
723 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
724 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
726 } else {
727 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
728 1, crfD(ctx->opcode));
729 }
730 }
731
732 /* cmpl */
733 static void gen_cmpl(DisasContext *ctx)
734 {
735 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
736 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
738 } else {
739 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
740 0, crfD(ctx->opcode));
741 }
742 }
743
744 /* cmpli */
745 static void gen_cmpli(DisasContext *ctx)
746 {
747 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
748 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
750 } else {
751 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
752 0, crfD(ctx->opcode));
753 }
754 }
755
756 /* isel (PowerPC 2.03 specification) */
757 static void gen_isel(DisasContext *ctx)
758 {
759 TCGLabel *l1, *l2;
760 uint32_t bi = rC(ctx->opcode);
761 uint32_t mask;
762 TCGv_i32 t0;
763
764 l1 = gen_new_label();
765 l2 = gen_new_label();
766
767 mask = 0x08 >> (bi & 0x03);
768 t0 = tcg_temp_new_i32();
769 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
770 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
771 if (rA(ctx->opcode) == 0)
772 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
773 else
774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
775 tcg_gen_br(l2);
776 gen_set_label(l1);
777 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
778 gen_set_label(l2);
779 tcg_temp_free_i32(t0);
780 }
781
782 /* cmpb: PowerPC 2.05 specification */
783 static void gen_cmpb(DisasContext *ctx)
784 {
785 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
786 cpu_gpr[rB(ctx->opcode)]);
787 }
788
789 /*** Integer arithmetic ***/
790
791 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
792 TCGv arg1, TCGv arg2, int sub)
793 {
794 TCGv t0 = tcg_temp_new();
795
796 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
797 tcg_gen_xor_tl(t0, arg1, arg2);
798 if (sub) {
799 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
800 } else {
801 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
802 }
803 tcg_temp_free(t0);
804 if (NARROW_MODE(ctx)) {
805 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
806 }
807 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
808 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
809 }
810
811 /* Common add function */
812 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
813 TCGv arg2, bool add_ca, bool compute_ca,
814 bool compute_ov, bool compute_rc0)
815 {
816 TCGv t0 = ret;
817
818 if (compute_ca || compute_ov) {
819 t0 = tcg_temp_new();
820 }
821
822 if (compute_ca) {
823 if (NARROW_MODE(ctx)) {
824 /* Caution: a non-obvious corner case of the spec is that we
825 must produce the *entire* 64-bit addition, but produce the
826 carry into bit 32. */
827 TCGv t1 = tcg_temp_new();
828 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
829 tcg_gen_add_tl(t0, arg1, arg2);
830 if (add_ca) {
831 tcg_gen_add_tl(t0, t0, cpu_ca);
832 }
833 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
834 tcg_temp_free(t1);
835 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
836 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
837 } else {
838 TCGv zero = tcg_const_tl(0);
839 if (add_ca) {
840 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
841 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
842 } else {
843 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
844 }
845 tcg_temp_free(zero);
846 }
847 } else {
848 tcg_gen_add_tl(t0, arg1, arg2);
849 if (add_ca) {
850 tcg_gen_add_tl(t0, t0, cpu_ca);
851 }
852 }
853
854 if (compute_ov) {
855 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
856 }
857 if (unlikely(compute_rc0)) {
858 gen_set_Rc0(ctx, t0);
859 }
860
861 if (!TCGV_EQUAL(t0, ret)) {
862 tcg_gen_mov_tl(ret, t0);
863 tcg_temp_free(t0);
864 }
865 }
866 /* Add functions with two operands */
867 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
868 static void glue(gen_, name)(DisasContext *ctx) \
869 { \
870 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
871 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
872 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
873 }
874 /* Add functions with one operand and one immediate */
875 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
876 add_ca, compute_ca, compute_ov) \
877 static void glue(gen_, name)(DisasContext *ctx) \
878 { \
879 TCGv t0 = tcg_const_tl(const_val); \
880 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
881 cpu_gpr[rA(ctx->opcode)], t0, \
882 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
883 tcg_temp_free(t0); \
884 }
885
886 /* add add. addo addo. */
887 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
888 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
889 /* addc addc. addco addco. */
890 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
891 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
892 /* adde adde. addeo addeo. */
893 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
894 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
895 /* addme addme. addmeo addmeo. */
896 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
897 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
898 /* addze addze. addzeo addzeo.*/
899 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
900 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
901 /* addi */
902 static void gen_addi(DisasContext *ctx)
903 {
904 target_long simm = SIMM(ctx->opcode);
905
906 if (rA(ctx->opcode) == 0) {
907 /* li case */
908 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
909 } else {
910 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
911 cpu_gpr[rA(ctx->opcode)], simm);
912 }
913 }
914 /* addic addic.*/
915 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
916 {
917 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
918 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
919 c, 0, 1, 0, compute_rc0);
920 tcg_temp_free(c);
921 }
922
923 static void gen_addic(DisasContext *ctx)
924 {
925 gen_op_addic(ctx, 0);
926 }
927
928 static void gen_addic_(DisasContext *ctx)
929 {
930 gen_op_addic(ctx, 1);
931 }
932
933 /* addis */
934 static void gen_addis(DisasContext *ctx)
935 {
936 target_long simm = SIMM(ctx->opcode);
937
938 if (rA(ctx->opcode) == 0) {
939 /* lis case */
940 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
941 } else {
942 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
943 cpu_gpr[rA(ctx->opcode)], simm << 16);
944 }
945 }
946
947 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
948 TCGv arg2, int sign, int compute_ov)
949 {
950 TCGLabel *l1 = gen_new_label();
951 TCGLabel *l2 = gen_new_label();
952 TCGv_i32 t0 = tcg_temp_local_new_i32();
953 TCGv_i32 t1 = tcg_temp_local_new_i32();
954
955 tcg_gen_trunc_tl_i32(t0, arg1);
956 tcg_gen_trunc_tl_i32(t1, arg2);
957 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
958 if (sign) {
959 TCGLabel *l3 = gen_new_label();
960 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
961 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
962 gen_set_label(l3);
963 tcg_gen_div_i32(t0, t0, t1);
964 } else {
965 tcg_gen_divu_i32(t0, t0, t1);
966 }
967 if (compute_ov) {
968 tcg_gen_movi_tl(cpu_ov, 0);
969 }
970 tcg_gen_br(l2);
971 gen_set_label(l1);
972 if (sign) {
973 tcg_gen_sari_i32(t0, t0, 31);
974 } else {
975 tcg_gen_movi_i32(t0, 0);
976 }
977 if (compute_ov) {
978 tcg_gen_movi_tl(cpu_ov, 1);
979 tcg_gen_movi_tl(cpu_so, 1);
980 }
981 gen_set_label(l2);
982 tcg_gen_extu_i32_tl(ret, t0);
983 tcg_temp_free_i32(t0);
984 tcg_temp_free_i32(t1);
985 if (unlikely(Rc(ctx->opcode) != 0))
986 gen_set_Rc0(ctx, ret);
987 }
988 /* Div functions */
989 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
990 static void glue(gen_, name)(DisasContext *ctx) \
991 { \
992 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
994 sign, compute_ov); \
995 }
996 /* divwu divwu. divwuo divwuo. */
997 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
998 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
999 /* divw divw. divwo divwo. */
1000 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1001 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1002
1003 /* div[wd]eu[o][.] */
1004 #define GEN_DIVE(name, hlpr, compute_ov) \
1005 static void gen_##name(DisasContext *ctx) \
1006 { \
1007 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1008 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1009 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1010 tcg_temp_free_i32(t0); \
1011 if (unlikely(Rc(ctx->opcode) != 0)) { \
1012 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1013 } \
1014 }
1015
1016 GEN_DIVE(divweu, divweu, 0);
1017 GEN_DIVE(divweuo, divweu, 1);
1018 GEN_DIVE(divwe, divwe, 0);
1019 GEN_DIVE(divweo, divwe, 1);
1020
1021 #if defined(TARGET_PPC64)
1022 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1023 TCGv arg2, int sign, int compute_ov)
1024 {
1025 TCGLabel *l1 = gen_new_label();
1026 TCGLabel *l2 = gen_new_label();
1027
1028 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1029 if (sign) {
1030 TCGLabel *l3 = gen_new_label();
1031 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1032 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1033 gen_set_label(l3);
1034 tcg_gen_div_i64(ret, arg1, arg2);
1035 } else {
1036 tcg_gen_divu_i64(ret, arg1, arg2);
1037 }
1038 if (compute_ov) {
1039 tcg_gen_movi_tl(cpu_ov, 0);
1040 }
1041 tcg_gen_br(l2);
1042 gen_set_label(l1);
1043 if (sign) {
1044 tcg_gen_sari_i64(ret, arg1, 63);
1045 } else {
1046 tcg_gen_movi_i64(ret, 0);
1047 }
1048 if (compute_ov) {
1049 tcg_gen_movi_tl(cpu_ov, 1);
1050 tcg_gen_movi_tl(cpu_so, 1);
1051 }
1052 gen_set_label(l2);
1053 if (unlikely(Rc(ctx->opcode) != 0))
1054 gen_set_Rc0(ctx, ret);
1055 }
1056 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1057 static void glue(gen_, name)(DisasContext *ctx) \
1058 { \
1059 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1060 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1061 sign, compute_ov); \
1062 }
1063 /* divwu divwu. divwuo divwuo. */
1064 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1065 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1066 /* divw divw. divwo divwo. */
1067 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1068 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1069
1070 GEN_DIVE(divdeu, divdeu, 0);
1071 GEN_DIVE(divdeuo, divdeu, 1);
1072 GEN_DIVE(divde, divde, 0);
1073 GEN_DIVE(divdeo, divde, 1);
1074 #endif
1075
1076 /* mulhw mulhw. */
1077 static void gen_mulhw(DisasContext *ctx)
1078 {
1079 TCGv_i32 t0 = tcg_temp_new_i32();
1080 TCGv_i32 t1 = tcg_temp_new_i32();
1081
1082 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1083 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1084 tcg_gen_muls2_i32(t0, t1, t0, t1);
1085 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1086 tcg_temp_free_i32(t0);
1087 tcg_temp_free_i32(t1);
1088 if (unlikely(Rc(ctx->opcode) != 0))
1089 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1090 }
1091
1092 /* mulhwu mulhwu. */
1093 static void gen_mulhwu(DisasContext *ctx)
1094 {
1095 TCGv_i32 t0 = tcg_temp_new_i32();
1096 TCGv_i32 t1 = tcg_temp_new_i32();
1097
1098 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1099 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1100 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1101 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i32(t1);
1104 if (unlikely(Rc(ctx->opcode) != 0))
1105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1106 }
1107
1108 /* mullw mullw. */
1109 static void gen_mullw(DisasContext *ctx)
1110 {
1111 #if defined(TARGET_PPC64)
1112 TCGv_i64 t0, t1;
1113 t0 = tcg_temp_new_i64();
1114 t1 = tcg_temp_new_i64();
1115 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1117 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1118 tcg_temp_free(t0);
1119 tcg_temp_free(t1);
1120 #else
1121 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1122 cpu_gpr[rB(ctx->opcode)]);
1123 #endif
1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1126 }
1127
1128 /* mullwo mullwo. */
1129 static void gen_mullwo(DisasContext *ctx)
1130 {
1131 TCGv_i32 t0 = tcg_temp_new_i32();
1132 TCGv_i32 t1 = tcg_temp_new_i32();
1133
1134 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1135 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1136 tcg_gen_muls2_i32(t0, t1, t0, t1);
1137 #if defined(TARGET_PPC64)
1138 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1139 #else
1140 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1141 #endif
1142
1143 tcg_gen_sari_i32(t0, t0, 31);
1144 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1145 tcg_gen_extu_i32_tl(cpu_ov, t0);
1146 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1147
1148 tcg_temp_free_i32(t0);
1149 tcg_temp_free_i32(t1);
1150 if (unlikely(Rc(ctx->opcode) != 0))
1151 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1152 }
1153
1154 /* mulli */
1155 static void gen_mulli(DisasContext *ctx)
1156 {
1157 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1158 SIMM(ctx->opcode));
1159 }
1160
1161 #if defined(TARGET_PPC64)
1162 /* mulhd mulhd. */
1163 static void gen_mulhd(DisasContext *ctx)
1164 {
1165 TCGv lo = tcg_temp_new();
1166 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1168 tcg_temp_free(lo);
1169 if (unlikely(Rc(ctx->opcode) != 0)) {
1170 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1171 }
1172 }
1173
1174 /* mulhdu mulhdu. */
1175 static void gen_mulhdu(DisasContext *ctx)
1176 {
1177 TCGv lo = tcg_temp_new();
1178 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1179 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1180 tcg_temp_free(lo);
1181 if (unlikely(Rc(ctx->opcode) != 0)) {
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183 }
1184 }
1185
1186 /* mulld mulld. */
1187 static void gen_mulld(DisasContext *ctx)
1188 {
1189 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1190 cpu_gpr[rB(ctx->opcode)]);
1191 if (unlikely(Rc(ctx->opcode) != 0))
1192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1193 }
1194
1195 /* mulldo mulldo. */
1196 static void gen_mulldo(DisasContext *ctx)
1197 {
1198 TCGv_i64 t0 = tcg_temp_new_i64();
1199 TCGv_i64 t1 = tcg_temp_new_i64();
1200
1201 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1202 cpu_gpr[rB(ctx->opcode)]);
1203 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1204
1205 tcg_gen_sari_i64(t0, t0, 63);
1206 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1207 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1208
1209 tcg_temp_free_i64(t0);
1210 tcg_temp_free_i64(t1);
1211
1212 if (unlikely(Rc(ctx->opcode) != 0)) {
1213 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1214 }
1215 }
1216 #endif
1217
1218 /* Common subf function */
1219 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1220 TCGv arg2, bool add_ca, bool compute_ca,
1221 bool compute_ov, bool compute_rc0)
1222 {
1223 TCGv t0 = ret;
1224
1225 if (compute_ca || compute_ov) {
1226 t0 = tcg_temp_new();
1227 }
1228
1229 if (compute_ca) {
1230 /* dest = ~arg1 + arg2 [+ ca]. */
1231 if (NARROW_MODE(ctx)) {
1232 /* Caution: a non-obvious corner case of the spec is that we
1233 must produce the *entire* 64-bit addition, but produce the
1234 carry into bit 32. */
1235 TCGv inv1 = tcg_temp_new();
1236 TCGv t1 = tcg_temp_new();
1237 tcg_gen_not_tl(inv1, arg1);
1238 if (add_ca) {
1239 tcg_gen_add_tl(t0, arg2, cpu_ca);
1240 } else {
1241 tcg_gen_addi_tl(t0, arg2, 1);
1242 }
1243 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1244 tcg_gen_add_tl(t0, t0, inv1);
1245 tcg_temp_free(inv1);
1246 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1247 tcg_temp_free(t1);
1248 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1249 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1250 } else if (add_ca) {
1251 TCGv zero, inv1 = tcg_temp_new();
1252 tcg_gen_not_tl(inv1, arg1);
1253 zero = tcg_const_tl(0);
1254 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1255 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1256 tcg_temp_free(zero);
1257 tcg_temp_free(inv1);
1258 } else {
1259 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1260 tcg_gen_sub_tl(t0, arg2, arg1);
1261 }
1262 } else if (add_ca) {
1263 /* Since we're ignoring carry-out, we can simplify the
1264 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1265 tcg_gen_sub_tl(t0, arg2, arg1);
1266 tcg_gen_add_tl(t0, t0, cpu_ca);
1267 tcg_gen_subi_tl(t0, t0, 1);
1268 } else {
1269 tcg_gen_sub_tl(t0, arg2, arg1);
1270 }
1271
1272 if (compute_ov) {
1273 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1274 }
1275 if (unlikely(compute_rc0)) {
1276 gen_set_Rc0(ctx, t0);
1277 }
1278
1279 if (!TCGV_EQUAL(t0, ret)) {
1280 tcg_gen_mov_tl(ret, t0);
1281 tcg_temp_free(t0);
1282 }
1283 }
1284 /* Sub functions with Two operands functions */
1285 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1286 static void glue(gen_, name)(DisasContext *ctx) \
1287 { \
1288 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1289 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1290 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1291 }
1292 /* Sub functions with one operand and one immediate */
1293 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1294 add_ca, compute_ca, compute_ov) \
1295 static void glue(gen_, name)(DisasContext *ctx) \
1296 { \
1297 TCGv t0 = tcg_const_tl(const_val); \
1298 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1299 cpu_gpr[rA(ctx->opcode)], t0, \
1300 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1301 tcg_temp_free(t0); \
1302 }
1303 /* subf subf. subfo subfo. */
1304 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1305 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1306 /* subfc subfc. subfco subfco. */
1307 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1308 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1309 /* subfe subfe. subfeo subfo. */
1310 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1312 /* subfme subfme. subfmeo subfmeo. */
1313 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1314 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1315 /* subfze subfze. subfzeo subfzeo.*/
1316 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1317 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1318
1319 /* subfic */
1320 static void gen_subfic(DisasContext *ctx)
1321 {
1322 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1323 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1324 c, 0, 1, 0, 0);
1325 tcg_temp_free(c);
1326 }
1327
1328 /* neg neg. nego nego. */
1329 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1330 {
1331 TCGv zero = tcg_const_tl(0);
1332 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1333 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1334 tcg_temp_free(zero);
1335 }
1336
1337 static void gen_neg(DisasContext *ctx)
1338 {
1339 gen_op_arith_neg(ctx, 0);
1340 }
1341
1342 static void gen_nego(DisasContext *ctx)
1343 {
1344 gen_op_arith_neg(ctx, 1);
1345 }
1346
1347 /*** Integer logical ***/
1348 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1349 static void glue(gen_, name)(DisasContext *ctx) \
1350 { \
1351 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1352 cpu_gpr[rB(ctx->opcode)]); \
1353 if (unlikely(Rc(ctx->opcode) != 0)) \
1354 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1355 }
1356
1357 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1358 static void glue(gen_, name)(DisasContext *ctx) \
1359 { \
1360 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1361 if (unlikely(Rc(ctx->opcode) != 0)) \
1362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1363 }
1364
1365 /* and & and. */
1366 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1367 /* andc & andc. */
1368 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1369
1370 /* andi. */
1371 static void gen_andi_(DisasContext *ctx)
1372 {
1373 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1375 }
1376
1377 /* andis. */
1378 static void gen_andis_(DisasContext *ctx)
1379 {
1380 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1382 }
1383
1384 /* cntlzw */
1385 static void gen_cntlzw(DisasContext *ctx)
1386 {
1387 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1388 if (unlikely(Rc(ctx->opcode) != 0))
1389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1390 }
1391 /* eqv & eqv. */
1392 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1393 /* extsb & extsb. */
1394 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1395 /* extsh & extsh. */
1396 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1397 /* nand & nand. */
1398 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1399 /* nor & nor. */
1400 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1401
1402 /* or & or. */
1403 static void gen_or(DisasContext *ctx)
1404 {
1405 int rs, ra, rb;
1406
1407 rs = rS(ctx->opcode);
1408 ra = rA(ctx->opcode);
1409 rb = rB(ctx->opcode);
1410 /* Optimisation for mr. ri case */
1411 if (rs != ra || rs != rb) {
1412 if (rs != rb)
1413 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1414 else
1415 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1416 if (unlikely(Rc(ctx->opcode) != 0))
1417 gen_set_Rc0(ctx, cpu_gpr[ra]);
1418 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1419 gen_set_Rc0(ctx, cpu_gpr[rs]);
1420 #if defined(TARGET_PPC64)
1421 } else {
1422 int prio = 0;
1423
1424 switch (rs) {
1425 case 1:
1426 /* Set process priority to low */
1427 prio = 2;
1428 break;
1429 case 6:
1430 /* Set process priority to medium-low */
1431 prio = 3;
1432 break;
1433 case 2:
1434 /* Set process priority to normal */
1435 prio = 4;
1436 break;
1437 #if !defined(CONFIG_USER_ONLY)
1438 case 31:
1439 if (!ctx->pr) {
1440 /* Set process priority to very low */
1441 prio = 1;
1442 }
1443 break;
1444 case 5:
1445 if (!ctx->pr) {
1446 /* Set process priority to medium-hight */
1447 prio = 5;
1448 }
1449 break;
1450 case 3:
1451 if (!ctx->pr) {
1452 /* Set process priority to high */
1453 prio = 6;
1454 }
1455 break;
1456 case 7:
1457 if (ctx->hv) {
1458 /* Set process priority to very high */
1459 prio = 7;
1460 }
1461 break;
1462 #endif
1463 default:
1464 /* nop */
1465 break;
1466 }
1467 if (prio) {
1468 TCGv t0 = tcg_temp_new();
1469 gen_load_spr(t0, SPR_PPR);
1470 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1471 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1472 gen_store_spr(SPR_PPR, t0);
1473 tcg_temp_free(t0);
1474 }
1475 #endif
1476 }
1477 }
1478 /* orc & orc. */
1479 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1480
1481 /* xor & xor. */
1482 static void gen_xor(DisasContext *ctx)
1483 {
1484 /* Optimisation for "set to zero" case */
1485 if (rS(ctx->opcode) != rB(ctx->opcode))
1486 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1487 else
1488 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1489 if (unlikely(Rc(ctx->opcode) != 0))
1490 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1491 }
1492
1493 /* ori */
1494 static void gen_ori(DisasContext *ctx)
1495 {
1496 target_ulong uimm = UIMM(ctx->opcode);
1497
1498 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1499 /* NOP */
1500 /* XXX: should handle special NOPs for POWER series */
1501 return;
1502 }
1503 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1504 }
1505
1506 /* oris */
1507 static void gen_oris(DisasContext *ctx)
1508 {
1509 target_ulong uimm = UIMM(ctx->opcode);
1510
1511 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1512 /* NOP */
1513 return;
1514 }
1515 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1516 }
1517
1518 /* xori */
1519 static void gen_xori(DisasContext *ctx)
1520 {
1521 target_ulong uimm = UIMM(ctx->opcode);
1522
1523 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1524 /* NOP */
1525 return;
1526 }
1527 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1528 }
1529
1530 /* xoris */
1531 static void gen_xoris(DisasContext *ctx)
1532 {
1533 target_ulong uimm = UIMM(ctx->opcode);
1534
1535 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1536 /* NOP */
1537 return;
1538 }
1539 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1540 }
1541
1542 /* popcntb : PowerPC 2.03 specification */
1543 static void gen_popcntb(DisasContext *ctx)
1544 {
1545 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1546 }
1547
1548 static void gen_popcntw(DisasContext *ctx)
1549 {
1550 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1551 }
1552
1553 #if defined(TARGET_PPC64)
1554 /* popcntd: PowerPC 2.06 specification */
1555 static void gen_popcntd(DisasContext *ctx)
1556 {
1557 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1558 }
1559 #endif
1560
1561 /* prtyw: PowerPC 2.05 specification */
1562 static void gen_prtyw(DisasContext *ctx)
1563 {
1564 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1565 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1566 TCGv t0 = tcg_temp_new();
1567 tcg_gen_shri_tl(t0, rs, 16);
1568 tcg_gen_xor_tl(ra, rs, t0);
1569 tcg_gen_shri_tl(t0, ra, 8);
1570 tcg_gen_xor_tl(ra, ra, t0);
1571 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1572 tcg_temp_free(t0);
1573 }
1574
1575 #if defined(TARGET_PPC64)
1576 /* prtyd: PowerPC 2.05 specification */
1577 static void gen_prtyd(DisasContext *ctx)
1578 {
1579 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1580 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1581 TCGv t0 = tcg_temp_new();
1582 tcg_gen_shri_tl(t0, rs, 32);
1583 tcg_gen_xor_tl(ra, rs, t0);
1584 tcg_gen_shri_tl(t0, ra, 16);
1585 tcg_gen_xor_tl(ra, ra, t0);
1586 tcg_gen_shri_tl(t0, ra, 8);
1587 tcg_gen_xor_tl(ra, ra, t0);
1588 tcg_gen_andi_tl(ra, ra, 1);
1589 tcg_temp_free(t0);
1590 }
1591 #endif
1592
1593 #if defined(TARGET_PPC64)
1594 /* bpermd */
1595 static void gen_bpermd(DisasContext *ctx)
1596 {
1597 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1598 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1599 }
1600 #endif
1601
1602 #if defined(TARGET_PPC64)
1603 /* extsw & extsw. */
1604 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1605
1606 /* cntlzd */
1607 static void gen_cntlzd(DisasContext *ctx)
1608 {
1609 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613 #endif
1614
1615 /*** Integer rotate ***/
1616
1617 /* rlwimi & rlwimi. */
1618 static void gen_rlwimi(DisasContext *ctx)
1619 {
1620 uint32_t mb, me, sh;
1621
1622 mb = MB(ctx->opcode);
1623 me = ME(ctx->opcode);
1624 sh = SH(ctx->opcode);
1625 if (likely(sh == (31-me) && mb <= me)) {
1626 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1627 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1628 } else {
1629 target_ulong mask;
1630 TCGv t1;
1631 TCGv t0 = tcg_temp_new();
1632 #if defined(TARGET_PPC64)
1633 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1634 cpu_gpr[rS(ctx->opcode)], 32, 32);
1635 tcg_gen_rotli_i64(t0, t0, sh);
1636 #else
1637 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1638 #endif
1639 #if defined(TARGET_PPC64)
1640 mb += 32;
1641 me += 32;
1642 #endif
1643 mask = MASK(mb, me);
1644 t1 = tcg_temp_new();
1645 tcg_gen_andi_tl(t0, t0, mask);
1646 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1647 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1648 tcg_temp_free(t0);
1649 tcg_temp_free(t1);
1650 }
1651 if (unlikely(Rc(ctx->opcode) != 0))
1652 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1653 }
1654
1655 /* rlwinm & rlwinm. */
1656 static void gen_rlwinm(DisasContext *ctx)
1657 {
1658 uint32_t mb, me, sh;
1659
1660 sh = SH(ctx->opcode);
1661 mb = MB(ctx->opcode);
1662 me = ME(ctx->opcode);
1663
1664 if (likely(mb == 0 && me == (31 - sh))) {
1665 if (likely(sh == 0)) {
1666 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1667 } else {
1668 TCGv t0 = tcg_temp_new();
1669 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1670 tcg_gen_shli_tl(t0, t0, sh);
1671 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1672 tcg_temp_free(t0);
1673 }
1674 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1675 TCGv t0 = tcg_temp_new();
1676 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1677 tcg_gen_shri_tl(t0, t0, mb);
1678 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1679 tcg_temp_free(t0);
1680 } else if (likely(mb == 0 && me == 31)) {
1681 TCGv_i32 t0 = tcg_temp_new_i32();
1682 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1683 tcg_gen_rotli_i32(t0, t0, sh);
1684 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1685 tcg_temp_free_i32(t0);
1686 } else {
1687 TCGv t0 = tcg_temp_new();
1688 #if defined(TARGET_PPC64)
1689 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1690 cpu_gpr[rS(ctx->opcode)], 32, 32);
1691 tcg_gen_rotli_i64(t0, t0, sh);
1692 #else
1693 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1694 #endif
1695 #if defined(TARGET_PPC64)
1696 mb += 32;
1697 me += 32;
1698 #endif
1699 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1700 tcg_temp_free(t0);
1701 }
1702 if (unlikely(Rc(ctx->opcode) != 0))
1703 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1704 }
1705
1706 /* rlwnm & rlwnm. */
1707 static void gen_rlwnm(DisasContext *ctx)
1708 {
1709 uint32_t mb, me;
1710 mb = MB(ctx->opcode);
1711 me = ME(ctx->opcode);
1712
1713 if (likely(mb == 0 && me == 31)) {
1714 TCGv_i32 t0, t1;
1715 t0 = tcg_temp_new_i32();
1716 t1 = tcg_temp_new_i32();
1717 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1718 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1719 tcg_gen_andi_i32(t0, t0, 0x1f);
1720 tcg_gen_rotl_i32(t1, t1, t0);
1721 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1722 tcg_temp_free_i32(t0);
1723 tcg_temp_free_i32(t1);
1724 } else {
1725 TCGv t0;
1726 #if defined(TARGET_PPC64)
1727 TCGv t1;
1728 #endif
1729
1730 t0 = tcg_temp_new();
1731 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1732 #if defined(TARGET_PPC64)
1733 t1 = tcg_temp_new_i64();
1734 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1735 cpu_gpr[rS(ctx->opcode)], 32, 32);
1736 tcg_gen_rotl_i64(t0, t1, t0);
1737 tcg_temp_free_i64(t1);
1738 #else
1739 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1740 #endif
1741 if (unlikely(mb != 0 || me != 31)) {
1742 #if defined(TARGET_PPC64)
1743 mb += 32;
1744 me += 32;
1745 #endif
1746 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1747 } else {
1748 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1749 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1750 }
1751 tcg_temp_free(t0);
1752 }
1753 if (unlikely(Rc(ctx->opcode) != 0))
1754 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1755 }
1756
1757 #if defined(TARGET_PPC64)
1758 #define GEN_PPC64_R2(name, opc1, opc2) \
1759 static void glue(gen_, name##0)(DisasContext *ctx) \
1760 { \
1761 gen_##name(ctx, 0); \
1762 } \
1763 \
1764 static void glue(gen_, name##1)(DisasContext *ctx) \
1765 { \
1766 gen_##name(ctx, 1); \
1767 }
1768 #define GEN_PPC64_R4(name, opc1, opc2) \
1769 static void glue(gen_, name##0)(DisasContext *ctx) \
1770 { \
1771 gen_##name(ctx, 0, 0); \
1772 } \
1773 \
1774 static void glue(gen_, name##1)(DisasContext *ctx) \
1775 { \
1776 gen_##name(ctx, 0, 1); \
1777 } \
1778 \
1779 static void glue(gen_, name##2)(DisasContext *ctx) \
1780 { \
1781 gen_##name(ctx, 1, 0); \
1782 } \
1783 \
1784 static void glue(gen_, name##3)(DisasContext *ctx) \
1785 { \
1786 gen_##name(ctx, 1, 1); \
1787 }
1788
1789 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1790 uint32_t sh)
1791 {
1792 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1793 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1794 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1795 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1796 } else {
1797 TCGv t0 = tcg_temp_new();
1798 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1799 if (likely(mb == 0 && me == 63)) {
1800 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1801 } else {
1802 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1803 }
1804 tcg_temp_free(t0);
1805 }
1806 if (unlikely(Rc(ctx->opcode) != 0))
1807 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1808 }
1809 /* rldicl - rldicl. */
1810 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1811 {
1812 uint32_t sh, mb;
1813
1814 sh = SH(ctx->opcode) | (shn << 5);
1815 mb = MB(ctx->opcode) | (mbn << 5);
1816 gen_rldinm(ctx, mb, 63, sh);
1817 }
1818 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1819 /* rldicr - rldicr. */
1820 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1821 {
1822 uint32_t sh, me;
1823
1824 sh = SH(ctx->opcode) | (shn << 5);
1825 me = MB(ctx->opcode) | (men << 5);
1826 gen_rldinm(ctx, 0, me, sh);
1827 }
1828 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1829 /* rldic - rldic. */
1830 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1831 {
1832 uint32_t sh, mb;
1833
1834 sh = SH(ctx->opcode) | (shn << 5);
1835 mb = MB(ctx->opcode) | (mbn << 5);
1836 gen_rldinm(ctx, mb, 63 - sh, sh);
1837 }
1838 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1839
1840 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1841 {
1842 TCGv t0;
1843
1844 t0 = tcg_temp_new();
1845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1846 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1847 if (unlikely(mb != 0 || me != 63)) {
1848 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1849 } else {
1850 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1851 }
1852 tcg_temp_free(t0);
1853 if (unlikely(Rc(ctx->opcode) != 0))
1854 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1855 }
1856
1857 /* rldcl - rldcl. */
1858 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1859 {
1860 uint32_t mb;
1861
1862 mb = MB(ctx->opcode) | (mbn << 5);
1863 gen_rldnm(ctx, mb, 63);
1864 }
1865 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1866 /* rldcr - rldcr. */
1867 static inline void gen_rldcr(DisasContext *ctx, int men)
1868 {
1869 uint32_t me;
1870
1871 me = MB(ctx->opcode) | (men << 5);
1872 gen_rldnm(ctx, 0, me);
1873 }
1874 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1875 /* rldimi - rldimi. */
1876 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1877 {
1878 uint32_t sh, mb, me;
1879
1880 sh = SH(ctx->opcode) | (shn << 5);
1881 mb = MB(ctx->opcode) | (mbn << 5);
1882 me = 63 - sh;
1883 if (unlikely(sh == 0 && mb == 0)) {
1884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1885 } else {
1886 TCGv t0, t1;
1887 target_ulong mask;
1888
1889 t0 = tcg_temp_new();
1890 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1891 t1 = tcg_temp_new();
1892 mask = MASK(mb, me);
1893 tcg_gen_andi_tl(t0, t0, mask);
1894 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1895 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1896 tcg_temp_free(t0);
1897 tcg_temp_free(t1);
1898 }
1899 if (unlikely(Rc(ctx->opcode) != 0))
1900 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1901 }
1902 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1903 #endif
1904
1905 /*** Integer shift ***/
1906
1907 /* slw & slw. */
1908 static void gen_slw(DisasContext *ctx)
1909 {
1910 TCGv t0, t1;
1911
1912 t0 = tcg_temp_new();
1913 /* AND rS with a mask that is 0 when rB >= 0x20 */
1914 #if defined(TARGET_PPC64)
1915 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1916 tcg_gen_sari_tl(t0, t0, 0x3f);
1917 #else
1918 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1919 tcg_gen_sari_tl(t0, t0, 0x1f);
1920 #endif
1921 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1922 t1 = tcg_temp_new();
1923 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1924 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1925 tcg_temp_free(t1);
1926 tcg_temp_free(t0);
1927 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1928 if (unlikely(Rc(ctx->opcode) != 0))
1929 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1930 }
1931
1932 /* sraw & sraw. */
1933 static void gen_sraw(DisasContext *ctx)
1934 {
1935 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1936 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939 }
1940
1941 /* srawi & srawi. */
1942 static void gen_srawi(DisasContext *ctx)
1943 {
1944 int sh = SH(ctx->opcode);
1945 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1946 TCGv src = cpu_gpr[rS(ctx->opcode)];
1947 if (sh == 0) {
1948 tcg_gen_ext32s_tl(dst, src);
1949 tcg_gen_movi_tl(cpu_ca, 0);
1950 } else {
1951 TCGv t0;
1952 tcg_gen_ext32s_tl(dst, src);
1953 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1954 t0 = tcg_temp_new();
1955 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1956 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1957 tcg_temp_free(t0);
1958 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1959 tcg_gen_sari_tl(dst, dst, sh);
1960 }
1961 if (unlikely(Rc(ctx->opcode) != 0)) {
1962 gen_set_Rc0(ctx, dst);
1963 }
1964 }
1965
1966 /* srw & srw. */
1967 static void gen_srw(DisasContext *ctx)
1968 {
1969 TCGv t0, t1;
1970
1971 t0 = tcg_temp_new();
1972 /* AND rS with a mask that is 0 when rB >= 0x20 */
1973 #if defined(TARGET_PPC64)
1974 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1975 tcg_gen_sari_tl(t0, t0, 0x3f);
1976 #else
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1978 tcg_gen_sari_tl(t0, t0, 0x1f);
1979 #endif
1980 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1981 tcg_gen_ext32u_tl(t0, t0);
1982 t1 = tcg_temp_new();
1983 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1984 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1985 tcg_temp_free(t1);
1986 tcg_temp_free(t0);
1987 if (unlikely(Rc(ctx->opcode) != 0))
1988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1989 }
1990
1991 #if defined(TARGET_PPC64)
1992 /* sld & sld. */
1993 static void gen_sld(DisasContext *ctx)
1994 {
1995 TCGv t0, t1;
1996
1997 t0 = tcg_temp_new();
1998 /* AND rS with a mask that is 0 when rB >= 0x40 */
1999 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2000 tcg_gen_sari_tl(t0, t0, 0x3f);
2001 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2002 t1 = tcg_temp_new();
2003 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2004 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2005 tcg_temp_free(t1);
2006 tcg_temp_free(t0);
2007 if (unlikely(Rc(ctx->opcode) != 0))
2008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2009 }
2010
2011 /* srad & srad. */
2012 static void gen_srad(DisasContext *ctx)
2013 {
2014 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2015 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2016 if (unlikely(Rc(ctx->opcode) != 0))
2017 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2018 }
2019 /* sradi & sradi. */
2020 static inline void gen_sradi(DisasContext *ctx, int n)
2021 {
2022 int sh = SH(ctx->opcode) + (n << 5);
2023 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2024 TCGv src = cpu_gpr[rS(ctx->opcode)];
2025 if (sh == 0) {
2026 tcg_gen_mov_tl(dst, src);
2027 tcg_gen_movi_tl(cpu_ca, 0);
2028 } else {
2029 TCGv t0;
2030 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2031 t0 = tcg_temp_new();
2032 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2033 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2034 tcg_temp_free(t0);
2035 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2036 tcg_gen_sari_tl(dst, src, sh);
2037 }
2038 if (unlikely(Rc(ctx->opcode) != 0)) {
2039 gen_set_Rc0(ctx, dst);
2040 }
2041 }
2042
2043 static void gen_sradi0(DisasContext *ctx)
2044 {
2045 gen_sradi(ctx, 0);
2046 }
2047
2048 static void gen_sradi1(DisasContext *ctx)
2049 {
2050 gen_sradi(ctx, 1);
2051 }
2052
2053 /* srd & srd. */
2054 static void gen_srd(DisasContext *ctx)
2055 {
2056 TCGv t0, t1;
2057
2058 t0 = tcg_temp_new();
2059 /* AND rS with a mask that is 0 when rB >= 0x40 */
2060 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2061 tcg_gen_sari_tl(t0, t0, 0x3f);
2062 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2063 t1 = tcg_temp_new();
2064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2065 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2066 tcg_temp_free(t1);
2067 tcg_temp_free(t0);
2068 if (unlikely(Rc(ctx->opcode) != 0))
2069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2070 }
2071 #endif
2072
2073 #if defined(TARGET_PPC64)
2074 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2075 {
2076 TCGv_i32 tmp = tcg_temp_new_i32();
2077 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2078 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2079 tcg_temp_free_i32(tmp);
2080 }
2081 #else
2082 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2083 {
2084 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2085 }
2086 #endif
2087
2088 /*** Floating-Point arithmetic ***/
2089 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2090 static void gen_f##name(DisasContext *ctx) \
2091 { \
2092 if (unlikely(!ctx->fpu_enabled)) { \
2093 gen_exception(ctx, POWERPC_EXCP_FPU); \
2094 return; \
2095 } \
2096 /* NIP cannot be restored if the memory exception comes from an helper */ \
2097 gen_update_nip(ctx, ctx->nip - 4); \
2098 gen_reset_fpstatus(); \
2099 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2100 cpu_fpr[rA(ctx->opcode)], \
2101 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2102 if (isfloat) { \
2103 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2104 cpu_fpr[rD(ctx->opcode)]); \
2105 } \
2106 if (set_fprf) { \
2107 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2108 } \
2109 if (unlikely(Rc(ctx->opcode) != 0)) { \
2110 gen_set_cr1_from_fpscr(ctx); \
2111 } \
2112 }
2113
2114 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2115 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2116 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2117
2118 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2119 static void gen_f##name(DisasContext *ctx) \
2120 { \
2121 if (unlikely(!ctx->fpu_enabled)) { \
2122 gen_exception(ctx, POWERPC_EXCP_FPU); \
2123 return; \
2124 } \
2125 /* NIP cannot be restored if the memory exception comes from an helper */ \
2126 gen_update_nip(ctx, ctx->nip - 4); \
2127 gen_reset_fpstatus(); \
2128 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2129 cpu_fpr[rA(ctx->opcode)], \
2130 cpu_fpr[rB(ctx->opcode)]); \
2131 if (isfloat) { \
2132 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2133 cpu_fpr[rD(ctx->opcode)]); \
2134 } \
2135 if (set_fprf) { \
2136 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2137 } \
2138 if (unlikely(Rc(ctx->opcode) != 0)) { \
2139 gen_set_cr1_from_fpscr(ctx); \
2140 } \
2141 }
2142 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2143 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2144 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2145
2146 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2147 static void gen_f##name(DisasContext *ctx) \
2148 { \
2149 if (unlikely(!ctx->fpu_enabled)) { \
2150 gen_exception(ctx, POWERPC_EXCP_FPU); \
2151 return; \
2152 } \
2153 /* NIP cannot be restored if the memory exception comes from an helper */ \
2154 gen_update_nip(ctx, ctx->nip - 4); \
2155 gen_reset_fpstatus(); \
2156 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2157 cpu_fpr[rA(ctx->opcode)], \
2158 cpu_fpr[rC(ctx->opcode)]); \
2159 if (isfloat) { \
2160 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2161 cpu_fpr[rD(ctx->opcode)]); \
2162 } \
2163 if (set_fprf) { \
2164 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2165 } \
2166 if (unlikely(Rc(ctx->opcode) != 0)) { \
2167 gen_set_cr1_from_fpscr(ctx); \
2168 } \
2169 }
2170 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2171 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2172 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2173
2174 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2175 static void gen_f##name(DisasContext *ctx) \
2176 { \
2177 if (unlikely(!ctx->fpu_enabled)) { \
2178 gen_exception(ctx, POWERPC_EXCP_FPU); \
2179 return; \
2180 } \
2181 /* NIP cannot be restored if the memory exception comes from an helper */ \
2182 gen_update_nip(ctx, ctx->nip - 4); \
2183 gen_reset_fpstatus(); \
2184 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2185 cpu_fpr[rB(ctx->opcode)]); \
2186 if (set_fprf) { \
2187 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2188 } \
2189 if (unlikely(Rc(ctx->opcode) != 0)) { \
2190 gen_set_cr1_from_fpscr(ctx); \
2191 } \
2192 }
2193
2194 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2195 static void gen_f##name(DisasContext *ctx) \
2196 { \
2197 if (unlikely(!ctx->fpu_enabled)) { \
2198 gen_exception(ctx, POWERPC_EXCP_FPU); \
2199 return; \
2200 } \
2201 /* NIP cannot be restored if the memory exception comes from an helper */ \
2202 gen_update_nip(ctx, ctx->nip - 4); \
2203 gen_reset_fpstatus(); \
2204 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2205 cpu_fpr[rB(ctx->opcode)]); \
2206 if (set_fprf) { \
2207 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2208 } \
2209 if (unlikely(Rc(ctx->opcode) != 0)) { \
2210 gen_set_cr1_from_fpscr(ctx); \
2211 } \
2212 }
2213
2214 /* fadd - fadds */
2215 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2216 /* fdiv - fdivs */
2217 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2218 /* fmul - fmuls */
2219 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2220
2221 /* fre */
2222 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2223
2224 /* fres */
2225 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2226
2227 /* frsqrte */
2228 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2229
2230 /* frsqrtes */
2231 static void gen_frsqrtes(DisasContext *ctx)
2232 {
2233 if (unlikely(!ctx->fpu_enabled)) {
2234 gen_exception(ctx, POWERPC_EXCP_FPU);
2235 return;
2236 }
2237 /* NIP cannot be restored if the memory exception comes from an helper */
2238 gen_update_nip(ctx, ctx->nip - 4);
2239 gen_reset_fpstatus();
2240 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2241 cpu_fpr[rB(ctx->opcode)]);
2242 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2243 cpu_fpr[rD(ctx->opcode)]);
2244 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2245 if (unlikely(Rc(ctx->opcode) != 0)) {
2246 gen_set_cr1_from_fpscr(ctx);
2247 }
2248 }
2249
2250 /* fsel */
2251 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2252 /* fsub - fsubs */
2253 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2254 /* Optional: */
2255
2256 /* fsqrt */
2257 static void gen_fsqrt(DisasContext *ctx)
2258 {
2259 if (unlikely(!ctx->fpu_enabled)) {
2260 gen_exception(ctx, POWERPC_EXCP_FPU);
2261 return;
2262 }
2263 /* NIP cannot be restored if the memory exception comes from an helper */
2264 gen_update_nip(ctx, ctx->nip - 4);
2265 gen_reset_fpstatus();
2266 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2267 cpu_fpr[rB(ctx->opcode)]);
2268 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2269 if (unlikely(Rc(ctx->opcode) != 0)) {
2270 gen_set_cr1_from_fpscr(ctx);
2271 }
2272 }
2273
2274 static void gen_fsqrts(DisasContext *ctx)
2275 {
2276 if (unlikely(!ctx->fpu_enabled)) {
2277 gen_exception(ctx, POWERPC_EXCP_FPU);
2278 return;
2279 }
2280 /* NIP cannot be restored if the memory exception comes from an helper */
2281 gen_update_nip(ctx, ctx->nip - 4);
2282 gen_reset_fpstatus();
2283 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2284 cpu_fpr[rB(ctx->opcode)]);
2285 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2286 cpu_fpr[rD(ctx->opcode)]);
2287 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2288 if (unlikely(Rc(ctx->opcode) != 0)) {
2289 gen_set_cr1_from_fpscr(ctx);
2290 }
2291 }
2292
2293 /*** Floating-Point multiply-and-add ***/
2294 /* fmadd - fmadds */
2295 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2296 /* fmsub - fmsubs */
2297 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2298 /* fnmadd - fnmadds */
2299 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2300 /* fnmsub - fnmsubs */
2301 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2302
2303 /*** Floating-Point round & convert ***/
2304 /* fctiw */
2305 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2306 /* fctiwu */
2307 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2308 /* fctiwz */
2309 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2310 /* fctiwuz */
2311 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2312 /* frsp */
2313 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2314 /* fcfid */
2315 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2316 /* fcfids */
2317 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2318 /* fcfidu */
2319 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2320 /* fcfidus */
2321 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2322 /* fctid */
2323 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2324 /* fctidu */
2325 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2326 /* fctidz */
2327 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2328 /* fctidu */
2329 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2330
2331 /* frin */
2332 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2333 /* friz */
2334 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2335 /* frip */
2336 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2337 /* frim */
2338 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2339
2340 static void gen_ftdiv(DisasContext *ctx)
2341 {
2342 if (unlikely(!ctx->fpu_enabled)) {
2343 gen_exception(ctx, POWERPC_EXCP_FPU);
2344 return;
2345 }
2346 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2347 cpu_fpr[rB(ctx->opcode)]);
2348 }
2349
2350 static void gen_ftsqrt(DisasContext *ctx)
2351 {
2352 if (unlikely(!ctx->fpu_enabled)) {
2353 gen_exception(ctx, POWERPC_EXCP_FPU);
2354 return;
2355 }
2356 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2357 }
2358
2359
2360
2361 /*** Floating-Point compare ***/
2362
2363 /* fcmpo */
2364 static void gen_fcmpo(DisasContext *ctx)
2365 {
2366 TCGv_i32 crf;
2367 if (unlikely(!ctx->fpu_enabled)) {
2368 gen_exception(ctx, POWERPC_EXCP_FPU);
2369 return;
2370 }
2371 /* NIP cannot be restored if the memory exception comes from an helper */
2372 gen_update_nip(ctx, ctx->nip - 4);
2373 gen_reset_fpstatus();
2374 crf = tcg_const_i32(crfD(ctx->opcode));
2375 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2376 cpu_fpr[rB(ctx->opcode)], crf);
2377 tcg_temp_free_i32(crf);
2378 gen_helper_float_check_status(cpu_env);
2379 }
2380
2381 /* fcmpu */
2382 static void gen_fcmpu(DisasContext *ctx)
2383 {
2384 TCGv_i32 crf;
2385 if (unlikely(!ctx->fpu_enabled)) {
2386 gen_exception(ctx, POWERPC_EXCP_FPU);
2387 return;
2388 }
2389 /* NIP cannot be restored if the memory exception comes from an helper */
2390 gen_update_nip(ctx, ctx->nip - 4);
2391 gen_reset_fpstatus();
2392 crf = tcg_const_i32(crfD(ctx->opcode));
2393 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2394 cpu_fpr[rB(ctx->opcode)], crf);
2395 tcg_temp_free_i32(crf);
2396 gen_helper_float_check_status(cpu_env);
2397 }
2398
2399 /*** Floating-point move ***/
2400 /* fabs */
2401 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2402 static void gen_fabs(DisasContext *ctx)
2403 {
2404 if (unlikely(!ctx->fpu_enabled)) {
2405 gen_exception(ctx, POWERPC_EXCP_FPU);
2406 return;
2407 }
2408 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2409 ~(1ULL << 63));
2410 if (unlikely(Rc(ctx->opcode))) {
2411 gen_set_cr1_from_fpscr(ctx);
2412 }
2413 }
2414
2415 /* fmr - fmr. */
2416 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2417 static void gen_fmr(DisasContext *ctx)
2418 {
2419 if (unlikely(!ctx->fpu_enabled)) {
2420 gen_exception(ctx, POWERPC_EXCP_FPU);
2421 return;
2422 }
2423 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2424 if (unlikely(Rc(ctx->opcode))) {
2425 gen_set_cr1_from_fpscr(ctx);
2426 }
2427 }
2428
2429 /* fnabs */
2430 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2431 static void gen_fnabs(DisasContext *ctx)
2432 {
2433 if (unlikely(!ctx->fpu_enabled)) {
2434 gen_exception(ctx, POWERPC_EXCP_FPU);
2435 return;
2436 }
2437 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2438 1ULL << 63);
2439 if (unlikely(Rc(ctx->opcode))) {
2440 gen_set_cr1_from_fpscr(ctx);
2441 }
2442 }
2443
2444 /* fneg */
2445 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2446 static void gen_fneg(DisasContext *ctx)
2447 {
2448 if (unlikely(!ctx->fpu_enabled)) {
2449 gen_exception(ctx, POWERPC_EXCP_FPU);
2450 return;
2451 }
2452 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2453 1ULL << 63);
2454 if (unlikely(Rc(ctx->opcode))) {
2455 gen_set_cr1_from_fpscr(ctx);
2456 }
2457 }
2458
2459 /* fcpsgn: PowerPC 2.05 specification */
2460 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2461 static void gen_fcpsgn(DisasContext *ctx)
2462 {
2463 if (unlikely(!ctx->fpu_enabled)) {
2464 gen_exception(ctx, POWERPC_EXCP_FPU);
2465 return;
2466 }
2467 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2468 cpu_fpr[rB(ctx->opcode)], 0, 63);
2469 if (unlikely(Rc(ctx->opcode))) {
2470 gen_set_cr1_from_fpscr(ctx);
2471 }
2472 }
2473
2474 static void gen_fmrgew(DisasContext *ctx)
2475 {
2476 TCGv_i64 b0;
2477 if (unlikely(!ctx->fpu_enabled)) {
2478 gen_exception(ctx, POWERPC_EXCP_FPU);
2479 return;
2480 }
2481 b0 = tcg_temp_new_i64();
2482 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2483 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2484 b0, 0, 32);
2485 tcg_temp_free_i64(b0);
2486 }
2487
2488 static void gen_fmrgow(DisasContext *ctx)
2489 {
2490 if (unlikely(!ctx->fpu_enabled)) {
2491 gen_exception(ctx, POWERPC_EXCP_FPU);
2492 return;
2493 }
2494 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2495 cpu_fpr[rB(ctx->opcode)],
2496 cpu_fpr[rA(ctx->opcode)],
2497 32, 32);
2498 }
2499
2500 /*** Floating-Point status & ctrl register ***/
2501
2502 /* mcrfs */
2503 static void gen_mcrfs(DisasContext *ctx)
2504 {
2505 TCGv tmp = tcg_temp_new();
2506 TCGv_i32 tmask;
2507 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2508 int bfa;
2509 int nibble;
2510 int shift;
2511
2512 if (unlikely(!ctx->fpu_enabled)) {
2513 gen_exception(ctx, POWERPC_EXCP_FPU);
2514 return;
2515 }
2516 bfa = crfS(ctx->opcode);
2517 nibble = 7 - bfa;
2518 shift = 4 * nibble;
2519 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2520 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2521 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2522 tcg_temp_free(tmp);
2523 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2524 /* Only the exception bits (including FX) should be cleared if read */
2525 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2526 /* FEX and VX need to be updated, so don't set fpscr directly */
2527 tmask = tcg_const_i32(1 << nibble);
2528 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2529 tcg_temp_free_i32(tmask);
2530 tcg_temp_free_i64(tnew_fpscr);
2531 }
2532
2533 /* mffs */
2534 static void gen_mffs(DisasContext *ctx)
2535 {
2536 if (unlikely(!ctx->fpu_enabled)) {
2537 gen_exception(ctx, POWERPC_EXCP_FPU);
2538 return;
2539 }
2540 gen_reset_fpstatus();
2541 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2542 if (unlikely(Rc(ctx->opcode))) {
2543 gen_set_cr1_from_fpscr(ctx);
2544 }
2545 }
2546
2547 /* mtfsb0 */
2548 static void gen_mtfsb0(DisasContext *ctx)
2549 {
2550 uint8_t crb;
2551
2552 if (unlikely(!ctx->fpu_enabled)) {
2553 gen_exception(ctx, POWERPC_EXCP_FPU);
2554 return;
2555 }
2556 crb = 31 - crbD(ctx->opcode);
2557 gen_reset_fpstatus();
2558 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2559 TCGv_i32 t0;
2560 /* NIP cannot be restored if the memory exception comes from an helper */
2561 gen_update_nip(ctx, ctx->nip - 4);
2562 t0 = tcg_const_i32(crb);
2563 gen_helper_fpscr_clrbit(cpu_env, t0);
2564 tcg_temp_free_i32(t0);
2565 }
2566 if (unlikely(Rc(ctx->opcode) != 0)) {
2567 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2568 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2569 }
2570 }
2571
2572 /* mtfsb1 */
2573 static void gen_mtfsb1(DisasContext *ctx)
2574 {
2575 uint8_t crb;
2576
2577 if (unlikely(!ctx->fpu_enabled)) {
2578 gen_exception(ctx, POWERPC_EXCP_FPU);
2579 return;
2580 }
2581 crb = 31 - crbD(ctx->opcode);
2582 gen_reset_fpstatus();
2583 /* XXX: we pretend we can only do IEEE floating-point computations */
2584 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2585 TCGv_i32 t0;
2586 /* NIP cannot be restored if the memory exception comes from an helper */
2587 gen_update_nip(ctx, ctx->nip - 4);
2588 t0 = tcg_const_i32(crb);
2589 gen_helper_fpscr_setbit(cpu_env, t0);
2590 tcg_temp_free_i32(t0);
2591 }
2592 if (unlikely(Rc(ctx->opcode) != 0)) {
2593 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2594 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2595 }
2596 /* We can raise a differed exception */
2597 gen_helper_float_check_status(cpu_env);
2598 }
2599
2600 /* mtfsf */
2601 static void gen_mtfsf(DisasContext *ctx)
2602 {
2603 TCGv_i32 t0;
2604 int flm, l, w;
2605
2606 if (unlikely(!ctx->fpu_enabled)) {
2607 gen_exception(ctx, POWERPC_EXCP_FPU);
2608 return;
2609 }
2610 flm = FPFLM(ctx->opcode);
2611 l = FPL(ctx->opcode);
2612 w = FPW(ctx->opcode);
2613 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2615 return;
2616 }
2617 /* NIP cannot be restored if the memory exception comes from an helper */
2618 gen_update_nip(ctx, ctx->nip - 4);
2619 gen_reset_fpstatus();
2620 if (l) {
2621 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2622 } else {
2623 t0 = tcg_const_i32(flm << (w * 8));
2624 }
2625 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2626 tcg_temp_free_i32(t0);
2627 if (unlikely(Rc(ctx->opcode) != 0)) {
2628 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2629 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2630 }
2631 /* We can raise a differed exception */
2632 gen_helper_float_check_status(cpu_env);
2633 }
2634
2635 /* mtfsfi */
2636 static void gen_mtfsfi(DisasContext *ctx)
2637 {
2638 int bf, sh, w;
2639 TCGv_i64 t0;
2640 TCGv_i32 t1;
2641
2642 if (unlikely(!ctx->fpu_enabled)) {
2643 gen_exception(ctx, POWERPC_EXCP_FPU);
2644 return;
2645 }
2646 w = FPW(ctx->opcode);
2647 bf = FPBF(ctx->opcode);
2648 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2649 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2650 return;
2651 }
2652 sh = (8 * w) + 7 - bf;
2653 /* NIP cannot be restored if the memory exception comes from an helper */
2654 gen_update_nip(ctx, ctx->nip - 4);
2655 gen_reset_fpstatus();
2656 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2657 t1 = tcg_const_i32(1 << sh);
2658 gen_helper_store_fpscr(cpu_env, t0, t1);
2659 tcg_temp_free_i64(t0);
2660 tcg_temp_free_i32(t1);
2661 if (unlikely(Rc(ctx->opcode) != 0)) {
2662 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2663 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2664 }
2665 /* We can raise a differed exception */
2666 gen_helper_float_check_status(cpu_env);
2667 }
2668
2669 /*** Addressing modes ***/
2670 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2671 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2672 target_long maskl)
2673 {
2674 target_long simm = SIMM(ctx->opcode);
2675
2676 simm &= ~maskl;
2677 if (rA(ctx->opcode) == 0) {
2678 if (NARROW_MODE(ctx)) {
2679 simm = (uint32_t)simm;
2680 }
2681 tcg_gen_movi_tl(EA, simm);
2682 } else if (likely(simm != 0)) {
2683 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2684 if (NARROW_MODE(ctx)) {
2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
2687 } else {
2688 if (NARROW_MODE(ctx)) {
2689 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2690 } else {
2691 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2692 }
2693 }
2694 }
2695
2696 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2697 {
2698 if (rA(ctx->opcode) == 0) {
2699 if (NARROW_MODE(ctx)) {
2700 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2701 } else {
2702 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2703 }
2704 } else {
2705 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2706 if (NARROW_MODE(ctx)) {
2707 tcg_gen_ext32u_tl(EA, EA);
2708 }
2709 }
2710 }
2711
2712 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2713 {
2714 if (rA(ctx->opcode) == 0) {
2715 tcg_gen_movi_tl(EA, 0);
2716 } else if (NARROW_MODE(ctx)) {
2717 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2718 } else {
2719 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2720 }
2721 }
2722
2723 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2724 target_long val)
2725 {
2726 tcg_gen_addi_tl(ret, arg1, val);
2727 if (NARROW_MODE(ctx)) {
2728 tcg_gen_ext32u_tl(ret, ret);
2729 }
2730 }
2731
2732 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2733 {
2734 TCGLabel *l1 = gen_new_label();
2735 TCGv t0 = tcg_temp_new();
2736 TCGv_i32 t1, t2;
2737 /* NIP cannot be restored if the memory exception comes from an helper */
2738 gen_update_nip(ctx, ctx->nip - 4);
2739 tcg_gen_andi_tl(t0, EA, mask);
2740 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2741 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2742 t2 = tcg_const_i32(0);
2743 gen_helper_raise_exception_err(cpu_env, t1, t2);
2744 tcg_temp_free_i32(t1);
2745 tcg_temp_free_i32(t2);
2746 gen_set_label(l1);
2747 tcg_temp_free(t0);
2748 }
2749
2750 /*** Integer load ***/
2751 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2752 {
2753 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2754 }
2755
2756 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2757 {
2758 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2759 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2760 }
2761
2762 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2763 {
2764 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2765 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2766 }
2767
2768 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2769 {
2770 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2771 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2772 }
2773
2774 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2775 {
2776 TCGv tmp = tcg_temp_new();
2777 gen_qemu_ld32u(ctx, tmp, addr);
2778 tcg_gen_extu_tl_i64(val, tmp);
2779 tcg_temp_free(tmp);
2780 }
2781
2782 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2783 {
2784 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2785 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2786 }
2787
2788 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2789 {
2790 TCGv tmp = tcg_temp_new();
2791 gen_qemu_ld32s(ctx, tmp, addr);
2792 tcg_gen_ext_tl_i64(val, tmp);
2793 tcg_temp_free(tmp);
2794 }
2795
2796 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2797 {
2798 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2799 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2800 }
2801
2802 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2803 {
2804 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2805 }
2806
2807 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2808 {
2809 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2810 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2811 }
2812
2813 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2814 {
2815 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2816 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2817 }
2818
2819 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2820 {
2821 TCGv tmp = tcg_temp_new();
2822 tcg_gen_trunc_i64_tl(tmp, val);
2823 gen_qemu_st32(ctx, tmp, addr);
2824 tcg_temp_free(tmp);
2825 }
2826
2827 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2828 {
2829 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2830 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2831 }
2832
2833 #define GEN_LD(name, ldop, opc, type) \
2834 static void glue(gen_, name)(DisasContext *ctx) \
2835 { \
2836 TCGv EA; \
2837 gen_set_access_type(ctx, ACCESS_INT); \
2838 EA = tcg_temp_new(); \
2839 gen_addr_imm_index(ctx, EA, 0); \
2840 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2841 tcg_temp_free(EA); \
2842 }
2843
2844 #define GEN_LDU(name, ldop, opc, type) \
2845 static void glue(gen_, name##u)(DisasContext *ctx) \
2846 { \
2847 TCGv EA; \
2848 if (unlikely(rA(ctx->opcode) == 0 || \
2849 rA(ctx->opcode) == rD(ctx->opcode))) { \
2850 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2851 return; \
2852 } \
2853 gen_set_access_type(ctx, ACCESS_INT); \
2854 EA = tcg_temp_new(); \
2855 if (type == PPC_64B) \
2856 gen_addr_imm_index(ctx, EA, 0x03); \
2857 else \
2858 gen_addr_imm_index(ctx, EA, 0); \
2859 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2860 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2861 tcg_temp_free(EA); \
2862 }
2863
2864 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2865 static void glue(gen_, name##ux)(DisasContext *ctx) \
2866 { \
2867 TCGv EA; \
2868 if (unlikely(rA(ctx->opcode) == 0 || \
2869 rA(ctx->opcode) == rD(ctx->opcode))) { \
2870 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2871 return; \
2872 } \
2873 gen_set_access_type(ctx, ACCESS_INT); \
2874 EA = tcg_temp_new(); \
2875 gen_addr_reg_index(ctx, EA); \
2876 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2877 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2878 tcg_temp_free(EA); \
2879 }
2880
2881 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2882 static void glue(gen_, name##x)(DisasContext *ctx) \
2883 { \
2884 TCGv EA; \
2885 gen_set_access_type(ctx, ACCESS_INT); \
2886 EA = tcg_temp_new(); \
2887 gen_addr_reg_index(ctx, EA); \
2888 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2889 tcg_temp_free(EA); \
2890 }
2891 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2892 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2893
2894 #define GEN_LDS(name, ldop, op, type) \
2895 GEN_LD(name, ldop, op | 0x20, type); \
2896 GEN_LDU(name, ldop, op | 0x21, type); \
2897 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2898 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2899
2900 /* lbz lbzu lbzux lbzx */
2901 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2902 /* lha lhau lhaux lhax */
2903 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2904 /* lhz lhzu lhzux lhzx */
2905 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2906 /* lwz lwzu lwzux lwzx */
2907 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2908 #if defined(TARGET_PPC64)
2909 /* lwaux */
2910 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2911 /* lwax */
2912 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2913 /* ldux */
2914 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2915 /* ldx */
2916 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2917
2918 static void gen_ld(DisasContext *ctx)
2919 {
2920 TCGv EA;
2921 if (Rc(ctx->opcode)) {
2922 if (unlikely(rA(ctx->opcode) == 0 ||
2923 rA(ctx->opcode) == rD(ctx->opcode))) {
2924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2925 return;
2926 }
2927 }
2928 gen_set_access_type(ctx, ACCESS_INT);
2929 EA = tcg_temp_new();
2930 gen_addr_imm_index(ctx, EA, 0x03);
2931 if (ctx->opcode & 0x02) {
2932 /* lwa (lwau is undefined) */
2933 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2934 } else {
2935 /* ld - ldu */
2936 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2937 }
2938 if (Rc(ctx->opcode))
2939 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2940 tcg_temp_free(EA);
2941 }
2942
2943 /* lq */
2944 static void gen_lq(DisasContext *ctx)
2945 {
2946 int ra, rd;
2947 TCGv EA;
2948
2949 /* lq is a legal user mode instruction starting in ISA 2.07 */
2950 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2952
2953 if (!legal_in_user_mode && ctx->pr) {
2954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2955 return;
2956 }
2957
2958 if (!le_is_supported && ctx->le_mode) {
2959 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2960 return;
2961 }
2962
2963 ra = rA(ctx->opcode);
2964 rd = rD(ctx->opcode);
2965 if (unlikely((rd & 1) || rd == ra)) {
2966 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2967 return;
2968 }
2969
2970 gen_set_access_type(ctx, ACCESS_INT);
2971 EA = tcg_temp_new();
2972 gen_addr_imm_index(ctx, EA, 0x0F);
2973
2974 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2975 64-bit byteswap already. */
2976 if (unlikely(ctx->le_mode)) {
2977 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2978 gen_addr_add(ctx, EA, EA, 8);
2979 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2980 } else {
2981 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2982 gen_addr_add(ctx, EA, EA, 8);
2983 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2984 }
2985 tcg_temp_free(EA);
2986 }
2987 #endif
2988
2989 /*** Integer store ***/
2990 #define GEN_ST(name, stop, opc, type) \
2991 static void glue(gen_, name)(DisasContext *ctx) \
2992 { \
2993 TCGv EA; \
2994 gen_set_access_type(ctx, ACCESS_INT); \
2995 EA = tcg_temp_new(); \
2996 gen_addr_imm_index(ctx, EA, 0); \
2997 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2998 tcg_temp_free(EA); \
2999 }
3000
3001 #define GEN_STU(name, stop, opc, type) \
3002 static void glue(gen_, stop##u)(DisasContext *ctx) \
3003 { \
3004 TCGv EA; \
3005 if (unlikely(rA(ctx->opcode) == 0)) { \
3006 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3007 return; \
3008 } \
3009 gen_set_access_type(ctx, ACCESS_INT); \
3010 EA = tcg_temp_new(); \
3011 if (type == PPC_64B) \
3012 gen_addr_imm_index(ctx, EA, 0x03); \
3013 else \
3014 gen_addr_imm_index(ctx, EA, 0); \
3015 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3016 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3017 tcg_temp_free(EA); \
3018 }
3019
3020 #define GEN_STUX(name, stop, opc2, opc3, type) \
3021 static void glue(gen_, name##ux)(DisasContext *ctx) \
3022 { \
3023 TCGv EA; \
3024 if (unlikely(rA(ctx->opcode) == 0)) { \
3025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3026 return; \
3027 } \
3028 gen_set_access_type(ctx, ACCESS_INT); \
3029 EA = tcg_temp_new(); \
3030 gen_addr_reg_index(ctx, EA); \
3031 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3032 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3033 tcg_temp_free(EA); \
3034 }
3035
3036 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3037 static void glue(gen_, name##x)(DisasContext *ctx) \
3038 { \
3039 TCGv EA; \
3040 gen_set_access_type(ctx, ACCESS_INT); \
3041 EA = tcg_temp_new(); \
3042 gen_addr_reg_index(ctx, EA); \
3043 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3044 tcg_temp_free(EA); \
3045 }
3046 #define GEN_STX(name, stop, opc2, opc3, type) \
3047 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3048
3049 #define GEN_STS(name, stop, op, type) \
3050 GEN_ST(name, stop, op | 0x20, type); \
3051 GEN_STU(name, stop, op | 0x21, type); \
3052 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3053 GEN_STX(name, stop, 0x17, op | 0x00, type)
3054
3055 /* stb stbu stbux stbx */
3056 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3057 /* sth sthu sthux sthx */
3058 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3059 /* stw stwu stwux stwx */
3060 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3061 #if defined(TARGET_PPC64)
3062 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3063 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3064
3065 static void gen_std(DisasContext *ctx)
3066 {
3067 int rs;
3068 TCGv EA;
3069
3070 rs = rS(ctx->opcode);
3071 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3072
3073 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3075
3076 if (!legal_in_user_mode && ctx->pr) {
3077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3078 return;
3079 }
3080
3081 if (!le_is_supported && ctx->le_mode) {
3082 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3083 return;
3084 }
3085
3086 if (unlikely(rs & 1)) {
3087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3088 return;
3089 }
3090 gen_set_access_type(ctx, ACCESS_INT);
3091 EA = tcg_temp_new();
3092 gen_addr_imm_index(ctx, EA, 0x03);
3093
3094 /* We only need to swap high and low halves. gen_qemu_st64 does
3095 necessary 64-bit byteswap already. */
3096 if (unlikely(ctx->le_mode)) {
3097 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3098 gen_addr_add(ctx, EA, EA, 8);
3099 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3100 } else {
3101 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3102 gen_addr_add(ctx, EA, EA, 8);
3103 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3104 }
3105 tcg_temp_free(EA);
3106 } else {
3107 /* std / stdu*/
3108 if (Rc(ctx->opcode)) {
3109 if (unlikely(rA(ctx->opcode) == 0)) {
3110 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3111 return;
3112 }
3113 }
3114 gen_set_access_type(ctx, ACCESS_INT);
3115 EA = tcg_temp_new();
3116 gen_addr_imm_index(ctx, EA, 0x03);
3117 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3118 if (Rc(ctx->opcode))
3119 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3120 tcg_temp_free(EA);
3121 }
3122 }
3123 #endif
3124 /*** Integer load and store with byte reverse ***/
3125
3126 /* lhbrx */
3127 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3128 {
3129 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3130 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3131 }
3132 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3133
3134 /* lwbrx */
3135 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3136 {
3137 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3138 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3139 }
3140 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3141
3142 #if defined(TARGET_PPC64)
3143 /* ldbrx */
3144 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3145 {
3146 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3147 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3148 }
3149 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3150 #endif /* TARGET_PPC64 */
3151
3152 /* sthbrx */
3153 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3154 {
3155 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3156 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3157 }
3158 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3159
3160 /* stwbrx */
3161 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3162 {
3163 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3164 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3165 }
3166 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3167
3168 #if defined(TARGET_PPC64)
3169 /* stdbrx */
3170 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3171 {
3172 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3173 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3174 }
3175 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3176 #endif /* TARGET_PPC64 */
3177
3178 /*** Integer load and store multiple ***/
3179
3180 /* lmw */
3181 static void gen_lmw(DisasContext *ctx)
3182 {
3183 TCGv t0;
3184 TCGv_i32 t1;
3185 gen_set_access_type(ctx, ACCESS_INT);
3186 /* NIP cannot be restored if the memory exception comes from an helper */
3187 gen_update_nip(ctx, ctx->nip - 4);
3188 t0 = tcg_temp_new();
3189 t1 = tcg_const_i32(rD(ctx->opcode));
3190 gen_addr_imm_index(ctx, t0, 0);
3191 gen_helper_lmw(cpu_env, t0, t1);
3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
3194 }
3195
3196 /* stmw */
3197 static void gen_stmw(DisasContext *ctx)
3198 {
3199 TCGv t0;
3200 TCGv_i32 t1;
3201 gen_set_access_type(ctx, ACCESS_INT);
3202 /* NIP cannot be restored if the memory exception comes from an helper */
3203 gen_update_nip(ctx, ctx->nip - 4);
3204 t0 = tcg_temp_new();
3205 t1 = tcg_const_i32(rS(ctx->opcode));
3206 gen_addr_imm_index(ctx, t0, 0);
3207 gen_helper_stmw(cpu_env, t0, t1);
3208 tcg_temp_free(t0);
3209 tcg_temp_free_i32(t1);
3210 }
3211
3212 /*** Integer load and store strings ***/
3213
3214 /* lswi */
3215 /* PowerPC32 specification says we must generate an exception if
3216 * rA is in the range of registers to be loaded.
3217 * In an other hand, IBM says this is valid, but rA won't be loaded.
3218 * For now, I'll follow the spec...
3219 */
3220 static void gen_lswi(DisasContext *ctx)
3221 {
3222 TCGv t0;
3223 TCGv_i32 t1, t2;
3224 int nb = NB(ctx->opcode);
3225 int start = rD(ctx->opcode);
3226 int ra = rA(ctx->opcode);
3227 int nr;
3228
3229 if (nb == 0)
3230 nb = 32;
3231 nr = (nb + 3) / 4;
3232 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3233 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3234 return;
3235 }
3236 gen_set_access_type(ctx, ACCESS_INT);
3237 /* NIP cannot be restored if the memory exception comes from an helper */
3238 gen_update_nip(ctx, ctx->nip - 4);
3239 t0 = tcg_temp_new();
3240 gen_addr_register(ctx, t0);
3241 t1 = tcg_const_i32(nb);
3242 t2 = tcg_const_i32(start);
3243 gen_helper_lsw(cpu_env, t0, t1, t2);
3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 }
3248
3249 /* lswx */
3250 static void gen_lswx(DisasContext *ctx)
3251 {
3252 TCGv t0;
3253 TCGv_i32 t1, t2, t3;
3254 gen_set_access_type(ctx, ACCESS_INT);
3255 /* NIP cannot be restored if the memory exception comes from an helper */
3256 gen_update_nip(ctx, ctx->nip - 4);
3257 t0 = tcg_temp_new();
3258 gen_addr_reg_index(ctx, t0);
3259 t1 = tcg_const_i32(rD(ctx->opcode));
3260 t2 = tcg_const_i32(rA(ctx->opcode));
3261 t3 = tcg_const_i32(rB(ctx->opcode));
3262 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3263 tcg_temp_free(t0);
3264 tcg_temp_free_i32(t1);
3265 tcg_temp_free_i32(t2);
3266 tcg_temp_free_i32(t3);
3267 }
3268
3269 /* stswi */
3270 static void gen_stswi(DisasContext *ctx)
3271 {
3272 TCGv t0;
3273 TCGv_i32 t1, t2;
3274 int nb = NB(ctx->opcode);
3275 gen_set_access_type(ctx, ACCESS_INT);
3276 /* NIP cannot be restored if the memory exception comes from an helper */
3277 gen_update_nip(ctx, ctx->nip - 4);
3278 t0 = tcg_temp_new();
3279 gen_addr_register(ctx, t0);
3280 if (nb == 0)
3281 nb = 32;
3282 t1 = tcg_const_i32(nb);
3283 t2 = tcg_const_i32(rS(ctx->opcode));
3284 gen_helper_stsw(cpu_env, t0, t1, t2);
3285 tcg_temp_free(t0);
3286 tcg_temp_free_i32(t1);
3287 tcg_temp_free_i32(t2);
3288 }
3289
3290 /* stswx */
3291 static void gen_stswx(DisasContext *ctx)
3292 {
3293 TCGv t0;
3294 TCGv_i32 t1, t2;
3295 gen_set_access_type(ctx, ACCESS_INT);
3296 /* NIP cannot be restored if the memory exception comes from an helper */
3297 gen_update_nip(ctx, ctx->nip - 4);
3298 t0 = tcg_temp_new();
3299 gen_addr_reg_index(ctx, t0);
3300 t1 = tcg_temp_new_i32();
3301 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3302 tcg_gen_andi_i32(t1, t1, 0x7F);
3303 t2 = tcg_const_i32(rS(ctx->opcode));
3304 gen_helper_stsw(cpu_env, t0, t1, t2);
3305 tcg_temp_free(t0);
3306 tcg_temp_free_i32(t1);
3307 tcg_temp_free_i32(t2);
3308 }
3309
3310 /*** Memory synchronisation ***/
3311 /* eieio */
3312 static void gen_eieio(DisasContext *ctx)
3313 {
3314 }
3315
3316 /* isync */
3317 static void gen_isync(DisasContext *ctx)
3318 {
3319 gen_stop_exception(ctx);
3320 }
3321
3322 #define LARX(name, len, loadop) \
3323 static void gen_##name(DisasContext *ctx) \
3324 { \
3325 TCGv t0; \
3326 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3327 gen_set_access_type(ctx, ACCESS_RES); \
3328 t0 = tcg_temp_local_new(); \
3329 gen_addr_reg_index(ctx, t0); \
3330 if ((len) > 1) { \
3331 gen_check_align(ctx, t0, (len)-1); \
3332 } \
3333 gen_qemu_##loadop(ctx, gpr, t0); \
3334 tcg_gen_mov_tl(cpu_reserve, t0); \
3335 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3336 tcg_temp_free(t0); \
3337 }
3338
3339 /* lwarx */
3340 LARX(lbarx, 1, ld8u);
3341 LARX(lharx, 2, ld16u);
3342 LARX(lwarx, 4, ld32u);
3343
3344
3345 #if defined(CONFIG_USER_ONLY)
3346 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3347 int reg, int size)
3348 {
3349 TCGv t0 = tcg_temp_new();
3350 uint32_t save_exception = ctx->exception;
3351
3352 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3353 tcg_gen_movi_tl(t0, (size << 5) | reg);
3354 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3355 tcg_temp_free(t0);
3356 gen_update_nip(ctx, ctx->nip-4);
3357 ctx->exception = POWERPC_EXCP_BRANCH;
3358 gen_exception(ctx, POWERPC_EXCP_STCX);
3359 ctx->exception = save_exception;
3360 }
3361 #else
3362 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3363 int reg, int size)
3364 {
3365 TCGLabel *l1;
3366
3367 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3368 l1 = gen_new_label();
3369 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3370 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3371 #if defined(TARGET_PPC64)
3372 if (size == 8) {
3373 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3374 } else
3375 #endif
3376 if (size == 4) {
3377 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3378 } else if (size == 2) {
3379 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3380 #if defined(TARGET_PPC64)
3381 } else if (size == 16) {
3382 TCGv gpr1, gpr2 , EA8;
3383 if (unlikely(ctx->le_mode)) {
3384 gpr1 = cpu_gpr[reg+1];
3385 gpr2 = cpu_gpr[reg];
3386 } else {
3387 gpr1 = cpu_gpr[reg];
3388 gpr2 = cpu_gpr[reg+1];
3389 }
3390 gen_qemu_st64(ctx, gpr1, EA);
3391 EA8 = tcg_temp_local_new();
3392 gen_addr_add(ctx, EA8, EA, 8);
3393 gen_qemu_st64(ctx, gpr2, EA8);
3394 tcg_temp_free(EA8);
3395 #endif
3396 } else {
3397 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3398 }
3399 gen_set_label(l1);
3400 tcg_gen_movi_tl(cpu_reserve, -1);
3401 }
3402 #endif
3403
3404 #define STCX(name, len) \
3405 static void gen_##name(DisasContext *ctx) \
3406 { \
3407 TCGv t0; \
3408 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3409 gen_inval_exception(ctx, \
3410 POWERPC_EXCP_INVAL_INVAL); \
3411 return; \
3412 } \
3413 gen_set_access_type(ctx, ACCESS_RES); \
3414 t0 = tcg_temp_local_new(); \
3415 gen_addr_reg_index(ctx, t0); \
3416 if (len > 1) { \
3417 gen_check_align(ctx, t0, (len)-1); \
3418 } \
3419 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3420 tcg_temp_free(t0); \
3421 }
3422
3423 STCX(stbcx_, 1);
3424 STCX(sthcx_, 2);
3425 STCX(stwcx_, 4);
3426
3427 #if defined(TARGET_PPC64)
3428 /* ldarx */
3429 LARX(ldarx, 8, ld64);
3430
3431 /* lqarx */
3432 static void gen_lqarx(DisasContext *ctx)
3433 {
3434 TCGv EA;
3435 int rd = rD(ctx->opcode);
3436 TCGv gpr1, gpr2;
3437
3438 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3439 (rd == rB(ctx->opcode)))) {
3440 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3441 return;
3442 }
3443
3444 gen_set_access_type(ctx, ACCESS_RES);
3445 EA = tcg_temp_local_new();
3446 gen_addr_reg_index(ctx, EA);
3447 gen_check_align(ctx, EA, 15);
3448 if (unlikely(ctx->le_mode)) {
3449 gpr1 = cpu_gpr[rd+1];
3450 gpr2 = cpu_gpr[rd];
3451 } else {
3452 gpr1 = cpu_gpr[rd];
3453 gpr2 = cpu_gpr[rd+1];
3454 }
3455 gen_qemu_ld64(ctx, gpr1, EA);
3456 tcg_gen_mov_tl(cpu_reserve, EA);
3457
3458 gen_addr_add(ctx, EA, EA, 8);
3459 gen_qemu_ld64(ctx, gpr2, EA);
3460
3461 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3462 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3463
3464 tcg_temp_free(EA);
3465 }
3466
3467 /* stdcx. */
3468 STCX(stdcx_, 8);
3469 STCX(stqcx_, 16);
3470 #endif /* defined(TARGET_PPC64) */
3471
3472 /* sync */
3473 static void gen_sync(DisasContext *ctx)
3474 {
3475 }
3476
3477 /* wait */
3478 static void gen_wait(DisasContext *ctx)
3479 {
3480 TCGv_i32 t0 = tcg_temp_new_i32();
3481 tcg_gen_st_i32(t0, cpu_env,
3482 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3483 tcg_temp_free_i32(t0);
3484 /* Stop translation, as the CPU is supposed to sleep from now */
3485 gen_exception_err(ctx, EXCP_HLT, 1);
3486 }
3487
3488 /*** Floating-point load ***/
3489 #define GEN_LDF(name, ldop, opc, type) \
3490 static void glue(gen_, name)(DisasContext *ctx) \
3491 { \
3492 TCGv EA; \
3493 if (unlikely(!ctx->fpu_enabled)) { \
3494 gen_exception(ctx, POWERPC_EXCP_FPU); \
3495 return; \
3496 } \
3497 gen_set_access_type(ctx, ACCESS_FLOAT); \
3498 EA = tcg_temp_new(); \
3499 gen_addr_imm_index(ctx, EA, 0); \
3500 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3501 tcg_temp_free(EA); \
3502 }
3503
3504 #define GEN_LDUF(name, ldop, opc, type) \
3505 static void glue(gen_, name##u)(DisasContext *ctx) \
3506 { \
3507 TCGv EA; \
3508 if (unlikely(!ctx->fpu_enabled)) { \
3509 gen_exception(ctx, POWERPC_EXCP_FPU); \
3510 return; \
3511 } \
3512 if (unlikely(rA(ctx->opcode) == 0)) { \
3513 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3514 return; \
3515 } \
3516 gen_set_access_type(ctx, ACCESS_FLOAT); \
3517 EA = tcg_temp_new(); \
3518 gen_addr_imm_index(ctx, EA, 0); \
3519 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3520 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3521 tcg_temp_free(EA); \
3522 }
3523
3524 #define GEN_LDUXF(name, ldop, opc, type) \
3525 static void glue(gen_, name##ux)(DisasContext *ctx) \
3526 { \
3527 TCGv EA; \
3528 if (unlikely(!ctx->fpu_enabled)) { \
3529 gen_exception(ctx, POWERPC_EXCP_FPU); \
3530 return; \
3531 } \
3532 if (unlikely(rA(ctx->opcode) == 0)) { \
3533 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3534 return; \
3535 } \
3536 gen_set_access_type(ctx, ACCESS_FLOAT); \
3537 EA = tcg_temp_new(); \
3538 gen_addr_reg_index(ctx, EA); \
3539 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3541 tcg_temp_free(EA); \
3542 }
3543
3544 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3545 static void glue(gen_, name##x)(DisasContext *ctx) \
3546 { \
3547 TCGv EA; \
3548 if (unlikely(!ctx->fpu_enabled)) { \
3549 gen_exception(ctx, POWERPC_EXCP_FPU); \
3550 return; \
3551 } \
3552 gen_set_access_type(ctx, ACCESS_FLOAT); \
3553 EA = tcg_temp_new(); \
3554 gen_addr_reg_index(ctx, EA); \
3555 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3556 tcg_temp_free(EA); \
3557 }
3558
3559 #define GEN_LDFS(name, ldop, op, type) \
3560 GEN_LDF(name, ldop, op | 0x20, type); \
3561 GEN_LDUF(name, ldop, op | 0x21, type); \
3562 GEN_LDUXF(name, ldop, op | 0x01, type); \
3563 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3564
3565 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3566 {
3567 TCGv t0 = tcg_temp_new();
3568 TCGv_i32 t1 = tcg_temp_new_i32();
3569 gen_qemu_ld32u(ctx, t0, arg2);
3570 tcg_gen_trunc_tl_i32(t1, t0);
3571 tcg_temp_free(t0);
3572 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3573 tcg_temp_free_i32(t1);
3574 }
3575
3576 /* lfd lfdu lfdux lfdx */
3577 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3578 /* lfs lfsu lfsux lfsx */
3579 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3580
3581 /* lfdp */
3582 static void gen_lfdp(DisasContext *ctx)
3583 {
3584 TCGv EA;
3585 if (unlikely(!ctx->fpu_enabled)) {
3586 gen_exception(ctx, POWERPC_EXCP_FPU);
3587 return;
3588 }
3589 gen_set_access_type(ctx, ACCESS_FLOAT);
3590 EA = tcg_temp_new();
3591 gen_addr_imm_index(ctx, EA, 0);
3592 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3593 64-bit byteswap already. */
3594 if (unlikely(ctx->le_mode)) {
3595 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3596 tcg_gen_addi_tl(EA, EA, 8);
3597 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3598 } else {
3599 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3600 tcg_gen_addi_tl(EA, EA, 8);
3601 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3602 }
3603 tcg_temp_free(EA);
3604 }
3605
3606 /* lfdpx */
3607 static void gen_lfdpx(DisasContext *ctx)
3608 {
3609 TCGv EA;
3610 if (unlikely(!ctx->fpu_enabled)) {
3611 gen_exception(ctx, POWERPC_EXCP_FPU);
3612 return;
3613 }
3614 gen_set_access_type(ctx, ACCESS_FLOAT);
3615 EA = tcg_temp_new();
3616 gen_addr_reg_index(ctx, EA);
3617 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3618 64-bit byteswap already. */
3619 if (unlikely(ctx->le_mode)) {
3620 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3621 tcg_gen_addi_tl(EA, EA, 8);
3622 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3623 } else {
3624 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3625 tcg_gen_addi_tl(EA, EA, 8);
3626 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3627 }
3628 tcg_temp_free(EA);
3629 }
3630
3631 /* lfiwax */
3632 static void gen_lfiwax(DisasContext *ctx)
3633 {
3634 TCGv EA;
3635 TCGv t0;
3636 if (unlikely(!ctx->fpu_enabled)) {
3637 gen_exception(ctx, POWERPC_EXCP_FPU);
3638 return;
3639 }
3640 gen_set_access_type(ctx, ACCESS_FLOAT);
3641 EA = tcg_temp_new();
3642 t0 = tcg_temp_new();
3643 gen_addr_reg_index(ctx, EA);
3644 gen_qemu_ld32s(ctx, t0, EA);
3645 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3646 tcg_temp_free(EA);
3647 tcg_temp_free(t0);
3648 }
3649
3650 /* lfiwzx */
3651 static void gen_lfiwzx(DisasContext *ctx)
3652 {
3653 TCGv EA;
3654 if (unlikely(!ctx->fpu_enabled)) {
3655 gen_exception(ctx, POWERPC_EXCP_FPU);
3656 return;
3657 }
3658 gen_set_access_type(ctx, ACCESS_FLOAT);
3659 EA = tcg_temp_new();
3660 gen_addr_reg_index(ctx, EA);
3661 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3662 tcg_temp_free(EA);
3663 }
3664 /*** Floating-point store ***/
3665 #define GEN_STF(name, stop, opc, type) \
3666 static void glue(gen_, name)(DisasContext *ctx) \
3667 { \
3668 TCGv EA; \
3669 if (unlikely(!ctx->fpu_enabled)) { \
3670 gen_exception(ctx, POWERPC_EXCP_FPU); \
3671 return; \
3672 } \
3673 gen_set_access_type(ctx, ACCESS_FLOAT); \
3674 EA = tcg_temp_new(); \
3675 gen_addr_imm_index(ctx, EA, 0); \
3676 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3677 tcg_temp_free(EA); \
3678 }
3679
3680 #define GEN_STUF(name, stop, opc, type) \
3681 static void glue(gen_, name##u)(DisasContext *ctx) \
3682 { \
3683 TCGv EA; \
3684 if (unlikely(!ctx->fpu_enabled)) { \
3685 gen_exception(ctx, POWERPC_EXCP_FPU); \
3686 return; \
3687 } \
3688 if (unlikely(rA(ctx->opcode) == 0)) { \
3689 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3690 return; \
3691 } \
3692 gen_set_access_type(ctx, ACCESS_FLOAT); \
3693 EA = tcg_temp_new(); \
3694 gen_addr_imm_index(ctx, EA, 0); \
3695 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3696 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3697 tcg_temp_free(EA); \
3698 }
3699
3700 #define GEN_STUXF(name, stop, opc, type) \
3701 static void glue(gen_, name##ux)(DisasContext *ctx) \
3702 { \
3703 TCGv EA; \
3704 if (unlikely(!ctx->fpu_enabled)) { \
3705 gen_exception(ctx, POWERPC_EXCP_FPU); \
3706 return; \
3707 } \
3708 if (unlikely(rA(ctx->opcode) == 0)) { \
3709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3710 return; \
3711 } \
3712 gen_set_access_type(ctx, ACCESS_FLOAT); \
3713 EA = tcg_temp_new(); \
3714 gen_addr_reg_index(ctx, EA); \
3715 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3716 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3717 tcg_temp_free(EA); \
3718 }
3719
3720 #define GEN_STXF(name, stop, opc2, opc3, type) \
3721 static void glue(gen_, name##x)(DisasContext *ctx) \
3722 { \
3723 TCGv EA; \
3724 if (unlikely(!ctx->fpu_enabled)) { \
3725 gen_exception(ctx, POWERPC_EXCP_FPU); \
3726 return; \
3727 } \
3728 gen_set_access_type(ctx, ACCESS_FLOAT); \
3729 EA = tcg_temp_new(); \
3730 gen_addr_reg_index(ctx, EA); \
3731 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3732 tcg_temp_free(EA); \
3733 }
3734
3735 #define GEN_STFS(name, stop, op, type) \
3736 GEN_STF(name, stop, op | 0x20, type); \
3737 GEN_STUF(name, stop, op | 0x21, type); \
3738 GEN_STUXF(name, stop, op | 0x01, type); \
3739 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3740
3741 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3742 {
3743 TCGv_i32 t0 = tcg_temp_new_i32();
3744 TCGv t1 = tcg_temp_new();
3745 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3746 tcg_gen_extu_i32_tl(t1, t0);
3747 tcg_temp_free_i32(t0);
3748 gen_qemu_st32(ctx, t1, arg2);
3749 tcg_temp_free(t1);
3750 }
3751
3752 /* stfd stfdu stfdux stfdx */
3753 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3754 /* stfs stfsu stfsux stfsx */
3755 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3756
3757 /* stfdp */
3758 static void gen_stfdp(DisasContext *ctx)
3759 {
3760 TCGv EA;
3761 if (unlikely(!ctx->fpu_enabled)) {
3762 gen_exception(ctx, POWERPC_EXCP_FPU);
3763 return;
3764 }
3765 gen_set_access_type(ctx, ACCESS_FLOAT);
3766 EA = tcg_temp_new();
3767 gen_addr_imm_index(ctx, EA, 0);
3768 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3769 64-bit byteswap already. */
3770 if (unlikely(ctx->le_mode)) {
3771 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3772 tcg_gen_addi_tl(EA, EA, 8);
3773 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3774 } else {
3775 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3776 tcg_gen_addi_tl(EA, EA, 8);
3777 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3778 }
3779 tcg_temp_free(EA);
3780 }
3781
3782 /* stfdpx */
3783 static void gen_stfdpx(DisasContext *ctx)
3784 {
3785 TCGv EA;
3786 if (unlikely(!ctx->fpu_enabled)) {
3787 gen_exception(ctx, POWERPC_EXCP_FPU);
3788 return;
3789 }
3790 gen_set_access_type(ctx, ACCESS_FLOAT);
3791 EA = tcg_temp_new();
3792 gen_addr_reg_index(ctx, EA);
3793 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3794 64-bit byteswap already. */
3795 if (unlikely(ctx->le_mode)) {
3796 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3797 tcg_gen_addi_tl(EA, EA, 8);
3798 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3799 } else {
3800 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3801 tcg_gen_addi_tl(EA, EA, 8);
3802 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3803 }
3804 tcg_temp_free(EA);
3805 }
3806
3807 /* Optional: */
3808 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3809 {
3810 TCGv t0 = tcg_temp_new();
3811 tcg_gen_trunc_i64_tl(t0, arg1),
3812 gen_qemu_st32(ctx, t0, arg2);
3813 tcg_temp_free(t0);
3814 }
3815 /* stfiwx */
3816 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3817
3818 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3819 {
3820 #if defined(TARGET_PPC64)
3821 if (ctx->has_cfar)
3822 tcg_gen_movi_tl(cpu_cfar, nip);
3823 #endif
3824 }
3825
3826 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3827 {
3828 if (unlikely(ctx->singlestep_enabled)) {
3829 return false;
3830 }
3831
3832 #ifndef CONFIG_USER_ONLY
3833 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3834 #else
3835 return true;
3836 #endif
3837 }
3838
3839 /*** Branch ***/
3840 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3841 {
3842 if (NARROW_MODE(ctx)) {
3843 dest = (uint32_t) dest;
3844 }
3845 if (use_goto_tb(ctx, dest)) {
3846 tcg_gen_goto_tb(n);
3847 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3848 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3849 } else {
3850 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3851 if (unlikely(ctx->singlestep_enabled)) {
3852 if ((ctx->singlestep_enabled &
3853 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3854 (ctx->exception == POWERPC_EXCP_BRANCH ||
3855 ctx->exception == POWERPC_EXCP_TRACE)) {
3856 target_ulong tmp = ctx->nip;
3857 ctx->nip = dest;
3858 gen_exception(ctx, POWERPC_EXCP_TRACE);
3859 ctx->nip = tmp;
3860 }
3861 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3862 gen_debug_exception(ctx);
3863 }
3864 }
3865 tcg_gen_exit_tb(0);
3866 }
3867 }
3868
3869 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3870 {
3871 if (NARROW_MODE(ctx)) {
3872 nip = (uint32_t)nip;
3873 }
3874 tcg_gen_movi_tl(cpu_lr, nip);
3875 }
3876
3877 /* b ba bl bla */
3878 static void gen_b(DisasContext *ctx)
3879 {
3880 target_ulong li, target;
3881
3882 ctx->exception = POWERPC_EXCP_BRANCH;
3883 /* sign extend LI */
3884 li = LI(ctx->opcode);
3885 li = (li ^ 0x02000000) - 0x02000000;
3886 if (likely(AA(ctx->opcode) == 0)) {
3887 target = ctx->nip + li - 4;
3888 } else {
3889 target = li;
3890 }
3891 if (LK(ctx->opcode)) {
3892 gen_setlr(ctx, ctx->nip);
3893 }
3894 gen_update_cfar(ctx, ctx->nip);
3895 gen_goto_tb(ctx, 0, target);
3896 }
3897
3898 #define BCOND_IM 0
3899 #define BCOND_LR 1
3900 #define BCOND_CTR 2
3901 #define BCOND_TAR 3
3902
3903 static inline void gen_bcond(DisasContext *ctx, int type)
3904 {
3905 uint32_t bo = BO(ctx->opcode);
3906 TCGLabel *l1;
3907 TCGv target;
3908
3909 ctx->exception = POWERPC_EXCP_BRANCH;
3910 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3911 target = tcg_temp_local_new();
3912 if (type == BCOND_CTR)
3913 tcg_gen_mov_tl(target, cpu_ctr);
3914 else if (type == BCOND_TAR)
3915 gen_load_spr(target, SPR_TAR);
3916 else
3917 tcg_gen_mov_tl(target, cpu_lr);
3918 } else {
3919 TCGV_UNUSED(target);
3920 }
3921 if (LK(ctx->opcode))
3922 gen_setlr(ctx, ctx->nip);
3923 l1 = gen_new_label();
3924 if ((bo & 0x4) == 0) {
3925 /* Decrement and test CTR */
3926 TCGv temp = tcg_temp_new();
3927 if (unlikely(type == BCOND_CTR)) {
3928 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3929 return;
3930 }
3931 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3932 if (NARROW_MODE(ctx)) {
3933 tcg_gen_ext32u_tl(temp, cpu_ctr);
3934 } else {
3935 tcg_gen_mov_tl(temp, cpu_ctr);
3936 }
3937 if (bo & 0x2) {
3938 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3939 } else {
3940 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3941 }
3942 tcg_temp_free(temp);
3943 }
3944 if ((bo & 0x10) == 0) {
3945 /* Test CR */
3946 uint32_t bi = BI(ctx->opcode);
3947 uint32_t mask = 0x08 >> (bi & 0x03);
3948 TCGv_i32 temp = tcg_temp_new_i32();
3949
3950 if (bo & 0x8) {
3951 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3952 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3953 } else {
3954 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3955 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3956 }
3957 tcg_temp_free_i32(temp);
3958 }
3959 gen_update_cfar(ctx, ctx->nip);
3960 if (type == BCOND_IM) {
3961 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3962 if (likely(AA(ctx->opcode) == 0)) {
3963 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3964 } else {
3965 gen_goto_tb(ctx, 0, li);
3966 }
3967 gen_set_label(l1);
3968 gen_goto_tb(ctx, 1, ctx->nip);
3969 } else {
3970 if (NARROW_MODE(ctx)) {
3971 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3972 } else {
3973 tcg_gen_andi_tl(cpu_nip, target, ~3);
3974 }
3975 tcg_gen_exit_tb(0);
3976 gen_set_label(l1);
3977 gen_update_nip(ctx, ctx->nip);
3978 tcg_gen_exit_tb(0);
3979 }
3980 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3981 tcg_temp_free(target);
3982 }
3983 }
3984
3985 static void gen_bc(DisasContext *ctx)
3986 {
3987 gen_bcond(ctx, BCOND_IM);
3988 }
3989
3990 static void gen_bcctr(DisasContext *ctx)
3991 {
3992 gen_bcond(ctx, BCOND_CTR);
3993 }
3994
3995 static void gen_bclr(DisasContext *ctx)
3996 {
3997 gen_bcond(ctx, BCOND_LR);
3998 }
3999
4000 static void gen_bctar(DisasContext *ctx)
4001 {
4002 gen_bcond(ctx, BCOND_TAR);
4003 }
4004
4005 /*** Condition register logical ***/
4006 #define GEN_CRLOGIC(name, tcg_op, opc) \
4007 static void glue(gen_, name)(DisasContext *ctx) \
4008 { \
4009 uint8_t bitmask; \
4010 int sh; \
4011 TCGv_i32 t0, t1; \
4012 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4013 t0 = tcg_temp_new_i32(); \
4014 if (sh > 0) \
4015 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4016 else if (sh < 0) \
4017 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4018 else \
4019 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4020 t1 = tcg_temp_new_i32(); \
4021 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4022 if (sh > 0) \
4023 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4024 else if (sh < 0) \
4025 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4026 else \
4027 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4028 tcg_op(t0, t0, t1); \
4029 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4030 tcg_gen_andi_i32(t0, t0, bitmask); \
4031 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4032 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4033 tcg_temp_free_i32(t0); \
4034 tcg_temp_free_i32(t1); \
4035 }
4036
4037 /* crand */
4038 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4039 /* crandc */
4040 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4041 /* creqv */
4042 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4043 /* crnand */
4044 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4045 /* crnor */
4046 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4047 /* cror */
4048 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4049 /* crorc */
4050 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4051 /* crxor */
4052 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4053
4054 /* mcrf */
4055 static void gen_mcrf(DisasContext *ctx)
4056 {
4057 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4058 }
4059
4060 /*** System linkage ***/
4061
4062 /* rfi (supervisor only) */
4063 static void gen_rfi(DisasContext *ctx)
4064 {
4065 #if defined(CONFIG_USER_ONLY)
4066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4067 #else
4068 /* Restore CPU state */
4069 if (unlikely(ctx->pr)) {
4070 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4071 return;
4072 }
4073 gen_update_cfar(ctx, ctx->nip);
4074 gen_helper_rfi(cpu_env);
4075 gen_sync_exception(ctx);
4076 #endif
4077 }
4078
4079 #if defined(TARGET_PPC64)
4080 static void gen_rfid(DisasContext *ctx)
4081 {
4082 #if defined(CONFIG_USER_ONLY)
4083 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4084 #else
4085 /* Restore CPU state */
4086 if (unlikely(ctx->pr)) {
4087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4088 return;
4089 }
4090 gen_update_cfar(ctx, ctx->nip);
4091 gen_helper_rfid(cpu_env);
4092 gen_sync_exception(ctx);
4093 #endif
4094 }
4095
4096 static void gen_hrfid(DisasContext *ctx)
4097 {
4098 #if defined(CONFIG_USER_ONLY)
4099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4100 #else
4101 /* Restore CPU state */
4102 if (unlikely(!ctx->hv)) {
4103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4104 return;
4105 }
4106 gen_helper_hrfid(cpu_env);
4107 gen_sync_exception(ctx);
4108 #endif
4109 }
4110 #endif
4111
4112 /* sc */
4113 #if defined(CONFIG_USER_ONLY)
4114 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4115 #else
4116 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4117 #endif
4118 static void gen_sc(DisasContext *ctx)
4119 {
4120 uint32_t lev;
4121
4122 lev = (ctx->opcode >> 5) & 0x7F;
4123 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4124 }
4125
4126 /*** Trap ***/
4127
4128 /* tw */
4129 static void gen_tw(DisasContext *ctx)
4130 {
4131 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4132 /* Update the nip since this might generate a trap exception */
4133 gen_update_nip(ctx, ctx->nip);
4134 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4135 t0);
4136 tcg_temp_free_i32(t0);
4137 }
4138
4139 /* twi */
4140 static void gen_twi(DisasContext *ctx)
4141 {
4142 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4143 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4144 /* Update the nip since this might generate a trap exception */
4145 gen_update_nip(ctx, ctx->nip);
4146 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4147 tcg_temp_free(t0);
4148 tcg_temp_free_i32(t1);
4149 }
4150
4151 #if defined(TARGET_PPC64)
4152 /* td */
4153 static void gen_td(DisasContext *ctx)
4154 {
4155 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4156 /* Update the nip since this might generate a trap exception */
4157 gen_update_nip(ctx, ctx->nip);
4158 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4159 t0);
4160 tcg_temp_free_i32(t0);
4161 }
4162
4163 /* tdi */
4164 static void gen_tdi(DisasContext *ctx)
4165 {
4166 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4167 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4168 /* Update the nip since this might generate a trap exception */
4169 gen_update_nip(ctx, ctx->nip);
4170 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4171 tcg_temp_free(t0);
4172 tcg_temp_free_i32(t1);
4173 }
4174 #endif
4175
4176 /*** Processor control ***/
4177
4178 static void gen_read_xer(TCGv dst)
4179 {
4180 TCGv t0 = tcg_temp_new();
4181 TCGv t1 = tcg_temp_new();
4182 TCGv t2 = tcg_temp_new();
4183 tcg_gen_mov_tl(dst, cpu_xer);
4184 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4185 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4186 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4187 tcg_gen_or_tl(t0, t0, t1);
4188 tcg_gen_or_tl(dst, dst, t2);
4189 tcg_gen_or_tl(dst, dst, t0);
4190 tcg_temp_free(t0);
4191 tcg_temp_free(t1);
4192 tcg_temp_free(t2);
4193 }
4194
4195 static void gen_write_xer(TCGv src)
4196 {
4197 tcg_gen_andi_tl(cpu_xer, src,
4198 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4199 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4200 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4201 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4202 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4203 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4204 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4205 }
4206
4207 /* mcrxr */
4208 static void gen_mcrxr(DisasContext *ctx)
4209 {
4210 TCGv_i32 t0 = tcg_temp_new_i32();
4211 TCGv_i32 t1 = tcg_temp_new_i32();
4212 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4213
4214 tcg_gen_trunc_tl_i32(t0, cpu_so);
4215 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4216 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4217 tcg_gen_shli_i32(t0, t0, 3);
4218 tcg_gen_shli_i32(t1, t1, 2);
4219 tcg_gen_shli_i32(dst, dst, 1);
4220 tcg_gen_or_i32(dst, dst, t0);
4221 tcg_gen_or_i32(dst, dst, t1);
4222 tcg_temp_free_i32(t0);
4223 tcg_temp_free_i32(t1);
4224
4225 tcg_gen_movi_tl(cpu_so, 0);
4226 tcg_gen_movi_tl(cpu_ov, 0);
4227 tcg_gen_movi_tl(cpu_ca, 0);
4228 }
4229
4230 /* mfcr mfocrf */
4231 static void gen_mfcr(DisasContext *ctx)
4232 {
4233 uint32_t crm, crn;
4234
4235 if (likely(ctx->opcode & 0x00100000)) {
4236 crm = CRM(ctx->opcode);
4237 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4238 crn = ctz32 (crm);
4239 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4240 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4241 cpu_gpr[rD(ctx->opcode)], crn * 4);
4242 }
4243 } else {
4244 TCGv_i32 t0 = tcg_temp_new_i32();
4245 tcg_gen_mov_i32(t0, cpu_crf[0]);
4246 tcg_gen_shli_i32(t0, t0, 4);
4247 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4248 tcg_gen_shli_i32(t0, t0, 4);
4249 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4250 tcg_gen_shli_i32(t0, t0, 4);
4251 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4252 tcg_gen_shli_i32(t0, t0, 4);
4253 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4254 tcg_gen_shli_i32(t0, t0, 4);
4255 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4256 tcg_gen_shli_i32(t0, t0, 4);
4257 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4258 tcg_gen_shli_i32(t0, t0, 4);
4259 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4260 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4261 tcg_temp_free_i32(t0);
4262 }
4263 }
4264
4265 /* mfmsr */
4266 static void gen_mfmsr(DisasContext *ctx)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4270 #else
4271 if (unlikely(ctx->pr)) {
4272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4273 return;
4274 }
4275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4276 #endif
4277 }
4278
4279 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4280 {
4281 #if 0
4282 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4283 printf("ERROR: try to access SPR %d !\n", sprn);
4284 #endif
4285 }
4286 #define SPR_NOACCESS (&spr_noaccess)
4287
4288 /* mfspr */
4289 static inline void gen_op_mfspr(DisasContext *ctx)
4290 {
4291 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4292 uint32_t sprn = SPR(ctx->opcode);
4293
4294 #if defined(CONFIG_USER_ONLY)
4295 read_cb = ctx->spr_cb[sprn].uea_read;
4296 #else
4297 if (ctx->pr) {
4298 read_cb = ctx->spr_cb[sprn].uea_read;
4299 } else if (ctx->hv) {
4300 read_cb = ctx->spr_cb[sprn].hea_read;
4301 } else {
4302 read_cb = ctx->spr_cb[sprn].oea_read;
4303 }
4304 #endif
4305 if (likely(read_cb != NULL)) {
4306 if (likely(read_cb != SPR_NOACCESS)) {
4307 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4308 } else {
4309 /* Privilege exception */
4310 /* This is a hack to avoid warnings when running Linux:
4311 * this OS breaks the PowerPC virtualisation model,
4312 * allowing userland application to read the PVR
4313 */
4314 if (sprn != SPR_PVR) {
4315 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4316 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4317 if (qemu_log_separate()) {
4318 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4319 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4320 }
4321 }
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4323 }
4324 } else {
4325 /* Not defined */
4326 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4327 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4328 if (qemu_log_separate()) {
4329 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4330 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4331 }
4332 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4333 }
4334 }
4335
4336 static void gen_mfspr(DisasContext *ctx)
4337 {
4338 gen_op_mfspr(ctx);
4339 }
4340
4341 /* mftb */
4342 static void gen_mftb(DisasContext *ctx)
4343 {
4344 gen_op_mfspr(ctx);
4345 }
4346
4347 /* mtcrf mtocrf*/
4348 static void gen_mtcrf(DisasContext *ctx)
4349 {
4350 uint32_t crm, crn;
4351
4352 crm = CRM(ctx->opcode);
4353 if (likely((ctx->opcode & 0x00100000))) {
4354 if (crm && ((crm & (crm - 1)) == 0)) {
4355 TCGv_i32 temp = tcg_temp_new_i32();
4356 crn = ctz32 (crm);
4357 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4358 tcg_gen_shri_i32(temp, temp, crn * 4);
4359 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4360 tcg_temp_free_i32(temp);
4361 }
4362 } else {
4363 TCGv_i32 temp = tcg_temp_new_i32();
4364 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4365 for (crn = 0 ; crn < 8 ; crn++) {
4366 if (crm & (1 << crn)) {
4367 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4368 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4369 }
4370 }
4371 tcg_temp_free_i32(temp);
4372 }
4373 }
4374
4375 /* mtmsr */
4376 #if defined(TARGET_PPC64)
4377 static void gen_mtmsrd(DisasContext *ctx)
4378 {
4379 #if defined(CONFIG_USER_ONLY)
4380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4381 #else
4382 if (unlikely(ctx->pr)) {
4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4384 return;
4385 }
4386 if (ctx->opcode & 0x00010000) {
4387 /* Special form that does not need any synchronisation */
4388 TCGv t0 = tcg_temp_new();
4389 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4390 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4391 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4392 tcg_temp_free(t0);
4393 } else {
4394 /* XXX: we need to update nip before the store
4395 * if we enter power saving mode, we will exit the loop
4396 * directly from ppc_store_msr
4397 */
4398 gen_update_nip(ctx, ctx->nip);
4399 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4400 /* Must stop the translation as machine state (may have) changed */
4401 /* Note that mtmsr is not always defined as context-synchronizing */
4402 gen_stop_exception(ctx);
4403 }
4404 #endif
4405 }
4406 #endif
4407
4408 static void gen_mtmsr(DisasContext *ctx)
4409 {
4410 #if defined(CONFIG_USER_ONLY)
4411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4412 #else
4413 if (unlikely(ctx->pr)) {
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4415 return;
4416 }
4417 if (ctx->opcode & 0x00010000) {
4418 /* Special form that does not need any synchronisation */
4419 TCGv t0 = tcg_temp_new();
4420 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4421 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4422 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4423 tcg_temp_free(t0);
4424 } else {
4425 TCGv msr = tcg_temp_new();
4426
4427 /* XXX: we need to update nip before the store
4428 * if we enter power saving mode, we will exit the loop
4429 * directly from ppc_store_msr
4430 */
4431 gen_update_nip(ctx, ctx->nip);
4432 #if defined(TARGET_PPC64)
4433 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4434 #else
4435 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4436 #endif
4437 gen_helper_store_msr(cpu_env, msr);
4438 tcg_temp_free(msr);
4439 /* Must stop the translation as machine state (may have) changed */
4440 /* Note that mtmsr is not always defined as context-synchronizing */
4441 gen_stop_exception(ctx);
4442 }
4443 #endif
4444 }
4445
4446 /* mtspr */
4447 static void gen_mtspr(DisasContext *ctx)
4448 {
4449 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4450 uint32_t sprn = SPR(ctx->opcode);
4451
4452 #if defined(CONFIG_USER_ONLY)
4453 write_cb = ctx->spr_cb[sprn].uea_write;
4454 #else
4455 if (ctx->pr) {
4456 write_cb = ctx->spr_cb[sprn].uea_write;
4457 } else if (ctx->hv) {
4458 write_cb = ctx->spr_cb[sprn].hea_write;
4459 } else {
4460 write_cb = ctx->spr_cb[sprn].oea_write;
4461 }
4462 #endif
4463 if (likely(write_cb != NULL)) {
4464 if (likely(write_cb != SPR_NOACCESS)) {
4465 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4466 } else {
4467 /* Privilege exception */
4468 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4469 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4470 if (qemu_log_separate()) {
4471 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4472 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4473 }
4474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4475 }
4476 } else {
4477 /* Not defined */
4478 if (qemu_log_separate()) {
4479 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4480 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4481 }
4482 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4483 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4484 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4485 }
4486 }
4487
4488 /*** Cache management ***/
4489
4490 /* dcbf */
4491 static void gen_dcbf(DisasContext *ctx)
4492 {
4493 /* XXX: specification says this is treated as a load by the MMU */
4494 TCGv t0;
4495 gen_set_access_type(ctx, ACCESS_CACHE);
4496 t0 = tcg_temp_new();
4497 gen_addr_reg_index(ctx, t0);
4498 gen_qemu_ld8u(ctx, t0, t0);
4499 tcg_temp_free(t0);
4500 }
4501
4502 /* dcbi (Supervisor only) */
4503 static void gen_dcbi(DisasContext *ctx)
4504 {
4505 #if defined(CONFIG_USER_ONLY)
4506 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4507 #else
4508 TCGv EA, val;
4509 if (unlikely(ctx->pr)) {
4510 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4511 return;
4512 }
4513 EA = tcg_temp_new();
4514 gen_set_access_type(ctx, ACCESS_CACHE);
4515 gen_addr_reg_index(ctx, EA);
4516 val = tcg_temp_new();
4517 /* XXX: specification says this should be treated as a store by the MMU */
4518 gen_qemu_ld8u(ctx, val, EA);
4519 gen_qemu_st8(ctx, val, EA);
4520 tcg_temp_free(val);
4521 tcg_temp_free(EA);
4522 #endif
4523 }
4524
4525 /* dcdst */
4526 static void gen_dcbst(DisasContext *ctx)
4527 {
4528 /* XXX: specification say this is treated as a load by the MMU */
4529 TCGv t0;
4530 gen_set_access_type(ctx, ACCESS_CACHE);
4531 t0 = tcg_temp_new();
4532 gen_addr_reg_index(ctx, t0);
4533 gen_qemu_ld8u(ctx, t0, t0);
4534 tcg_temp_free(t0);
4535 }
4536
4537 /* dcbt */
4538 static void gen_dcbt(DisasContext *ctx)
4539 {
4540 /* interpreted as no-op */
4541 /* XXX: specification say this is treated as a load by the MMU
4542 * but does not generate any exception
4543 */
4544 }
4545
4546 /* dcbtst */
4547 static void gen_dcbtst(DisasContext *ctx)
4548 {
4549 /* interpreted as no-op */
4550 /* XXX: specification say this is treated as a load by the MMU
4551 * but does not generate any exception
4552 */
4553 }
4554
4555 /* dcbtls */
4556 static void gen_dcbtls(DisasContext *ctx)
4557 {
4558 /* Always fails locking the cache */
4559 TCGv t0 = tcg_temp_new();
4560 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4561 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4562 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4563 tcg_temp_free(t0);
4564 }
4565
4566 /* dcbz */
4567 static void gen_dcbz(DisasContext *ctx)
4568 {
4569 TCGv tcgv_addr;
4570 TCGv_i32 tcgv_is_dcbzl;
4571 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4572
4573 gen_set_access_type(ctx, ACCESS_CACHE);
4574 /* NIP cannot be restored if the memory exception comes from an helper */
4575 gen_update_nip(ctx, ctx->nip - 4);
4576 tcgv_addr = tcg_temp_new();
4577 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4578
4579 gen_addr_reg_index(ctx, tcgv_addr);
4580 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4581
4582 tcg_temp_free(tcgv_addr);
4583 tcg_temp_free_i32(tcgv_is_dcbzl);
4584 }
4585
4586 /* dst / dstt */
4587 static void gen_dst(DisasContext *ctx)
4588 {
4589 if (rA(ctx->opcode) == 0) {
4590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4591 } else {
4592 /* interpreted as no-op */
4593 }
4594 }
4595
4596 /* dstst /dststt */
4597 static void gen_dstst(DisasContext *ctx)
4598 {
4599 if (rA(ctx->opcode) == 0) {
4600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4601 } else {
4602 /* interpreted as no-op */
4603 }
4604
4605 }
4606
4607 /* dss / dssall */
4608 static void gen_dss(DisasContext *ctx)
4609 {
4610 /* interpreted as no-op */
4611 }
4612
4613 /* icbi */
4614 static void gen_icbi(DisasContext *ctx)
4615 {
4616 TCGv t0;
4617 gen_set_access_type(ctx, ACCESS_CACHE);
4618 /* NIP cannot be restored if the memory exception comes from an helper */
4619 gen_update_nip(ctx, ctx->nip - 4);
4620 t0 = tcg_temp_new();
4621 gen_addr_reg_index(ctx, t0);
4622 gen_helper_icbi(cpu_env, t0);
4623 tcg_temp_free(t0);
4624 }
4625
4626 /* Optional: */
4627 /* dcba */
4628 static void gen_dcba(DisasContext *ctx)
4629 {
4630 /* interpreted as no-op */
4631 /* XXX: specification say this is treated as a store by the MMU
4632 * but does not generate any exception
4633 */
4634 }
4635
4636 /*** Segment register manipulation ***/
4637 /* Supervisor only: */
4638
4639 /* mfsr */
4640 static void gen_mfsr(DisasContext *ctx)
4641 {
4642 #if defined(CONFIG_USER_ONLY)
4643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4644 #else
4645 TCGv t0;
4646 if (unlikely(ctx->pr)) {
4647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4648 return;
4649 }
4650 t0 = tcg_const_tl(SR(ctx->opcode));
4651 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4652 tcg_temp_free(t0);
4653 #endif
4654 }
4655
4656 /* mfsrin */
4657 static void gen_mfsrin(DisasContext *ctx)
4658 {
4659 #if defined(CONFIG_USER_ONLY)
4660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4661 #else
4662 TCGv t0;
4663 if (unlikely(ctx->pr)) {
4664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4665 return;
4666 }
4667 t0 = tcg_temp_new();
4668 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4669 tcg_gen_andi_tl(t0, t0, 0xF);
4670 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4671 tcg_temp_free(t0);
4672 #endif
4673 }
4674
4675 /* mtsr */
4676 static void gen_mtsr(DisasContext *ctx)
4677 {
4678 #if defined(CONFIG_USER_ONLY)
4679 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4680 #else
4681 TCGv t0;
4682 if (unlikely(ctx->pr)) {
4683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4684 return;
4685 }
4686 t0 = tcg_const_tl(SR(ctx->opcode));
4687 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4688 tcg_temp_free(t0);
4689 #endif
4690 }
4691
4692 /* mtsrin */
4693 static void gen_mtsrin(DisasContext *ctx)
4694 {
4695 #if defined(CONFIG_USER_ONLY)
4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4697 #else
4698 TCGv t0;
4699 if (unlikely(ctx->pr)) {
4700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4701 return;
4702 }
4703 t0 = tcg_temp_new();
4704 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4705 tcg_gen_andi_tl(t0, t0, 0xF);
4706 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4707 tcg_temp_free(t0);
4708 #endif
4709 }
4710
4711 #if defined(TARGET_PPC64)
4712 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4713
4714 /* mfsr */
4715 static void gen_mfsr_64b(DisasContext *ctx)
4716 {
4717 #if defined(CONFIG_USER_ONLY)
4718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4719 #else
4720 TCGv t0;
4721 if (unlikely(ctx->pr)) {
4722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4723 return;
4724 }
4725 t0 = tcg_const_tl(SR(ctx->opcode));
4726 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4727 tcg_temp_free(t0);
4728 #endif
4729 }
4730
4731 /* mfsrin */
4732 static void gen_mfsrin_64b(DisasContext *ctx)
4733 {
4734 #if defined(CONFIG_USER_ONLY)
4735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4736 #else
4737 TCGv t0;
4738 if (unlikely(ctx->pr)) {
4739 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4740 return;
4741 }
4742 t0 = tcg_temp_new();
4743 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4744 tcg_gen_andi_tl(t0, t0, 0xF);
4745 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4746 tcg_temp_free(t0);
4747 #endif
4748 }
4749
4750 /* mtsr */
4751 static void gen_mtsr_64b(DisasContext *ctx)
4752 {
4753 #if defined(CONFIG_USER_ONLY)
4754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4755 #else
4756 TCGv t0;
4757 if (unlikely(ctx->pr)) {
4758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4759 return;
4760 }
4761 t0 = tcg_const_tl(SR(ctx->opcode));
4762 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4763 tcg_temp_free(t0);
4764 #endif
4765 }
4766
4767 /* mtsrin */
4768 static void gen_mtsrin_64b(DisasContext *ctx)
4769 {
4770 #if defined(CONFIG_USER_ONLY)
4771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4772 #else
4773 TCGv t0;
4774 if (unlikely(ctx->pr)) {
4775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4776 return;
4777 }
4778 t0 = tcg_temp_new();
4779 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4780 tcg_gen_andi_tl(t0, t0, 0xF);
4781 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4782 tcg_temp_free(t0);
4783 #endif
4784 }
4785
4786 /* slbmte */
4787 static void gen_slbmte(DisasContext *ctx)
4788 {
4789 #if defined(CONFIG_USER_ONLY)
4790 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4791 #else
4792 if (unlikely(ctx->pr)) {
4793 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4794 return;
4795 }
4796 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4797 cpu_gpr[rS(ctx->opcode)]);
4798 #endif
4799 }
4800
4801 static void gen_slbmfee(DisasContext *ctx)
4802 {
4803 #if defined(CONFIG_USER_ONLY)
4804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4805 #else
4806 if (unlikely(ctx->pr)) {
4807 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4808 return;
4809 }
4810 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4811 cpu_gpr[rB(ctx->opcode)]);
4812 #endif
4813 }
4814
4815 static void gen_slbmfev(DisasContext *ctx)
4816 {
4817 #if defined(CONFIG_USER_ONLY)
4818 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4819 #else
4820 if (unlikely(ctx->pr)) {
4821 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4822 return;
4823 }
4824 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4825 cpu_gpr[rB(ctx->opcode)]);
4826 #endif
4827 }
4828 #endif /* defined(TARGET_PPC64) */
4829
4830 /*** Lookaside buffer management ***/
4831 /* Optional & supervisor only: */
4832
4833 /* tlbia */
4834 static void gen_tlbia(DisasContext *ctx)
4835 {
4836 #if defined(CONFIG_USER_ONLY)
4837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4838 #else
4839 if (unlikely(ctx->pr)) {
4840 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4841 return;
4842 }
4843 gen_helper_tlbia(cpu_env);
4844 #endif
4845 }
4846
4847 /* tlbiel */
4848 static void gen_tlbiel(DisasContext *ctx)
4849 {
4850 #if defined(CONFIG_USER_ONLY)
4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4852 #else
4853 if (unlikely(ctx->pr)) {
4854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4855 return;
4856 }
4857 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4858 #endif
4859 }
4860
4861 /* tlbie */
4862 static void gen_tlbie(DisasContext *ctx)
4863 {
4864 #if defined(CONFIG_USER_ONLY)
4865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4866 #else
4867 if (unlikely(ctx->pr)) {
4868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4869 return;
4870 }
4871 if (NARROW_MODE(ctx)) {
4872 TCGv t0 = tcg_temp_new();
4873 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4874 gen_helper_tlbie(cpu_env, t0);
4875 tcg_temp_free(t0);
4876 } else {
4877 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4878 }
4879 #endif
4880 }
4881
4882 /* tlbsync */
4883 static void gen_tlbsync(DisasContext *ctx)
4884 {
4885 #if defined(CONFIG_USER_ONLY)
4886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4887 #else
4888 if (unlikely(ctx->pr)) {
4889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4890 return;
4891 }
4892 /* This has no effect: it should ensure that all previous
4893 * tlbie have completed
4894 */
4895 gen_stop_exception(ctx);
4896 #endif
4897 }
4898
4899 #if defined(TARGET_PPC64)
4900 /* slbia */
4901 static void gen_slbia(DisasContext *ctx)
4902 {
4903 #if defined(CONFIG_USER_ONLY)
4904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4905 #else
4906 if (unlikely(ctx->pr)) {
4907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4908 return;
4909 }
4910 gen_helper_slbia(cpu_env);
4911 #endif
4912 }
4913
4914 /* slbie */
4915 static void gen_slbie(DisasContext *ctx)
4916 {
4917 #if defined(CONFIG_USER_ONLY)
4918 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4919 #else
4920 if (unlikely(ctx->pr)) {
4921 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4922 return;
4923 }
4924 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4925 #endif
4926 }
4927 #endif
4928
4929 /*** External control ***/
4930 /* Optional: */
4931
4932 /* eciwx */
4933 static void gen_eciwx(DisasContext *ctx)
4934 {
4935 TCGv t0;
4936 /* Should check EAR[E] ! */
4937 gen_set_access_type(ctx, ACCESS_EXT);
4938 t0 = tcg_temp_new();
4939 gen_addr_reg_index(ctx, t0);
4940 gen_check_align(ctx, t0, 0x03);
4941 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4942 tcg_temp_free(t0);
4943 }
4944
4945 /* ecowx */
4946 static void gen_ecowx(DisasContext *ctx)
4947 {
4948 TCGv t0;
4949 /* Should check EAR[E] ! */
4950 gen_set_access_type(ctx, ACCESS_EXT);
4951 t0 = tcg_temp_new();
4952 gen_addr_reg_index(ctx, t0);
4953 gen_check_align(ctx, t0, 0x03);
4954 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4955 tcg_temp_free(t0);
4956 }
4957
4958 /* PowerPC 601 specific instructions */
4959
4960 /* abs - abs. */
4961 static void gen_abs(DisasContext *ctx)
4962 {
4963 TCGLabel *l1 = gen_new_label();
4964 TCGLabel *l2 = gen_new_label();
4965 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4966 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4967 tcg_gen_br(l2);
4968 gen_set_label(l1);
4969 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4970 gen_set_label(l2);
4971 if (unlikely(Rc(ctx->opcode) != 0))
4972 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4973 }
4974
4975 /* abso - abso. */
4976 static void gen_abso(DisasContext *ctx)
4977 {
4978 TCGLabel *l1 = gen_new_label();
4979 TCGLabel *l2 = gen_new_label();
4980 TCGLabel *l3 = gen_new_label();
4981 /* Start with XER OV disabled, the most likely case */
4982 tcg_gen_movi_tl(cpu_ov, 0);
4983 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4984 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4985 tcg_gen_movi_tl(cpu_ov, 1);
4986 tcg_gen_movi_tl(cpu_so, 1);
4987 tcg_gen_br(l2);
4988 gen_set_label(l1);
4989 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4990 tcg_gen_br(l3);
4991 gen_set_label(l2);
4992 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4993 gen_set_label(l3);
4994 if (unlikely(Rc(ctx->opcode) != 0))
4995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4996 }
4997
4998 /* clcs */
4999 static void gen_clcs(DisasContext *ctx)
5000 {
5001 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5002 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5003 tcg_temp_free_i32(t0);
5004 /* Rc=1 sets CR0 to an undefined state */
5005 }
5006
5007 /* div - div. */
5008 static void gen_div(DisasContext *ctx)
5009 {
5010 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5011 cpu_gpr[rB(ctx->opcode)]);
5012 if (unlikely(Rc(ctx->opcode) != 0))
5013 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5014 }
5015
5016 /* divo - divo. */
5017 static void gen_divo(DisasContext *ctx)
5018 {
5019 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5020 cpu_gpr[rB(ctx->opcode)]);
5021 if (unlikely(Rc(ctx->opcode) != 0))
5022 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5023 }
5024
5025 /* divs - divs. */
5026 static void gen_divs(DisasContext *ctx)
5027 {
5028 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5029 cpu_gpr[rB(ctx->opcode)]);
5030 if (unlikely(Rc(ctx->opcode) != 0))
5031 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5032 }
5033
5034 /* divso - divso. */
5035 static void gen_divso(DisasContext *ctx)
5036 {
5037 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5039 if (unlikely(Rc(ctx->opcode) != 0))
5040 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5041 }
5042
5043 /* doz - doz. */
5044 static void gen_doz(DisasContext *ctx)
5045 {
5046 TCGLabel *l1 = gen_new_label();
5047 TCGLabel *l2 = gen_new_label();
5048 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5049 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5050 tcg_gen_br(l2);
5051 gen_set_label(l1);
5052 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5053 gen_set_label(l2);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5056 }
5057
5058 /* dozo - dozo. */
5059 static void gen_dozo(DisasContext *ctx)
5060 {
5061 TCGLabel *l1 = gen_new_label();
5062 TCGLabel *l2 = gen_new_label();
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 TCGv t2 = tcg_temp_new();
5066 /* Start with XER OV disabled, the most likely case */
5067 tcg_gen_movi_tl(cpu_ov, 0);
5068 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5069 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5070 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5071 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5072 tcg_gen_andc_tl(t1, t1, t2);
5073 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5074 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5075 tcg_gen_movi_tl(cpu_ov, 1);
5076 tcg_gen_movi_tl(cpu_so, 1);
5077 tcg_gen_br(l2);
5078 gen_set_label(l1);
5079 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5080 gen_set_label(l2);
5081 tcg_temp_free(t0);
5082 tcg_temp_free(t1);
5083 tcg_temp_free(t2);
5084 if (unlikely(Rc(ctx->opcode) != 0))
5085 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5086 }
5087
5088 /* dozi */
5089 static void gen_dozi(DisasContext *ctx)
5090 {
5091 target_long simm = SIMM(ctx->opcode);
5092 TCGLabel *l1 = gen_new_label();
5093 TCGLabel *l2 = gen_new_label();
5094 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5095 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5096 tcg_gen_br(l2);
5097 gen_set_label(l1);
5098 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5099 gen_set_label(l2);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5102 }
5103
5104 /* lscbx - lscbx. */
5105 static void gen_lscbx(DisasContext *ctx)
5106 {
5107 TCGv t0 = tcg_temp_new();
5108 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5109 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5110 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5111
5112 gen_addr_reg_index(ctx, t0);
5113 /* NIP cannot be restored if the memory exception comes from an helper */
5114 gen_update_nip(ctx, ctx->nip - 4);
5115 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5116 tcg_temp_free_i32(t1);
5117 tcg_temp_free_i32(t2);
5118 tcg_temp_free_i32(t3);
5119 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5120 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5121 if (unlikely(Rc(ctx->opcode) != 0))
5122 gen_set_Rc0(ctx, t0);
5123 tcg_temp_free(t0);
5124 }
5125
5126 /* maskg - maskg. */
5127 static void gen_maskg(DisasContext *ctx)
5128 {
5129 TCGLabel *l1 = gen_new_label();
5130 TCGv t0 = tcg_temp_new();
5131 TCGv t1 = tcg_temp_new();
5132 TCGv t2 = tcg_temp_new();
5133 TCGv t3 = tcg_temp_new();
5134 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5135 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5136 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5137 tcg_gen_addi_tl(t2, t0, 1);
5138 tcg_gen_shr_tl(t2, t3, t2);
5139 tcg_gen_shr_tl(t3, t3, t1);
5140 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5141 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5142 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5143 gen_set_label(l1);
5144 tcg_temp_free(t0);
5145 tcg_temp_free(t1);
5146 tcg_temp_free(t2);
5147 tcg_temp_free(t3);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* maskir - maskir. */
5153 static void gen_maskir(DisasContext *ctx)
5154 {
5155 TCGv t0 = tcg_temp_new();
5156 TCGv t1 = tcg_temp_new();
5157 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5158 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5159 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5160 tcg_temp_free(t0);
5161 tcg_temp_free(t1);
5162 if (unlikely(Rc(ctx->opcode) != 0))
5163 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5164 }
5165
5166 /* mul - mul. */
5167 static void gen_mul(DisasContext *ctx)
5168 {
5169 TCGv_i64 t0 = tcg_temp_new_i64();
5170 TCGv_i64 t1 = tcg_temp_new_i64();
5171 TCGv t2 = tcg_temp_new();
5172 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5173 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5174 tcg_gen_mul_i64(t0, t0, t1);
5175 tcg_gen_trunc_i64_tl(t2, t0);
5176 gen_store_spr(SPR_MQ, t2);
5177 tcg_gen_shri_i64(t1, t0, 32);
5178 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5179 tcg_temp_free_i64(t0);
5180 tcg_temp_free_i64(t1);
5181 tcg_temp_free(t2);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5184 }
5185
5186 /* mulo - mulo. */
5187 static void gen_mulo(DisasContext *ctx)
5188 {
5189 TCGLabel *l1 = gen_new_label();
5190 TCGv_i64 t0 = tcg_temp_new_i64();
5191 TCGv_i64 t1 = tcg_temp_new_i64();
5192 TCGv t2 = tcg_temp_new();
5193 /* Start with XER OV disabled, the most likely case */
5194 tcg_gen_movi_tl(cpu_ov, 0);
5195 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5196 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5197 tcg_gen_mul_i64(t0, t0, t1);
5198 tcg_gen_trunc_i64_tl(t2, t0);
5199 gen_store_spr(SPR_MQ, t2);
5200 tcg_gen_shri_i64(t1, t0, 32);
5201 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5202 tcg_gen_ext32s_i64(t1, t0);
5203 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5204 tcg_gen_movi_tl(cpu_ov, 1);
5205 tcg_gen_movi_tl(cpu_so, 1);
5206 gen_set_label(l1);
5207 tcg_temp_free_i64(t0);
5208 tcg_temp_free_i64(t1);
5209 tcg_temp_free(t2);
5210 if (unlikely(Rc(ctx->opcode) != 0))
5211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5212 }
5213
5214 /* nabs - nabs. */
5215 static void gen_nabs(DisasContext *ctx)
5216 {
5217 TCGLabel *l1 = gen_new_label();
5218 TCGLabel *l2 = gen_new_label();
5219 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5220 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5221 tcg_gen_br(l2);
5222 gen_set_label(l1);
5223 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5224 gen_set_label(l2);
5225 if (unlikely(Rc(ctx->opcode) != 0))
5226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5227 }
5228
5229 /* nabso - nabso. */
5230 static void gen_nabso(DisasContext *ctx)
5231 {
5232 TCGLabel *l1 = gen_new_label();
5233 TCGLabel *l2 = gen_new_label();
5234 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5235 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5236 tcg_gen_br(l2);
5237 gen_set_label(l1);
5238 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5239 gen_set_label(l2);
5240 /* nabs never overflows */
5241 tcg_gen_movi_tl(cpu_ov, 0);
5242 if (unlikely(Rc(ctx->opcode) != 0))
5243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5244 }
5245
5246 /* rlmi - rlmi. */
5247 static void gen_rlmi(DisasContext *ctx)
5248 {
5249 uint32_t mb = MB(ctx->opcode);
5250 uint32_t me = ME(ctx->opcode);
5251 TCGv t0 = tcg_temp_new();
5252 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5253 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5254 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5255 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5256 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5257 tcg_temp_free(t0);
5258 if (unlikely(Rc(ctx->opcode) != 0))
5259 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5260 }
5261
5262 /* rrib - rrib. */
5263 static void gen_rrib(DisasContext *ctx)
5264 {
5265 TCGv t0 = tcg_temp_new();
5266 TCGv t1 = tcg_temp_new();
5267 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5268 tcg_gen_movi_tl(t1, 0x80000000);
5269 tcg_gen_shr_tl(t1, t1, t0);
5270 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5271 tcg_gen_and_tl(t0, t0, t1);
5272 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5273 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5274 tcg_temp_free(t0);
5275 tcg_temp_free(t1);
5276 if (unlikely(Rc(ctx->opcode) != 0))
5277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5278 }
5279
5280 /* sle - sle. */
5281 static void gen_sle(DisasContext *ctx)
5282 {
5283 TCGv t0 = tcg_temp_new();
5284 TCGv t1 = tcg_temp_new();
5285 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5286 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5287 tcg_gen_subfi_tl(t1, 32, t1);
5288 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5289 tcg_gen_or_tl(t1, t0, t1);
5290 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5291 gen_store_spr(SPR_MQ, t1);
5292 tcg_temp_free(t0);
5293 tcg_temp_free(t1);
5294 if (unlikely(Rc(ctx->opcode) != 0))
5295 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5296 }
5297
5298 /* sleq - sleq. */
5299 static void gen_sleq(DisasContext *ctx)
5300 {
5301 TCGv t0 = tcg_temp_new();
5302 TCGv t1 = tcg_temp_new();
5303 TCGv t2 = tcg_temp_new();
5304 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5305 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5306 tcg_gen_shl_tl(t2, t2, t0);
5307 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5308 gen_load_spr(t1, SPR_MQ);
5309 gen_store_spr(SPR_MQ, t0);
5310 tcg_gen_and_tl(t0, t0, t2);
5311 tcg_gen_andc_tl(t1, t1, t2);
5312 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5313 tcg_temp_free(t0);
5314 tcg_temp_free(t1);
5315 tcg_temp_free(t2);
5316 if (unlikely(Rc(ctx->opcode) != 0))
5317 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5318 }
5319
5320 /* sliq - sliq. */
5321 static void gen_sliq(DisasContext *ctx)
5322 {
5323 int sh = SH(ctx->opcode);
5324 TCGv t0 = tcg_temp_new();
5325 TCGv t1 = tcg_temp_new();
5326 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5327 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5328 tcg_gen_or_tl(t1, t0, t1);
5329 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5330 gen_store_spr(SPR_MQ, t1);
5331 tcg_temp_free(t0);
5332 tcg_temp_free(t1);
5333 if (unlikely(Rc(ctx->opcode) != 0))
5334 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5335 }
5336
5337 /* slliq - slliq. */
5338 static void gen_slliq(DisasContext *ctx)
5339 {
5340 int sh = SH(ctx->opcode);
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_new();
5343 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5344 gen_load_spr(t1, SPR_MQ);
5345 gen_store_spr(SPR_MQ, t0);
5346 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5347 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5348 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5349 tcg_temp_free(t0);
5350 tcg_temp_free(t1);
5351 if (unlikely(Rc(ctx->opcode) != 0))
5352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5353 }
5354
5355 /* sllq - sllq. */
5356 static void gen_sllq(DisasContext *ctx)
5357 {
5358 TCGLabel *l1 = gen_new_label();
5359 TCGLabel *l2 = gen_new_label();
5360 TCGv t0 = tcg_temp_local_new();
5361 TCGv t1 = tcg_temp_local_new();
5362 TCGv t2 = tcg_temp_local_new();
5363 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5364 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5365 tcg_gen_shl_tl(t1, t1, t2);
5366 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5367 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5368 gen_load_spr(t0, SPR_MQ);
5369 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5370 tcg_gen_br(l2);
5371 gen_set_label(l1);
5372 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5373 gen_load_spr(t2, SPR_MQ);
5374 tcg_gen_andc_tl(t1, t2, t1);
5375 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5376 gen_set_label(l2);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
5379 tcg_temp_free(t2);
5380 if (unlikely(Rc(ctx->opcode) != 0))
5381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5382 }
5383
5384 /* slq - slq. */
5385 static void gen_slq(DisasContext *ctx)
5386 {
5387 TCGLabel *l1 = gen_new_label();
5388 TCGv t0 = tcg_temp_new();
5389 TCGv t1 = tcg_temp_new();
5390 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5391 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5392 tcg_gen_subfi_tl(t1, 32, t1);
5393 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5394 tcg_gen_or_tl(t1, t0, t1);
5395 gen_store_spr(SPR_MQ, t1);
5396 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5397 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5398 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5399 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5400 gen_set_label(l1);
5401 tcg_temp_free(t0);
5402 tcg_temp_free(t1);
5403 if (unlikely(Rc(ctx->opcode) != 0))
5404 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5405 }
5406
5407 /* sraiq - sraiq. */
5408 static void gen_sraiq(DisasContext *ctx)
5409 {
5410 int sh = SH(ctx->opcode);
5411 TCGLabel *l1 = gen_new_label();
5412 TCGv t0 = tcg_temp_new();
5413 TCGv t1 = tcg_temp_new();
5414 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5415 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5416 tcg_gen_or_tl(t0, t0, t1);
5417 gen_store_spr(SPR_MQ, t0);
5418 tcg_gen_movi_tl(cpu_ca, 0);
5419 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5420 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5421 tcg_gen_movi_tl(cpu_ca, 1);
5422 gen_set_label(l1);
5423 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5424 tcg_temp_free(t0);
5425 tcg_temp_free(t1);
5426 if (unlikely(Rc(ctx->opcode) != 0))
5427 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5428 }
5429
5430 /* sraq - sraq. */
5431 static void gen_sraq(DisasContext *ctx)
5432 {
5433 TCGLabel *l1 = gen_new_label();
5434 TCGLabel *l2 = gen_new_label();
5435 TCGv t0 = tcg_temp_new();
5436 TCGv t1 = tcg_temp_local_new();
5437 TCGv t2 = tcg_temp_local_new();
5438 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5439 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5440 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5441 tcg_gen_subfi_tl(t2, 32, t2);
5442 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5443 tcg_gen_or_tl(t0, t0, t2);
5444 gen_store_spr(SPR_MQ, t0);
5445 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5446 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5447 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5448 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5449 gen_set_label(l1);
5450 tcg_temp_free(t0);
5451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5452 tcg_gen_movi_tl(cpu_ca, 0);
5453 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5454 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5455 tcg_gen_movi_tl(cpu_ca, 1);
5456 gen_set_label(l2);
5457 tcg_temp_free(t1);
5458 tcg_temp_free(t2);
5459 if (unlikely(Rc(ctx->opcode) != 0))
5460 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5461 }
5462
5463 /* sre - sre. */
5464 static void gen_sre(DisasContext *ctx)
5465 {
5466 TCGv t0 = tcg_temp_new();
5467 TCGv t1 = tcg_temp_new();
5468 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5469 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5470 tcg_gen_subfi_tl(t1, 32, t1);
5471 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5472 tcg_gen_or_tl(t1, t0, t1);
5473 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5474 gen_store_spr(SPR_MQ, t1);
5475 tcg_temp_free(t0);
5476 tcg_temp_free(t1);
5477 if (unlikely(Rc(ctx->opcode) != 0))
5478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5479 }
5480
5481 /* srea - srea. */
5482 static void gen_srea(DisasContext *ctx)
5483 {
5484 TCGv t0 = tcg_temp_new();
5485 TCGv t1 = tcg_temp_new();
5486 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5487 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5488 gen_store_spr(SPR_MQ, t0);
5489 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5490 tcg_temp_free(t0);
5491 tcg_temp_free(t1);
5492 if (unlikely(Rc(ctx->opcode) != 0))
5493 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5494 }
5495
5496 /* sreq */
5497 static void gen_sreq(DisasContext *ctx)
5498 {
5499 TCGv t0 = tcg_temp_new();
5500 TCGv t1 = tcg_temp_new();
5501 TCGv t2 = tcg_temp_new();
5502 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5503 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5504 tcg_gen_shr_tl(t1, t1, t0);
5505 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5506 gen_load_spr(t2, SPR_MQ);
5507 gen_store_spr(SPR_MQ, t0);
5508 tcg_gen_and_tl(t0, t0, t1);
5509 tcg_gen_andc_tl(t2, t2, t1);
5510 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5511 tcg_temp_free(t0);
5512 tcg_temp_free(t1);
5513 tcg_temp_free(t2);
5514 if (unlikely(Rc(ctx->opcode) != 0))
5515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5516 }
5517
5518 /* sriq */
5519 static void gen_sriq(DisasContext *ctx)
5520 {
5521 int sh = SH(ctx->opcode);
5522 TCGv t0 = tcg_temp_new();
5523 TCGv t1 = tcg_temp_new();
5524 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5525 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5526 tcg_gen_or_tl(t1, t0, t1);
5527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5528 gen_store_spr(SPR_MQ, t1);
5529 tcg_temp_free(t0);
5530 tcg_temp_free(t1);
5531 if (unlikely(Rc(ctx->opcode) != 0))
5532 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5533 }
5534
5535 /* srliq */
5536 static void gen_srliq(DisasContext *ctx)
5537 {
5538 int sh = SH(ctx->opcode);
5539 TCGv t0 = tcg_temp_new();
5540 TCGv t1 = tcg_temp_new();
5541 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5542 gen_load_spr(t1, SPR_MQ);
5543 gen_store_spr(SPR_MQ, t0);
5544 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5545 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5546 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5547 tcg_temp_free(t0);
5548 tcg_temp_free(t1);
5549 if (unlikely(Rc(ctx->opcode) != 0))
5550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5551 }
5552
5553 /* srlq */
5554 static void gen_srlq(DisasContext *ctx)
5555 {
5556 TCGLabel *l1 = gen_new_label();
5557 TCGLabel *l2 = gen_new_label();
5558 TCGv t0 = tcg_temp_local_new();
5559 TCGv t1 = tcg_temp_local_new();
5560 TCGv t2 = tcg_temp_local_new();
5561 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5562 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5563 tcg_gen_shr_tl(t2, t1, t2);
5564 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5565 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5566 gen_load_spr(t0, SPR_MQ);
5567 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5568 tcg_gen_br(l2);
5569 gen_set_label(l1);
5570 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5571 tcg_gen_and_tl(t0, t0, t2);
5572 gen_load_spr(t1, SPR_MQ);
5573 tcg_gen_andc_tl(t1, t1, t2);
5574 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5575 gen_set_label(l2);
5576 tcg_temp_free(t0);
5577 tcg_temp_free(t1);
5578 tcg_temp_free(t2);
5579 if (unlikely(Rc(ctx->opcode) != 0))
5580 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5581 }
5582
5583 /* srq */
5584 static void gen_srq(DisasContext *ctx)
5585 {
5586 TCGLabel *l1 = gen_new_label();
5587 TCGv t0 = tcg_temp_new();
5588 TCGv t1 = tcg_temp_new();
5589 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5590 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5591 tcg_gen_subfi_tl(t1, 32, t1);
5592 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5593 tcg_gen_or_tl(t1, t0, t1);
5594 gen_store_spr(SPR_MQ, t1);
5595 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5596 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5597 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5598 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5599 gen_set_label(l1);
5600 tcg_temp_free(t0);
5601 tcg_temp_free(t1);
5602 if (unlikely(Rc(ctx->opcode) != 0))
5603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5604 }
5605
5606 /* PowerPC 602 specific instructions */
5607
5608 /* dsa */
5609 static void gen_dsa(DisasContext *ctx)
5610 {
5611 /* XXX: TODO */
5612 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5613 }
5614
5615 /* esa */
5616 static void gen_esa(DisasContext *ctx)
5617 {
5618 /* XXX: TODO */
5619 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5620 }
5621
5622 /* mfrom */
5623 static void gen_mfrom(DisasContext *ctx)
5624 {
5625 #if defined(CONFIG_USER_ONLY)
5626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5627 #else
5628 if (unlikely(ctx->pr)) {
5629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5630 return;
5631 }
5632 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5633 #endif
5634 }
5635
5636 /* 602 - 603 - G2 TLB management */
5637
5638 /* tlbld */
5639 static void gen_tlbld_6xx(DisasContext *ctx)
5640 {
5641 #if defined(CONFIG_USER_ONLY)
5642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5643 #else
5644 if (unlikely(ctx->pr)) {
5645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5646 return;
5647 }
5648 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5649 #endif
5650 }
5651
5652 /* tlbli */
5653 static void gen_tlbli_6xx(DisasContext *ctx)
5654 {
5655 #if defined(CONFIG_USER_ONLY)
5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5657 #else
5658 if (unlikely(ctx->pr)) {
5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5660 return;
5661 }
5662 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5663 #endif
5664 }
5665
5666 /* 74xx TLB management */
5667
5668 /* tlbld */
5669 static void gen_tlbld_74xx(DisasContext *ctx)
5670 {
5671 #if defined(CONFIG_USER_ONLY)
5672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5673 #else
5674 if (unlikely(ctx->pr)) {
5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5676 return;
5677 }
5678 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5679 #endif
5680 }
5681
5682 /* tlbli */
5683 static void gen_tlbli_74xx(DisasContext *ctx)
5684 {
5685 #if defined(CONFIG_USER_ONLY)
5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5687 #else
5688 if (unlikely(ctx->pr)) {
5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5690 return;
5691 }
5692 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5693 #endif
5694 }
5695
5696 /* POWER instructions not in PowerPC 601 */
5697
5698 /* clf */
5699 static void gen_clf(DisasContext *ctx)
5700 {
5701 /* Cache line flush: implemented as no-op */
5702 }
5703
5704 /* cli */
5705 static void gen_cli(DisasContext *ctx)
5706 {
5707 /* Cache line invalidate: privileged and treated as no-op */
5708 #if defined(CONFIG_USER_ONLY)
5709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5710 #else
5711 if (unlikely(ctx->pr)) {
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 return;
5714 }
5715 #endif
5716 }
5717
5718 /* dclst */
5719 static void gen_dclst(DisasContext *ctx)
5720 {
5721 /* Data cache line store: treated as no-op */
5722 }
5723
5724 static void gen_mfsri(DisasContext *ctx)
5725 {
5726 #if defined(CONFIG_USER_ONLY)
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 #else
5729 int ra = rA(ctx->opcode);
5730 int rd = rD(ctx->opcode);
5731 TCGv t0;
5732 if (unlikely(ctx->pr)) {
5733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5734 return;
5735 }
5736 t0 = tcg_temp_new();
5737 gen_addr_reg_index(ctx, t0);
5738 tcg_gen_shri_tl(t0, t0, 28);
5739 tcg_gen_andi_tl(t0, t0, 0xF);
5740 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5741 tcg_temp_free(t0);
5742 if (ra != 0 && ra != rd)
5743 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5744 #endif
5745 }
5746
5747 static void gen_rac(DisasContext *ctx)
5748 {
5749 #if defined(CONFIG_USER_ONLY)
5750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5751 #else
5752 TCGv t0;
5753 if (unlikely(ctx->pr)) {
5754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5755 return;
5756 }
5757 t0 = tcg_temp_new();
5758 gen_addr_reg_index(ctx, t0);
5759 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5760 tcg_temp_free(t0);
5761 #endif
5762 }
5763
5764 static void gen_rfsvc(DisasContext *ctx)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5768 #else
5769 if (unlikely(ctx->pr)) {
5770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5771 return;
5772 }
5773 gen_helper_rfsvc(cpu_env);
5774 gen_sync_exception(ctx);
5775 #endif
5776 }
5777
5778 /* svc is not implemented for now */
5779
5780 /* POWER2 specific instructions */
5781 /* Quad manipulation (load/store two floats at a time) */
5782
5783 /* lfq */
5784 static void gen_lfq(DisasContext *ctx)
5785 {
5786 int rd = rD(ctx->opcode);
5787 TCGv t0;
5788 gen_set_access_type(ctx, ACCESS_FLOAT);
5789 t0 = tcg_temp_new();
5790 gen_addr_imm_index(ctx, t0, 0);
5791 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5792 gen_addr_add(ctx, t0, t0, 8);
5793 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5794 tcg_temp_free(t0);
5795 }
5796
5797 /* lfqu */
5798 static void gen_lfqu(DisasContext *ctx)
5799 {
5800 int ra = rA(ctx->opcode);
5801 int rd = rD(ctx->opcode);
5802 TCGv t0, t1;
5803 gen_set_access_type(ctx, ACCESS_FLOAT);
5804 t0 = tcg_temp_new();
5805 t1 = tcg_temp_new();
5806 gen_addr_imm_index(ctx, t0, 0);
5807 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5808 gen_addr_add(ctx, t1, t0, 8);
5809 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5810 if (ra != 0)
5811 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5812 tcg_temp_free(t0);
5813 tcg_temp_free(t1);
5814 }
5815
5816 /* lfqux */
5817 static void gen_lfqux(DisasContext *ctx)
5818 {
5819 int ra = rA(ctx->opcode);
5820 int rd = rD(ctx->opcode);
5821 gen_set_access_type(ctx, ACCESS_FLOAT);
5822 TCGv t0, t1;
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5826 t1 = tcg_temp_new();
5827 gen_addr_add(ctx, t1, t0, 8);
5828 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5829 tcg_temp_free(t1);
5830 if (ra != 0)
5831 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5832 tcg_temp_free(t0);
5833 }
5834
5835 /* lfqx */
5836 static void gen_lfqx(DisasContext *ctx)
5837 {
5838 int rd = rD(ctx->opcode);
5839 TCGv t0;
5840 gen_set_access_type(ctx, ACCESS_FLOAT);
5841 t0 = tcg_temp_new();
5842 gen_addr_reg_index(ctx, t0);
5843 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5844 gen_addr_add(ctx, t0, t0, 8);
5845 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5846 tcg_temp_free(t0);
5847 }
5848
5849 /* stfq */
5850 static void gen_stfq(DisasContext *ctx)
5851 {
5852 int rd = rD(ctx->opcode);
5853 TCGv t0;
5854 gen_set_access_type(ctx, ACCESS_FLOAT);
5855 t0 = tcg_temp_new();
5856 gen_addr_imm_index(ctx, t0, 0);
5857 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5858 gen_addr_add(ctx, t0, t0, 8);
5859 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5860 tcg_temp_free(t0);
5861 }
5862
5863 /* stfqu */
5864 static void gen_stfqu(DisasContext *ctx)
5865 {
5866 int ra = rA(ctx->opcode);
5867 int rd = rD(ctx->opcode);
5868 TCGv t0, t1;
5869 gen_set_access_type(ctx, ACCESS_FLOAT);
5870 t0 = tcg_temp_new();
5871 gen_addr_imm_index(ctx, t0, 0);
5872 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5873 t1 = tcg_temp_new();
5874 gen_addr_add(ctx, t1, t0, 8);
5875 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5876 tcg_temp_free(t1);
5877 if (ra != 0)
5878 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5879 tcg_temp_free(t0);
5880 }
5881
5882 /* stfqux */
5883 static void gen_stfqux(DisasContext *ctx)
5884 {
5885 int ra = rA(ctx->opcode);
5886 int rd = rD(ctx->opcode);
5887 TCGv t0, t1;
5888 gen_set_access_type(ctx, ACCESS_FLOAT);
5889 t0 = tcg_temp_new();
5890 gen_addr_reg_index(ctx, t0);
5891 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5892 t1 = tcg_temp_new();
5893 gen_addr_add(ctx, t1, t0, 8);
5894 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5895 tcg_temp_free(t1);
5896 if (ra != 0)
5897 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5898 tcg_temp_free(t0);
5899 }
5900
5901 /* stfqx */
5902 static void gen_stfqx(DisasContext *ctx)
5903 {
5904 int rd = rD(ctx->opcode);
5905 TCGv t0;
5906 gen_set_access_type(ctx, ACCESS_FLOAT);
5907 t0 = tcg_temp_new();
5908 gen_addr_reg_index(ctx, t0);
5909 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5910 gen_addr_add(ctx, t0, t0, 8);
5911 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5912 tcg_temp_free(t0);
5913 }
5914
5915 /* BookE specific instructions */
5916
5917 /* XXX: not implemented on 440 ? */
5918 static void gen_mfapidi(DisasContext *ctx)
5919 {
5920 /* XXX: TODO */
5921 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5922 }
5923
5924 /* XXX: not implemented on 440 ? */
5925 static void gen_tlbiva(DisasContext *ctx)
5926 {
5927 #if defined(CONFIG_USER_ONLY)
5928 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5929 #else
5930 TCGv t0;
5931 if (unlikely(ctx->pr)) {
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5933 return;
5934 }
5935 t0 = tcg_temp_new();
5936 gen_addr_reg_index(ctx, t0);
5937 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5938 tcg_temp_free(t0);
5939 #endif
5940 }
5941
5942 /* All 405 MAC instructions are translated here */
5943 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5944 int ra, int rb, int rt, int Rc)
5945 {
5946 TCGv t0, t1;
5947
5948 t0 = tcg_temp_local_new();
5949 t1 = tcg_temp_local_new();
5950
5951 switch (opc3 & 0x0D) {
5952 case 0x05:
5953 /* macchw - macchw. - macchwo - macchwo. */
5954 /* macchws - macchws. - macchwso - macchwso. */
5955 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5956 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5957 /* mulchw - mulchw. */
5958 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5959 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5960 tcg_gen_ext16s_tl(t1, t1);
5961 break;
5962 case 0x04:
5963 /* macchwu - macchwu. - macchwuo - macchwuo. */
5964 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5965 /* mulchwu - mulchwu. */
5966 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5967 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5968 tcg_gen_ext16u_tl(t1, t1);
5969 break;
5970 case 0x01:
5971 /* machhw - machhw. - machhwo - machhwo. */
5972 /* machhws - machhws. - machhwso - machhwso. */
5973 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5974 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5975 /* mulhhw - mulhhw. */
5976 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5977 tcg_gen_ext16s_tl(t0, t0);
5978 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5979 tcg_gen_ext16s_tl(t1, t1);
5980 break;
5981 case 0x00:
5982 /* machhwu - machhwu. - machhwuo - machhwuo. */
5983 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5984 /* mulhhwu - mulhhwu. */
5985 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5986 tcg_gen_ext16u_tl(t0, t0);
5987 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5988 tcg_gen_ext16u_tl(t1, t1);
5989 break;
5990 case 0x0D:
5991 /* maclhw - maclhw. - maclhwo - maclhwo. */
5992 /* maclhws - maclhws. - maclhwso - maclhwso. */
5993 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5994 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5995 /* mullhw - mullhw. */
5996 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5997 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5998 break;
5999 case 0x0C:
6000 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6001 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6002 /* mullhwu - mullhwu. */
6003 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6004 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6005 break;
6006 }
6007 if (opc2 & 0x04) {
6008 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6009 tcg_gen_mul_tl(t1, t0, t1);
6010 if (opc2 & 0x02) {
6011 /* nmultiply-and-accumulate (0x0E) */
6012 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6013 } else {
6014 /* multiply-and-accumulate (0x0C) */
6015 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6016 }
6017
6018 if (opc3 & 0x12) {
6019 /* Check overflow and/or saturate */
6020 TCGLabel *l1 = gen_new_label();
6021
6022 if (opc3 & 0x10) {
6023 /* Start with XER OV disabled, the most likely case */
6024 tcg_gen_movi_tl(cpu_ov, 0);
6025 }
6026 if (opc3 & 0x01) {
6027 /* Signed */
6028 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6029 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6030 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6031 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6032 if (opc3 & 0x02) {
6033 /* Saturate */
6034 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6035 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6036 }
6037 } else {
6038 /* Unsigned */
6039 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6040 if (opc3 & 0x02) {
6041 /* Saturate */
6042 tcg_gen_movi_tl(t0, UINT32_MAX);
6043 }
6044 }
6045 if (opc3 & 0x10) {
6046 /* Check overflow */
6047 tcg_gen_movi_tl(cpu_ov, 1);
6048 tcg_gen_movi_tl(cpu_so, 1);
6049 }
6050 gen_set_label(l1);
6051 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6052 }
6053 } else {
6054 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6055 }
6056 tcg_temp_free(t0);
6057 tcg_temp_free(t1);
6058 if (unlikely(Rc) != 0) {
6059 /* Update Rc0 */
6060 gen_set_Rc0(ctx, cpu_gpr[rt]);
6061 }
6062 }
6063
6064 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6065 static void glue(gen_, name)(DisasContext *ctx) \
6066 { \
6067 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6068 rD(ctx->opcode), Rc(ctx->opcode)); \
6069 }
6070
6071 /* macchw - macchw. */
6072 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6073 /* macchwo - macchwo. */
6074 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6075 /* macchws - macchws. */
6076 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6077 /* macchwso - macchwso. */
6078 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6079 /* macchwsu - macchwsu. */
6080 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6081 /* macchwsuo - macchwsuo. */
6082 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6083 /* macchwu - macchwu. */
6084 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6085 /* macchwuo - macchwuo. */
6086 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6087 /* machhw - machhw. */
6088 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6089 /* machhwo - machhwo. */
6090 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6091 /* machhws - machhws. */
6092 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6093 /* machhwso - machhwso. */
6094 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6095 /* machhwsu - machhwsu. */
6096 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6097 /* machhwsuo - machhwsuo. */
6098 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6099 /* machhwu - machhwu. */
6100 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6101 /* machhwuo - machhwuo. */
6102 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6103 /* maclhw - maclhw. */
6104 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6105 /* maclhwo - maclhwo. */
6106 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6107 /* maclhws - maclhws. */
6108 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6109 /* maclhwso - maclhwso. */
6110 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6111 /* maclhwu - maclhwu. */
6112 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6113 /* maclhwuo - maclhwuo. */
6114 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6115 /* maclhwsu - maclhwsu. */
6116 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6117 /* maclhwsuo - maclhwsuo. */
6118 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6119 /* nmacchw - nmacchw. */
6120 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6121 /* nmacchwo - nmacchwo. */
6122 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6123 /* nmacchws - nmacchws. */
6124 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6125 /* nmacchwso - nmacchwso. */
6126 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6127 /* nmachhw - nmachhw. */
6128 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6129 /* nmachhwo - nmachhwo. */
6130 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6131 /* nmachhws - nmachhws. */
6132 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6133 /* nmachhwso - nmachhwso. */
6134 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6135 /* nmaclhw - nmaclhw. */
6136 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6137 /* nmaclhwo - nmaclhwo. */
6138 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6139 /* nmaclhws - nmaclhws. */
6140 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6141 /* nmaclhwso - nmaclhwso. */
6142 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6143
6144 /* mulchw - mulchw. */
6145 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6146 /* mulchwu - mulchwu. */
6147 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6148 /* mulhhw - mulhhw. */
6149 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6150 /* mulhhwu - mulhhwu. */
6151 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6152 /* mullhw - mullhw. */
6153 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6154 /* mullhwu - mullhwu. */
6155 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6156
6157 /* mfdcr */
6158 static void gen_mfdcr(DisasContext *ctx)
6159 {
6160 #if defined(CONFIG_USER_ONLY)
6161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6162 #else
6163 TCGv dcrn;
6164 if (unlikely(ctx->pr)) {
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6166 return;
6167 }
6168 /* NIP cannot be restored if the memory exception comes from an helper */
6169 gen_update_nip(ctx, ctx->nip - 4);
6170 dcrn = tcg_const_tl(SPR(ctx->opcode));
6171 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6172 tcg_temp_free(dcrn);
6173 #endif
6174 }
6175
6176 /* mtdcr */
6177 static void gen_mtdcr(DisasContext *ctx)
6178 {
6179 #if defined(CONFIG_USER_ONLY)
6180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6181 #else
6182 TCGv dcrn;
6183 if (unlikely(ctx->pr)) {
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6185 return;
6186 }
6187 /* NIP cannot be restored if the memory exception comes from an helper */
6188 gen_update_nip(ctx, ctx->nip - 4);
6189 dcrn = tcg_const_tl(SPR(ctx->opcode));
6190 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6191 tcg_temp_free(dcrn);
6192 #endif
6193 }
6194
6195 /* mfdcrx */
6196 /* XXX: not implemented on 440 ? */
6197 static void gen_mfdcrx(DisasContext *ctx)
6198 {
6199 #if defined(CONFIG_USER_ONLY)
6200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6201 #else
6202 if (unlikely(ctx->pr)) {
6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6204 return;
6205 }
6206 /* NIP cannot be restored if the memory exception comes from an helper */
6207 gen_update_nip(ctx, ctx->nip - 4);
6208 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6209 cpu_gpr[rA(ctx->opcode)]);
6210 /* Note: Rc update flag set leads to undefined state of Rc0 */
6211 #endif
6212 }
6213
6214 /* mtdcrx */
6215 /* XXX: not implemented on 440 ? */
6216 static void gen_mtdcrx(DisasContext *ctx)
6217 {
6218 #if defined(CONFIG_USER_ONLY)
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6220 #else
6221 if (unlikely(ctx->pr)) {
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6223 return;
6224 }
6225 /* NIP cannot be restored if the memory exception comes from an helper */
6226 gen_update_nip(ctx, ctx->nip - 4);
6227 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6228 cpu_gpr[rS(ctx->opcode)]);
6229 /* Note: Rc update flag set leads to undefined state of Rc0 */
6230 #endif
6231 }
6232
6233 /* mfdcrux (PPC 460) : user-mode access to DCR */
6234 static void gen_mfdcrux(DisasContext *ctx)
6235 {
6236 /* NIP cannot be restored if the memory exception comes from an helper */
6237 gen_update_nip(ctx, ctx->nip - 4);
6238 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6239 cpu_gpr[rA(ctx->opcode)]);
6240 /* Note: Rc update flag set leads to undefined state of Rc0 */
6241 }
6242
6243 /* mtdcrux (PPC 460) : user-mode access to DCR */
6244 static void gen_mtdcrux(DisasContext *ctx)
6245 {
6246 /* NIP cannot be restored if the memory exception comes from an helper */
6247 gen_update_nip(ctx, ctx->nip - 4);
6248 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6249 cpu_gpr[rS(ctx->opcode)]);
6250 /* Note: Rc update flag set leads to undefined state of Rc0 */
6251 }
6252
6253 /* dccci */
6254 static void gen_dccci(DisasContext *ctx)
6255 {
6256 #if defined(CONFIG_USER_ONLY)
6257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6258 #else
6259 if (unlikely(ctx->pr)) {
6260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6261 return;
6262 }
6263 /* interpreted as no-op */
6264 #endif
6265 }
6266
6267 /* dcread */
6268 static void gen_dcread(DisasContext *ctx)
6269 {
6270 #if defined(CONFIG_USER_ONLY)
6271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6272 #else
6273 TCGv EA, val;
6274 if (unlikely(ctx->pr)) {
6275 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6276 return;
6277 }
6278 gen_set_access_type(ctx, ACCESS_CACHE);
6279 EA = tcg_temp_new();
6280 gen_addr_reg_index(ctx, EA);
6281 val = tcg_temp_new();
6282 gen_qemu_ld32u(ctx, val, EA);
6283 tcg_temp_free(val);
6284 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6285 tcg_temp_free(EA);
6286 #endif
6287 }
6288
6289 /* icbt */
6290 static void gen_icbt_40x(DisasContext *ctx)
6291 {
6292 /* interpreted as no-op */
6293 /* XXX: specification say this is treated as a load by the MMU
6294 * but does not generate any exception
6295 */
6296 }
6297
6298 /* iccci */
6299 static void gen_iccci(DisasContext *ctx)
6300 {
6301 #if defined(CONFIG_USER_ONLY)
6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6303 #else
6304 if (unlikely(ctx->pr)) {
6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6306 return;
6307 }
6308 /* interpreted as no-op */
6309 #endif
6310 }
6311
6312 /* icread */
6313 static void gen_icread(DisasContext *ctx)
6314 {
6315 #if defined(CONFIG_USER_ONLY)
6316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6317 #else
6318 if (unlikely(ctx->pr)) {
6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6320 return;
6321 }
6322 /* interpreted as no-op */
6323 #endif
6324 }
6325
6326 /* rfci (supervisor only) */
6327 static void gen_rfci_40x(DisasContext *ctx)
6328 {
6329 #if defined(CONFIG_USER_ONLY)
6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6331 #else
6332 if (unlikely(ctx->pr)) {
6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6334 return;
6335 }
6336 /* Restore CPU state */
6337 gen_helper_40x_rfci(cpu_env);
6338 gen_sync_exception(ctx);
6339 #endif
6340 }
6341
6342 static void gen_rfci(DisasContext *ctx)
6343 {
6344 #if defined(CONFIG_USER_ONLY)
6345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6346 #else
6347 if (unlikely(ctx->pr)) {
6348 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6349 return;
6350 }
6351 /* Restore CPU state */
6352 gen_helper_rfci(cpu_env);
6353 gen_sync_exception(ctx);
6354 #endif
6355 }
6356
6357 /* BookE specific */
6358
6359 /* XXX: not implemented on 440 ? */
6360 static void gen_rfdi(DisasContext *ctx)
6361 {
6362 #if defined(CONFIG_USER_ONLY)
6363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6364 #else
6365 if (unlikely(ctx->pr)) {
6366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6367 return;
6368 }
6369 /* Restore CPU state */
6370 gen_helper_rfdi(cpu_env);
6371 gen_sync_exception(ctx);
6372 #endif
6373 }
6374
6375 /* XXX: not implemented on 440 ? */
6376 static void gen_rfmci(DisasContext *ctx)
6377 {
6378 #if defined(CONFIG_USER_ONLY)
6379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6380 #else
6381 if (unlikely(ctx->pr)) {
6382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6383 return;
6384 }
6385 /* Restore CPU state */
6386 gen_helper_rfmci(cpu_env);
6387 gen_sync_exception(ctx);
6388 #endif
6389 }
6390
6391 /* TLB management - PowerPC 405 implementation */
6392
6393 /* tlbre */
6394 static void gen_tlbre_40x(DisasContext *ctx)
6395 {
6396 #if defined(CONFIG_USER_ONLY)
6397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6398 #else
6399 if (unlikely(ctx->pr)) {
6400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6401 return;
6402 }
6403 switch (rB(ctx->opcode)) {
6404 case 0:
6405 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6406 cpu_gpr[rA(ctx->opcode)]);
6407 break;
6408 case 1:
6409 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6410 cpu_gpr[rA(ctx->opcode)]);
6411 break;
6412 default:
6413 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6414 break;
6415 }
6416 #endif
6417 }
6418
6419 /* tlbsx - tlbsx. */
6420 static void gen_tlbsx_40x(DisasContext *ctx)
6421 {
6422 #if defined(CONFIG_USER_ONLY)
6423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6424 #else
6425 TCGv t0;
6426 if (unlikely(ctx->pr)) {
6427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6428 return;
6429 }
6430 t0 = tcg_temp_new();
6431 gen_addr_reg_index(ctx, t0);
6432 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6433 tcg_temp_free(t0);
6434 if (Rc(ctx->opcode)) {
6435 TCGLabel *l1 = gen_new_label();
6436 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6437 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6438 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6439 gen_set_label(l1);
6440 }
6441 #endif
6442 }
6443
6444 /* tlbwe */
6445 static void gen_tlbwe_40x(DisasContext *ctx)
6446 {
6447 #if defined(CONFIG_USER_ONLY)
6448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6449 #else
6450 if (unlikely(ctx->pr)) {
6451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6452 return;
6453 }
6454 switch (rB(ctx->opcode)) {
6455 case 0:
6456 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6457 cpu_gpr[rS(ctx->opcode)]);
6458 break;
6459 case 1:
6460 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6461 cpu_gpr[rS(ctx->opcode)]);
6462 break;
6463 default:
6464 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6465 break;
6466 }
6467 #endif
6468 }
6469
6470 /* TLB management - PowerPC 440 implementation */
6471
6472 /* tlbre */
6473 static void gen_tlbre_440(DisasContext *ctx)
6474 {
6475 #if defined(CONFIG_USER_ONLY)
6476 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6477 #else
6478 if (unlikely(ctx->pr)) {
6479 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6480 return;
6481 }
6482 switch (rB(ctx->opcode)) {
6483 case 0:
6484 case 1:
6485 case 2:
6486 {
6487 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6488 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6489 t0, cpu_gpr[rA(ctx->opcode)]);
6490 tcg_temp_free_i32(t0);
6491 }
6492 break;
6493 default:
6494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6495 break;
6496 }
6497 #endif
6498 }
6499
6500 /* tlbsx - tlbsx. */
6501 static void gen_tlbsx_440(DisasContext *ctx)
6502 {
6503 #if defined(CONFIG_USER_ONLY)
6504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6505 #else
6506 TCGv t0;
6507 if (unlikely(ctx->pr)) {
6508 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6509 return;
6510 }
6511 t0 = tcg_temp_new();
6512 gen_addr_reg_index(ctx, t0);
6513 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6514 tcg_temp_free(t0);
6515 if (Rc(ctx->opcode)) {
6516 TCGLabel *l1 = gen_new_label();
6517 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6518 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6519 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6520 gen_set_label(l1);
6521 }
6522 #endif
6523 }
6524
6525 /* tlbwe */
6526 static void gen_tlbwe_440(DisasContext *ctx)
6527 {
6528 #if defined(CONFIG_USER_ONLY)
6529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6530 #else
6531 if (unlikely(ctx->pr)) {
6532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6533 return;
6534 }
6535 switch (rB(ctx->opcode)) {
6536 case 0:
6537 case 1:
6538 case 2:
6539 {
6540 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6541 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6542 cpu_gpr[rS(ctx->opcode)]);
6543 tcg_temp_free_i32(t0);
6544 }
6545 break;
6546 default:
6547 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6548 break;
6549 }
6550 #endif
6551 }
6552
6553 /* TLB management - PowerPC BookE 2.06 implementation */
6554
6555 /* tlbre */
6556 static void gen_tlbre_booke206(DisasContext *ctx)
6557 {
6558 #if defined(CONFIG_USER_ONLY)
6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560 #else
6561 if (unlikely(ctx->pr)) {
6562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6563 return;
6564 }
6565
6566 gen_helper_booke206_tlbre(cpu_env);
6567 #endif
6568 }
6569
6570 /* tlbsx - tlbsx. */
6571 static void gen_tlbsx_booke206(DisasContext *ctx)
6572 {
6573 #if defined(CONFIG_USER_ONLY)
6574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6575 #else
6576 TCGv t0;
6577 if (unlikely(ctx->pr)) {
6578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6579 return;
6580 }
6581
6582 if (rA(ctx->opcode)) {
6583 t0 = tcg_temp_new();
6584 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6585 } else {
6586 t0 = tcg_const_tl(0);
6587 }
6588
6589 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6590 gen_helper_booke206_tlbsx(cpu_env, t0);
6591 tcg_temp_free(t0);
6592 #endif
6593 }
6594
6595 /* tlbwe */
6596 static void gen_tlbwe_booke206(DisasContext *ctx)
6597 {
6598 #if defined(CONFIG_USER_ONLY)
6599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6600 #else
6601 if (unlikely(ctx->pr)) {
6602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6603 return;
6604 }
6605 gen_update_nip(ctx, ctx->nip - 4);
6606 gen_helper_booke206_tlbwe(cpu_env);
6607 #endif
6608 }
6609
6610 static void gen_tlbivax_booke206(DisasContext *ctx)
6611 {
6612 #if defined(CONFIG_USER_ONLY)
6613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6614 #else
6615 TCGv t0;
6616 if (unlikely(ctx->pr)) {
6617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6618 return;
6619 }
6620
6621 t0 = tcg_temp_new();
6622 gen_addr_reg_index(ctx, t0);
6623
6624 gen_helper_booke206_tlbivax(cpu_env, t0);
6625 tcg_temp_free(t0);
6626 #endif
6627 }
6628
6629 static void gen_tlbilx_booke206(DisasContext *ctx)
6630 {
6631 #if defined(CONFIG_USER_ONLY)
6632 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6633 #else
6634 TCGv t0;
6635 if (unlikely(ctx->pr)) {
6636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6637 return;
6638 }
6639
6640 t0 = tcg_temp_new();
6641 gen_addr_reg_index(ctx, t0);
6642
6643 switch((ctx->opcode >> 21) & 0x3) {
6644 case 0:
6645 gen_helper_booke206_tlbilx0(cpu_env, t0);
6646 break;
6647 case 1:
6648 gen_helper_booke206_tlbilx1(cpu_env, t0);
6649 break;
6650 case 3:
6651 gen_helper_booke206_tlbilx3(cpu_env, t0);
6652 break;
6653 default:
6654 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6655 break;
6656 }
6657
6658 tcg_temp_free(t0);
6659 #endif
6660 }
6661
6662
6663 /* wrtee */
6664 static void gen_wrtee(DisasContext *ctx)
6665 {
6666 #if defined(CONFIG_USER_ONLY)
6667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6668 #else
6669 TCGv t0;
6670 if (unlikely(ctx->pr)) {
6671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6672 return;
6673 }
6674 t0 = tcg_temp_new();
6675 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6676 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6677 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6678 tcg_temp_free(t0);
6679 /* Stop translation to have a chance to raise an exception
6680 * if we just set msr_ee to 1
6681 */
6682 gen_stop_exception(ctx);
6683 #endif
6684 }
6685
6686 /* wrteei */
6687 static void gen_wrteei(DisasContext *ctx)
6688 {
6689 #if defined(CONFIG_USER_ONLY)
6690 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6691 #else
6692 if (unlikely(ctx->pr)) {
6693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6694 return;
6695 }
6696 if (ctx->opcode & 0x00008000) {
6697 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6698 /* Stop translation to have a chance to raise an exception */
6699 gen_stop_exception(ctx);
6700 } else {
6701 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6702 }
6703 #endif
6704 }
6705
6706 /* PowerPC 440 specific instructions */
6707
6708 /* dlmzb */
6709 static void gen_dlmzb(DisasContext *ctx)
6710 {
6711 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6712 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6713 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6714 tcg_temp_free_i32(t0);
6715 }
6716
6717 /* mbar replaces eieio on 440 */
6718 static void gen_mbar(DisasContext *ctx)
6719 {
6720 /* interpreted as no-op */
6721 }
6722
6723 /* msync replaces sync on 440 */
6724 static void gen_msync_4xx(DisasContext *ctx)
6725 {
6726 /* interpreted as no-op */
6727 }
6728
6729 /* icbt */
6730 static void gen_icbt_440(DisasContext *ctx)
6731 {
6732 /* interpreted as no-op */
6733 /* XXX: specification say this is treated as a load by the MMU
6734 * but does not generate any exception
6735 */
6736 }
6737
6738 /* Embedded.Processor Control */
6739
6740 static void gen_msgclr(DisasContext *ctx)
6741 {
6742 #if defined(CONFIG_USER_ONLY)
6743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6744 #else
6745 if (unlikely(ctx->pr)) {
6746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6747 return;
6748 }
6749
6750 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6751 #endif
6752 }
6753
6754 static void gen_msgsnd(DisasContext *ctx)
6755 {
6756 #if defined(CONFIG_USER_ONLY)
6757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6758 #else
6759 if (unlikely(ctx->pr)) {
6760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6761 return;
6762 }
6763
6764 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6765 #endif
6766 }
6767
6768 /*** Altivec vector extension ***/
6769 /* Altivec registers moves */
6770
6771 static inline TCGv_ptr gen_avr_ptr(int reg)
6772 {
6773 TCGv_ptr r = tcg_temp_new_ptr();
6774 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6775 return r;
6776 }
6777
6778 #define GEN_VR_LDX(name, opc2, opc3) \
6779 static void glue(gen_, name)(DisasContext *ctx) \
6780 { \
6781 TCGv EA; \
6782 if (unlikely(!ctx->altivec_enabled)) { \
6783 gen_exception(ctx, POWERPC_EXCP_VPU); \
6784 return; \
6785 } \
6786 gen_set_access_type(ctx, ACCESS_INT); \
6787 EA = tcg_temp_new(); \
6788 gen_addr_reg_index(ctx, EA); \
6789 tcg_gen_andi_tl(EA, EA, ~0xf); \
6790 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6791 64-bit byteswap already. */ \
6792 if (ctx->le_mode) { \
6793 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6794 tcg_gen_addi_tl(EA, EA, 8); \
6795 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6796 } else { \
6797 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6798 tcg_gen_addi_tl(EA, EA, 8); \
6799 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6800 } \
6801 tcg_temp_free(EA); \
6802 }
6803
6804 #define GEN_VR_STX(name, opc2, opc3) \
6805 static void gen_st##name(DisasContext *ctx) \
6806 { \
6807 TCGv EA; \
6808 if (unlikely(!ctx->altivec_enabled)) { \
6809 gen_exception(ctx, POWERPC_EXCP_VPU); \
6810 return; \
6811 } \
6812 gen_set_access_type(ctx, ACCESS_INT); \
6813 EA = tcg_temp_new(); \
6814 gen_addr_reg_index(ctx, EA); \
6815 tcg_gen_andi_tl(EA, EA, ~0xf); \
6816 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6817 64-bit byteswap already. */ \
6818 if (ctx->le_mode) { \
6819 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6820 tcg_gen_addi_tl(EA, EA, 8); \
6821 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6822 } else { \
6823 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6824 tcg_gen_addi_tl(EA, EA, 8); \
6825 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6826 } \
6827 tcg_temp_free(EA); \
6828 }
6829
6830 #define GEN_VR_LVE(name, opc2, opc3, size) \
6831 static void gen_lve##name(DisasContext *ctx) \
6832 { \
6833 TCGv EA; \
6834 TCGv_ptr rs; \
6835 if (unlikely(!ctx->altivec_enabled)) { \
6836 gen_exception(ctx, POWERPC_EXCP_VPU); \
6837 return; \
6838 } \
6839 gen_set_access_type(ctx, ACCESS_INT); \
6840 EA = tcg_temp_new(); \
6841 gen_addr_reg_index(ctx, EA); \
6842 if (size > 1) { \
6843 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6844 } \
6845 rs = gen_avr_ptr(rS(ctx->opcode)); \
6846 gen_helper_lve##name(cpu_env, rs, EA); \
6847 tcg_temp_free(EA); \
6848 tcg_temp_free_ptr(rs); \
6849 }
6850
6851 #define GEN_VR_STVE(name, opc2, opc3, size) \
6852 static void gen_stve##name(DisasContext *ctx) \
6853 { \
6854 TCGv EA; \
6855 TCGv_ptr rs; \
6856 if (unlikely(!ctx->altivec_enabled)) { \
6857 gen_exception(ctx, POWERPC_EXCP_VPU); \
6858 return; \
6859 } \
6860 gen_set_access_type(ctx, ACCESS_INT); \
6861 EA = tcg_temp_new(); \
6862 gen_addr_reg_index(ctx, EA); \
6863 if (size > 1) { \
6864 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6865 } \
6866 rs = gen_avr_ptr(rS(ctx->opcode)); \
6867 gen_helper_stve##name(cpu_env, rs, EA); \
6868 tcg_temp_free(EA); \
6869 tcg_temp_free_ptr(rs); \
6870 }
6871
6872 GEN_VR_LDX(lvx, 0x07, 0x03);
6873 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6874 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6875
6876 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6877 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6878 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6879
6880 GEN_VR_STX(svx, 0x07, 0x07);
6881 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6882 GEN_VR_STX(svxl, 0x07, 0x0F);
6883
6884 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6885 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6886 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6887
6888 static void gen_lvsl(DisasContext *ctx)
6889 {
6890 TCGv_ptr rd;
6891 TCGv EA;
6892 if (unlikely(!ctx->altivec_enabled)) {
6893 gen_exception(ctx, POWERPC_EXCP_VPU);
6894 return;
6895 }
6896 EA = tcg_temp_new();
6897 gen_addr_reg_index(ctx, EA);
6898 rd = gen_avr_ptr(rD(ctx->opcode));
6899 gen_helper_lvsl(rd, EA);
6900 tcg_temp_free(EA);
6901 tcg_temp_free_ptr(rd);
6902 }
6903
6904 static void gen_lvsr(DisasContext *ctx)
6905 {
6906 TCGv_ptr rd;
6907 TCGv EA;
6908 if (unlikely(!ctx->altivec_enabled)) {
6909 gen_exception(ctx, POWERPC_EXCP_VPU);
6910 return;
6911 }
6912 EA = tcg_temp_new();
6913 gen_addr_reg_index(ctx, EA);
6914 rd = gen_avr_ptr(rD(ctx->opcode));
6915 gen_helper_lvsr(rd, EA);
6916 tcg_temp_free(EA);
6917 tcg_temp_free_ptr(rd);
6918 }
6919
6920 static void gen_mfvscr(DisasContext *ctx)
6921 {
6922 TCGv_i32 t;
6923 if (unlikely(!ctx->altivec_enabled)) {
6924 gen_exception(ctx, POWERPC_EXCP_VPU);
6925 return;
6926 }
6927 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6928 t = tcg_temp_new_i32();
6929 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6930 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6931 tcg_temp_free_i32(t);
6932 }
6933
6934 static void gen_mtvscr(DisasContext *ctx)
6935 {
6936 TCGv_ptr p;
6937 if (unlikely(!ctx->altivec_enabled)) {
6938 gen_exception(ctx, POWERPC_EXCP_VPU);
6939 return;
6940 }
6941 p = gen_avr_ptr(rB(ctx->opcode));
6942 gen_helper_mtvscr(cpu_env, p);
6943 tcg_temp_free_ptr(p);
6944 }
6945
6946 /* Logical operations */
6947 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6948 static void glue(gen_, name)(DisasContext *ctx) \
6949 { \
6950 if (unlikely(!ctx->altivec_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_VPU); \
6952 return; \
6953 } \
6954 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6955 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6956 }
6957
6958 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6959 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6960 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6961 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6962 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6963 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6964 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6965 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6966
6967 #define GEN_VXFORM(name, opc2, opc3) \
6968 static void glue(gen_, name)(DisasContext *ctx) \
6969 { \
6970 TCGv_ptr ra, rb, rd; \
6971 if (unlikely(!ctx->altivec_enabled)) { \
6972 gen_exception(ctx, POWERPC_EXCP_VPU); \
6973 return; \
6974 } \
6975 ra = gen_avr_ptr(rA(ctx->opcode)); \
6976 rb = gen_avr_ptr(rB(ctx->opcode)); \
6977 rd = gen_avr_ptr(rD(ctx->opcode)); \
6978 gen_helper_##name (rd, ra, rb); \
6979 tcg_temp_free_ptr(ra); \
6980 tcg_temp_free_ptr(rb); \
6981 tcg_temp_free_ptr(rd); \
6982 }
6983
6984 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6985 static void glue(gen_, name)(DisasContext *ctx) \
6986 { \
6987 TCGv_ptr ra, rb, rd; \
6988 if (unlikely(!ctx->altivec_enabled)) { \
6989 gen_exception(ctx, POWERPC_EXCP_VPU); \
6990 return; \
6991 } \
6992 ra = gen_avr_ptr(rA(ctx->opcode)); \
6993 rb = gen_avr_ptr(rB(ctx->opcode)); \
6994 rd = gen_avr_ptr(rD(ctx->opcode)); \
6995 gen_helper_##name(cpu_env, rd, ra, rb); \
6996 tcg_temp_free_ptr(ra); \
6997 tcg_temp_free_ptr(rb); \
6998 tcg_temp_free_ptr(rd); \
6999 }
7000
7001 #define GEN_VXFORM3(name, opc2, opc3) \
7002 static void glue(gen_, name)(DisasContext *ctx) \
7003 { \
7004 TCGv_ptr ra, rb, rc, rd; \
7005 if (unlikely(!ctx->altivec_enabled)) { \
7006 gen_exception(ctx, POWERPC_EXCP_VPU); \
7007 return; \
7008 } \
7009 ra = gen_avr_ptr(rA(ctx->opcode)); \
7010 rb = gen_avr_ptr(rB(ctx->opcode)); \
7011 rc = gen_avr_ptr(rC(ctx->opcode)); \
7012 rd = gen_avr_ptr(rD(ctx->opcode)); \
7013 gen_helper_##name(rd, ra, rb, rc); \
7014 tcg_temp_free_ptr(ra); \
7015 tcg_temp_free_ptr(rb); \
7016 tcg_temp_free_ptr(rc); \
7017 tcg_temp_free_ptr(rd); \
7018 }
7019
7020 /*
7021 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7022 * an opcode bit. In general, these pairs come from different
7023 * versions of the ISA, so we must also support a pair of flags for
7024 * each instruction.
7025 */
7026 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7027 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7028 { \
7029 if ((Rc(ctx->opcode) == 0) && \
7030 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7031 gen_##name0(ctx); \
7032 } else if ((Rc(ctx->opcode) == 1) && \
7033 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7034 gen_##name1(ctx); \
7035 } else { \
7036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7037 } \
7038 }
7039
7040 GEN_VXFORM(vaddubm, 0, 0);
7041 GEN_VXFORM(vadduhm, 0, 1);
7042 GEN_VXFORM(vadduwm, 0, 2);
7043 GEN_VXFORM(vaddudm, 0, 3);
7044 GEN_VXFORM(vsububm, 0, 16);
7045 GEN_VXFORM(vsubuhm, 0, 17);
7046 GEN_VXFORM(vsubuwm, 0, 18);
7047 GEN_VXFORM(vsubudm, 0, 19);
7048 GEN_VXFORM(vmaxub, 1, 0);
7049 GEN_VXFORM(vmaxuh, 1, 1);
7050 GEN_VXFORM(vmaxuw, 1, 2);
7051 GEN_VXFORM(vmaxud, 1, 3);
7052 GEN_VXFORM(vmaxsb, 1, 4);
7053 GEN_VXFORM(vmaxsh, 1, 5);
7054 GEN_VXFORM(vmaxsw, 1, 6);
7055 GEN_VXFORM(vmaxsd, 1, 7);
7056 GEN_VXFORM(vminub, 1, 8);
7057 GEN_VXFORM(vminuh, 1, 9);
7058 GEN_VXFORM(vminuw, 1, 10);
7059 GEN_VXFORM(vminud, 1, 11);
7060 GEN_VXFORM(vminsb, 1, 12);
7061 GEN_VXFORM(vminsh, 1, 13);
7062 GEN_VXFORM(vminsw, 1, 14);
7063 GEN_VXFORM(vminsd, 1, 15);
7064 GEN_VXFORM(vavgub, 1, 16);
7065 GEN_VXFORM(vavguh, 1, 17);
7066 GEN_VXFORM(vavguw, 1, 18);
7067 GEN_VXFORM(vavgsb, 1, 20);
7068 GEN_VXFORM(vavgsh, 1, 21);
7069 GEN_VXFORM(vavgsw, 1, 22);
7070 GEN_VXFORM(vmrghb, 6, 0);
7071 GEN_VXFORM(vmrghh, 6, 1);
7072 GEN_VXFORM(vmrghw, 6, 2);
7073 GEN_VXFORM(vmrglb, 6, 4);
7074 GEN_VXFORM(vmrglh, 6, 5);
7075 GEN_VXFORM(vmrglw, 6, 6);
7076
7077 static void gen_vmrgew(DisasContext *ctx)
7078 {
7079 TCGv_i64 tmp;
7080 int VT, VA, VB;
7081 if (unlikely(!ctx->altivec_enabled)) {
7082 gen_exception(ctx, POWERPC_EXCP_VPU);
7083 return;
7084 }
7085 VT = rD(ctx->opcode);
7086 VA = rA(ctx->opcode);
7087 VB = rB(ctx->opcode);
7088 tmp = tcg_temp_new_i64();
7089 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7090 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7091 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7092 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7093 tcg_temp_free_i64(tmp);
7094 }
7095
7096 static void gen_vmrgow(DisasContext *ctx)
7097 {
7098 int VT, VA, VB;
7099 if (unlikely(!ctx->altivec_enabled)) {
7100 gen_exception(ctx, POWERPC_EXCP_VPU);
7101 return;
7102 }
7103 VT = rD(ctx->opcode);
7104 VA = rA(ctx->opcode);
7105 VB = rB(ctx->opcode);
7106
7107 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7108 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7109 }
7110
7111 GEN_VXFORM(vmuloub, 4, 0);
7112 GEN_VXFORM(vmulouh, 4, 1);
7113 GEN_VXFORM(vmulouw, 4, 2);
7114 GEN_VXFORM(vmuluwm, 4, 2);
7115 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7116 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7117 GEN_VXFORM(vmulosb, 4, 4);
7118 GEN_VXFORM(vmulosh, 4, 5);
7119 GEN_VXFORM(vmulosw, 4, 6);
7120 GEN_VXFORM(vmuleub, 4, 8);
7121 GEN_VXFORM(vmuleuh, 4, 9);
7122 GEN_VXFORM(vmuleuw, 4, 10);
7123 GEN_VXFORM(vmulesb, 4, 12);
7124 GEN_VXFORM(vmulesh, 4, 13);
7125 GEN_VXFORM(vmulesw, 4, 14);
7126 GEN_VXFORM(vslb, 2, 4);
7127 GEN_VXFORM(vslh, 2, 5);
7128 GEN_VXFORM(vslw, 2, 6);
7129 GEN_VXFORM(vsld, 2, 23);
7130 GEN_VXFORM(vsrb, 2, 8);
7131 GEN_VXFORM(vsrh, 2, 9);
7132 GEN_VXFORM(vsrw, 2, 10);
7133 GEN_VXFORM(vsrd, 2, 27);
7134 GEN_VXFORM(vsrab, 2, 12);
7135 GEN_VXFORM(vsrah, 2, 13);
7136 GEN_VXFORM(vsraw, 2, 14);
7137 GEN_VXFORM(vsrad, 2, 15);
7138 GEN_VXFORM(vslo, 6, 16);
7139 GEN_VXFORM(vsro, 6, 17);
7140 GEN_VXFORM(vaddcuw, 0, 6);
7141 GEN_VXFORM(vsubcuw, 0, 22);
7142 GEN_VXFORM_ENV(vaddubs, 0, 8);
7143 GEN_VXFORM_ENV(vadduhs, 0, 9);
7144 GEN_VXFORM_ENV(vadduws, 0, 10);
7145 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7146 GEN_VXFORM_ENV(vaddshs, 0, 13);
7147 GEN_VXFORM_ENV(vaddsws, 0, 14);
7148 GEN_VXFORM_ENV(vsububs, 0, 24);
7149 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7150 GEN_VXFORM_ENV(vsubuws, 0, 26);
7151 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7152 GEN_VXFORM_ENV(vsubshs, 0, 29);
7153 GEN_VXFORM_ENV(vsubsws, 0, 30);
7154 GEN_VXFORM(vadduqm, 0, 4);
7155 GEN_VXFORM(vaddcuq, 0, 5);
7156 GEN_VXFORM3(vaddeuqm, 30, 0);
7157 GEN_VXFORM3(vaddecuq, 30, 0);
7158 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7159 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7160 GEN_VXFORM(vsubuqm, 0, 20);
7161 GEN_VXFORM(vsubcuq, 0, 21);
7162 GEN_VXFORM3(vsubeuqm, 31, 0);
7163 GEN_VXFORM3(vsubecuq, 31, 0);
7164 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7165 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7166 GEN_VXFORM(vrlb, 2, 0);
7167 GEN_VXFORM(vrlh, 2, 1);
7168 GEN_VXFORM(vrlw, 2, 2);
7169 GEN_VXFORM(vrld, 2, 3);
7170 GEN_VXFORM(vsl, 2, 7);
7171 GEN_VXFORM(vsr, 2, 11);
7172 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7173 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7174 GEN_VXFORM_ENV(vpkudum, 7, 17);
7175 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7176 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7177 GEN_VXFORM_ENV(vpkudus, 7, 19);
7178 GEN_VXFORM_ENV(vpkshus, 7, 4);
7179 GEN_VXFORM_ENV(vpkswus, 7, 5);
7180 GEN_VXFORM_ENV(vpksdus, 7, 21);
7181 GEN_VXFORM_ENV(vpkshss, 7, 6);
7182 GEN_VXFORM_ENV(vpkswss, 7, 7);
7183 GEN_VXFORM_ENV(vpksdss, 7, 23);
7184 GEN_VXFORM(vpkpx, 7, 12);
7185 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7186 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7187 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7188 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7189 GEN_VXFORM_ENV(vsumsws, 4, 30);
7190 GEN_VXFORM_ENV(vaddfp, 5, 0);
7191 GEN_VXFORM_ENV(vsubfp, 5, 1);
7192 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7193 GEN_VXFORM_ENV(vminfp, 5, 17);
7194
7195 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7196 static void glue(gen_, name)(DisasContext *ctx) \
7197 { \
7198 TCGv_ptr ra, rb, rd; \
7199 if (unlikely(!ctx->altivec_enabled)) { \
7200 gen_exception(ctx, POWERPC_EXCP_VPU); \
7201 return; \
7202 } \
7203 ra = gen_avr_ptr(rA(ctx->opcode)); \
7204 rb = gen_avr_ptr(rB(ctx->opcode)); \
7205 rd = gen_avr_ptr(rD(ctx->opcode)); \
7206 gen_helper_##opname(cpu_env, rd, ra, rb); \
7207 tcg_temp_free_ptr(ra); \
7208 tcg_temp_free_ptr(rb); \
7209 tcg_temp_free_ptr(rd); \
7210 }
7211
7212 #define GEN_VXRFORM(name, opc2, opc3) \
7213 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7214 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7215
7216 /*
7217 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7218 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7219 * come from different versions of the ISA, so we must also support a
7220 * pair of flags for each instruction.
7221 */
7222 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7223 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7224 { \
7225 if ((Rc(ctx->opcode) == 0) && \
7226 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7227 if (Rc21(ctx->opcode) == 0) { \
7228 gen_##name0(ctx); \
7229 } else { \
7230 gen_##name0##_(ctx); \
7231 } \
7232 } else if ((Rc(ctx->opcode) == 1) && \
7233 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7234 if (Rc21(ctx->opcode) == 0) { \
7235 gen_##name1(ctx); \
7236 } else { \
7237 gen_##name1##_(ctx); \
7238 } \
7239 } else { \
7240 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7241 } \
7242 }
7243
7244 GEN_VXRFORM(vcmpequb, 3, 0)
7245 GEN_VXRFORM(vcmpequh, 3, 1)
7246 GEN_VXRFORM(vcmpequw, 3, 2)
7247 GEN_VXRFORM(vcmpequd, 3, 3)
7248 GEN_VXRFORM(vcmpgtsb, 3, 12)
7249 GEN_VXRFORM(vcmpgtsh, 3, 13)
7250 GEN_VXRFORM(vcmpgtsw, 3, 14)
7251 GEN_VXRFORM(vcmpgtsd, 3, 15)
7252 GEN_VXRFORM(vcmpgtub, 3, 8)
7253 GEN_VXRFORM(vcmpgtuh, 3, 9)
7254 GEN_VXRFORM(vcmpgtuw, 3, 10)
7255 GEN_VXRFORM(vcmpgtud, 3, 11)
7256 GEN_VXRFORM(vcmpeqfp, 3, 3)
7257 GEN_VXRFORM(vcmpgefp, 3, 7)
7258 GEN_VXRFORM(vcmpgtfp, 3, 11)
7259 GEN_VXRFORM(vcmpbfp, 3, 15)
7260
7261 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7262 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7263 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7264 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7265 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7266 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7267
7268 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7269 static void glue(gen_, name)(DisasContext *ctx) \
7270 { \
7271 TCGv_ptr rd; \
7272 TCGv_i32 simm; \
7273 if (unlikely(!ctx->altivec_enabled)) { \
7274 gen_exception(ctx, POWERPC_EXCP_VPU); \
7275 return; \
7276 } \
7277 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7278 rd = gen_avr_ptr(rD(ctx->opcode)); \
7279 gen_helper_##name (rd, simm); \
7280 tcg_temp_free_i32(simm); \
7281 tcg_temp_free_ptr(rd); \
7282 }
7283
7284 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7285 GEN_VXFORM_SIMM(vspltish, 6, 13);
7286 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7287
7288 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7289 static void glue(gen_, name)(DisasContext *ctx) \
7290 { \
7291 TCGv_ptr rb, rd; \
7292 if (unlikely(!ctx->altivec_enabled)) { \
7293 gen_exception(ctx, POWERPC_EXCP_VPU); \
7294 return; \
7295 } \
7296 rb = gen_avr_ptr(rB(ctx->opcode)); \
7297 rd = gen_avr_ptr(rD(ctx->opcode)); \
7298 gen_helper_##name (rd, rb); \
7299 tcg_temp_free_ptr(rb); \
7300 tcg_temp_free_ptr(rd); \
7301 }
7302
7303 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7304 static void glue(gen_, name)(DisasContext *ctx) \
7305 { \
7306 TCGv_ptr rb, rd; \
7307 \
7308 if (unlikely(!ctx->altivec_enabled)) { \
7309 gen_exception(ctx, POWERPC_EXCP_VPU); \
7310 return; \
7311 } \
7312 rb = gen_avr_ptr(rB(ctx->opcode)); \
7313 rd = gen_avr_ptr(rD(ctx->opcode)); \
7314 gen_helper_##name(cpu_env, rd, rb); \
7315 tcg_temp_free_ptr(rb); \
7316 tcg_temp_free_ptr(rd); \
7317 }
7318
7319 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7320 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7321 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7322 GEN_VXFORM_NOA(vupklsb, 7, 10);
7323 GEN_VXFORM_NOA(vupklsh, 7, 11);
7324 GEN_VXFORM_NOA(vupklsw, 7, 27);
7325 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7326 GEN_VXFORM_NOA(vupklpx, 7, 15);
7327 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7328 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7329 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7330 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7331 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7332 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7333 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7334 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7335
7336 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7337 static void glue(gen_, name)(DisasContext *ctx) \
7338 { \
7339 TCGv_ptr rd; \
7340 TCGv_i32 simm; \
7341 if (unlikely(!ctx->altivec_enabled)) { \
7342 gen_exception(ctx, POWERPC_EXCP_VPU); \
7343 return; \
7344 } \
7345 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7346 rd = gen_avr_ptr(rD(ctx->opcode)); \
7347 gen_helper_##name (rd, simm); \
7348 tcg_temp_free_i32(simm); \
7349 tcg_temp_free_ptr(rd); \
7350 }
7351
7352 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7353 static void glue(gen_, name)(DisasContext *ctx) \
7354 { \
7355 TCGv_ptr rb, rd; \
7356 TCGv_i32 uimm; \
7357 if (unlikely(!ctx->altivec_enabled)) { \
7358 gen_exception(ctx, POWERPC_EXCP_VPU); \
7359 return; \
7360 } \
7361 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7362 rb = gen_avr_ptr(rB(ctx->opcode)); \
7363 rd = gen_avr_ptr(rD(ctx->opcode)); \
7364 gen_helper_##name (rd, rb, uimm); \
7365 tcg_temp_free_i32(uimm); \
7366 tcg_temp_free_ptr(rb); \
7367 tcg_temp_free_ptr(rd); \
7368 }
7369
7370 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7371 static void glue(gen_, name)(DisasContext *ctx) \
7372 { \
7373 TCGv_ptr rb, rd; \
7374 TCGv_i32 uimm; \
7375 \
7376 if (unlikely(!ctx->altivec_enabled)) { \
7377 gen_exception(ctx, POWERPC_EXCP_VPU); \
7378 return; \
7379 } \
7380 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7381 rb = gen_avr_ptr(rB(ctx->opcode)); \
7382 rd = gen_avr_ptr(rD(ctx->opcode)); \
7383 gen_helper_##name(cpu_env, rd, rb, uimm); \
7384 tcg_temp_free_i32(uimm); \
7385 tcg_temp_free_ptr(rb); \
7386 tcg_temp_free_ptr(rd); \
7387 }
7388
7389 GEN_VXFORM_UIMM(vspltb, 6, 8);
7390 GEN_VXFORM_UIMM(vsplth, 6, 9);
7391 GEN_VXFORM_UIMM(vspltw, 6, 10);
7392 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7393 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7394 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7395 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7396
7397 static void gen_vsldoi(DisasContext *ctx)
7398 {
7399 TCGv_ptr ra, rb, rd;
7400 TCGv_i32 sh;
7401 if (unlikely(!ctx->altivec_enabled)) {
7402 gen_exception(ctx, POWERPC_EXCP_VPU);
7403 return;
7404 }
7405 ra = gen_avr_ptr(rA(ctx->opcode));
7406 rb = gen_avr_ptr(rB(ctx->opcode));
7407 rd = gen_avr_ptr(rD(ctx->opcode));
7408 sh = tcg_const_i32(VSH(ctx->opcode));
7409 gen_helper_vsldoi (rd, ra, rb, sh);
7410 tcg_temp_free_ptr(ra);
7411 tcg_temp_free_ptr(rb);
7412 tcg_temp_free_ptr(rd);
7413 tcg_temp_free_i32(sh);
7414 }
7415
7416 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7417 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7418 { \
7419 TCGv_ptr ra, rb, rc, rd; \
7420 if (unlikely(!ctx->altivec_enabled)) { \
7421 gen_exception(ctx, POWERPC_EXCP_VPU); \
7422 return; \
7423 } \
7424 ra = gen_avr_ptr(rA(ctx->opcode)); \
7425 rb = gen_avr_ptr(rB(ctx->opcode)); \
7426 rc = gen_avr_ptr(rC(ctx->opcode)); \
7427 rd = gen_avr_ptr(rD(ctx->opcode)); \
7428 if (Rc(ctx->opcode)) { \
7429 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7430 } else { \
7431 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7432 } \
7433 tcg_temp_free_ptr(ra); \
7434 tcg_temp_free_ptr(rb); \
7435 tcg_temp_free_ptr(rc); \
7436 tcg_temp_free_ptr(rd); \
7437 }
7438
7439 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7440
7441 static void gen_vmladduhm(DisasContext *ctx)
7442 {
7443 TCGv_ptr ra, rb, rc, rd;
7444 if (unlikely(!ctx->altivec_enabled)) {
7445 gen_exception(ctx, POWERPC_EXCP_VPU);
7446 return;
7447 }
7448 ra = gen_avr_ptr(rA(ctx->opcode));
7449 rb = gen_avr_ptr(rB(ctx->opcode));
7450 rc = gen_avr_ptr(rC(ctx->opcode));
7451 rd = gen_avr_ptr(rD(ctx->opcode));
7452 gen_helper_vmladduhm(rd, ra, rb, rc);
7453 tcg_temp_free_ptr(ra);
7454 tcg_temp_free_ptr(rb);
7455 tcg_temp_free_ptr(rc);
7456 tcg_temp_free_ptr(rd);
7457 }
7458
7459 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7460 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7461 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7462 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7463 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7464
7465 GEN_VXFORM_NOA(vclzb, 1, 28)
7466 GEN_VXFORM_NOA(vclzh, 1, 29)
7467 GEN_VXFORM_NOA(vclzw, 1, 30)
7468 GEN_VXFORM_NOA(vclzd, 1, 31)
7469 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7470 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7471 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7472 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7473 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7474 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7475 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7476 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7477 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7478 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7479 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7480 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7481 GEN_VXFORM(vbpermq, 6, 21);
7482 GEN_VXFORM_NOA(vgbbd, 6, 20);
7483 GEN_VXFORM(vpmsumb, 4, 16)
7484 GEN_VXFORM(vpmsumh, 4, 17)
7485 GEN_VXFORM(vpmsumw, 4, 18)
7486 GEN_VXFORM(vpmsumd, 4, 19)
7487
7488 #define GEN_BCD(op) \
7489 static void gen_##op(DisasContext *ctx) \
7490 { \
7491 TCGv_ptr ra, rb, rd; \
7492 TCGv_i32 ps; \
7493 \
7494 if (unlikely(!ctx->altivec_enabled)) { \
7495 gen_exception(ctx, POWERPC_EXCP_VPU); \
7496 return; \
7497 } \
7498 \
7499 ra = gen_avr_ptr(rA(ctx->opcode)); \
7500 rb = gen_avr_ptr(rB(ctx->opcode)); \
7501 rd = gen_avr_ptr(rD(ctx->opcode)); \
7502 \
7503 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7504 \
7505 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7506 \
7507 tcg_temp_free_ptr(ra); \
7508 tcg_temp_free_ptr(rb); \
7509 tcg_temp_free_ptr(rd); \
7510 tcg_temp_free_i32(ps); \
7511 }
7512
7513 GEN_BCD(bcdadd)
7514 GEN_BCD(bcdsub)
7515
7516 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7517 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7518 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7519 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7520 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7521 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7522 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7523 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7524
7525 static void gen_vsbox(DisasContext *ctx)
7526 {
7527 TCGv_ptr ra, rd;
7528 if (unlikely(!ctx->altivec_enabled)) {
7529 gen_exception(ctx, POWERPC_EXCP_VPU);
7530 return;
7531 }
7532 ra = gen_avr_ptr(rA(ctx->opcode));
7533 rd = gen_avr_ptr(rD(ctx->opcode));
7534 gen_helper_vsbox(rd, ra);
7535 tcg_temp_free_ptr(ra);
7536 tcg_temp_free_ptr(rd);
7537 }
7538
7539 GEN_VXFORM(vcipher, 4, 20)
7540 GEN_VXFORM(vcipherlast, 4, 20)
7541 GEN_VXFORM(vncipher, 4, 21)
7542 GEN_VXFORM(vncipherlast, 4, 21)
7543
7544 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7545 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7546 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7547 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7548
7549 #define VSHASIGMA(op) \
7550 static void gen_##op(DisasContext *ctx) \
7551 { \
7552 TCGv_ptr ra, rd; \
7553 TCGv_i32 st_six; \
7554 if (unlikely(!ctx->altivec_enabled)) { \
7555 gen_exception(ctx, POWERPC_EXCP_VPU); \
7556 return; \
7557 } \
7558 ra = gen_avr_ptr(rA(ctx->opcode)); \
7559 rd = gen_avr_ptr(rD(ctx->opcode)); \
7560 st_six = tcg_const_i32(rB(ctx->opcode)); \
7561 gen_helper_##op(rd, ra, st_six); \
7562 tcg_temp_free_ptr(ra); \
7563 tcg_temp_free_ptr(rd); \
7564 tcg_temp_free_i32(st_six); \
7565 }
7566
7567 VSHASIGMA(vshasigmaw)
7568 VSHASIGMA(vshasigmad)
7569
7570 GEN_VXFORM3(vpermxor, 22, 0xFF)
7571 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7572 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7573
7574 /*** VSX extension ***/
7575
7576 static inline TCGv_i64 cpu_vsrh(int n)
7577 {
7578 if (n < 32) {
7579 return cpu_fpr[n];
7580 } else {
7581 return cpu_avrh[n-32];
7582 }
7583 }
7584
7585 static inline TCGv_i64 cpu_vsrl(int n)
7586 {
7587 if (n < 32) {
7588 return cpu_vsr[n];
7589 } else {
7590 return cpu_avrl[n-32];
7591 }
7592 }
7593
7594 #define VSX_LOAD_SCALAR(name, operation) \
7595 static void gen_##name(DisasContext *ctx) \
7596 { \
7597 TCGv EA; \
7598 if (unlikely(!ctx->vsx_enabled)) { \
7599 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7600 return; \
7601 } \
7602 gen_set_access_type(ctx, ACCESS_INT); \
7603 EA = tcg_temp_new(); \
7604 gen_addr_reg_index(ctx, EA); \
7605 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7606 /* NOTE: cpu_vsrl is undefined */ \
7607 tcg_temp_free(EA); \
7608 }
7609
7610 VSX_LOAD_SCALAR(lxsdx, ld64)
7611 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7612 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7613 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7614
7615 static void gen_lxvd2x(DisasContext *ctx)
7616 {
7617 TCGv EA;
7618 if (unlikely(!ctx->vsx_enabled)) {
7619 gen_exception(ctx, POWERPC_EXCP_VSXU);
7620 return;
7621 }
7622 gen_set_access_type(ctx, ACCESS_INT);
7623 EA = tcg_temp_new();
7624 gen_addr_reg_index(ctx, EA);
7625 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7626 tcg_gen_addi_tl(EA, EA, 8);
7627 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7628 tcg_temp_free(EA);
7629 }
7630
7631 static void gen_lxvdsx(DisasContext *ctx)
7632 {
7633 TCGv EA;
7634 if (unlikely(!ctx->vsx_enabled)) {
7635 gen_exception(ctx, POWERPC_EXCP_VSXU);
7636 return;
7637 }
7638 gen_set_access_type(ctx, ACCESS_INT);
7639 EA = tcg_temp_new();
7640 gen_addr_reg_index(ctx, EA);
7641 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7642 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7643 tcg_temp_free(EA);
7644 }
7645
7646 static void gen_lxvw4x(DisasContext *ctx)
7647 {
7648 TCGv EA;
7649 TCGv_i64 tmp;
7650 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7651 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7652 if (unlikely(!ctx->vsx_enabled)) {
7653 gen_exception(ctx, POWERPC_EXCP_VSXU);
7654 return;
7655 }
7656 gen_set_access_type(ctx, ACCESS_INT);
7657 EA = tcg_temp_new();
7658 tmp = tcg_temp_new_i64();
7659
7660 gen_addr_reg_index(ctx, EA);
7661 gen_qemu_ld32u_i64(ctx, tmp, EA);
7662 tcg_gen_addi_tl(EA, EA, 4);
7663 gen_qemu_ld32u_i64(ctx, xth, EA);
7664 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7665
7666 tcg_gen_addi_tl(EA, EA, 4);
7667 gen_qemu_ld32u_i64(ctx, tmp, EA);
7668 tcg_gen_addi_tl(EA, EA, 4);
7669 gen_qemu_ld32u_i64(ctx, xtl, EA);
7670 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7671
7672 tcg_temp_free(EA);
7673 tcg_temp_free_i64(tmp);
7674 }
7675
7676 #define VSX_STORE_SCALAR(name, operation) \
7677 static void gen_##name(DisasContext *ctx) \
7678 { \
7679 TCGv EA; \
7680 if (unlikely(!ctx->vsx_enabled)) { \
7681 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7682 return; \
7683 } \
7684 gen_set_access_type(ctx, ACCESS_INT); \
7685 EA = tcg_temp_new(); \
7686 gen_addr_reg_index(ctx, EA); \
7687 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7688 tcg_temp_free(EA); \
7689 }
7690
7691 VSX_STORE_SCALAR(stxsdx, st64)
7692 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7693 VSX_STORE_SCALAR(stxsspx, st32fs)
7694
7695 static void gen_stxvd2x(DisasContext *ctx)
7696 {
7697 TCGv EA;
7698 if (unlikely(!ctx->vsx_enabled)) {
7699 gen_exception(ctx, POWERPC_EXCP_VSXU);
7700 return;
7701 }
7702 gen_set_access_type(ctx, ACCESS_INT);
7703 EA = tcg_temp_new();
7704 gen_addr_reg_index(ctx, EA);
7705 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7706 tcg_gen_addi_tl(EA, EA, 8);
7707 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7708 tcg_temp_free(EA);
7709 }
7710
7711 static void gen_stxvw4x(DisasContext *ctx)
7712 {
7713 TCGv_i64 tmp;
7714 TCGv EA;
7715 if (unlikely(!ctx->vsx_enabled)) {
7716 gen_exception(ctx, POWERPC_EXCP_VSXU);
7717 return;
7718 }
7719 gen_set_access_type(ctx, ACCESS_INT);
7720 EA = tcg_temp_new();
7721 gen_addr_reg_index(ctx, EA);
7722 tmp = tcg_temp_new_i64();
7723
7724 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7725 gen_qemu_st32_i64(ctx, tmp, EA);
7726 tcg_gen_addi_tl(EA, EA, 4);
7727 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7728
7729 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7730 tcg_gen_addi_tl(EA, EA, 4);
7731 gen_qemu_st32_i64(ctx, tmp, EA);
7732 tcg_gen_addi_tl(EA, EA, 4);
7733 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7734
7735 tcg_temp_free(EA);
7736 tcg_temp_free_i64(tmp);
7737 }
7738
7739 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7740 static void gen_##name(DisasContext *ctx) \
7741 { \
7742 if (xS(ctx->opcode) < 32) { \
7743 if (unlikely(!ctx->fpu_enabled)) { \
7744 gen_exception(ctx, POWERPC_EXCP_FPU); \
7745 return; \
7746 } \
7747 } else { \
7748 if (unlikely(!ctx->altivec_enabled)) { \
7749 gen_exception(ctx, POWERPC_EXCP_VPU); \
7750 return; \
7751 } \
7752 } \
7753 TCGv_i64 tmp = tcg_temp_new_i64(); \
7754 tcg_gen_##tcgop1(tmp, source); \
7755 tcg_gen_##tcgop2(target, tmp); \
7756 tcg_temp_free_i64(tmp); \
7757 }
7758
7759
7760 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7761 cpu_vsrh(xS(ctx->opcode)))
7762 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7763 cpu_gpr[rA(ctx->opcode)])
7764 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7765 cpu_gpr[rA(ctx->opcode)])
7766
7767 #if defined(TARGET_PPC64)
7768 #define MV_VSRD(name, target, source) \
7769 static void gen_##name(DisasContext *ctx) \
7770 { \
7771 if (xS(ctx->opcode) < 32) { \
7772 if (unlikely(!ctx->fpu_enabled)) { \
7773 gen_exception(ctx, POWERPC_EXCP_FPU); \
7774 return; \
7775 } \
7776 } else { \
7777 if (unlikely(!ctx->altivec_enabled)) { \
7778 gen_exception(ctx, POWERPC_EXCP_VPU); \
7779 return; \
7780 } \
7781 } \
7782 tcg_gen_mov_i64(target, source); \
7783 }
7784
7785 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7786 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7787
7788 #endif
7789
7790 static void gen_xxpermdi(DisasContext *ctx)
7791 {
7792 if (unlikely(!ctx->vsx_enabled)) {
7793 gen_exception(ctx, POWERPC_EXCP_VSXU);
7794 return;
7795 }
7796
7797 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7798 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7799 TCGv_i64 xh, xl;
7800
7801 xh = tcg_temp_new_i64();
7802 xl = tcg_temp_new_i64();
7803
7804 if ((DM(ctx->opcode) & 2) == 0) {
7805 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7806 } else {
7807 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7808 }
7809 if ((DM(ctx->opcode) & 1) == 0) {
7810 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7811 } else {
7812 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7813 }
7814
7815 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7816 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7817
7818 tcg_temp_free_i64(xh);
7819 tcg_temp_free_i64(xl);
7820 } else {
7821 if ((DM(ctx->opcode) & 2) == 0) {
7822 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7823 } else {
7824 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7825 }
7826 if ((DM(ctx->opcode) & 1) == 0) {
7827 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7828 } else {
7829 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7830 }
7831 }
7832 }
7833
7834 #define OP_ABS 1
7835 #define OP_NABS 2
7836 #define OP_NEG 3
7837 #define OP_CPSGN 4
7838 #define SGN_MASK_DP 0x8000000000000000ull
7839 #define SGN_MASK_SP 0x8000000080000000ull
7840
7841 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7842 static void glue(gen_, name)(DisasContext * ctx) \
7843 { \
7844 TCGv_i64 xb, sgm; \
7845 if (unlikely(!ctx->vsx_enabled)) { \
7846 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7847 return; \
7848 } \
7849 xb = tcg_temp_new_i64(); \
7850 sgm = tcg_temp_new_i64(); \
7851 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7852 tcg_gen_movi_i64(sgm, sgn_mask); \
7853 switch (op) { \
7854 case OP_ABS: { \
7855 tcg_gen_andc_i64(xb, xb, sgm); \
7856 break; \
7857 } \
7858 case OP_NABS: { \
7859 tcg_gen_or_i64(xb, xb, sgm); \
7860 break; \
7861 } \
7862 case OP_NEG: { \
7863 tcg_gen_xor_i64(xb, xb, sgm); \
7864 break; \
7865 } \
7866 case OP_CPSGN: { \
7867 TCGv_i64 xa = tcg_temp_new_i64(); \
7868 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7869 tcg_gen_and_i64(xa, xa, sgm); \
7870 tcg_gen_andc_i64(xb, xb, sgm); \
7871 tcg_gen_or_i64(xb, xb, xa); \
7872 tcg_temp_free_i64(xa); \
7873 break; \
7874 } \
7875 } \
7876 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7877 tcg_temp_free_i64(xb); \
7878 tcg_temp_free_i64(sgm); \
7879 }
7880
7881 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7882 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7883 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7884 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7885
7886 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7887 static void glue(gen_, name)(DisasContext * ctx) \
7888 { \
7889 TCGv_i64 xbh, xbl, sgm; \
7890 if (unlikely(!ctx->vsx_enabled)) { \
7891 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7892 return; \
7893 } \
7894 xbh = tcg_temp_new_i64(); \
7895 xbl = tcg_temp_new_i64(); \
7896 sgm = tcg_temp_new_i64(); \
7897 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7898 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7899 tcg_gen_movi_i64(sgm, sgn_mask); \
7900 switch (op) { \
7901 case OP_ABS: { \
7902 tcg_gen_andc_i64(xbh, xbh, sgm); \
7903 tcg_gen_andc_i64(xbl, xbl, sgm); \
7904 break; \
7905 } \
7906 case OP_NABS: { \
7907 tcg_gen_or_i64(xbh, xbh, sgm); \
7908 tcg_gen_or_i64(xbl, xbl, sgm); \
7909 break; \
7910 } \
7911 case OP_NEG: { \
7912 tcg_gen_xor_i64(xbh, xbh, sgm); \
7913 tcg_gen_xor_i64(xbl, xbl, sgm); \
7914 break; \
7915 } \
7916 case OP_CPSGN: { \
7917 TCGv_i64 xah = tcg_temp_new_i64(); \
7918 TCGv_i64 xal = tcg_temp_new_i64(); \
7919 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7920 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7921 tcg_gen_and_i64(xah, xah, sgm); \
7922 tcg_gen_and_i64(xal, xal, sgm); \
7923 tcg_gen_andc_i64(xbh, xbh, sgm); \
7924 tcg_gen_andc_i64(xbl, xbl, sgm); \
7925 tcg_gen_or_i64(xbh, xbh, xah); \
7926 tcg_gen_or_i64(xbl, xbl, xal); \
7927 tcg_temp_free_i64(xah); \
7928 tcg_temp_free_i64(xal); \
7929 break; \
7930 } \
7931 } \
7932 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7933 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7934 tcg_temp_free_i64(xbh); \
7935 tcg_temp_free_i64(xbl); \
7936 tcg_temp_free_i64(sgm); \
7937 }
7938
7939 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7940 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7941 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7942 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7943 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7944 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7945 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7946 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7947
7948 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7949 static void gen_##name(DisasContext * ctx) \
7950 { \
7951 TCGv_i32 opc; \
7952 if (unlikely(!ctx->vsx_enabled)) { \
7953 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7954 return; \
7955 } \
7956 /* NIP cannot be restored if the memory exception comes from an helper */ \
7957 gen_update_nip(ctx, ctx->nip - 4); \
7958 opc = tcg_const_i32(ctx->opcode); \
7959 gen_helper_##name(cpu_env, opc); \
7960 tcg_temp_free_i32(opc); \
7961 }
7962
7963 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7964 static void gen_##name(DisasContext * ctx) \
7965 { \
7966 if (unlikely(!ctx->vsx_enabled)) { \
7967 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7968 return; \
7969 } \
7970 /* NIP cannot be restored if the exception comes */ \
7971 /* from a helper. */ \
7972 gen_update_nip(ctx, ctx->nip - 4); \
7973 \
7974 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7975 cpu_vsrh(xB(ctx->opcode))); \
7976 }
7977
7978 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8001 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8003 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8015
8016 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8017 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8018 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8019 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8020 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8021 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8022 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8023 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8024 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8025 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8026 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8027 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8028 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8029 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8030 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8031 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8032 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8033
8034 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8070
8071 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8088 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8106 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8107
8108 #define VSX_LOGICAL(name, tcg_op) \
8109 static void glue(gen_, name)(DisasContext * ctx) \
8110 { \
8111 if (unlikely(!ctx->vsx_enabled)) { \
8112 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8113 return; \
8114 } \
8115 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8116 cpu_vsrh(xB(ctx->opcode))); \
8117 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8118 cpu_vsrl(xB(ctx->opcode))); \
8119 }
8120
8121 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8122 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8123 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8124 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8125 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8126 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8127 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8128 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8129
8130 #define VSX_XXMRG(name, high) \
8131 static void glue(gen_, name)(DisasContext * ctx) \
8132 { \
8133 TCGv_i64 a0, a1, b0, b1; \
8134 if (unlikely(!ctx->vsx_enabled)) { \
8135 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8136 return; \
8137 } \
8138 a0 = tcg_temp_new_i64(); \
8139 a1 = tcg_temp_new_i64(); \
8140 b0 = tcg_temp_new_i64(); \
8141 b1 = tcg_temp_new_i64(); \
8142 if (high) { \
8143 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8144 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8145 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8146 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8147 } else { \
8148 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8149 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8150 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8151 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8152 } \
8153 tcg_gen_shri_i64(a0, a0, 32); \
8154 tcg_gen_shri_i64(b0, b0, 32); \
8155 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8156 b0, a0, 32, 32); \
8157 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8158 b1, a1, 32, 32); \
8159 tcg_temp_free_i64(a0); \
8160 tcg_temp_free_i64(a1); \
8161 tcg_temp_free_i64(b0); \
8162 tcg_temp_free_i64(b1); \
8163 }
8164
8165 VSX_XXMRG(xxmrghw, 1)
8166 VSX_XXMRG(xxmrglw, 0)
8167
8168 static void gen_xxsel(DisasContext * ctx)
8169 {
8170 TCGv_i64 a, b, c;
8171 if (unlikely(!ctx->vsx_enabled)) {
8172 gen_exception(ctx, POWERPC_EXCP_VSXU);
8173 return;
8174 }
8175 a = tcg_temp_new_i64();
8176 b = tcg_temp_new_i64();
8177 c = tcg_temp_new_i64();
8178
8179 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8180 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8181 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8182
8183 tcg_gen_and_i64(b, b, c);
8184 tcg_gen_andc_i64(a, a, c);
8185 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8186
8187 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8188 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8189 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8190
8191 tcg_gen_and_i64(b, b, c);
8192 tcg_gen_andc_i64(a, a, c);
8193 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8194
8195 tcg_temp_free_i64(a);
8196 tcg_temp_free_i64(b);
8197 tcg_temp_free_i64(c);
8198 }
8199
8200 static void gen_xxspltw(DisasContext *ctx)
8201 {
8202 TCGv_i64 b, b2;
8203 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8204 cpu_vsrl(xB(ctx->opcode)) :
8205 cpu_vsrh(xB(ctx->opcode));
8206
8207 if (unlikely(!ctx->vsx_enabled)) {
8208 gen_exception(ctx, POWERPC_EXCP_VSXU);
8209 return;
8210 }
8211
8212 b = tcg_temp_new_i64();
8213 b2 = tcg_temp_new_i64();
8214
8215 if (UIM(ctx->opcode) & 1) {
8216 tcg_gen_ext32u_i64(b, vsr);
8217 } else {
8218 tcg_gen_shri_i64(b, vsr, 32);
8219 }
8220
8221 tcg_gen_shli_i64(b2, b, 32);
8222 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8223 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8224
8225 tcg_temp_free_i64(b);
8226 tcg_temp_free_i64(b2);
8227 }
8228
8229 static void gen_xxsldwi(DisasContext *ctx)
8230 {
8231 TCGv_i64 xth, xtl;
8232 if (unlikely(!ctx->vsx_enabled)) {
8233 gen_exception(ctx, POWERPC_EXCP_VSXU);
8234 return;
8235 }
8236 xth = tcg_temp_new_i64();
8237 xtl = tcg_temp_new_i64();
8238
8239 switch (SHW(ctx->opcode)) {
8240 case 0: {
8241 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8242 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8243 break;
8244 }
8245 case 1: {
8246 TCGv_i64 t0 = tcg_temp_new_i64();
8247 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8248 tcg_gen_shli_i64(xth, xth, 32);
8249 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8250 tcg_gen_shri_i64(t0, t0, 32);
8251 tcg_gen_or_i64(xth, xth, t0);
8252 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8253 tcg_gen_shli_i64(xtl, xtl, 32);
8254 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8255 tcg_gen_shri_i64(t0, t0, 32);
8256 tcg_gen_or_i64(xtl, xtl, t0);
8257 tcg_temp_free_i64(t0);
8258 break;
8259 }
8260 case 2: {
8261 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8262 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8263 break;
8264 }
8265 case 3: {
8266 TCGv_i64 t0 = tcg_temp_new_i64();
8267 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8268 tcg_gen_shli_i64(xth, xth, 32);
8269 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8270 tcg_gen_shri_i64(t0, t0, 32);
8271 tcg_gen_or_i64(xth, xth, t0);
8272 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8273 tcg_gen_shli_i64(xtl, xtl, 32);
8274 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8275 tcg_gen_shri_i64(t0, t0, 32);
8276 tcg_gen_or_i64(xtl, xtl, t0);
8277 tcg_temp_free_i64(t0);
8278 break;
8279 }
8280 }
8281
8282 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8283 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8284
8285 tcg_temp_free_i64(xth);
8286 tcg_temp_free_i64(xtl);
8287 }
8288
8289 /*** Decimal Floating Point ***/
8290
8291 static inline TCGv_ptr gen_fprp_ptr(int reg)
8292 {
8293 TCGv_ptr r = tcg_temp_new_ptr();
8294 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8295 return r;
8296 }
8297
8298 #define GEN_DFP_T_A_B_Rc(name) \
8299 static void gen_##name(DisasContext *ctx) \
8300 { \
8301 TCGv_ptr rd, ra, rb; \
8302 if (unlikely(!ctx->fpu_enabled)) { \
8303 gen_exception(ctx, POWERPC_EXCP_FPU); \
8304 return; \
8305 } \
8306 gen_update_nip(ctx, ctx->nip - 4); \
8307 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8308 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8309 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8310 gen_helper_##name(cpu_env, rd, ra, rb); \
8311 if (unlikely(Rc(ctx->opcode) != 0)) { \
8312 gen_set_cr1_from_fpscr(ctx); \
8313 } \
8314 tcg_temp_free_ptr(rd); \
8315 tcg_temp_free_ptr(ra); \
8316 tcg_temp_free_ptr(rb); \
8317 }
8318
8319 #define GEN_DFP_BF_A_B(name) \
8320 static void gen_##name(DisasContext *ctx) \
8321 { \
8322 TCGv_ptr ra, rb; \
8323 if (unlikely(!ctx->fpu_enabled)) { \
8324 gen_exception(ctx, POWERPC_EXCP_FPU); \
8325 return; \
8326 } \
8327 gen_update_nip(ctx, ctx->nip - 4); \
8328 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8329 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8330 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8331 cpu_env, ra, rb); \
8332 tcg_temp_free_ptr(ra); \
8333 tcg_temp_free_ptr(rb); \
8334 }
8335
8336 #define GEN_DFP_BF_A_DCM(name) \
8337 static void gen_##name(DisasContext *ctx) \
8338 { \
8339 TCGv_ptr ra; \
8340 TCGv_i32 dcm; \
8341 if (unlikely(!ctx->fpu_enabled)) { \
8342 gen_exception(ctx, POWERPC_EXCP_FPU); \
8343 return; \
8344 } \
8345 gen_update_nip(ctx, ctx->nip - 4); \
8346 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8347 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8348 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8349 cpu_env, ra, dcm); \
8350 tcg_temp_free_ptr(ra); \
8351 tcg_temp_free_i32(dcm); \
8352 }
8353
8354 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8355 static void gen_##name(DisasContext *ctx) \
8356 { \
8357 TCGv_ptr rt, rb; \
8358 TCGv_i32 u32_1, u32_2; \
8359 if (unlikely(!ctx->fpu_enabled)) { \
8360 gen_exception(ctx, POWERPC_EXCP_FPU); \
8361 return; \
8362 } \
8363 gen_update_nip(ctx, ctx->nip - 4); \
8364 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8365 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8366 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8367 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8368 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8369 if (unlikely(Rc(ctx->opcode) != 0)) { \
8370 gen_set_cr1_from_fpscr(ctx); \
8371 } \
8372 tcg_temp_free_ptr(rt); \
8373 tcg_temp_free_ptr(rb); \
8374 tcg_temp_free_i32(u32_1); \
8375 tcg_temp_free_i32(u32_2); \
8376 }
8377
8378 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8379 static void gen_##name(DisasContext *ctx) \
8380 { \
8381 TCGv_ptr rt, ra, rb; \
8382 TCGv_i32 i32; \
8383 if (unlikely(!ctx->fpu_enabled)) { \
8384 gen_exception(ctx, POWERPC_EXCP_FPU); \
8385 return; \
8386 } \
8387 gen_update_nip(ctx, ctx->nip - 4); \
8388 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8389 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8390 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8391 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8392 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8393 if (unlikely(Rc(ctx->opcode) != 0)) { \
8394 gen_set_cr1_from_fpscr(ctx); \
8395 } \
8396 tcg_temp_free_ptr(rt); \
8397 tcg_temp_free_ptr(rb); \
8398 tcg_temp_free_ptr(ra); \
8399 tcg_temp_free_i32(i32); \
8400 }
8401
8402 #define GEN_DFP_T_B_Rc(name) \
8403 static void gen_##name(DisasContext *ctx) \
8404 { \
8405 TCGv_ptr rt, rb; \
8406 if (unlikely(!ctx->fpu_enabled)) { \
8407 gen_exception(ctx, POWERPC_EXCP_FPU); \
8408 return; \
8409 } \
8410 gen_update_nip(ctx, ctx->nip - 4); \
8411 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8412 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8413 gen_helper_##name(cpu_env, rt, rb); \
8414 if (unlikely(Rc(ctx->opcode) != 0)) { \
8415 gen_set_cr1_from_fpscr(ctx); \
8416 } \
8417 tcg_temp_free_ptr(rt); \
8418 tcg_temp_free_ptr(rb); \
8419 }
8420
8421 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8422 static void gen_##name(DisasContext *ctx) \
8423 { \
8424 TCGv_ptr rt, rs; \
8425 TCGv_i32 i32; \
8426 if (unlikely(!ctx->fpu_enabled)) { \
8427 gen_exception(ctx, POWERPC_EXCP_FPU); \
8428 return; \
8429 } \
8430 gen_update_nip(ctx, ctx->nip - 4); \
8431 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8432 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8433 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8434 gen_helper_##name(cpu_env, rt, rs, i32); \
8435 if (unlikely(Rc(ctx->opcode) != 0)) { \
8436 gen_set_cr1_from_fpscr(ctx); \
8437 } \
8438 tcg_temp_free_ptr(rt); \
8439 tcg_temp_free_ptr(rs); \
8440 tcg_temp_free_i32(i32); \
8441 }
8442
8443 GEN_DFP_T_A_B_Rc(dadd)
8444 GEN_DFP_T_A_B_Rc(daddq)
8445 GEN_DFP_T_A_B_Rc(dsub)
8446 GEN_DFP_T_A_B_Rc(dsubq)
8447 GEN_DFP_T_A_B_Rc(dmul)
8448 GEN_DFP_T_A_B_Rc(dmulq)
8449 GEN_DFP_T_A_B_Rc(ddiv)
8450 GEN_DFP_T_A_B_Rc(ddivq)
8451 GEN_DFP_BF_A_B(dcmpu)
8452 GEN_DFP_BF_A_B(dcmpuq)
8453 GEN_DFP_BF_A_B(dcmpo)
8454 GEN_DFP_BF_A_B(dcmpoq)
8455 GEN_DFP_BF_A_DCM(dtstdc)
8456 GEN_DFP_BF_A_DCM(dtstdcq)
8457 GEN_DFP_BF_A_DCM(dtstdg)
8458 GEN_DFP_BF_A_DCM(dtstdgq)
8459 GEN_DFP_BF_A_B(dtstex)
8460 GEN_DFP_BF_A_B(dtstexq)
8461 GEN_DFP_BF_A_B(dtstsf)
8462 GEN_DFP_BF_A_B(dtstsfq)
8463 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8464 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8465 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8466 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8467 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8468 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8469 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8470 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8471 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8472 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8473 GEN_DFP_T_B_Rc(dctdp)
8474 GEN_DFP_T_B_Rc(dctqpq)
8475 GEN_DFP_T_B_Rc(drsp)
8476 GEN_DFP_T_B_Rc(drdpq)
8477 GEN_DFP_T_B_Rc(dcffix)
8478 GEN_DFP_T_B_Rc(dcffixq)
8479 GEN_DFP_T_B_Rc(dctfix)
8480 GEN_DFP_T_B_Rc(dctfixq)
8481 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8482 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8483 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8484 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8485 GEN_DFP_T_B_Rc(dxex)
8486 GEN_DFP_T_B_Rc(dxexq)
8487 GEN_DFP_T_A_B_Rc(diex)
8488 GEN_DFP_T_A_B_Rc(diexq)
8489 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8490 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8491 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8492 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8493
8494 /*** SPE extension ***/
8495 /* Register moves */
8496
8497 static inline void gen_evmra(DisasContext *ctx)
8498 {
8499
8500 if (unlikely(!ctx->spe_enabled)) {
8501 gen_exception(ctx, POWERPC_EXCP_SPEU);
8502 return;
8503 }
8504
8505 TCGv_i64 tmp = tcg_temp_new_i64();
8506
8507 /* tmp := rA_lo + rA_hi << 32 */
8508 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8509
8510 /* spe_acc := tmp */
8511 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8512 tcg_temp_free_i64(tmp);
8513
8514 /* rD := rA */
8515 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8516 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8517 }
8518
8519 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8520 {
8521 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8522 }
8523
8524 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8525 {
8526 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8527 }
8528
8529 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8530 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8531 { \
8532 if (Rc(ctx->opcode)) \
8533 gen_##name1(ctx); \
8534 else \
8535 gen_##name0(ctx); \
8536 }
8537
8538 /* Handler for undefined SPE opcodes */
8539 static inline void gen_speundef(DisasContext *ctx)
8540 {
8541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8542 }
8543
8544 /* SPE logic */
8545 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8546 static inline void gen_##name(DisasContext *ctx) \
8547 { \
8548 if (unlikely(!ctx->spe_enabled)) { \
8549 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8550 return; \
8551 } \
8552 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8553 cpu_gpr[rB(ctx->opcode)]); \
8554 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8555 cpu_gprh[rB(ctx->opcode)]); \
8556 }
8557
8558 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8559 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8560 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8561 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8562 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8563 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8564 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8565 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8566
8567 /* SPE logic immediate */
8568 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8569 static inline void gen_##name(DisasContext *ctx) \
8570 { \
8571 TCGv_i32 t0; \
8572 if (unlikely(!ctx->spe_enabled)) { \
8573 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8574 return; \
8575 } \
8576 t0 = tcg_temp_new_i32(); \
8577 \
8578 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8579 tcg_opi(t0, t0, rB(ctx->opcode)); \
8580 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8581 \
8582 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8583 tcg_opi(t0, t0, rB(ctx->opcode)); \
8584 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8585 \
8586 tcg_temp_free_i32(t0); \
8587 }
8588 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8589 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8590 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8591 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8592
8593 /* SPE arithmetic */
8594 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8595 static inline void gen_##name(DisasContext *ctx) \
8596 { \
8597 TCGv_i32 t0; \
8598 if (unlikely(!ctx->spe_enabled)) { \
8599 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8600 return; \
8601 } \
8602 t0 = tcg_temp_new_i32(); \
8603 \
8604 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8605 tcg_op(t0, t0); \
8606 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8607 \
8608 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8609 tcg_op(t0, t0); \
8610 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8611 \
8612 tcg_temp_free_i32(t0); \
8613 }
8614
8615 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8616 {
8617 TCGLabel *l1 = gen_new_label();
8618 TCGLabel *l2 = gen_new_label();
8619
8620 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8621 tcg_gen_neg_i32(ret, arg1);
8622 tcg_gen_br(l2);
8623 gen_set_label(l1);
8624 tcg_gen_mov_i32(ret, arg1);
8625 gen_set_label(l2);
8626 }
8627 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8628 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8629 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8630 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8631 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8632 {
8633 tcg_gen_addi_i32(ret, arg1, 0x8000);
8634 tcg_gen_ext16u_i32(ret, ret);
8635 }
8636 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8637 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8638 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8639
8640 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8641 static inline void gen_##name(DisasContext *ctx) \
8642 { \
8643 TCGv_i32 t0, t1; \
8644 if (unlikely(!ctx->spe_enabled)) { \
8645 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8646 return; \
8647 } \
8648 t0 = tcg_temp_new_i32(); \
8649 t1 = tcg_temp_new_i32(); \
8650 \
8651 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8652 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8653 tcg_op(t0, t0, t1); \
8654 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8655 \
8656 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8657 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8658 tcg_op(t0, t0, t1); \
8659 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8660 \
8661 tcg_temp_free_i32(t0); \
8662 tcg_temp_free_i32(t1); \
8663 }
8664
8665 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8666 {
8667 TCGLabel *l1 = gen_new_label();
8668 TCGLabel *l2 = gen_new_label();
8669 TCGv_i32 t0 = tcg_temp_local_new_i32();
8670
8671 /* No error here: 6 bits are used */
8672 tcg_gen_andi_i32(t0, arg2, 0x3F);
8673 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8674 tcg_gen_shr_i32(ret, arg1, t0);
8675 tcg_gen_br(l2);
8676 gen_set_label(l1);
8677 tcg_gen_movi_i32(ret, 0);
8678 gen_set_label(l2);
8679 tcg_temp_free_i32(t0);
8680 }
8681 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8682 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8683 {
8684 TCGLabel *l1 = gen_new_label();
8685 TCGLabel *l2 = gen_new_label();
8686 TCGv_i32 t0 = tcg_temp_local_new_i32();
8687
8688 /* No error here: 6 bits are used */
8689 tcg_gen_andi_i32(t0, arg2, 0x3F);
8690 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8691 tcg_gen_sar_i32(ret, arg1, t0);
8692 tcg_gen_br(l2);
8693 gen_set_label(l1);
8694 tcg_gen_movi_i32(ret, 0);
8695 gen_set_label(l2);
8696 tcg_temp_free_i32(t0);
8697 }
8698 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8699 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8700 {
8701 TCGLabel *l1 = gen_new_label();
8702 TCGLabel *l2 = gen_new_label();
8703 TCGv_i32 t0 = tcg_temp_local_new_i32();
8704
8705 /* No error here: 6 bits are used */
8706 tcg_gen_andi_i32(t0, arg2, 0x3F);
8707 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8708 tcg_gen_shl_i32(ret, arg1, t0);
8709 tcg_gen_br(l2);
8710 gen_set_label(l1);
8711 tcg_gen_movi_i32(ret, 0);
8712 gen_set_label(l2);
8713 tcg_temp_free_i32(t0);
8714 }
8715 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8716 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8717 {
8718 TCGv_i32 t0 = tcg_temp_new_i32();
8719 tcg_gen_andi_i32(t0, arg2, 0x1F);
8720 tcg_gen_rotl_i32(ret, arg1, t0);
8721 tcg_temp_free_i32(t0);
8722 }
8723 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8724 static inline void gen_evmergehi(DisasContext *ctx)
8725 {
8726 if (unlikely(!ctx->spe_enabled)) {
8727 gen_exception(ctx, POWERPC_EXCP_SPEU);
8728 return;
8729 }
8730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8731 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8732 }
8733 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8734 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8735 {
8736 tcg_gen_sub_i32(ret, arg2, arg1);
8737 }
8738 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8739
8740 /* SPE arithmetic immediate */
8741 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8742 static inline void gen_##name(DisasContext *ctx) \
8743 { \
8744 TCGv_i32 t0; \
8745 if (unlikely(!ctx->spe_enabled)) { \
8746 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8747 return; \
8748 } \
8749 t0 = tcg_temp_new_i32(); \
8750 \
8751 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8752 tcg_op(t0, t0, rA(ctx->opcode)); \
8753 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8754 \
8755 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8756 tcg_op(t0, t0, rA(ctx->opcode)); \
8757 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8758 \
8759 tcg_temp_free_i32(t0); \
8760 }
8761 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8762 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8763
8764 /* SPE comparison */
8765 #define GEN_SPEOP_COMP(name, tcg_cond) \
8766 static inline void gen_##name(DisasContext *ctx) \
8767 { \
8768 if (unlikely(!ctx->spe_enabled)) { \
8769 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8770 return; \
8771 } \
8772 TCGLabel *l1 = gen_new_label(); \
8773 TCGLabel *l2 = gen_new_label(); \
8774 TCGLabel *l3 = gen_new_label(); \
8775 TCGLabel *l4 = gen_new_label(); \
8776 \
8777 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8778 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8779 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8780 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8781 \
8782 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8783 cpu_gpr[rB(ctx->opcode)], l1); \
8784 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8785 tcg_gen_br(l2); \
8786 gen_set_label(l1); \
8787 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8788 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8789 gen_set_label(l2); \
8790 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8791 cpu_gprh[rB(ctx->opcode)], l3); \
8792 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8793 ~(CRF_CH | CRF_CH_AND_CL)); \
8794 tcg_gen_br(l4); \
8795 gen_set_label(l3); \
8796 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8797 CRF_CH | CRF_CH_OR_CL); \
8798 gen_set_label(l4); \
8799 }
8800 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8801 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8802 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8803 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8804 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8805
8806 /* SPE misc */
8807 static inline void gen_brinc(DisasContext *ctx)
8808 {
8809 /* Note: brinc is usable even if SPE is disabled */
8810 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8811 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8812 }
8813 static inline void gen_evmergelo(DisasContext *ctx)
8814 {
8815 if (unlikely(!ctx->spe_enabled)) {
8816 gen_exception(ctx, POWERPC_EXCP_SPEU);
8817 return;
8818 }
8819 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8820 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8821 }
8822 static inline void gen_evmergehilo(DisasContext *ctx)
8823 {
8824 if (unlikely(!ctx->spe_enabled)) {
8825 gen_exception(ctx, POWERPC_EXCP_SPEU);
8826 return;
8827 }
8828 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8829 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8830 }
8831 static inline void gen_evmergelohi(DisasContext *ctx)
8832 {
8833 if (unlikely(!ctx->spe_enabled)) {
8834 gen_exception(ctx, POWERPC_EXCP_SPEU);
8835 return;
8836 }
8837 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8838 TCGv tmp = tcg_temp_new();
8839 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8840 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8841 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8842 tcg_temp_free(tmp);
8843 } else {
8844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8845 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8846 }
8847 }
8848 static inline void gen_evsplati(DisasContext *ctx)
8849 {
8850 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8851
8852 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8853 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8854 }
8855 static inline void gen_evsplatfi(DisasContext *ctx)
8856 {
8857 uint64_t imm = rA(ctx->opcode) << 27;
8858
8859 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8860 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8861 }
8862
8863 static inline void gen_evsel(DisasContext *ctx)
8864 {
8865 TCGLabel *l1 = gen_new_label();
8866 TCGLabel *l2 = gen_new_label();
8867 TCGLabel *l3 = gen_new_label();
8868 TCGLabel *l4 = gen_new_label();
8869 TCGv_i32 t0 = tcg_temp_local_new_i32();
8870
8871 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8872 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8873 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8874 tcg_gen_br(l2);
8875 gen_set_label(l1);
8876 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8877 gen_set_label(l2);
8878 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8879 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8880 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8881 tcg_gen_br(l4);
8882 gen_set_label(l3);
8883 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8884 gen_set_label(l4);
8885 tcg_temp_free_i32(t0);
8886 }
8887
8888 static void gen_evsel0(DisasContext *ctx)
8889 {
8890 gen_evsel(ctx);
8891 }
8892
8893 static void gen_evsel1(DisasContext *ctx)
8894 {
8895 gen_evsel(ctx);
8896 }
8897
8898 static void gen_evsel2(DisasContext *ctx)
8899 {
8900 gen_evsel(ctx);
8901 }
8902
8903 static void gen_evsel3(DisasContext *ctx)
8904 {
8905 gen_evsel(ctx);
8906 }
8907
8908 /* Multiply */
8909
8910 static inline void gen_evmwumi(DisasContext *ctx)
8911 {
8912 TCGv_i64 t0, t1;
8913
8914 if (unlikely(!ctx->spe_enabled)) {
8915 gen_exception(ctx, POWERPC_EXCP_SPEU);
8916 return;
8917 }
8918
8919 t0 = tcg_temp_new_i64();
8920 t1 = tcg_temp_new_i64();
8921
8922 /* t0 := rA; t1 := rB */
8923 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8924 tcg_gen_ext32u_i64(t0, t0);
8925 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8926 tcg_gen_ext32u_i64(t1, t1);
8927
8928 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8929
8930 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8931
8932 tcg_temp_free_i64(t0);
8933 tcg_temp_free_i64(t1);
8934 }
8935
8936 static inline void gen_evmwumia(DisasContext *ctx)
8937 {
8938 TCGv_i64 tmp;
8939
8940 if (unlikely(!ctx->spe_enabled)) {
8941 gen_exception(ctx, POWERPC_EXCP_SPEU);
8942 return;
8943 }
8944
8945 gen_evmwumi(ctx); /* rD := rA * rB */
8946
8947 tmp = tcg_temp_new_i64();
8948
8949 /* acc := rD */
8950 gen_load_gpr64(tmp, rD(ctx->opcode));
8951 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8952 tcg_temp_free_i64(tmp);
8953 }
8954
8955 static inline void gen_evmwumiaa(DisasContext *ctx)
8956 {
8957 TCGv_i64 acc;
8958 TCGv_i64 tmp;
8959
8960 if (unlikely(!ctx->spe_enabled)) {
8961 gen_exception(ctx, POWERPC_EXCP_SPEU);
8962 return;
8963 }
8964
8965 gen_evmwumi(ctx); /* rD := rA * rB */
8966
8967 acc = tcg_temp_new_i64();
8968 tmp = tcg_temp_new_i64();
8969
8970 /* tmp := rD */
8971 gen_load_gpr64(tmp, rD(ctx->opcode));
8972
8973 /* Load acc */
8974 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8975
8976 /* acc := tmp + acc */
8977 tcg_gen_add_i64(acc, acc, tmp);
8978
8979 /* Store acc */
8980 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8981
8982 /* rD := acc */
8983 gen_store_gpr64(rD(ctx->opcode), acc);
8984
8985 tcg_temp_free_i64(acc);
8986 tcg_temp_free_i64(tmp);
8987 }
8988
8989 static inline void gen_evmwsmi(DisasContext *ctx)
8990 {
8991 TCGv_i64 t0, t1;
8992
8993 if (unlikely(!ctx->spe_enabled)) {
8994 gen_exception(ctx, POWERPC_EXCP_SPEU);
8995 return;
8996 }
8997
8998 t0 = tcg_temp_new_i64();
8999 t1 = tcg_temp_new_i64();
9000
9001 /* t0 := rA; t1 := rB */
9002 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9003 tcg_gen_ext32s_i64(t0, t0);
9004 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9005 tcg_gen_ext32s_i64(t1, t1);
9006
9007 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9008
9009 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9010
9011 tcg_temp_free_i64(t0);
9012 tcg_temp_free_i64(t1);
9013 }
9014
9015 static inline void gen_evmwsmia(DisasContext *ctx)
9016 {
9017 TCGv_i64 tmp;
9018
9019 gen_evmwsmi(ctx); /* rD := rA * rB */
9020
9021 tmp = tcg_temp_new_i64();
9022
9023 /* acc := rD */
9024 gen_load_gpr64(tmp, rD(ctx->opcode));
9025 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9026
9027 tcg_temp_free_i64(tmp);
9028 }
9029
9030 static inline void gen_evmwsmiaa(DisasContext *ctx)
9031 {
9032 TCGv_i64 acc = tcg_temp_new_i64();
9033 TCGv_i64 tmp = tcg_temp_new_i64();
9034
9035 gen_evmwsmi(ctx); /* rD := rA * rB */
9036
9037 acc = tcg_temp_new_i64();
9038 tmp = tcg_temp_new_i64();
9039
9040 /* tmp := rD */
9041 gen_load_gpr64(tmp, rD(ctx->opcode));
9042
9043 /* Load acc */
9044 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9045
9046 /* acc := tmp + acc */
9047 tcg_gen_add_i64(acc, acc, tmp);
9048
9049 /* Store acc */
9050 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9051
9052 /* rD := acc */
9053 gen_store_gpr64(rD(ctx->opcode), acc);
9054
9055 tcg_temp_free_i64(acc);
9056 tcg_temp_free_i64(tmp);
9057 }
9058
9059 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9060 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9061 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9062 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9063 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9064 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9065 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9066 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9067 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9068 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9069 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9070 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9071 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9072 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9073 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9074 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9075 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9076 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9077 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9078 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9079 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9080 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9081 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9082 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9083 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9084 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9085 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9086 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9087 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9088
9089 /* SPE load and stores */
9090 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9091 {
9092 target_ulong uimm = rB(ctx->opcode);
9093
9094 if (rA(ctx->opcode) == 0) {
9095 tcg_gen_movi_tl(EA, uimm << sh);
9096 } else {
9097 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9098 if (NARROW_MODE(ctx)) {
9099 tcg_gen_ext32u_tl(EA, EA);
9100 }
9101 }
9102 }
9103
9104 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9105 {
9106 TCGv_i64 t0 = tcg_temp_new_i64();
9107 gen_qemu_ld64(ctx, t0, addr);
9108 gen_store_gpr64(rD(ctx->opcode), t0);
9109 tcg_temp_free_i64(t0);
9110 }
9111
9112 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9113 {
9114 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9115 gen_addr_add(ctx, addr, addr, 4);
9116 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9117 }
9118
9119 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9120 {
9121 TCGv t0 = tcg_temp_new();
9122 gen_qemu_ld16u(ctx, t0, addr);
9123 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9124 gen_addr_add(ctx, addr, addr, 2);
9125 gen_qemu_ld16u(ctx, t0, addr);
9126 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9127 gen_addr_add(ctx, addr, addr, 2);
9128 gen_qemu_ld16u(ctx, t0, addr);
9129 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9130 gen_addr_add(ctx, addr, addr, 2);
9131 gen_qemu_ld16u(ctx, t0, addr);
9132 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9133 tcg_temp_free(t0);
9134 }
9135
9136 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9137 {
9138 TCGv t0 = tcg_temp_new();
9139 gen_qemu_ld16u(ctx, t0, addr);
9140 tcg_gen_shli_tl(t0, t0, 16);
9141 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9142 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9143 tcg_temp_free(t0);
9144 }
9145
9146 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9147 {
9148 TCGv t0 = tcg_temp_new();
9149 gen_qemu_ld16u(ctx, t0, addr);
9150 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9152 tcg_temp_free(t0);
9153 }
9154
9155 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9156 {
9157 TCGv t0 = tcg_temp_new();
9158 gen_qemu_ld16s(ctx, t0, addr);
9159 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9160 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9161 tcg_temp_free(t0);
9162 }
9163
9164 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9165 {
9166 TCGv t0 = tcg_temp_new();
9167 gen_qemu_ld16u(ctx, t0, addr);
9168 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9169 gen_addr_add(ctx, addr, addr, 2);
9170 gen_qemu_ld16u(ctx, t0, addr);
9171 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9172 tcg_temp_free(t0);
9173 }
9174
9175 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9176 {
9177 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9178 gen_addr_add(ctx, addr, addr, 2);
9179 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9180 }
9181
9182 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9183 {
9184 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9185 gen_addr_add(ctx, addr, addr, 2);
9186 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9187 }
9188
9189 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9190 {
9191 TCGv t0 = tcg_temp_new();
9192 gen_qemu_ld32u(ctx, t0, addr);
9193 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9194 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9195 tcg_temp_free(t0);
9196 }
9197
9198 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9199 {
9200 TCGv t0 = tcg_temp_new();
9201 gen_qemu_ld16u(ctx, t0, addr);
9202 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9203 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9204 gen_addr_add(ctx, addr, addr, 2);
9205 gen_qemu_ld16u(ctx, t0, addr);
9206 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9207 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9208 tcg_temp_free(t0);
9209 }
9210
9211 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9212 {
9213 TCGv_i64 t0 = tcg_temp_new_i64();
9214 gen_load_gpr64(t0, rS(ctx->opcode));
9215 gen_qemu_st64(ctx, t0, addr);
9216 tcg_temp_free_i64(t0);
9217 }
9218
9219 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9220 {
9221 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9222 gen_addr_add(ctx, addr, addr, 4);
9223 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9224 }
9225
9226 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9227 {
9228 TCGv t0 = tcg_temp_new();
9229 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9230 gen_qemu_st16(ctx, t0, addr);
9231 gen_addr_add(ctx, addr, addr, 2);
9232 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9233 gen_addr_add(ctx, addr, addr, 2);
9234 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9235 gen_qemu_st16(ctx, t0, addr);
9236 tcg_temp_free(t0);
9237 gen_addr_add(ctx, addr, addr, 2);
9238 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9239 }
9240
9241 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9242 {
9243 TCGv t0 = tcg_temp_new();
9244 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9245 gen_qemu_st16(ctx, t0, addr);
9246 gen_addr_add(ctx, addr, addr, 2);
9247 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9248 gen_qemu_st16(ctx, t0, addr);
9249 tcg_temp_free(t0);
9250 }
9251
9252 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9253 {
9254 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9255 gen_addr_add(ctx, addr, addr, 2);
9256 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9257 }
9258
9259 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9260 {
9261 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9262 }
9263
9264 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9265 {
9266 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9267 }
9268
9269 #define GEN_SPEOP_LDST(name, opc2, sh) \
9270 static void glue(gen_, name)(DisasContext *ctx) \
9271 { \
9272 TCGv t0; \
9273 if (unlikely(!ctx->spe_enabled)) { \
9274 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9275 return; \
9276 } \
9277 gen_set_access_type(ctx, ACCESS_INT); \
9278 t0 = tcg_temp_new(); \
9279 if (Rc(ctx->opcode)) { \
9280 gen_addr_spe_imm_index(ctx, t0, sh); \
9281 } else { \
9282 gen_addr_reg_index(ctx, t0); \
9283 } \
9284 gen_op_##name(ctx, t0); \
9285 tcg_temp_free(t0); \
9286 }
9287
9288 GEN_SPEOP_LDST(evldd, 0x00, 3);
9289 GEN_SPEOP_LDST(evldw, 0x01, 3);
9290 GEN_SPEOP_LDST(evldh, 0x02, 3);
9291 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9292 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9293 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9294 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9295 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9296 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9297 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9298 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9299
9300 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9301 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9302 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9303 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9304 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9305 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9306 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9307
9308 /* Multiply and add - TODO */
9309 #if 0
9310 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9311 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9312 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9313 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9314 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9315 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9316 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9318 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9319 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9320 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9321 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9322
9323 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9324 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9325 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9326 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9327 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9331 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9334 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335
9336 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9337 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9338 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9339 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9340 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9341
9342 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9343 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9344 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9345 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9346 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9347 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9348 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9349 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9350 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9351 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9352 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9353 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9354
9355 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9356 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9357 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9358 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9359
9360 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9361 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9362 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9363 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9364 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9365 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9366 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9367 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9368 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9369 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9370 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9371 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372
9373 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9374 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9375 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9376 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9377 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9378 #endif
9379
9380 /*** SPE floating-point extension ***/
9381 #define GEN_SPEFPUOP_CONV_32_32(name) \
9382 static inline void gen_##name(DisasContext *ctx) \
9383 { \
9384 TCGv_i32 t0 = tcg_temp_new_i32(); \
9385 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9386 gen_helper_##name(t0, cpu_env, t0); \
9387 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9388 tcg_temp_free_i32(t0); \
9389 }
9390 #define GEN_SPEFPUOP_CONV_32_64(name) \
9391 static inline void gen_##name(DisasContext *ctx) \
9392 { \
9393 TCGv_i64 t0 = tcg_temp_new_i64(); \
9394 TCGv_i32 t1 = tcg_temp_new_i32(); \
9395 gen_load_gpr64(t0, rB(ctx->opcode)); \
9396 gen_helper_##name(t1, cpu_env, t0); \
9397 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9398 tcg_temp_free_i64(t0); \
9399 tcg_temp_free_i32(t1); \
9400 }
9401 #define GEN_SPEFPUOP_CONV_64_32(name) \
9402 static inline void gen_##name(DisasContext *ctx) \
9403 { \
9404 TCGv_i64 t0 = tcg_temp_new_i64(); \
9405 TCGv_i32 t1 = tcg_temp_new_i32(); \
9406 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9407 gen_helper_##name(t0, cpu_env, t1); \
9408 gen_store_gpr64(rD(ctx->opcode), t0); \
9409 tcg_temp_free_i64(t0); \
9410 tcg_temp_free_i32(t1); \
9411 }
9412 #define GEN_SPEFPUOP_CONV_64_64(name) \
9413 static inline void gen_##name(DisasContext *ctx) \
9414 { \
9415 TCGv_i64 t0 = tcg_temp_new_i64(); \
9416 gen_load_gpr64(t0, rB(ctx->opcode)); \
9417 gen_helper_##name(t0, cpu_env, t0); \
9418 gen_store_gpr64(rD(ctx->opcode), t0); \
9419 tcg_temp_free_i64(t0); \
9420 }
9421 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9422 static inline void gen_##name(DisasContext *ctx) \
9423 { \
9424 TCGv_i32 t0, t1; \
9425 if (unlikely(!ctx->spe_enabled)) { \
9426 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9427 return; \
9428 } \
9429 t0 = tcg_temp_new_i32(); \
9430 t1 = tcg_temp_new_i32(); \
9431 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9432 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9433 gen_helper_##name(t0, cpu_env, t0, t1); \
9434 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9435 \
9436 tcg_temp_free_i32(t0); \
9437 tcg_temp_free_i32(t1); \
9438 }
9439 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9440 static inline void gen_##name(DisasContext *ctx) \
9441 { \
9442 TCGv_i64 t0, t1; \
9443 if (unlikely(!ctx->spe_enabled)) { \
9444 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9445 return; \
9446 } \
9447 t0 = tcg_temp_new_i64(); \
9448 t1 = tcg_temp_new_i64(); \
9449 gen_load_gpr64(t0, rA(ctx->opcode)); \
9450 gen_load_gpr64(t1, rB(ctx->opcode)); \
9451 gen_helper_##name(t0, cpu_env, t0, t1); \
9452 gen_store_gpr64(rD(ctx->opcode), t0); \
9453 tcg_temp_free_i64(t0); \
9454 tcg_temp_free_i64(t1); \
9455 }
9456 #define GEN_SPEFPUOP_COMP_32(name) \
9457 static inline void gen_##name(DisasContext *ctx) \
9458 { \
9459 TCGv_i32 t0, t1; \
9460 if (unlikely(!ctx->spe_enabled)) { \
9461 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9462 return; \
9463 } \
9464 t0 = tcg_temp_new_i32(); \
9465 t1 = tcg_temp_new_i32(); \
9466 \
9467 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9468 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9469 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9470 \
9471 tcg_temp_free_i32(t0); \
9472 tcg_temp_free_i32(t1); \
9473 }
9474 #define GEN_SPEFPUOP_COMP_64(name) \
9475 static inline void gen_##name(DisasContext *ctx) \
9476 { \
9477 TCGv_i64 t0, t1; \
9478 if (unlikely(!ctx->spe_enabled)) { \
9479 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9480 return; \
9481 } \
9482 t0 = tcg_temp_new_i64(); \
9483 t1 = tcg_temp_new_i64(); \
9484 gen_load_gpr64(t0, rA(ctx->opcode)); \
9485 gen_load_gpr64(t1, rB(ctx->opcode)); \
9486 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9487 tcg_temp_free_i64(t0); \
9488 tcg_temp_free_i64(t1); \
9489 }
9490
9491 /* Single precision floating-point vectors operations */
9492 /* Arithmetic */
9493 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9494 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9495 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9496 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9497 static inline void gen_evfsabs(DisasContext *ctx)
9498 {
9499 if (unlikely(!ctx->spe_enabled)) {
9500 gen_exception(ctx, POWERPC_EXCP_SPEU);
9501 return;
9502 }
9503 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9504 ~0x80000000);
9505 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9506 ~0x80000000);
9507 }
9508 static inline void gen_evfsnabs(DisasContext *ctx)
9509 {
9510 if (unlikely(!ctx->spe_enabled)) {
9511 gen_exception(ctx, POWERPC_EXCP_SPEU);
9512 return;
9513 }
9514 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9515 0x80000000);
9516 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9517 0x80000000);
9518 }
9519 static inline void gen_evfsneg(DisasContext *ctx)
9520 {
9521 if (unlikely(!ctx->spe_enabled)) {
9522 gen_exception(ctx, POWERPC_EXCP_SPEU);
9523 return;
9524 }
9525 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9526 0x80000000);
9527 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9528 0x80000000);
9529 }
9530
9531 /* Conversion */
9532 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9533 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9534 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9535 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9536 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9537 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9538 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9539 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9540 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9541 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9542
9543 /* Comparison */
9544 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9545 GEN_SPEFPUOP_COMP_64(evfscmplt);
9546 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9547 GEN_SPEFPUOP_COMP_64(evfststgt);
9548 GEN_SPEFPUOP_COMP_64(evfststlt);
9549 GEN_SPEFPUOP_COMP_64(evfststeq);
9550
9551 /* Opcodes definitions */
9552 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9553 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9554 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9555 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9556 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9557 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9558 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9559 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9560 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9561 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9562 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9563 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9564 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9565 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9566
9567 /* Single precision floating-point operations */
9568 /* Arithmetic */
9569 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9570 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9571 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9572 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9573 static inline void gen_efsabs(DisasContext *ctx)
9574 {
9575 if (unlikely(!ctx->spe_enabled)) {
9576 gen_exception(ctx, POWERPC_EXCP_SPEU);
9577 return;
9578 }
9579 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9580 }
9581 static inline void gen_efsnabs(DisasContext *ctx)
9582 {
9583 if (unlikely(!ctx->spe_enabled)) {
9584 gen_exception(ctx, POWERPC_EXCP_SPEU);
9585 return;
9586 }
9587 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9588 }
9589 static inline void gen_efsneg(DisasContext *ctx)
9590 {
9591 if (unlikely(!ctx->spe_enabled)) {
9592 gen_exception(ctx, POWERPC_EXCP_SPEU);
9593 return;
9594 }
9595 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9596 }
9597
9598 /* Conversion */
9599 GEN_SPEFPUOP_CONV_32_32(efscfui);
9600 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9601 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9602 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9603 GEN_SPEFPUOP_CONV_32_32(efsctui);
9604 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9605 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9606 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9607 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9608 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9609 GEN_SPEFPUOP_CONV_32_64(efscfd);
9610
9611 /* Comparison */
9612 GEN_SPEFPUOP_COMP_32(efscmpgt);
9613 GEN_SPEFPUOP_COMP_32(efscmplt);
9614 GEN_SPEFPUOP_COMP_32(efscmpeq);
9615 GEN_SPEFPUOP_COMP_32(efststgt);
9616 GEN_SPEFPUOP_COMP_32(efststlt);
9617 GEN_SPEFPUOP_COMP_32(efststeq);
9618
9619 /* Opcodes definitions */
9620 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9621 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9622 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9623 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9624 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9625 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9626 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9627 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9628 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9629 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9630 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9631 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9632 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9633 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9634
9635 /* Double precision floating-point operations */
9636 /* Arithmetic */
9637 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9638 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9639 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9640 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9641 static inline void gen_efdabs(DisasContext *ctx)
9642 {
9643 if (unlikely(!ctx->spe_enabled)) {
9644 gen_exception(ctx, POWERPC_EXCP_SPEU);
9645 return;
9646 }
9647 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9648 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9649 ~0x80000000);
9650 }
9651 static inline void gen_efdnabs(DisasContext *ctx)
9652 {
9653 if (unlikely(!ctx->spe_enabled)) {
9654 gen_exception(ctx, POWERPC_EXCP_SPEU);
9655 return;
9656 }
9657 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9658 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9659 0x80000000);
9660 }
9661 static inline void gen_efdneg(DisasContext *ctx)
9662 {
9663 if (unlikely(!ctx->spe_enabled)) {
9664 gen_exception(ctx, POWERPC_EXCP_SPEU);
9665 return;
9666 }
9667 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9668 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9669 0x80000000);
9670 }
9671
9672 /* Conversion */
9673 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9674 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9675 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9676 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9677 GEN_SPEFPUOP_CONV_32_64(efdctui);
9678 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9679 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9680 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9681 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9682 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9683 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9684 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9685 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9686 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9687 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9688
9689 /* Comparison */
9690 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9691 GEN_SPEFPUOP_COMP_64(efdcmplt);
9692 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9693 GEN_SPEFPUOP_COMP_64(efdtstgt);
9694 GEN_SPEFPUOP_COMP_64(efdtstlt);
9695 GEN_SPEFPUOP_COMP_64(efdtsteq);
9696
9697 /* Opcodes definitions */
9698 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9699 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9700 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9701 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9702 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9703 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9704 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9705 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9706 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9707 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9708 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9709 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9710 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9711 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9712 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9713 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9714
9715 static void gen_tbegin(DisasContext *ctx)
9716 {
9717 if (unlikely(!ctx->tm_enabled)) {
9718 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9719 return;
9720 }
9721 gen_helper_tbegin(cpu_env);
9722 }
9723
9724 #define GEN_TM_NOOP(name) \
9725 static inline void gen_##name(DisasContext *ctx) \
9726 { \
9727 if (unlikely(!ctx->tm_enabled)) { \
9728 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9729 return; \
9730 } \
9731 /* Because tbegin always fails in QEMU, these user \
9732 * space instructions all have a simple implementation: \
9733 * \
9734 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9735 * = 0b0 || 0b00 || 0b0 \
9736 */ \
9737 tcg_gen_movi_i32(cpu_crf[0], 0); \
9738 }
9739
9740 GEN_TM_NOOP(tend);
9741 GEN_TM_NOOP(tabort);
9742 GEN_TM_NOOP(tabortwc);
9743 GEN_TM_NOOP(tabortwci);
9744 GEN_TM_NOOP(tabortdc);
9745 GEN_TM_NOOP(tabortdci);
9746 GEN_TM_NOOP(tsr);
9747
9748 static void gen_tcheck(DisasContext *ctx)
9749 {
9750 if (unlikely(!ctx->tm_enabled)) {
9751 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9752 return;
9753 }
9754 /* Because tbegin always fails, the tcheck implementation
9755 * is simple:
9756 *
9757 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9758 * = 0b1 || 0b00 || 0b0
9759 */
9760 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9761 }
9762
9763 #if defined(CONFIG_USER_ONLY)
9764 #define GEN_TM_PRIV_NOOP(name) \
9765 static inline void gen_##name(DisasContext *ctx) \
9766 { \
9767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9768 }
9769
9770 #else
9771
9772 #define GEN_TM_PRIV_NOOP(name) \
9773 static inline void gen_##name(DisasContext *ctx) \
9774 { \
9775 if (unlikely(ctx->pr)) { \
9776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9777 return; \
9778 } \
9779 if (unlikely(!ctx->tm_enabled)) { \
9780 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9781 return; \
9782 } \
9783 /* Because tbegin always fails, the implementation is \
9784 * simple: \
9785 * \
9786 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9787 * = 0b0 || 0b00 | 0b0 \
9788 */ \
9789 tcg_gen_movi_i32(cpu_crf[0], 0); \
9790 }
9791
9792 #endif
9793
9794 GEN_TM_PRIV_NOOP(treclaim);
9795 GEN_TM_PRIV_NOOP(trechkpt);
9796
9797 static opcode_t opcodes[] = {
9798 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9799 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9800 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9801 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9802 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9803 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9804 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9805 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9806 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9807 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9808 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9809 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9810 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9811 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9812 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9813 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9814 #if defined(TARGET_PPC64)
9815 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9816 #endif
9817 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9818 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9819 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9820 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9821 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9822 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9823 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9824 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9825 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9826 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9827 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9828 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9829 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9830 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9831 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9832 #if defined(TARGET_PPC64)
9833 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9834 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9835 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9836 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9837 #endif
9838 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9839 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9840 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9841 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9842 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9843 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9844 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9845 #if defined(TARGET_PPC64)
9846 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9847 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9848 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9849 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9850 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9851 #endif
9852 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9853 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9854 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9855 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9856 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9857 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9858 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9859 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9860 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9861 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9862 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9863 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9864 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9865 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9866 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9867 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9868 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9869 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9870 #if defined(TARGET_PPC64)
9871 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9872 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9873 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9874 #endif
9875 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9877 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9878 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9879 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9880 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9881 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9882 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9883 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9884 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9885 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9886 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9887 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9888 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9889 #if defined(TARGET_PPC64)
9890 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9891 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9892 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9893 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9894 #endif
9895 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9896 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9897 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9898 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9899 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9900 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9901 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9902 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9903 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9904 #if defined(TARGET_PPC64)
9905 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9906 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9907 #endif
9908 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9909 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9910 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9911 #if defined(TARGET_PPC64)
9912 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9913 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9914 #endif
9915 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9916 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9917 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9918 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9919 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9920 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9921 #if defined(TARGET_PPC64)
9922 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9923 #endif
9924 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9925 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9926 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9927 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9928 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9929 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9930 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9931 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9932 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9933 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9934 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9935 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9936 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9937 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9938 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9939 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9940 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9941 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9942 #if defined(TARGET_PPC64)
9943 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9944 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9945 PPC_SEGMENT_64B),
9946 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9947 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9948 PPC_SEGMENT_64B),
9949 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9950 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9951 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9952 #endif
9953 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9954 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9955 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9956 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9957 #if defined(TARGET_PPC64)
9958 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9959 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9960 #endif
9961 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9962 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9963 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9964 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9965 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9966 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9967 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9968 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9969 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9970 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9971 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9972 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9973 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9974 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9975 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9976 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9977 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9978 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9979 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9980 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9981 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9982 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9983 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9984 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9985 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9986 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9987 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9988 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9989 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9990 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9991 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9992 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9993 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9994 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9995 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9996 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9997 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9998 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9999 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10000 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10001 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10002 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10003 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10004 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10005 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10006 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10007 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10008 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10009 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10010 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10011 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10012 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10013 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10014 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10015 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10016 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10017 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10018 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10019 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10020 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10021 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10022 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10023 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10024 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10025 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10026 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10027 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10028 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10029 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10030 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10031 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10032 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10033 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10034 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10035 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10036 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10037 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10038 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10039 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10040 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10041 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10042 PPC_NONE, PPC2_BOOKE206),
10043 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10044 PPC_NONE, PPC2_BOOKE206),
10045 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10046 PPC_NONE, PPC2_BOOKE206),
10047 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10048 PPC_NONE, PPC2_BOOKE206),
10049 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10050 PPC_NONE, PPC2_BOOKE206),
10051 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10052 PPC_NONE, PPC2_PRCNTL),
10053 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10054 PPC_NONE, PPC2_PRCNTL),
10055 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10056 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10057 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10058 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10059 PPC_BOOKE, PPC2_BOOKE206),
10060 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10061 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10062 PPC_BOOKE, PPC2_BOOKE206),
10063 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10064 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10065 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10066 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10067 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10068 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10069 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10070 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10071 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10072
10073 #undef GEN_INT_ARITH_ADD
10074 #undef GEN_INT_ARITH_ADD_CONST
10075 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10076 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10077 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10078 add_ca, compute_ca, compute_ov) \
10079 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10080 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10081 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10082 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10083 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10084 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10085 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10086 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10087 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10088 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10089 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10090
10091 #undef GEN_INT_ARITH_DIVW
10092 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10093 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10094 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10095 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10096 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10097 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10098 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10099 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10100 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10101 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10102
10103 #if defined(TARGET_PPC64)
10104 #undef GEN_INT_ARITH_DIVD
10105 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10106 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10107 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10108 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10109 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10110 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10111
10112 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10113 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10114 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10115 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10116
10117 #undef GEN_INT_ARITH_MUL_HELPER
10118 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10119 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10120 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10121 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10122 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10123 #endif
10124
10125 #undef GEN_INT_ARITH_SUBF
10126 #undef GEN_INT_ARITH_SUBF_CONST
10127 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10128 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10129 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10130 add_ca, compute_ca, compute_ov) \
10131 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10132 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10133 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10134 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10135 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10136 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10137 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10138 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10139 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10140 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10141 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10142
10143 #undef GEN_LOGICAL1
10144 #undef GEN_LOGICAL2
10145 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10146 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10147 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10148 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10149 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10150 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10151 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10152 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10153 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10154 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10155 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10156 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10157 #if defined(TARGET_PPC64)
10158 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10159 #endif
10160
10161 #if defined(TARGET_PPC64)
10162 #undef GEN_PPC64_R2
10163 #undef GEN_PPC64_R4
10164 #define GEN_PPC64_R2(name, opc1, opc2) \
10165 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10166 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10167 PPC_64B)
10168 #define GEN_PPC64_R4(name, opc1, opc2) \
10169 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10170 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10171 PPC_64B), \
10172 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10173 PPC_64B), \
10174 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10175 PPC_64B)
10176 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10177 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10178 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10179 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10180 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10181 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10182 #endif
10183
10184 #undef _GEN_FLOAT_ACB
10185 #undef GEN_FLOAT_ACB
10186 #undef _GEN_FLOAT_AB
10187 #undef GEN_FLOAT_AB
10188 #undef _GEN_FLOAT_AC
10189 #undef GEN_FLOAT_AC
10190 #undef GEN_FLOAT_B
10191 #undef GEN_FLOAT_BS
10192 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10193 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10194 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10195 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10196 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10197 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10198 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10199 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10200 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10201 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10202 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10203 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10204 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10205 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10206 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10207 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10208 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10209 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10210 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10211
10212 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10213 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10214 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10215 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10216 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10217 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10218 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10219 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10220 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10221 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10222 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10223 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10224 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10225 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10226 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10227 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10228 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10229 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10230 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10231 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10232 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10233 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10234 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10235 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10236 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10237 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10238 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10239 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10240 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10241 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10242 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10243
10244 #undef GEN_LD
10245 #undef GEN_LDU
10246 #undef GEN_LDUX
10247 #undef GEN_LDX_E
10248 #undef GEN_LDS
10249 #define GEN_LD(name, ldop, opc, type) \
10250 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10251 #define GEN_LDU(name, ldop, opc, type) \
10252 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10253 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10254 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10255 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10256 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10257 #define GEN_LDS(name, ldop, op, type) \
10258 GEN_LD(name, ldop, op | 0x20, type) \
10259 GEN_LDU(name, ldop, op | 0x21, type) \
10260 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10261 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10262
10263 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10264 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10265 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10266 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10267 #if defined(TARGET_PPC64)
10268 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10269 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10270 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10271 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10272 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10273 #endif
10274 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10275 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10276
10277 #undef GEN_ST
10278 #undef GEN_STU
10279 #undef GEN_STUX
10280 #undef GEN_STX_E
10281 #undef GEN_STS
10282 #define GEN_ST(name, stop, opc, type) \
10283 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10284 #define GEN_STU(name, stop, opc, type) \
10285 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10286 #define GEN_STUX(name, stop, opc2, opc3, type) \
10287 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10288 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10289 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10290 #define GEN_STS(name, stop, op, type) \
10291 GEN_ST(name, stop, op | 0x20, type) \
10292 GEN_STU(name, stop, op | 0x21, type) \
10293 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10294 GEN_STX(name, stop, 0x17, op | 0x00, type)
10295
10296 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10297 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10298 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10299 #if defined(TARGET_PPC64)
10300 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10301 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10302 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10303 #endif
10304 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10305 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10306
10307 #undef GEN_LDF
10308 #undef GEN_LDUF
10309 #undef GEN_LDUXF
10310 #undef GEN_LDXF
10311 #undef GEN_LDFS
10312 #define GEN_LDF(name, ldop, opc, type) \
10313 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10314 #define GEN_LDUF(name, ldop, opc, type) \
10315 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10316 #define GEN_LDUXF(name, ldop, opc, type) \
10317 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10318 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10319 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10320 #define GEN_LDFS(name, ldop, op, type) \
10321 GEN_LDF(name, ldop, op | 0x20, type) \
10322 GEN_LDUF(name, ldop, op | 0x21, type) \
10323 GEN_LDUXF(name, ldop, op | 0x01, type) \
10324 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10325
10326 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10327 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10328 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10329 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10330 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10331 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10332
10333 #undef GEN_STF
10334 #undef GEN_STUF
10335 #undef GEN_STUXF
10336 #undef GEN_STXF
10337 #undef GEN_STFS
10338 #define GEN_STF(name, stop, opc, type) \
10339 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10340 #define GEN_STUF(name, stop, opc, type) \
10341 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10342 #define GEN_STUXF(name, stop, opc, type) \
10343 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10344 #define GEN_STXF(name, stop, opc2, opc3, type) \
10345 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10346 #define GEN_STFS(name, stop, op, type) \
10347 GEN_STF(name, stop, op | 0x20, type) \
10348 GEN_STUF(name, stop, op | 0x21, type) \
10349 GEN_STUXF(name, stop, op | 0x01, type) \
10350 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10351
10352 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10353 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10354 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10355 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10356 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10357
10358 #undef GEN_CRLOGIC
10359 #define GEN_CRLOGIC(name, tcg_op, opc) \
10360 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10361 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10362 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10363 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10364 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10365 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10366 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10367 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10368 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10369
10370 #undef GEN_MAC_HANDLER
10371 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10372 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10373 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10374 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10375 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10376 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10377 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10378 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10379 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10380 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10381 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10382 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10383 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10384 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10385 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10386 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10387 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10388 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10389 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10390 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10391 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10392 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10393 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10394 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10395 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10396 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10397 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10398 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10399 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10400 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10401 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10402 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10403 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10404 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10405 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10406 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10407 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10408 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10409 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10410 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10411 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10412 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10413 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10414 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10415
10416 #undef GEN_VR_LDX
10417 #undef GEN_VR_STX
10418 #undef GEN_VR_LVE
10419 #undef GEN_VR_STVE
10420 #define GEN_VR_LDX(name, opc2, opc3) \
10421 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10422 #define GEN_VR_STX(name, opc2, opc3) \
10423 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10424 #define GEN_VR_LVE(name, opc2, opc3) \
10425 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10426 #define GEN_VR_STVE(name, opc2, opc3) \
10427 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10428 GEN_VR_LDX(lvx, 0x07, 0x03),
10429 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10430 GEN_VR_LVE(bx, 0x07, 0x00),
10431 GEN_VR_LVE(hx, 0x07, 0x01),
10432 GEN_VR_LVE(wx, 0x07, 0x02),
10433 GEN_VR_STX(svx, 0x07, 0x07),
10434 GEN_VR_STX(svxl, 0x07, 0x0F),
10435 GEN_VR_STVE(bx, 0x07, 0x04),
10436 GEN_VR_STVE(hx, 0x07, 0x05),
10437 GEN_VR_STVE(wx, 0x07, 0x06),
10438
10439 #undef GEN_VX_LOGICAL
10440 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10441 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10442
10443 #undef GEN_VX_LOGICAL_207
10444 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10445 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10446
10447 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10448 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10449 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10450 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10451 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10452 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10453 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10454 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10455
10456 #undef GEN_VXFORM
10457 #define GEN_VXFORM(name, opc2, opc3) \
10458 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10459
10460 #undef GEN_VXFORM_207
10461 #define GEN_VXFORM_207(name, opc2, opc3) \
10462 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10463
10464 #undef GEN_VXFORM_DUAL
10465 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10466 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10467
10468 #undef GEN_VXRFORM_DUAL
10469 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10470 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10471 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10472
10473 GEN_VXFORM(vaddubm, 0, 0),
10474 GEN_VXFORM(vadduhm, 0, 1),
10475 GEN_VXFORM(vadduwm, 0, 2),
10476 GEN_VXFORM_207(vaddudm, 0, 3),
10477 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10478 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10479 GEN_VXFORM(vsubuwm, 0, 18),
10480 GEN_VXFORM_207(vsubudm, 0, 19),
10481 GEN_VXFORM(vmaxub, 1, 0),
10482 GEN_VXFORM(vmaxuh, 1, 1),
10483 GEN_VXFORM(vmaxuw, 1, 2),
10484 GEN_VXFORM_207(vmaxud, 1, 3),
10485 GEN_VXFORM(vmaxsb, 1, 4),
10486 GEN_VXFORM(vmaxsh, 1, 5),
10487 GEN_VXFORM(vmaxsw, 1, 6),
10488 GEN_VXFORM_207(vmaxsd, 1, 7),
10489 GEN_VXFORM(vminub, 1, 8),
10490 GEN_VXFORM(vminuh, 1, 9),
10491 GEN_VXFORM(vminuw, 1, 10),
10492 GEN_VXFORM_207(vminud, 1, 11),
10493 GEN_VXFORM(vminsb, 1, 12),
10494 GEN_VXFORM(vminsh, 1, 13),
10495 GEN_VXFORM(vminsw, 1, 14),
10496 GEN_VXFORM_207(vminsd, 1, 15),
10497 GEN_VXFORM(vavgub, 1, 16),
10498 GEN_VXFORM(vavguh, 1, 17),
10499 GEN_VXFORM(vavguw, 1, 18),
10500 GEN_VXFORM(vavgsb, 1, 20),
10501 GEN_VXFORM(vavgsh, 1, 21),
10502 GEN_VXFORM(vavgsw, 1, 22),
10503 GEN_VXFORM(vmrghb, 6, 0),
10504 GEN_VXFORM(vmrghh, 6, 1),
10505 GEN_VXFORM(vmrghw, 6, 2),
10506 GEN_VXFORM(vmrglb, 6, 4),
10507 GEN_VXFORM(vmrglh, 6, 5),
10508 GEN_VXFORM(vmrglw, 6, 6),
10509 GEN_VXFORM_207(vmrgew, 6, 30),
10510 GEN_VXFORM_207(vmrgow, 6, 26),
10511 GEN_VXFORM(vmuloub, 4, 0),
10512 GEN_VXFORM(vmulouh, 4, 1),
10513 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10514 GEN_VXFORM(vmulosb, 4, 4),
10515 GEN_VXFORM(vmulosh, 4, 5),
10516 GEN_VXFORM_207(vmulosw, 4, 6),
10517 GEN_VXFORM(vmuleub, 4, 8),
10518 GEN_VXFORM(vmuleuh, 4, 9),
10519 GEN_VXFORM_207(vmuleuw, 4, 10),
10520 GEN_VXFORM(vmulesb, 4, 12),
10521 GEN_VXFORM(vmulesh, 4, 13),
10522 GEN_VXFORM_207(vmulesw, 4, 14),
10523 GEN_VXFORM(vslb, 2, 4),
10524 GEN_VXFORM(vslh, 2, 5),
10525 GEN_VXFORM(vslw, 2, 6),
10526 GEN_VXFORM_207(vsld, 2, 23),
10527 GEN_VXFORM(vsrb, 2, 8),
10528 GEN_VXFORM(vsrh, 2, 9),
10529 GEN_VXFORM(vsrw, 2, 10),
10530 GEN_VXFORM_207(vsrd, 2, 27),
10531 GEN_VXFORM(vsrab, 2, 12),
10532 GEN_VXFORM(vsrah, 2, 13),
10533 GEN_VXFORM(vsraw, 2, 14),
10534 GEN_VXFORM_207(vsrad, 2, 15),
10535 GEN_VXFORM(vslo, 6, 16),
10536 GEN_VXFORM(vsro, 6, 17),
10537 GEN_VXFORM(vaddcuw, 0, 6),
10538 GEN_VXFORM(vsubcuw, 0, 22),
10539 GEN_VXFORM(vaddubs, 0, 8),
10540 GEN_VXFORM(vadduhs, 0, 9),
10541 GEN_VXFORM(vadduws, 0, 10),
10542 GEN_VXFORM(vaddsbs, 0, 12),
10543 GEN_VXFORM(vaddshs, 0, 13),
10544 GEN_VXFORM(vaddsws, 0, 14),
10545 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10546 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10547 GEN_VXFORM(vsubuws, 0, 26),
10548 GEN_VXFORM(vsubsbs, 0, 28),
10549 GEN_VXFORM(vsubshs, 0, 29),
10550 GEN_VXFORM(vsubsws, 0, 30),
10551 GEN_VXFORM_207(vadduqm, 0, 4),
10552 GEN_VXFORM_207(vaddcuq, 0, 5),
10553 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10554 GEN_VXFORM_207(vsubuqm, 0, 20),
10555 GEN_VXFORM_207(vsubcuq, 0, 21),
10556 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10557 GEN_VXFORM(vrlb, 2, 0),
10558 GEN_VXFORM(vrlh, 2, 1),
10559 GEN_VXFORM(vrlw, 2, 2),
10560 GEN_VXFORM_207(vrld, 2, 3),
10561 GEN_VXFORM(vsl, 2, 7),
10562 GEN_VXFORM(vsr, 2, 11),
10563 GEN_VXFORM(vpkuhum, 7, 0),
10564 GEN_VXFORM(vpkuwum, 7, 1),
10565 GEN_VXFORM_207(vpkudum, 7, 17),
10566 GEN_VXFORM(vpkuhus, 7, 2),
10567 GEN_VXFORM(vpkuwus, 7, 3),
10568 GEN_VXFORM_207(vpkudus, 7, 19),
10569 GEN_VXFORM(vpkshus, 7, 4),
10570 GEN_VXFORM(vpkswus, 7, 5),
10571 GEN_VXFORM_207(vpksdus, 7, 21),
10572 GEN_VXFORM(vpkshss, 7, 6),
10573 GEN_VXFORM(vpkswss, 7, 7),
10574 GEN_VXFORM_207(vpksdss, 7, 23),
10575 GEN_VXFORM(vpkpx, 7, 12),
10576 GEN_VXFORM(vsum4ubs, 4, 24),
10577 GEN_VXFORM(vsum4sbs, 4, 28),
10578 GEN_VXFORM(vsum4shs, 4, 25),
10579 GEN_VXFORM(vsum2sws, 4, 26),
10580 GEN_VXFORM(vsumsws, 4, 30),
10581 GEN_VXFORM(vaddfp, 5, 0),
10582 GEN_VXFORM(vsubfp, 5, 1),
10583 GEN_VXFORM(vmaxfp, 5, 16),
10584 GEN_VXFORM(vminfp, 5, 17),
10585
10586 #undef GEN_VXRFORM1
10587 #undef GEN_VXRFORM
10588 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10589 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10590 #define GEN_VXRFORM(name, opc2, opc3) \
10591 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10592 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10593 GEN_VXRFORM(vcmpequb, 3, 0)
10594 GEN_VXRFORM(vcmpequh, 3, 1)
10595 GEN_VXRFORM(vcmpequw, 3, 2)
10596 GEN_VXRFORM(vcmpgtsb, 3, 12)
10597 GEN_VXRFORM(vcmpgtsh, 3, 13)
10598 GEN_VXRFORM(vcmpgtsw, 3, 14)
10599 GEN_VXRFORM(vcmpgtub, 3, 8)
10600 GEN_VXRFORM(vcmpgtuh, 3, 9)
10601 GEN_VXRFORM(vcmpgtuw, 3, 10)
10602 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10603 GEN_VXRFORM(vcmpgefp, 3, 7)
10604 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10605 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10606
10607 #undef GEN_VXFORM_SIMM
10608 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10609 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10610 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10611 GEN_VXFORM_SIMM(vspltish, 6, 13),
10612 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10613
10614 #undef GEN_VXFORM_NOA
10615 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10616 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10617 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10618 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10619 GEN_VXFORM_207(vupkhsw, 7, 25),
10620 GEN_VXFORM_NOA(vupklsb, 7, 10),
10621 GEN_VXFORM_NOA(vupklsh, 7, 11),
10622 GEN_VXFORM_207(vupklsw, 7, 27),
10623 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10624 GEN_VXFORM_NOA(vupklpx, 7, 15),
10625 GEN_VXFORM_NOA(vrefp, 5, 4),
10626 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10627 GEN_VXFORM_NOA(vexptefp, 5, 6),
10628 GEN_VXFORM_NOA(vlogefp, 5, 7),
10629 GEN_VXFORM_NOA(vrfim, 5, 11),
10630 GEN_VXFORM_NOA(vrfin, 5, 8),
10631 GEN_VXFORM_NOA(vrfip, 5, 10),
10632 GEN_VXFORM_NOA(vrfiz, 5, 9),
10633
10634 #undef GEN_VXFORM_UIMM
10635 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10636 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10637 GEN_VXFORM_UIMM(vspltb, 6, 8),
10638 GEN_VXFORM_UIMM(vsplth, 6, 9),
10639 GEN_VXFORM_UIMM(vspltw, 6, 10),
10640 GEN_VXFORM_UIMM(vcfux, 5, 12),
10641 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10642 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10643 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10644
10645 #undef GEN_VAFORM_PAIRED
10646 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10647 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10648 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10649 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10650 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10651 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10652 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10653 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10654
10655 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10656 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10657 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10658 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10659
10660 GEN_VXFORM_207(vbpermq, 6, 21),
10661 GEN_VXFORM_207(vgbbd, 6, 20),
10662 GEN_VXFORM_207(vpmsumb, 4, 16),
10663 GEN_VXFORM_207(vpmsumh, 4, 17),
10664 GEN_VXFORM_207(vpmsumw, 4, 18),
10665 GEN_VXFORM_207(vpmsumd, 4, 19),
10666
10667 GEN_VXFORM_207(vsbox, 4, 23),
10668
10669 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10670 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10671
10672 GEN_VXFORM_207(vshasigmaw, 1, 26),
10673 GEN_VXFORM_207(vshasigmad, 1, 27),
10674
10675 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10676
10677 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10678 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10679 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10680 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10681 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10682 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10683 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10684
10685 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10686 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10687 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10688 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10689 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10690
10691 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10692 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10693 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10694 #if defined(TARGET_PPC64)
10695 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10696 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10697 #endif
10698
10699 #undef GEN_XX2FORM
10700 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10703
10704 #undef GEN_XX3FORM
10705 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10709 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10710
10711 #undef GEN_XX2IFORM
10712 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10714 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10715 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10716 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10717
10718 #undef GEN_XX3_RC_FORM
10719 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10720 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10721 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10724 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10728
10729 #undef GEN_XX3FORM_DM
10730 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10731 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10733 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10734 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10735 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10736 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10737 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10738 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10739 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10740 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10741 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10742 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10743 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10744 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10745 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10746 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10747
10748 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10749 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10750 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10751 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10752
10753 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10754 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10755 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10756 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10757 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10758 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10759 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10760 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10761
10762 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10763 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10764 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10765 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10766 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10767 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10768 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10769 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10770 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10771 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10772 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10773 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10774 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10775 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10776 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10777 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10778 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10779 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10780 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10781 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10782 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10783 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10784 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10785 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10786 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10787 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10788 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10789 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10790 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10791 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10792 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10793 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10794 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10795 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10796 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10797 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10798
10799 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10800 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10801 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10802 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10803 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10804 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10805 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10806 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10807 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10808 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10809 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10810 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10811 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10812 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10813 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10814 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10815 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10816 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10817
10818 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10819 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10820 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10821 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10822 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10823 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10824 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10825 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10826 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10827 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10828 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10829 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10830 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10831 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10832 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10833 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10834 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10835 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10836 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10837 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10838 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10839 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10840 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10841 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10842 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10843 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10844 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10845 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10846 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10847 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10848 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10849 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10850 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10851 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10852 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10853 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10854
10855 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10856 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10857 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10858 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10859 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10860 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10861 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10862 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10863 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10864 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10865 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10866 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10867 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10868 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10869 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10870 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10871 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10872 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10873 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10874 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10875 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10876 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10877 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10878 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10879 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10880 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10881 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10882 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10883 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10884 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10885 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10886 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10887 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10888 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10889 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10890 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10891
10892 #undef VSX_LOGICAL
10893 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10894 GEN_XX3FORM(name, opc2, opc3, fl2)
10895
10896 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10897 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10898 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10899 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10900 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10901 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10902 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10903 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10904 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10905 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10906 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10907 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10908
10909 #define GEN_XXSEL_ROW(opc3) \
10910 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10911 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10912 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10913 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10914 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10915 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10916 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10917 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10918
10919 GEN_XXSEL_ROW(0x00)
10920 GEN_XXSEL_ROW(0x01)
10921 GEN_XXSEL_ROW(0x02)
10922 GEN_XXSEL_ROW(0x03)
10923 GEN_XXSEL_ROW(0x04)
10924 GEN_XXSEL_ROW(0x05)
10925 GEN_XXSEL_ROW(0x06)
10926 GEN_XXSEL_ROW(0x07)
10927 GEN_XXSEL_ROW(0x08)
10928 GEN_XXSEL_ROW(0x09)
10929 GEN_XXSEL_ROW(0x0A)
10930 GEN_XXSEL_ROW(0x0B)
10931 GEN_XXSEL_ROW(0x0C)
10932 GEN_XXSEL_ROW(0x0D)
10933 GEN_XXSEL_ROW(0x0E)
10934 GEN_XXSEL_ROW(0x0F)
10935 GEN_XXSEL_ROW(0x10)
10936 GEN_XXSEL_ROW(0x11)
10937 GEN_XXSEL_ROW(0x12)
10938 GEN_XXSEL_ROW(0x13)
10939 GEN_XXSEL_ROW(0x14)
10940 GEN_XXSEL_ROW(0x15)
10941 GEN_XXSEL_ROW(0x16)
10942 GEN_XXSEL_ROW(0x17)
10943 GEN_XXSEL_ROW(0x18)
10944 GEN_XXSEL_ROW(0x19)
10945 GEN_XXSEL_ROW(0x1A)
10946 GEN_XXSEL_ROW(0x1B)
10947 GEN_XXSEL_ROW(0x1C)
10948 GEN_XXSEL_ROW(0x1D)
10949 GEN_XXSEL_ROW(0x1E)
10950 GEN_XXSEL_ROW(0x1F)
10951
10952 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10953
10954 #undef GEN_DFP_T_A_B_Rc
10955 #undef GEN_DFP_BF_A_B
10956 #undef GEN_DFP_BF_A_DCM
10957 #undef GEN_DFP_T_B_U32_U32_Rc
10958 #undef GEN_DFP_T_A_B_I32_Rc
10959 #undef GEN_DFP_T_B_Rc
10960 #undef GEN_DFP_T_FPR_I32_Rc
10961
10962 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10963 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10964
10965 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10966 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10967 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10968
10969 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10970 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10971 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10972 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10973 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10974
10975 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10976 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10977
10978 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10979 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10980 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10981
10982 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10983 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10984 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10985 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10986 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10987
10988 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10989 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10990
10991 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10992 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10993
10994 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10995 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10996
10997 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10998 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10999
11000 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11001 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11002
11003 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11004 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11005
11006 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11007 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11008
11009 #define GEN_DFP_BF_A_B(name, op1, op2) \
11010 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11011
11012 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11013 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11014
11015 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11016 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11017
11018 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11019 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11020
11021 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11022 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11023
11024 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11025 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11026
11027 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11028 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11029
11030 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11031 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11032
11033 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11034 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11035
11036 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11037 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11038
11039 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11040 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11041
11042 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11043 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11044
11045 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11046 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11047
11048 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11049 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11050
11051 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11052 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11053
11054 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11055 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11056
11057 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11058 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11059
11060 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11061 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11062
11063 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11064 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11065 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11066 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11067 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11068 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11069 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11070 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11071 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11072 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11073 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11074 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11075 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11076 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11077 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11078 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11079 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11080 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11081 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11082 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11083 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11084 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11085 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11086 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11087 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11088 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11089 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11090 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11091 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11092 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11093 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11094 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11095 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11096 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11097 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11098 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11099 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11100 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11101 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11102 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11103 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11104 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11105 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11106 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11107 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11108 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11109 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11110 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11111 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11112 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11113
11114 #undef GEN_SPE
11115 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11116 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11117 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11118 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11119 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11120 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11121 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11122 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11123 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11124 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11125 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11126 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11127 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11128 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11129 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11130 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11131 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11132 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11133 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11134 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11135 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11136 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11137 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11138 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11139 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11140 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11141 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11142 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11143 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11144 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11145 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11146
11147 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11148 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11149 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11150 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11151 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11152 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11153 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11154 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11155 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11156 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11157 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11158 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11159 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11160 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11161
11162 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11163 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11164 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11165 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11166 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11167 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11168 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11169 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11170 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11171 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11172 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11173 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11174 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11175 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11176
11177 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11178 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11179 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11180 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11181 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11182 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11183 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11184 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11185 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11186 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11187 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11188 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11189 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11190 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11191 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11192 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11193
11194 #undef GEN_SPEOP_LDST
11195 #define GEN_SPEOP_LDST(name, opc2, sh) \
11196 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11197 GEN_SPEOP_LDST(evldd, 0x00, 3),
11198 GEN_SPEOP_LDST(evldw, 0x01, 3),
11199 GEN_SPEOP_LDST(evldh, 0x02, 3),
11200 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11201 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11202 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11203 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11204 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11205 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11206 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11207 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11208
11209 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11210 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11211 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11212 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11213 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11214 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11215 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11216
11217 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11218 PPC_NONE, PPC2_TM),
11219 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11220 PPC_NONE, PPC2_TM),
11221 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11222 PPC_NONE, PPC2_TM),
11223 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11224 PPC_NONE, PPC2_TM),
11225 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11226 PPC_NONE, PPC2_TM),
11227 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11228 PPC_NONE, PPC2_TM),
11229 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11230 PPC_NONE, PPC2_TM),
11231 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11232 PPC_NONE, PPC2_TM),
11233 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11234 PPC_NONE, PPC2_TM),
11235 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11236 PPC_NONE, PPC2_TM),
11237 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11238 PPC_NONE, PPC2_TM),
11239 };
11240
11241 #include "helper_regs.h"
11242 #include "translate_init.c"
11243
11244 /*****************************************************************************/
11245 /* Misc PowerPC helpers */
11246 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11247 int flags)
11248 {
11249 #define RGPL 4
11250 #define RFPL 4
11251
11252 PowerPCCPU *cpu = POWERPC_CPU(cs);
11253 CPUPPCState *env = &cpu->env;
11254 int i;
11255
11256 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11257 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11258 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11259 cs->cpu_index);
11260 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11261 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11262 env->hflags, env->mmu_idx);
11263 #if !defined(NO_TIMER_DUMP)
11264 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11265 #if !defined(CONFIG_USER_ONLY)
11266 " DECR %08" PRIu32
11267 #endif
11268 "\n",
11269 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11270 #if !defined(CONFIG_USER_ONLY)
11271 , cpu_ppc_load_decr(env)
11272 #endif
11273 );
11274 #endif
11275 for (i = 0; i < 32; i++) {
11276 if ((i & (RGPL - 1)) == 0)
11277 cpu_fprintf(f, "GPR%02d", i);
11278 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11279 if ((i & (RGPL - 1)) == (RGPL - 1))
11280 cpu_fprintf(f, "\n");
11281 }
11282 cpu_fprintf(f, "CR ");
11283 for (i = 0; i < 8; i++)
11284 cpu_fprintf(f, "%01x", env->crf[i]);
11285 cpu_fprintf(f, " [");
11286 for (i = 0; i < 8; i++) {
11287 char a = '-';
11288 if (env->crf[i] & 0x08)
11289 a = 'L';
11290 else if (env->crf[i] & 0x04)
11291 a = 'G';
11292 else if (env->crf[i] & 0x02)
11293 a = 'E';
11294 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11295 }
11296 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11297 env->reserve_addr);
11298 for (i = 0; i < 32; i++) {
11299 if ((i & (RFPL - 1)) == 0)
11300 cpu_fprintf(f, "FPR%02d", i);
11301 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11302 if ((i & (RFPL - 1)) == (RFPL - 1))
11303 cpu_fprintf(f, "\n");
11304 }
11305 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11306 #if !defined(CONFIG_USER_ONLY)
11307 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11308 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11309 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11310 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11311
11312 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11313 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11314 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11315 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11316
11317 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11318 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11319 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11320 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11321
11322 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11323 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11324 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11325 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11326 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11327
11328 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11329 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11330 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11331 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11332
11333 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11334 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11335 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11336 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11337
11338 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11339 " EPR " TARGET_FMT_lx "\n",
11340 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11341 env->spr[SPR_BOOKE_EPR]);
11342
11343 /* FSL-specific */
11344 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11345 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11346 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11347 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11348
11349 /*
11350 * IVORs are left out as they are large and do not change often --
11351 * they can be read with "p $ivor0", "p $ivor1", etc.
11352 */
11353 }
11354
11355 #if defined(TARGET_PPC64)
11356 if (env->flags & POWERPC_FLAG_CFAR) {
11357 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11358 }
11359 #endif
11360
11361 switch (env->mmu_model) {
11362 case POWERPC_MMU_32B:
11363 case POWERPC_MMU_601:
11364 case POWERPC_MMU_SOFT_6xx:
11365 case POWERPC_MMU_SOFT_74xx:
11366 #if defined(TARGET_PPC64)
11367 case POWERPC_MMU_64B:
11368 case POWERPC_MMU_2_03:
11369 case POWERPC_MMU_2_06:
11370 case POWERPC_MMU_2_06a:
11371 case POWERPC_MMU_2_07:
11372 case POWERPC_MMU_2_07a:
11373 #endif
11374 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11375 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11376 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11377 break;
11378 case POWERPC_MMU_BOOKE206:
11379 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11380 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11381 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11382 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11383
11384 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11385 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11386 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11387 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11388
11389 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11390 " TLB1CFG " TARGET_FMT_lx "\n",
11391 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11392 env->spr[SPR_BOOKE_TLB1CFG]);
11393 break;
11394 default:
11395 break;
11396 }
11397 #endif
11398
11399 #undef RGPL
11400 #undef RFPL
11401 }
11402
11403 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11404 fprintf_function cpu_fprintf, int flags)
11405 {
11406 #if defined(DO_PPC_STATISTICS)
11407 PowerPCCPU *cpu = POWERPC_CPU(cs);
11408 opc_handler_t **t1, **t2, **t3, *handler;
11409 int op1, op2, op3;
11410
11411 t1 = cpu->env.opcodes;
11412 for (op1 = 0; op1 < 64; op1++) {
11413 handler = t1[op1];
11414 if (is_indirect_opcode(handler)) {
11415 t2 = ind_table(handler);
11416 for (op2 = 0; op2 < 32; op2++) {
11417 handler = t2[op2];
11418 if (is_indirect_opcode(handler)) {
11419 t3 = ind_table(handler);
11420 for (op3 = 0; op3 < 32; op3++) {
11421 handler = t3[op3];
11422 if (handler->count == 0)
11423 continue;
11424 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11425 "%016" PRIx64 " %" PRId64 "\n",
11426 op1, op2, op3, op1, (op3 << 5) | op2,
11427 handler->oname,
11428 handler->count, handler->count);
11429 }
11430 } else {
11431 if (handler->count == 0)
11432 continue;
11433 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11434 "%016" PRIx64 " %" PRId64 "\n",
11435 op1, op2, op1, op2, handler->oname,
11436 handler->count, handler->count);
11437 }
11438 }
11439 } else {
11440 if (handler->count == 0)
11441 continue;
11442 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11443 " %" PRId64 "\n",
11444 op1, op1, handler->oname,
11445 handler->count, handler->count);
11446 }
11447 }
11448 #endif
11449 }
11450
11451 /*****************************************************************************/
11452 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11453 {
11454 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11455 CPUState *cs = CPU(cpu);
11456 DisasContext ctx, *ctxp = &ctx;
11457 opc_handler_t **table, *handler;
11458 target_ulong pc_start;
11459 int num_insns;
11460 int max_insns;
11461
11462 pc_start = tb->pc;
11463 ctx.nip = pc_start;
11464 ctx.tb = tb;
11465 ctx.exception = POWERPC_EXCP_NONE;
11466 ctx.spr_cb = env->spr_cb;
11467 ctx.pr = msr_pr;
11468 ctx.hv = !msr_pr && msr_hv;
11469 ctx.mem_idx = env->mmu_idx;
11470 ctx.insns_flags = env->insns_flags;
11471 ctx.insns_flags2 = env->insns_flags2;
11472 ctx.access_type = -1;
11473 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11474 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11475 #if defined(TARGET_PPC64)
11476 ctx.sf_mode = msr_is_64bit(env, env->msr);
11477 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11478 #endif
11479 ctx.fpu_enabled = msr_fp;
11480 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11481 ctx.spe_enabled = msr_spe;
11482 else
11483 ctx.spe_enabled = 0;
11484 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11485 ctx.altivec_enabled = msr_vr;
11486 else
11487 ctx.altivec_enabled = 0;
11488 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11489 ctx.vsx_enabled = msr_vsx;
11490 } else {
11491 ctx.vsx_enabled = 0;
11492 }
11493 #if defined(TARGET_PPC64)
11494 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11495 ctx.tm_enabled = msr_tm;
11496 } else {
11497 ctx.tm_enabled = 0;
11498 }
11499 #endif
11500 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11501 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11502 else
11503 ctx.singlestep_enabled = 0;
11504 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11505 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11506 if (unlikely(cs->singlestep_enabled)) {
11507 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11508 }
11509 #if defined (DO_SINGLE_STEP) && 0
11510 /* Single step trace mode */
11511 msr_se = 1;
11512 #endif
11513 num_insns = 0;
11514 max_insns = tb->cflags & CF_COUNT_MASK;
11515 if (max_insns == 0) {
11516 max_insns = CF_COUNT_MASK;
11517 }
11518 if (max_insns > TCG_MAX_INSNS) {
11519 max_insns = TCG_MAX_INSNS;
11520 }
11521
11522 gen_tb_start(tb);
11523 tcg_clear_temp_count();
11524 /* Set env in case of segfault during code fetch */
11525 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11526 tcg_gen_insn_start(ctx.nip);
11527 num_insns++;
11528
11529 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11530 gen_debug_exception(ctxp);
11531 /* The address covered by the breakpoint must be included in
11532 [tb->pc, tb->pc + tb->size) in order to for it to be
11533 properly cleared -- thus we increment the PC here so that
11534 the logic setting tb->size below does the right thing. */
11535 ctx.nip += 4;
11536 break;
11537 }
11538
11539 LOG_DISAS("----------------\n");
11540 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11541 ctx.nip, ctx.mem_idx, (int)msr_ir);
11542 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11543 gen_io_start();
11544 if (unlikely(need_byteswap(&ctx))) {
11545 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11546 } else {
11547 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11548 }
11549 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11550 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11551 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11552 ctx.nip += 4;
11553 table = env->opcodes;
11554 handler = table[opc1(ctx.opcode)];
11555 if (is_indirect_opcode(handler)) {
11556 table = ind_table(handler);
11557 handler = table[opc2(ctx.opcode)];
11558 if (is_indirect_opcode(handler)) {
11559 table = ind_table(handler);
11560 handler = table[opc3(ctx.opcode)];
11561 }
11562 }
11563 /* Is opcode *REALLY* valid ? */
11564 if (unlikely(handler->handler == &gen_invalid)) {
11565 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11566 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11567 opc1(ctx.opcode), opc2(ctx.opcode),
11568 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11569 } else {
11570 uint32_t inval;
11571
11572 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11573 inval = handler->inval2;
11574 } else {
11575 inval = handler->inval1;
11576 }
11577
11578 if (unlikely((ctx.opcode & inval) != 0)) {
11579 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11580 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11581 ctx.opcode & inval, opc1(ctx.opcode),
11582 opc2(ctx.opcode), opc3(ctx.opcode),
11583 ctx.opcode, ctx.nip - 4);
11584 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11585 break;
11586 }
11587 }
11588 (*(handler->handler))(&ctx);
11589 #if defined(DO_PPC_STATISTICS)
11590 handler->count++;
11591 #endif
11592 /* Check trace mode exceptions */
11593 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11594 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11595 ctx.exception != POWERPC_SYSCALL &&
11596 ctx.exception != POWERPC_EXCP_TRAP &&
11597 ctx.exception != POWERPC_EXCP_BRANCH)) {
11598 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11599 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11600 (cs->singlestep_enabled) ||
11601 singlestep ||
11602 num_insns >= max_insns)) {
11603 /* if we reach a page boundary or are single stepping, stop
11604 * generation
11605 */
11606 break;
11607 }
11608 if (tcg_check_temp_count()) {
11609 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11610 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11611 ctx.opcode);
11612 exit(1);
11613 }
11614 }
11615 if (tb->cflags & CF_LAST_IO)
11616 gen_io_end();
11617 if (ctx.exception == POWERPC_EXCP_NONE) {
11618 gen_goto_tb(&ctx, 0, ctx.nip);
11619 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11620 if (unlikely(cs->singlestep_enabled)) {
11621 gen_debug_exception(ctxp);
11622 }
11623 /* Generate the return instruction */
11624 tcg_gen_exit_tb(0);
11625 }
11626 gen_tb_end(tb, num_insns);
11627
11628 tb->size = ctx.nip - pc_start;
11629 tb->icount = num_insns;
11630
11631 #if defined(DEBUG_DISAS)
11632 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11633 int flags;
11634 flags = env->bfd_mach;
11635 flags |= ctx.le_mode << 16;
11636 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11637 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11638 qemu_log("\n");
11639 }
11640 #endif
11641 }
11642
11643 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11644 target_ulong *data)
11645 {
11646 env->nip = data[0];
11647 }
AR7 emulation for QEMU