hw/pci: Have safer pcie_bus_realize() by checking error path
[qemu/ar7.git] / linux-user / xtensa / target_syscall.h
blobafc86a153fc04a4113a7324118d3f78b29bb6917
1 #ifndef XTENSA_TARGET_SYSCALL_H
2 #define XTENSA_TARGET_SYSCALL_H
4 #define UNAME_MACHINE "xtensa"
6 #define UNAME_MINIMUM_RELEASE "3.19"
7 #define TARGET_CLONE_BACKWARDS
9 #define MMAP_SHIFT TARGET_PAGE_BITS
11 typedef uint32_t xtensa_reg_t;
12 typedef struct {
13 } xtregs_opt_t; /* TODO */
15 struct target_pt_regs {
16 xtensa_reg_t pc; /* 4 */
17 xtensa_reg_t ps; /* 8 */
18 xtensa_reg_t depc; /* 12 */
19 xtensa_reg_t exccause; /* 16 */
20 xtensa_reg_t excvaddr; /* 20 */
21 xtensa_reg_t debugcause; /* 24 */
22 xtensa_reg_t wmask; /* 28 */
23 xtensa_reg_t lbeg; /* 32 */
24 xtensa_reg_t lend; /* 36 */
25 xtensa_reg_t lcount; /* 40 */
26 xtensa_reg_t sar; /* 44 */
27 xtensa_reg_t windowbase; /* 48 */
28 xtensa_reg_t windowstart; /* 52 */
29 xtensa_reg_t syscall; /* 56 */
30 xtensa_reg_t icountlevel; /* 60 */
31 xtensa_reg_t scompare1; /* 64 */
32 xtensa_reg_t threadptr; /* 68 */
34 /* Additional configurable registers that are used by the compiler. */
35 xtregs_opt_t xtregs_opt;
37 /* Make sure the areg field is 16 bytes aligned. */
38 int align[0] __attribute__ ((aligned(16)));
40 /* current register frame.
41 * Note: The ESF for kernel exceptions ends after 16 registers!
43 xtensa_reg_t areg[16];
46 #define TARGET_MCL_CURRENT 1
47 #define TARGET_MCL_FUTURE 2
48 #define TARGET_MCL_ONFAULT 4
50 #endif