hw/pci: Have safer pcie_bus_realize() by checking error path
[qemu/ar7.git] / linux-user / riscv / target_syscall.h
blobdc597c897222bb7ad5d7a61cc5518b63e1c5169b
1 /*
2 * This struct defines the way the registers are stored on the
3 * stack during a system call.
5 * Reference: linux/arch/riscv/include/uapi/asm/ptrace.h
6 */
8 #ifndef LINUX_USER_RISCV_TARGET_SYSCALL_H
9 #define LINUX_USER_RISCV_TARGET_SYSCALL_H
11 struct target_pt_regs {
12 abi_long sepc;
13 abi_long ra;
14 abi_long sp;
15 abi_long gp;
16 abi_long tp;
17 abi_long t0;
18 abi_long t1;
19 abi_long t2;
20 abi_long s0;
21 abi_long s1;
22 abi_long a0;
23 abi_long a1;
24 abi_long a2;
25 abi_long a3;
26 abi_long a4;
27 abi_long a5;
28 abi_long a6;
29 abi_long a7;
30 abi_long s2;
31 abi_long s3;
32 abi_long s4;
33 abi_long s5;
34 abi_long s6;
35 abi_long s7;
36 abi_long s8;
37 abi_long s9;
38 abi_long s10;
39 abi_long s11;
40 abi_long t3;
41 abi_long t4;
42 abi_long t5;
43 abi_long t6;
46 #ifdef TARGET_RISCV32
47 #define UNAME_MACHINE "riscv32"
48 #else
49 #define UNAME_MACHINE "riscv64"
50 #endif
51 #define UNAME_MINIMUM_RELEASE "4.15.0"
53 #define TARGET_MINSIGSTKSZ 2048
54 #define TARGET_MCL_CURRENT 1
55 #define TARGET_MCL_FUTURE 2
56 #define TARGET_MCL_ONFAULT 4
58 /* clone(flags, newsp, ptidptr, tls, ctidptr) for RISC-V */
59 /* This comes from linux/kernel/fork.c, CONFIG_CLONE_BACKWARDS */
60 #define TARGET_CLONE_BACKWARDS
62 #endif