4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
30 #include "semihosting/semihost.h"
31 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "translate-a64.h"
37 #include "qemu/atomic128.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
45 static const char *regnames
[] = {
46 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
47 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
48 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
49 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
53 A64_SHIFT_TYPE_LSL
= 0,
54 A64_SHIFT_TYPE_LSR
= 1,
55 A64_SHIFT_TYPE_ASR
= 2,
56 A64_SHIFT_TYPE_ROR
= 3
59 /* Table based decoder typedefs - used when the relevant bits for decode
60 * are too awkwardly scattered across the instruction (eg SIMD).
62 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
64 typedef struct AArch64DecodeTable
{
67 AArch64DecodeFn
*disas_fn
;
70 /* initialize TCG globals. */
71 void a64_translate_init(void)
75 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
76 offsetof(CPUARMState
, pc
),
78 for (i
= 0; i
< 32; i
++) {
79 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
80 offsetof(CPUARMState
, xregs
[i
]),
84 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
85 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
89 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
91 static int get_a64_user_mem_index(DisasContext
*s
)
94 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
95 * which is the usual mmu_idx for this cpu state.
97 ARMMMUIdx useridx
= s
->mmu_idx
;
101 * We have pre-computed the condition for AccType_UNPRIV.
102 * Therefore we should never get here with a mmu_idx for
103 * which we do not know the corresponding user mmu_idx.
106 case ARMMMUIdx_E10_1
:
107 case ARMMMUIdx_E10_1_PAN
:
108 useridx
= ARMMMUIdx_E10_0
;
110 case ARMMMUIdx_E20_2
:
111 case ARMMMUIdx_E20_2_PAN
:
112 useridx
= ARMMMUIdx_E20_0
;
115 g_assert_not_reached();
118 return arm_to_core_mmu_idx(useridx
);
121 static void set_btype_raw(int val
)
123 tcg_gen_st_i32(tcg_constant_i32(val
), cpu_env
,
124 offsetof(CPUARMState
, btype
));
127 static void set_btype(DisasContext
*s
, int val
)
129 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
130 tcg_debug_assert(val
>= 1 && val
<= 3);
135 static void reset_btype(DisasContext
*s
)
143 void gen_a64_update_pc(DisasContext
*s
, target_long diff
)
145 tcg_gen_movi_i64(cpu_pc
, s
->pc_curr
+ diff
);
149 * Handle Top Byte Ignore (TBI) bits.
151 * If address tagging is enabled via the TCR TBI bits:
152 * + for EL2 and EL3 there is only one TBI bit, and if it is set
153 * then the address is zero-extended, clearing bits [63:56]
154 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
155 * and TBI1 controls addressses with bit 55 == 1.
156 * If the appropriate TBI bit is set for the address then
157 * the address is sign-extended from bit 55 into bits [63:56]
159 * Here We have concatenated TBI{1,0} into tbi.
161 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
162 TCGv_i64 src
, int tbi
)
165 /* Load unmodified address */
166 tcg_gen_mov_i64(dst
, src
);
167 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
168 /* Force tag byte to all zero */
169 tcg_gen_extract_i64(dst
, src
, 0, 56);
171 /* Sign-extend from bit 55. */
172 tcg_gen_sextract_i64(dst
, src
, 0, 56);
176 /* tbi0 but !tbi1: only use the extension if positive */
177 tcg_gen_and_i64(dst
, dst
, src
);
180 /* !tbi0 but tbi1: only use the extension if negative */
181 tcg_gen_or_i64(dst
, dst
, src
);
184 /* tbi0 and tbi1: always use the extension */
187 g_assert_not_reached();
192 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
195 * If address tagging is enabled for instructions via the TCR TBI bits,
196 * then loading an address into the PC will clear out any tag.
198 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
202 * Handle MTE and/or TBI.
204 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
205 * for the tag to be present in the FAR_ELx register. But for user-only
206 * mode we do not have a TLB with which to implement this, so we must
207 * remove the top byte now.
209 * Always return a fresh temporary that we can increment independently
210 * of the write-back address.
213 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
215 TCGv_i64 clean
= new_tmp_a64(s
);
216 #ifdef CONFIG_USER_ONLY
217 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
219 tcg_gen_mov_i64(clean
, addr
);
224 /* Insert a zero tag into src, with the result at dst. */
225 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
227 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
230 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
231 MMUAccessType acc
, int log2_size
)
233 gen_helper_probe_access(cpu_env
, ptr
,
234 tcg_constant_i32(acc
),
235 tcg_constant_i32(get_mem_index(s
)),
236 tcg_constant_i32(1 << log2_size
));
240 * For MTE, check a single logical or atomic access. This probes a single
241 * address, the exact one specified. The size and alignment of the access
242 * is not relevant to MTE, per se, but watchpoints do require the size,
243 * and we want to recognize those before making any other changes to state.
245 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
246 bool is_write
, bool tag_checked
,
247 int log2_size
, bool is_unpriv
,
250 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
254 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
255 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
256 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
257 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
258 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
260 ret
= new_tmp_a64(s
);
261 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
265 return clean_data_tbi(s
, addr
);
268 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
269 bool tag_checked
, int log2_size
)
271 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
272 false, get_mem_index(s
));
276 * For MTE, check multiple logical sequential accesses.
278 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
279 bool tag_checked
, int size
)
281 if (tag_checked
&& s
->mte_active
[0]) {
285 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
286 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
287 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
288 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
289 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
291 ret
= new_tmp_a64(s
);
292 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
296 return clean_data_tbi(s
, addr
);
299 typedef struct DisasCompare64
{
304 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
308 arm_test_cc(&c32
, cc
);
310 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
311 * properly. The NE/EQ comparisons are also fine with this choice. */
312 c64
->cond
= c32
.cond
;
313 c64
->value
= tcg_temp_new_i64();
314 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
319 static void a64_free_cc(DisasCompare64
*c64
)
321 tcg_temp_free_i64(c64
->value
);
324 static void gen_rebuild_hflags(DisasContext
*s
)
326 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_constant_i32(s
->current_el
));
329 static void gen_exception_internal(int excp
)
331 assert(excp_is_internal(excp
));
332 gen_helper_exception_internal(cpu_env
, tcg_constant_i32(excp
));
335 static void gen_exception_internal_insn(DisasContext
*s
, int excp
)
337 gen_a64_update_pc(s
, 0);
338 gen_exception_internal(excp
);
339 s
->base
.is_jmp
= DISAS_NORETURN
;
342 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
344 gen_a64_update_pc(s
, 0);
345 gen_helper_exception_bkpt_insn(cpu_env
, tcg_constant_i32(syndrome
));
346 s
->base
.is_jmp
= DISAS_NORETURN
;
349 static void gen_step_complete_exception(DisasContext
*s
)
351 /* We just completed step of an insn. Move from Active-not-pending
352 * to Active-pending, and then also take the swstep exception.
353 * This corresponds to making the (IMPDEF) choice to prioritize
354 * swstep exceptions over asynchronous exceptions taken to an exception
355 * level where debug is disabled. This choice has the advantage that
356 * we do not need to maintain internal state corresponding to the
357 * ISV/EX syndrome bits between completion of the step and generation
358 * of the exception, and our syndrome information is always correct.
361 gen_swstep_exception(s
, 1, s
->is_ldex
);
362 s
->base
.is_jmp
= DISAS_NORETURN
;
365 static inline bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
370 return translator_use_goto_tb(&s
->base
, dest
);
373 static void gen_goto_tb(DisasContext
*s
, int n
, int64_t diff
)
375 uint64_t dest
= s
->pc_curr
+ diff
;
377 if (use_goto_tb(s
, dest
)) {
379 gen_a64_update_pc(s
, diff
);
380 tcg_gen_exit_tb(s
->base
.tb
, n
);
381 s
->base
.is_jmp
= DISAS_NORETURN
;
383 gen_a64_update_pc(s
, diff
);
385 gen_step_complete_exception(s
);
387 tcg_gen_lookup_and_goto_ptr();
388 s
->base
.is_jmp
= DISAS_NORETURN
;
393 static void init_tmp_a64_array(DisasContext
*s
)
395 #ifdef CONFIG_DEBUG_TCG
396 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
398 s
->tmp_a64_count
= 0;
401 static void free_tmp_a64(DisasContext
*s
)
404 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
405 tcg_temp_free_i64(s
->tmp_a64
[i
]);
407 init_tmp_a64_array(s
);
410 TCGv_i64
new_tmp_a64(DisasContext
*s
)
412 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
413 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
416 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
418 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
419 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
422 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
424 TCGv_i64 t
= new_tmp_a64(s
);
425 tcg_gen_movi_i64(t
, 0);
430 * Register access functions
432 * These functions are used for directly accessing a register in where
433 * changes to the final register value are likely to be made. If you
434 * need to use a register for temporary calculation (e.g. index type
435 * operations) use the read_* form.
437 * B1.2.1 Register mappings
439 * In instruction register encoding 31 can refer to ZR (zero register) or
440 * the SP (stack pointer) depending on context. In QEMU's case we map SP
441 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
442 * This is the point of the _sp forms.
444 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
447 return new_tmp_a64_zero(s
);
453 /* register access for when 31 == SP */
454 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
459 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
460 * representing the register contents. This TCGv is an auto-freed
461 * temporary so it need not be explicitly freed, and may be modified.
463 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
465 TCGv_i64 v
= new_tmp_a64(s
);
468 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
470 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
473 tcg_gen_movi_i64(v
, 0);
478 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
480 TCGv_i64 v
= new_tmp_a64(s
);
482 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
484 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
489 /* Return the offset into CPUARMState of a slice (from
490 * the least significant end) of FP register Qn (ie
492 * (Note that this is not the same mapping as for A32; see cpu.h)
494 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
496 return vec_reg_offset(s
, regno
, 0, size
);
499 /* Offset of the high half of the 128 bit vector Qn */
500 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
502 return vec_reg_offset(s
, regno
, 1, MO_64
);
505 /* Convenience accessors for reading and writing single and double
506 * FP registers. Writing clears the upper parts of the associated
507 * 128 bit vector register, as required by the architecture.
508 * Note that unlike the GP register accessors, the values returned
509 * by the read functions must be manually freed.
511 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
513 TCGv_i64 v
= tcg_temp_new_i64();
515 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
519 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
521 TCGv_i32 v
= tcg_temp_new_i32();
523 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
527 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
529 TCGv_i32 v
= tcg_temp_new_i32();
531 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
535 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
536 * If SVE is not enabled, then there are only 128 bits in the vector.
538 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
540 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
541 unsigned vsz
= vec_full_reg_size(s
);
543 /* Nop move, with side effect of clearing the tail. */
544 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
547 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
549 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
551 tcg_gen_st_i64(v
, cpu_env
, ofs
);
552 clear_vec_high(s
, false, reg
);
555 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
557 TCGv_i64 tmp
= tcg_temp_new_i64();
559 tcg_gen_extu_i32_i64(tmp
, v
);
560 write_fp_dreg(s
, reg
, tmp
);
561 tcg_temp_free_i64(tmp
);
564 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
565 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
566 GVecGen2Fn
*gvec_fn
, int vece
)
568 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
569 is_q
? 16 : 8, vec_full_reg_size(s
));
572 /* Expand a 2-operand + immediate AdvSIMD vector operation using
573 * an expander function.
575 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
576 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
578 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
579 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
582 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
583 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
584 GVecGen3Fn
*gvec_fn
, int vece
)
586 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
587 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
590 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
591 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
592 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
594 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
595 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
596 is_q
? 16 : 8, vec_full_reg_size(s
));
599 /* Expand a 2-operand operation using an out-of-line helper. */
600 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
601 int rn
, int data
, gen_helper_gvec_2
*fn
)
603 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
604 vec_full_reg_offset(s
, rn
),
605 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
608 /* Expand a 3-operand operation using an out-of-line helper. */
609 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
610 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
612 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
613 vec_full_reg_offset(s
, rn
),
614 vec_full_reg_offset(s
, rm
),
615 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
618 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
619 * an out-of-line helper.
621 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
622 int rm
, bool is_fp16
, int data
,
623 gen_helper_gvec_3_ptr
*fn
)
625 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
626 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
627 vec_full_reg_offset(s
, rn
),
628 vec_full_reg_offset(s
, rm
), fpst
,
629 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
630 tcg_temp_free_ptr(fpst
);
633 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
634 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
635 int rm
, gen_helper_gvec_3_ptr
*fn
)
637 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
639 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
640 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
641 vec_full_reg_offset(s
, rn
),
642 vec_full_reg_offset(s
, rm
), qc_ptr
,
643 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
644 tcg_temp_free_ptr(qc_ptr
);
647 /* Expand a 4-operand operation using an out-of-line helper. */
648 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
649 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
651 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
652 vec_full_reg_offset(s
, rn
),
653 vec_full_reg_offset(s
, rm
),
654 vec_full_reg_offset(s
, ra
),
655 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
659 * Expand a 4-operand + fpstatus pointer + simd data value operation using
660 * an out-of-line helper.
662 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
663 int rm
, int ra
, bool is_fp16
, int data
,
664 gen_helper_gvec_4_ptr
*fn
)
666 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
667 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
668 vec_full_reg_offset(s
, rn
),
669 vec_full_reg_offset(s
, rm
),
670 vec_full_reg_offset(s
, ra
), fpst
,
671 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
672 tcg_temp_free_ptr(fpst
);
675 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
676 * than the 32 bit equivalent.
678 static inline void gen_set_NZ64(TCGv_i64 result
)
680 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
681 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
684 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
685 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
688 gen_set_NZ64(result
);
690 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
691 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
693 tcg_gen_movi_i32(cpu_CF
, 0);
694 tcg_gen_movi_i32(cpu_VF
, 0);
697 /* dest = T0 + T1; compute C, N, V and Z flags */
698 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
701 TCGv_i64 result
, flag
, tmp
;
702 result
= tcg_temp_new_i64();
703 flag
= tcg_temp_new_i64();
704 tmp
= tcg_temp_new_i64();
706 tcg_gen_movi_i64(tmp
, 0);
707 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
709 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
711 gen_set_NZ64(result
);
713 tcg_gen_xor_i64(flag
, result
, t0
);
714 tcg_gen_xor_i64(tmp
, t0
, t1
);
715 tcg_gen_andc_i64(flag
, flag
, tmp
);
716 tcg_temp_free_i64(tmp
);
717 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
719 tcg_gen_mov_i64(dest
, result
);
720 tcg_temp_free_i64(result
);
721 tcg_temp_free_i64(flag
);
723 /* 32 bit arithmetic */
724 TCGv_i32 t0_32
= tcg_temp_new_i32();
725 TCGv_i32 t1_32
= tcg_temp_new_i32();
726 TCGv_i32 tmp
= tcg_temp_new_i32();
728 tcg_gen_movi_i32(tmp
, 0);
729 tcg_gen_extrl_i64_i32(t0_32
, t0
);
730 tcg_gen_extrl_i64_i32(t1_32
, t1
);
731 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
732 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
733 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
734 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
735 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
736 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
738 tcg_temp_free_i32(tmp
);
739 tcg_temp_free_i32(t0_32
);
740 tcg_temp_free_i32(t1_32
);
744 /* dest = T0 - T1; compute C, N, V and Z flags */
745 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 /* 64 bit arithmetic */
749 TCGv_i64 result
, flag
, tmp
;
751 result
= tcg_temp_new_i64();
752 flag
= tcg_temp_new_i64();
753 tcg_gen_sub_i64(result
, t0
, t1
);
755 gen_set_NZ64(result
);
757 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
758 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
760 tcg_gen_xor_i64(flag
, result
, t0
);
761 tmp
= tcg_temp_new_i64();
762 tcg_gen_xor_i64(tmp
, t0
, t1
);
763 tcg_gen_and_i64(flag
, flag
, tmp
);
764 tcg_temp_free_i64(tmp
);
765 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
766 tcg_gen_mov_i64(dest
, result
);
767 tcg_temp_free_i64(flag
);
768 tcg_temp_free_i64(result
);
770 /* 32 bit arithmetic */
771 TCGv_i32 t0_32
= tcg_temp_new_i32();
772 TCGv_i32 t1_32
= tcg_temp_new_i32();
775 tcg_gen_extrl_i64_i32(t0_32
, t0
);
776 tcg_gen_extrl_i64_i32(t1_32
, t1
);
777 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
778 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
779 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
780 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
781 tmp
= tcg_temp_new_i32();
782 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
783 tcg_temp_free_i32(t0_32
);
784 tcg_temp_free_i32(t1_32
);
785 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
786 tcg_temp_free_i32(tmp
);
787 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
791 /* dest = T0 + T1 + CF; do not compute flags. */
792 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
794 TCGv_i64 flag
= tcg_temp_new_i64();
795 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
796 tcg_gen_add_i64(dest
, t0
, t1
);
797 tcg_gen_add_i64(dest
, dest
, flag
);
798 tcg_temp_free_i64(flag
);
801 tcg_gen_ext32u_i64(dest
, dest
);
805 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
806 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
809 TCGv_i64 result
= tcg_temp_new_i64();
810 TCGv_i64 cf_64
= tcg_temp_new_i64();
811 TCGv_i64 vf_64
= tcg_temp_new_i64();
812 TCGv_i64 tmp
= tcg_temp_new_i64();
813 TCGv_i64 zero
= tcg_constant_i64(0);
815 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
816 tcg_gen_add2_i64(result
, cf_64
, t0
, zero
, cf_64
, zero
);
817 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, zero
);
818 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
819 gen_set_NZ64(result
);
821 tcg_gen_xor_i64(vf_64
, result
, t0
);
822 tcg_gen_xor_i64(tmp
, t0
, t1
);
823 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
824 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
826 tcg_gen_mov_i64(dest
, result
);
828 tcg_temp_free_i64(tmp
);
829 tcg_temp_free_i64(vf_64
);
830 tcg_temp_free_i64(cf_64
);
831 tcg_temp_free_i64(result
);
833 TCGv_i32 t0_32
= tcg_temp_new_i32();
834 TCGv_i32 t1_32
= tcg_temp_new_i32();
835 TCGv_i32 tmp
= tcg_temp_new_i32();
836 TCGv_i32 zero
= tcg_constant_i32(0);
838 tcg_gen_extrl_i64_i32(t0_32
, t0
);
839 tcg_gen_extrl_i64_i32(t1_32
, t1
);
840 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, zero
, cpu_CF
, zero
);
841 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, zero
);
843 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
844 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
845 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
846 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
847 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
849 tcg_temp_free_i32(tmp
);
850 tcg_temp_free_i32(t1_32
);
851 tcg_temp_free_i32(t0_32
);
856 * Load/Store generators
860 * Store from GPR register to memory.
862 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
863 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
865 unsigned int iss_srt
,
866 bool iss_sf
, bool iss_ar
)
868 memop
= finalize_memop(s
, memop
);
869 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
874 syn
= syn_data_abort_with_iss(0,
880 0, 0, 0, 0, 0, false);
881 disas_set_insn_syndrome(s
, syn
);
885 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
886 TCGv_i64 tcg_addr
, MemOp memop
,
888 unsigned int iss_srt
,
889 bool iss_sf
, bool iss_ar
)
891 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
892 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
896 * Load from memory to GPR register
898 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
899 MemOp memop
, bool extend
, int memidx
,
900 bool iss_valid
, unsigned int iss_srt
,
901 bool iss_sf
, bool iss_ar
)
903 memop
= finalize_memop(s
, memop
);
904 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
906 if (extend
&& (memop
& MO_SIGN
)) {
907 g_assert((memop
& MO_SIZE
) <= MO_32
);
908 tcg_gen_ext32u_i64(dest
, dest
);
914 syn
= syn_data_abort_with_iss(0,
916 (memop
& MO_SIGN
) != 0,
920 0, 0, 0, 0, 0, false);
921 disas_set_insn_syndrome(s
, syn
);
925 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
926 MemOp memop
, bool extend
,
927 bool iss_valid
, unsigned int iss_srt
,
928 bool iss_sf
, bool iss_ar
)
930 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
931 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
935 * Store from FP register to memory
937 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
939 /* This writes the bottom N bits of a 128 bit wide vector to memory */
940 TCGv_i64 tmplo
= tcg_temp_new_i64();
943 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
946 mop
= finalize_memop(s
, size
);
947 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
949 bool be
= s
->be_data
== MO_BE
;
950 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
951 TCGv_i64 tmphi
= tcg_temp_new_i64();
953 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
955 mop
= s
->be_data
| MO_UQ
;
956 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
957 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
958 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
959 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
960 get_mem_index(s
), mop
);
962 tcg_temp_free_i64(tcg_hiaddr
);
963 tcg_temp_free_i64(tmphi
);
966 tcg_temp_free_i64(tmplo
);
970 * Load from memory to FP register
972 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
974 /* This always zero-extends and writes to a full 128 bit wide vector */
975 TCGv_i64 tmplo
= tcg_temp_new_i64();
976 TCGv_i64 tmphi
= NULL
;
980 mop
= finalize_memop(s
, size
);
981 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
983 bool be
= s
->be_data
== MO_BE
;
986 tmphi
= tcg_temp_new_i64();
987 tcg_hiaddr
= tcg_temp_new_i64();
989 mop
= s
->be_data
| MO_UQ
;
990 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
991 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
992 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
993 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
994 get_mem_index(s
), mop
);
995 tcg_temp_free_i64(tcg_hiaddr
);
998 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
999 tcg_temp_free_i64(tmplo
);
1002 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1003 tcg_temp_free_i64(tmphi
);
1005 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1009 * Vector load/store helpers.
1011 * The principal difference between this and a FP load is that we don't
1012 * zero extend as we are filling a partial chunk of the vector register.
1013 * These functions don't support 128 bit loads/stores, which would be
1014 * normal load/store operations.
1016 * The _i32 versions are useful when operating on 32 bit quantities
1017 * (eg for floating point single or using Neon helper functions).
1020 /* Get value of an element within a vector register */
1021 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1022 int element
, MemOp memop
)
1024 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1025 switch ((unsigned)memop
) {
1027 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1030 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1033 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1036 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1039 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1042 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1046 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1049 g_assert_not_reached();
1053 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1054 int element
, MemOp memop
)
1056 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1059 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1062 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1065 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1068 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1072 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1075 g_assert_not_reached();
1079 /* Set value of an element within a vector register */
1080 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1081 int element
, MemOp memop
)
1083 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1086 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1089 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1092 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1095 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1098 g_assert_not_reached();
1102 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1103 int destidx
, int element
, MemOp memop
)
1105 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1108 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1111 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1114 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1117 g_assert_not_reached();
1121 /* Store from vector register to memory */
1122 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1123 TCGv_i64 tcg_addr
, MemOp mop
)
1125 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1127 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1128 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1130 tcg_temp_free_i64(tcg_tmp
);
1133 /* Load from memory to vector register */
1134 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1135 TCGv_i64 tcg_addr
, MemOp mop
)
1137 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1139 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1140 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1142 tcg_temp_free_i64(tcg_tmp
);
1145 /* Check that FP/Neon access is enabled. If it is, return
1146 * true. If not, emit code to generate an appropriate exception,
1147 * and return false; the caller should not emit any code for
1148 * the instruction. Note that this check must happen after all
1149 * unallocated-encoding checks (otherwise the syndrome information
1150 * for the resulting exception will be incorrect).
1152 static bool fp_access_check_only(DisasContext
*s
)
1154 if (s
->fp_excp_el
) {
1155 assert(!s
->fp_access_checked
);
1156 s
->fp_access_checked
= true;
1158 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1159 syn_fp_access_trap(1, 0xe, false, 0),
1163 s
->fp_access_checked
= true;
1167 static bool fp_access_check(DisasContext
*s
)
1169 if (!fp_access_check_only(s
)) {
1172 if (s
->sme_trap_nonstreaming
&& s
->is_nonstreaming
) {
1173 gen_exception_insn(s
, 0, EXCP_UDEF
,
1174 syn_smetrap(SME_ET_Streaming
, false));
1181 * Check that SVE access is enabled. If it is, return true.
1182 * If not, emit code to generate an appropriate exception and return false.
1183 * This function corresponds to CheckSVEEnabled().
1185 bool sve_access_check(DisasContext
*s
)
1187 if (s
->pstate_sm
|| !dc_isar_feature(aa64_sve
, s
)) {
1188 assert(dc_isar_feature(aa64_sme
, s
));
1189 if (!sme_sm_enabled_check(s
)) {
1192 } else if (s
->sve_excp_el
) {
1193 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1194 syn_sve_access_trap(), s
->sve_excp_el
);
1197 s
->sve_access_checked
= true;
1198 return fp_access_check(s
);
1201 /* Assert that we only raise one exception per instruction. */
1202 assert(!s
->sve_access_checked
);
1203 s
->sve_access_checked
= true;
1208 * Check that SME access is enabled, raise an exception if not.
1209 * Note that this function corresponds to CheckSMEAccess and is
1210 * only used directly for cpregs.
1212 static bool sme_access_check(DisasContext
*s
)
1214 if (s
->sme_excp_el
) {
1215 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1216 syn_smetrap(SME_ET_AccessTrap
, false),
1223 /* This function corresponds to CheckSMEEnabled. */
1224 bool sme_enabled_check(DisasContext
*s
)
1227 * Note that unlike sve_excp_el, we have not constrained sme_excp_el
1228 * to be zero when fp_excp_el has priority. This is because we need
1229 * sme_excp_el by itself for cpregs access checks.
1231 if (!s
->fp_excp_el
|| s
->sme_excp_el
< s
->fp_excp_el
) {
1232 s
->fp_access_checked
= true;
1233 return sme_access_check(s
);
1235 return fp_access_check_only(s
);
1238 /* Common subroutine for CheckSMEAnd*Enabled. */
1239 bool sme_enabled_check_with_svcr(DisasContext
*s
, unsigned req
)
1241 if (!sme_enabled_check(s
)) {
1244 if (FIELD_EX64(req
, SVCR
, SM
) && !s
->pstate_sm
) {
1245 gen_exception_insn(s
, 0, EXCP_UDEF
,
1246 syn_smetrap(SME_ET_NotStreaming
, false));
1249 if (FIELD_EX64(req
, SVCR
, ZA
) && !s
->pstate_za
) {
1250 gen_exception_insn(s
, 0, EXCP_UDEF
,
1251 syn_smetrap(SME_ET_InactiveZA
, false));
1258 * This utility function is for doing register extension with an
1259 * optional shift. You will likely want to pass a temporary for the
1260 * destination register. See DecodeRegExtend() in the ARM ARM.
1262 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1263 int option
, unsigned int shift
)
1265 int extsize
= extract32(option
, 0, 2);
1266 bool is_signed
= extract32(option
, 2, 1);
1271 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1274 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1277 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1280 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1286 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1289 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1292 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1295 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1301 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1305 static inline void gen_check_sp_alignment(DisasContext
*s
)
1307 /* The AArch64 architecture mandates that (if enabled via PSTATE
1308 * or SCTLR bits) there is a check that SP is 16-aligned on every
1309 * SP-relative load or store (with an exception generated if it is not).
1310 * In line with general QEMU practice regarding misaligned accesses,
1311 * we omit these checks for the sake of guest program performance.
1312 * This function is provided as a hook so we can more easily add these
1313 * checks in future (possibly as a "favour catching guest program bugs
1314 * over speed" user selectable option).
1319 * This provides a simple table based table lookup decoder. It is
1320 * intended to be used when the relevant bits for decode are too
1321 * awkwardly placed and switch/if based logic would be confusing and
1322 * deeply nested. Since it's a linear search through the table, tables
1323 * should be kept small.
1325 * It returns the first handler where insn & mask == pattern, or
1326 * NULL if there is no match.
1327 * The table is terminated by an empty mask (i.e. 0)
1329 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1332 const AArch64DecodeTable
*tptr
= table
;
1334 while (tptr
->mask
) {
1335 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1336 return tptr
->disas_fn
;
1344 * The instruction disassembly implemented here matches
1345 * the instruction encoding classifications in chapter C4
1346 * of the ARM Architecture Reference Manual (DDI0487B_a);
1347 * classification names and decode diagrams here should generally
1348 * match up with those in the manual.
1351 /* Unconditional branch (immediate)
1353 * +----+-----------+-------------------------------------+
1354 * | op | 0 0 1 0 1 | imm26 |
1355 * +----+-----------+-------------------------------------+
1357 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1359 int64_t diff
= sextract32(insn
, 0, 26) * 4;
1361 if (insn
& (1U << 31)) {
1362 /* BL Branch with link */
1363 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1366 /* B Branch / BL Branch with link */
1368 gen_goto_tb(s
, 0, diff
);
1371 /* Compare and branch (immediate)
1372 * 31 30 25 24 23 5 4 0
1373 * +----+-------------+----+---------------------+--------+
1374 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1375 * +----+-------------+----+---------------------+--------+
1377 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1379 unsigned int sf
, op
, rt
;
1381 TCGLabel
*label_match
;
1384 sf
= extract32(insn
, 31, 1);
1385 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1386 rt
= extract32(insn
, 0, 5);
1387 diff
= sextract32(insn
, 5, 19) * 4;
1389 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1390 label_match
= gen_new_label();
1393 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1394 tcg_cmp
, 0, label_match
);
1396 gen_goto_tb(s
, 0, 4);
1397 gen_set_label(label_match
);
1398 gen_goto_tb(s
, 1, diff
);
1401 /* Test and branch (immediate)
1402 * 31 30 25 24 23 19 18 5 4 0
1403 * +----+-------------+----+-------+-------------+------+
1404 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1405 * +----+-------------+----+-------+-------------+------+
1407 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1409 unsigned int bit_pos
, op
, rt
;
1411 TCGLabel
*label_match
;
1414 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1415 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1416 diff
= sextract32(insn
, 5, 14) * 4;
1417 rt
= extract32(insn
, 0, 5);
1419 tcg_cmp
= tcg_temp_new_i64();
1420 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1421 label_match
= gen_new_label();
1424 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1425 tcg_cmp
, 0, label_match
);
1426 tcg_temp_free_i64(tcg_cmp
);
1427 gen_goto_tb(s
, 0, 4);
1428 gen_set_label(label_match
);
1429 gen_goto_tb(s
, 1, diff
);
1432 /* Conditional branch (immediate)
1433 * 31 25 24 23 5 4 3 0
1434 * +---------------+----+---------------------+----+------+
1435 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1436 * +---------------+----+---------------------+----+------+
1438 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1443 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1444 unallocated_encoding(s
);
1447 diff
= sextract32(insn
, 5, 19) * 4;
1448 cond
= extract32(insn
, 0, 4);
1452 /* genuinely conditional branches */
1453 TCGLabel
*label_match
= gen_new_label();
1454 arm_gen_test_cc(cond
, label_match
);
1455 gen_goto_tb(s
, 0, 4);
1456 gen_set_label(label_match
);
1457 gen_goto_tb(s
, 1, diff
);
1459 /* 0xe and 0xf are both "always" conditions */
1460 gen_goto_tb(s
, 0, diff
);
1464 /* HINT instruction group, including various allocated HINTs */
1465 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1466 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1468 unsigned int selector
= crm
<< 3 | op2
;
1471 unallocated_encoding(s
);
1476 case 0b00000: /* NOP */
1478 case 0b00011: /* WFI */
1479 s
->base
.is_jmp
= DISAS_WFI
;
1481 case 0b00001: /* YIELD */
1482 /* When running in MTTCG we don't generate jumps to the yield and
1483 * WFE helpers as it won't affect the scheduling of other vCPUs.
1484 * If we wanted to more completely model WFE/SEV so we don't busy
1485 * spin unnecessarily we would need to do something more involved.
1487 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1488 s
->base
.is_jmp
= DISAS_YIELD
;
1491 case 0b00010: /* WFE */
1492 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1493 s
->base
.is_jmp
= DISAS_WFE
;
1496 case 0b00100: /* SEV */
1497 case 0b00101: /* SEVL */
1498 case 0b00110: /* DGH */
1499 /* we treat all as NOP at least for now */
1501 case 0b00111: /* XPACLRI */
1502 if (s
->pauth_active
) {
1503 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1506 case 0b01000: /* PACIA1716 */
1507 if (s
->pauth_active
) {
1508 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1511 case 0b01010: /* PACIB1716 */
1512 if (s
->pauth_active
) {
1513 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1516 case 0b01100: /* AUTIA1716 */
1517 if (s
->pauth_active
) {
1518 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1521 case 0b01110: /* AUTIB1716 */
1522 if (s
->pauth_active
) {
1523 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1526 case 0b10000: /* ESB */
1527 /* Without RAS, we must implement this as NOP. */
1528 if (dc_isar_feature(aa64_ras
, s
)) {
1530 * QEMU does not have a source of physical SErrors,
1531 * so we are only concerned with virtual SErrors.
1532 * The pseudocode in the ARM for this case is
1533 * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
1534 * AArch64.vESBOperation();
1535 * Most of the condition can be evaluated at translation time.
1536 * Test for EL2 present, and defer test for SEL2 to runtime.
1538 if (s
->current_el
<= 1 && arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
1539 gen_helper_vesb(cpu_env
);
1543 case 0b11000: /* PACIAZ */
1544 if (s
->pauth_active
) {
1545 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1546 new_tmp_a64_zero(s
));
1549 case 0b11001: /* PACIASP */
1550 if (s
->pauth_active
) {
1551 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1554 case 0b11010: /* PACIBZ */
1555 if (s
->pauth_active
) {
1556 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1557 new_tmp_a64_zero(s
));
1560 case 0b11011: /* PACIBSP */
1561 if (s
->pauth_active
) {
1562 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1565 case 0b11100: /* AUTIAZ */
1566 if (s
->pauth_active
) {
1567 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1568 new_tmp_a64_zero(s
));
1571 case 0b11101: /* AUTIASP */
1572 if (s
->pauth_active
) {
1573 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1576 case 0b11110: /* AUTIBZ */
1577 if (s
->pauth_active
) {
1578 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1579 new_tmp_a64_zero(s
));
1582 case 0b11111: /* AUTIBSP */
1583 if (s
->pauth_active
) {
1584 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1588 /* default specified as NOP equivalent */
1593 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1595 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1598 /* CLREX, DSB, DMB, ISB */
1599 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1600 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1605 unallocated_encoding(s
);
1616 case 1: /* MBReqTypes_Reads */
1617 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1619 case 2: /* MBReqTypes_Writes */
1620 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1622 default: /* MBReqTypes_All */
1623 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1629 /* We need to break the TB after this insn to execute
1630 * a self-modified code correctly and also to take
1631 * any pending interrupts immediately.
1634 gen_goto_tb(s
, 0, 4);
1638 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1639 goto do_unallocated
;
1642 * TODO: There is no speculation barrier opcode for TCG;
1643 * MB and end the TB instead.
1645 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1646 gen_goto_tb(s
, 0, 4);
1651 unallocated_encoding(s
);
1656 static void gen_xaflag(void)
1658 TCGv_i32 z
= tcg_temp_new_i32();
1660 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1669 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1670 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1673 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1674 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1676 /* (!C & Z) << 31 -> -(Z & ~C) */
1677 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1678 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1681 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1683 tcg_temp_free_i32(z
);
1686 static void gen_axflag(void)
1688 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1689 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1691 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1692 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1694 tcg_gen_movi_i32(cpu_NF
, 0);
1695 tcg_gen_movi_i32(cpu_VF
, 0);
1698 /* MSR (immediate) - move immediate to processor state field */
1699 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1700 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1702 int op
= op1
<< 3 | op2
;
1704 /* End the TB by default, chaining is ok. */
1705 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1708 case 0x00: /* CFINV */
1709 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1710 goto do_unallocated
;
1712 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1713 s
->base
.is_jmp
= DISAS_NEXT
;
1716 case 0x01: /* XAFlag */
1717 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1718 goto do_unallocated
;
1721 s
->base
.is_jmp
= DISAS_NEXT
;
1724 case 0x02: /* AXFlag */
1725 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1726 goto do_unallocated
;
1729 s
->base
.is_jmp
= DISAS_NEXT
;
1732 case 0x03: /* UAO */
1733 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1734 goto do_unallocated
;
1737 set_pstate_bits(PSTATE_UAO
);
1739 clear_pstate_bits(PSTATE_UAO
);
1741 gen_rebuild_hflags(s
);
1744 case 0x04: /* PAN */
1745 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1746 goto do_unallocated
;
1749 set_pstate_bits(PSTATE_PAN
);
1751 clear_pstate_bits(PSTATE_PAN
);
1753 gen_rebuild_hflags(s
);
1756 case 0x05: /* SPSel */
1757 if (s
->current_el
== 0) {
1758 goto do_unallocated
;
1760 gen_helper_msr_i_spsel(cpu_env
, tcg_constant_i32(crm
& PSTATE_SP
));
1763 case 0x19: /* SSBS */
1764 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1765 goto do_unallocated
;
1768 set_pstate_bits(PSTATE_SSBS
);
1770 clear_pstate_bits(PSTATE_SSBS
);
1772 /* Don't need to rebuild hflags since SSBS is a nop */
1775 case 0x1a: /* DIT */
1776 if (!dc_isar_feature(aa64_dit
, s
)) {
1777 goto do_unallocated
;
1780 set_pstate_bits(PSTATE_DIT
);
1782 clear_pstate_bits(PSTATE_DIT
);
1784 /* There's no need to rebuild hflags because DIT is a nop */
1787 case 0x1e: /* DAIFSet */
1788 gen_helper_msr_i_daifset(cpu_env
, tcg_constant_i32(crm
));
1791 case 0x1f: /* DAIFClear */
1792 gen_helper_msr_i_daifclear(cpu_env
, tcg_constant_i32(crm
));
1793 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1794 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1797 case 0x1c: /* TCO */
1798 if (dc_isar_feature(aa64_mte
, s
)) {
1799 /* Full MTE is enabled -- set the TCO bit as directed. */
1801 set_pstate_bits(PSTATE_TCO
);
1803 clear_pstate_bits(PSTATE_TCO
);
1805 gen_rebuild_hflags(s
);
1806 /* Many factors, including TCO, go into MTE_ACTIVE. */
1807 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1808 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1809 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1810 s
->base
.is_jmp
= DISAS_NEXT
;
1812 goto do_unallocated
;
1816 case 0x1b: /* SVCR* */
1817 if (!dc_isar_feature(aa64_sme
, s
) || crm
< 2 || crm
> 7) {
1818 goto do_unallocated
;
1820 if (sme_access_check(s
)) {
1822 bool changed
= false;
1824 if ((crm
& 2) && i
!= s
->pstate_sm
) {
1825 gen_helper_set_pstate_sm(cpu_env
, tcg_constant_i32(i
));
1828 if ((crm
& 4) && i
!= s
->pstate_za
) {
1829 gen_helper_set_pstate_za(cpu_env
, tcg_constant_i32(i
));
1833 gen_rebuild_hflags(s
);
1835 s
->base
.is_jmp
= DISAS_NEXT
;
1842 unallocated_encoding(s
);
1847 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1849 TCGv_i32 tmp
= tcg_temp_new_i32();
1850 TCGv_i32 nzcv
= tcg_temp_new_i32();
1852 /* build bit 31, N */
1853 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1854 /* build bit 30, Z */
1855 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1856 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1857 /* build bit 29, C */
1858 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1859 /* build bit 28, V */
1860 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1861 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1862 /* generate result */
1863 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1865 tcg_temp_free_i32(nzcv
);
1866 tcg_temp_free_i32(tmp
);
1869 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1871 TCGv_i32 nzcv
= tcg_temp_new_i32();
1873 /* take NZCV from R[t] */
1874 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1877 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1879 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1880 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1882 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1883 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1885 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1886 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1887 tcg_temp_free_i32(nzcv
);
1890 static void gen_sysreg_undef(DisasContext
*s
, bool isread
,
1891 uint8_t op0
, uint8_t op1
, uint8_t op2
,
1892 uint8_t crn
, uint8_t crm
, uint8_t rt
)
1895 * Generate code to emit an UNDEF with correct syndrome
1896 * information for a failed system register access.
1897 * This is EC_UNCATEGORIZED (ie a standard UNDEF) in most cases,
1898 * but if FEAT_IDST is implemented then read accesses to registers
1899 * in the feature ID space are reported with the EC_SYSTEMREGISTERTRAP
1904 if (isread
&& dc_isar_feature(aa64_ids
, s
) &&
1905 arm_cpreg_encoding_in_idspace(op0
, op1
, op2
, crn
, crm
)) {
1906 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1908 syndrome
= syn_uncategorized();
1910 gen_exception_insn(s
, 0, EXCP_UDEF
, syndrome
);
1913 /* MRS - move from system register
1914 * MSR (register) - move to system register
1917 * These are all essentially the same insn in 'read' and 'write'
1918 * versions, with varying op0 fields.
1920 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1921 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1922 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1924 const ARMCPRegInfo
*ri
;
1927 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1928 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1929 crn
, crm
, op0
, op1
, op2
));
1932 /* Unknown register; this might be a guest error or a QEMU
1933 * unimplemented feature.
1935 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1936 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1937 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1938 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
1942 /* Check access permissions */
1943 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1944 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
1949 /* Emit code to perform further access permissions checks at
1950 * runtime; this may result in an exception.
1954 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1955 gen_a64_update_pc(s
, 0);
1956 gen_helper_access_check_cp_reg(cpu_env
,
1957 tcg_constant_ptr(ri
),
1958 tcg_constant_i32(syndrome
),
1959 tcg_constant_i32(isread
));
1960 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1962 * The readfn or writefn might raise an exception;
1963 * synchronize the CPU state in case it does.
1965 gen_a64_update_pc(s
, 0);
1968 /* Handle special cases first */
1969 switch (ri
->type
& ARM_CP_SPECIAL_MASK
) {
1975 tcg_rt
= cpu_reg(s
, rt
);
1977 gen_get_nzcv(tcg_rt
);
1979 gen_set_nzcv(tcg_rt
);
1982 case ARM_CP_CURRENTEL
:
1983 /* Reads as current EL value from pstate, which is
1984 * guaranteed to be constant by the tb flags.
1986 tcg_rt
= cpu_reg(s
, rt
);
1987 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1990 /* Writes clear the aligned block of memory which rt points into. */
1991 if (s
->mte_active
[0]) {
1994 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1995 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1996 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1998 tcg_rt
= new_tmp_a64(s
);
1999 gen_helper_mte_check_zva(tcg_rt
, cpu_env
,
2000 tcg_constant_i32(desc
), cpu_reg(s
, rt
));
2002 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
2004 gen_helper_dc_zva(cpu_env
, tcg_rt
);
2008 TCGv_i64 clean_addr
, tag
;
2011 * DC_GVA, like DC_ZVA, requires that we supply the original
2012 * pointer for an invalid page. Probe that address first.
2014 tcg_rt
= cpu_reg(s
, rt
);
2015 clean_addr
= clean_data_tbi(s
, tcg_rt
);
2016 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
2019 /* Extract the tag from the register to match STZGM. */
2020 tag
= tcg_temp_new_i64();
2021 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
2022 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
2023 tcg_temp_free_i64(tag
);
2027 case ARM_CP_DC_GZVA
:
2029 TCGv_i64 clean_addr
, tag
;
2031 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
2032 tcg_rt
= cpu_reg(s
, rt
);
2033 clean_addr
= clean_data_tbi(s
, tcg_rt
);
2034 gen_helper_dc_zva(cpu_env
, clean_addr
);
2037 /* Extract the tag from the register to match STZGM. */
2038 tag
= tcg_temp_new_i64();
2039 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
2040 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
2041 tcg_temp_free_i64(tag
);
2046 g_assert_not_reached();
2048 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check_only(s
)) {
2050 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
2052 } else if ((ri
->type
& ARM_CP_SME
) && !sme_access_check(s
)) {
2056 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2060 tcg_rt
= cpu_reg(s
, rt
);
2063 if (ri
->type
& ARM_CP_CONST
) {
2064 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
2065 } else if (ri
->readfn
) {
2066 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tcg_constant_ptr(ri
));
2068 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2071 if (ri
->type
& ARM_CP_CONST
) {
2072 /* If not forbidden by access permissions, treat as WI */
2074 } else if (ri
->writefn
) {
2075 gen_helper_set_cp_reg64(cpu_env
, tcg_constant_ptr(ri
), tcg_rt
);
2077 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2081 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
2082 /* I/O operations must end the TB here (whether read or write) */
2083 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2085 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2087 * A write to any coprocessor regiser that ends a TB
2088 * must rebuild the hflags for the next TB.
2090 gen_rebuild_hflags(s
);
2092 * We default to ending the TB on a coprocessor register write,
2093 * but allow this to be suppressed by the register definition
2094 * (usually only necessary to work around guest bugs).
2096 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2101 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2102 * +---------------------+---+-----+-----+-------+-------+-----+------+
2103 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2104 * +---------------------+---+-----+-----+-------+-------+-----+------+
2106 static void disas_system(DisasContext
*s
, uint32_t insn
)
2108 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2109 l
= extract32(insn
, 21, 1);
2110 op0
= extract32(insn
, 19, 2);
2111 op1
= extract32(insn
, 16, 3);
2112 crn
= extract32(insn
, 12, 4);
2113 crm
= extract32(insn
, 8, 4);
2114 op2
= extract32(insn
, 5, 3);
2115 rt
= extract32(insn
, 0, 5);
2118 if (l
|| rt
!= 31) {
2119 unallocated_encoding(s
);
2123 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2124 handle_hint(s
, insn
, op1
, op2
, crm
);
2126 case 3: /* CLREX, DSB, DMB, ISB */
2127 handle_sync(s
, insn
, op1
, op2
, crm
);
2129 case 4: /* MSR (immediate) */
2130 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2133 unallocated_encoding(s
);
2138 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2141 /* Exception generation
2143 * 31 24 23 21 20 5 4 2 1 0
2144 * +-----------------+-----+------------------------+-----+----+
2145 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2146 * +-----------------------+------------------------+----------+
2148 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2150 int opc
= extract32(insn
, 21, 3);
2151 int op2_ll
= extract32(insn
, 0, 5);
2152 int imm16
= extract32(insn
, 5, 16);
2156 /* For SVC, HVC and SMC we advance the single-step state
2157 * machine before taking the exception. This is architecturally
2158 * mandated, to ensure that single-stepping a system call
2159 * instruction works properly.
2164 gen_exception_insn(s
, 4, EXCP_SWI
, syn_aa64_svc(imm16
));
2167 if (s
->current_el
== 0) {
2168 unallocated_encoding(s
);
2171 /* The pre HVC helper handles cases when HVC gets trapped
2172 * as an undefined insn by runtime configuration.
2174 gen_a64_update_pc(s
, 0);
2175 gen_helper_pre_hvc(cpu_env
);
2177 gen_exception_insn_el(s
, 4, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
2180 if (s
->current_el
== 0) {
2181 unallocated_encoding(s
);
2184 gen_a64_update_pc(s
, 0);
2185 gen_helper_pre_smc(cpu_env
, tcg_constant_i32(syn_aa64_smc(imm16
)));
2187 gen_exception_insn_el(s
, 4, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
2190 unallocated_encoding(s
);
2196 unallocated_encoding(s
);
2200 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2204 unallocated_encoding(s
);
2207 /* HLT. This has two purposes.
2208 * Architecturally, it is an external halting debug instruction.
2209 * Since QEMU doesn't implement external debug, we treat this as
2210 * it is required for halting debug disabled: it will UNDEF.
2211 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2213 if (semihosting_enabled(s
->current_el
== 0) && imm16
== 0xf000) {
2214 gen_exception_internal_insn(s
, EXCP_SEMIHOST
);
2216 unallocated_encoding(s
);
2220 if (op2_ll
< 1 || op2_ll
> 3) {
2221 unallocated_encoding(s
);
2224 /* DCPS1, DCPS2, DCPS3 */
2225 unallocated_encoding(s
);
2228 unallocated_encoding(s
);
2233 /* Unconditional branch (register)
2234 * 31 25 24 21 20 16 15 10 9 5 4 0
2235 * +---------------+-------+-------+-------+------+-------+
2236 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2237 * +---------------+-------+-------+-------+------+-------+
2239 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2241 unsigned int opc
, op2
, op3
, rn
, op4
;
2242 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2246 opc
= extract32(insn
, 21, 4);
2247 op2
= extract32(insn
, 16, 5);
2248 op3
= extract32(insn
, 10, 6);
2249 rn
= extract32(insn
, 5, 5);
2250 op4
= extract32(insn
, 0, 5);
2253 goto do_unallocated
;
2265 goto do_unallocated
;
2267 dst
= cpu_reg(s
, rn
);
2272 if (!dc_isar_feature(aa64_pauth
, s
)) {
2273 goto do_unallocated
;
2277 if (rn
!= 0x1f || op4
!= 0x1f) {
2278 goto do_unallocated
;
2281 modifier
= cpu_X
[31];
2283 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2285 goto do_unallocated
;
2287 modifier
= new_tmp_a64_zero(s
);
2289 if (s
->pauth_active
) {
2290 dst
= new_tmp_a64(s
);
2292 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2294 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2297 dst
= cpu_reg(s
, rn
);
2302 goto do_unallocated
;
2304 gen_a64_set_pc(s
, dst
);
2305 /* BLR also needs to load return address */
2307 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2313 if (!dc_isar_feature(aa64_pauth
, s
)) {
2314 goto do_unallocated
;
2316 if ((op3
& ~1) != 2) {
2317 goto do_unallocated
;
2319 btype_mod
= opc
& 1;
2320 if (s
->pauth_active
) {
2321 dst
= new_tmp_a64(s
);
2322 modifier
= cpu_reg_sp(s
, op4
);
2324 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2326 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2329 dst
= cpu_reg(s
, rn
);
2331 gen_a64_set_pc(s
, dst
);
2332 /* BLRAA also needs to load return address */
2334 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2339 if (s
->current_el
== 0) {
2340 goto do_unallocated
;
2345 goto do_unallocated
;
2347 dst
= tcg_temp_new_i64();
2348 tcg_gen_ld_i64(dst
, cpu_env
,
2349 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2352 case 2: /* ERETAA */
2353 case 3: /* ERETAB */
2354 if (!dc_isar_feature(aa64_pauth
, s
)) {
2355 goto do_unallocated
;
2357 if (rn
!= 0x1f || op4
!= 0x1f) {
2358 goto do_unallocated
;
2360 dst
= tcg_temp_new_i64();
2361 tcg_gen_ld_i64(dst
, cpu_env
,
2362 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2363 if (s
->pauth_active
) {
2364 modifier
= cpu_X
[31];
2366 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2368 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2374 goto do_unallocated
;
2376 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2380 gen_helper_exception_return(cpu_env
, dst
);
2381 tcg_temp_free_i64(dst
);
2382 /* Must exit loop to check un-masked IRQs */
2383 s
->base
.is_jmp
= DISAS_EXIT
;
2387 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2388 goto do_unallocated
;
2390 unallocated_encoding(s
);
2396 unallocated_encoding(s
);
2400 switch (btype_mod
) {
2402 if (dc_isar_feature(aa64_bti
, s
)) {
2403 /* BR to {x16,x17} or !guard -> 1, else 3. */
2404 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2409 if (dc_isar_feature(aa64_bti
, s
)) {
2410 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2415 default: /* RET or none of the above. */
2416 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2420 s
->base
.is_jmp
= DISAS_JUMP
;
2423 /* Branches, exception generating and system instructions */
2424 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2426 switch (extract32(insn
, 25, 7)) {
2427 case 0x0a: case 0x0b:
2428 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2429 disas_uncond_b_imm(s
, insn
);
2431 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2432 disas_comp_b_imm(s
, insn
);
2434 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2435 disas_test_b_imm(s
, insn
);
2437 case 0x2a: /* Conditional branch (immediate) */
2438 disas_cond_b_imm(s
, insn
);
2440 case 0x6a: /* Exception generation / System */
2441 if (insn
& (1 << 24)) {
2442 if (extract32(insn
, 22, 2) == 0) {
2443 disas_system(s
, insn
);
2445 unallocated_encoding(s
);
2451 case 0x6b: /* Unconditional branch (register) */
2452 disas_uncond_b_reg(s
, insn
);
2455 unallocated_encoding(s
);
2461 * Load/Store exclusive instructions are implemented by remembering
2462 * the value/address loaded, and seeing if these are the same
2463 * when the store is performed. This is not actually the architecturally
2464 * mandated semantics, but it works for typical guest code sequences
2465 * and avoids having to monitor regular stores.
2467 * The store exclusive uses the atomic cmpxchg primitives to avoid
2468 * races in multi-threaded linux-user and when MTTCG softmmu is
2471 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2472 TCGv_i64 addr
, int size
, bool is_pair
)
2474 int idx
= get_mem_index(s
);
2475 MemOp memop
= s
->be_data
;
2477 g_assert(size
<= 3);
2479 g_assert(size
>= 2);
2481 /* The pair must be single-copy atomic for the doubleword. */
2482 memop
|= MO_64
| MO_ALIGN
;
2483 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2484 if (s
->be_data
== MO_LE
) {
2485 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2486 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2488 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2489 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2492 /* The pair must be single-copy atomic for *each* doubleword, not
2493 the entire quadword, however it must be quadword aligned. */
2495 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2496 memop
| MO_ALIGN_16
);
2498 TCGv_i64 addr2
= tcg_temp_new_i64();
2499 tcg_gen_addi_i64(addr2
, addr
, 8);
2500 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2501 tcg_temp_free_i64(addr2
);
2503 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2504 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2507 memop
|= size
| MO_ALIGN
;
2508 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2509 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2511 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2514 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2515 TCGv_i64 addr
, int size
, int is_pair
)
2517 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2518 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2521 * [addr + datasize] = {Rt2};
2527 * env->exclusive_addr = -1;
2529 TCGLabel
*fail_label
= gen_new_label();
2530 TCGLabel
*done_label
= gen_new_label();
2533 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2535 tmp
= tcg_temp_new_i64();
2538 if (s
->be_data
== MO_LE
) {
2539 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2541 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2543 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2544 cpu_exclusive_val
, tmp
,
2546 MO_64
| MO_ALIGN
| s
->be_data
);
2547 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2548 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2549 if (!HAVE_CMPXCHG128
) {
2550 gen_helper_exit_atomic(cpu_env
);
2552 * Produce a result so we have a well-formed opcode
2553 * stream when the following (dead) code uses 'tmp'.
2554 * TCG will remove the dead ops for us.
2556 tcg_gen_movi_i64(tmp
, 0);
2557 } else if (s
->be_data
== MO_LE
) {
2558 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2563 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2568 } else if (s
->be_data
== MO_LE
) {
2569 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2570 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2572 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2573 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2576 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2577 cpu_reg(s
, rt
), get_mem_index(s
),
2578 size
| MO_ALIGN
| s
->be_data
);
2579 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2581 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2582 tcg_temp_free_i64(tmp
);
2583 tcg_gen_br(done_label
);
2585 gen_set_label(fail_label
);
2586 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2587 gen_set_label(done_label
);
2588 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2591 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2594 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2595 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2596 int memidx
= get_mem_index(s
);
2597 TCGv_i64 clean_addr
;
2600 gen_check_sp_alignment(s
);
2602 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2603 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2604 size
| MO_ALIGN
| s
->be_data
);
2607 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2610 TCGv_i64 s1
= cpu_reg(s
, rs
);
2611 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2612 TCGv_i64 t1
= cpu_reg(s
, rt
);
2613 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2614 TCGv_i64 clean_addr
;
2615 int memidx
= get_mem_index(s
);
2618 gen_check_sp_alignment(s
);
2621 /* This is a single atomic access, despite the "pair". */
2622 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2625 TCGv_i64 cmp
= tcg_temp_new_i64();
2626 TCGv_i64 val
= tcg_temp_new_i64();
2628 if (s
->be_data
== MO_LE
) {
2629 tcg_gen_concat32_i64(val
, t1
, t2
);
2630 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2632 tcg_gen_concat32_i64(val
, t2
, t1
);
2633 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2636 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2637 MO_64
| MO_ALIGN
| s
->be_data
);
2638 tcg_temp_free_i64(val
);
2640 if (s
->be_data
== MO_LE
) {
2641 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2643 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2645 tcg_temp_free_i64(cmp
);
2646 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2647 if (HAVE_CMPXCHG128
) {
2648 TCGv_i32 tcg_rs
= tcg_constant_i32(rs
);
2649 if (s
->be_data
== MO_LE
) {
2650 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2651 clean_addr
, t1
, t2
);
2653 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2654 clean_addr
, t1
, t2
);
2657 gen_helper_exit_atomic(cpu_env
);
2658 s
->base
.is_jmp
= DISAS_NORETURN
;
2661 TCGv_i64 d1
= tcg_temp_new_i64();
2662 TCGv_i64 d2
= tcg_temp_new_i64();
2663 TCGv_i64 a2
= tcg_temp_new_i64();
2664 TCGv_i64 c1
= tcg_temp_new_i64();
2665 TCGv_i64 c2
= tcg_temp_new_i64();
2666 TCGv_i64 zero
= tcg_constant_i64(0);
2668 /* Load the two words, in memory order. */
2669 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2670 MO_64
| MO_ALIGN_16
| s
->be_data
);
2671 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2672 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2674 /* Compare the two words, also in memory order. */
2675 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2676 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2677 tcg_gen_and_i64(c2
, c2
, c1
);
2679 /* If compare equal, write back new data, else write back old data. */
2680 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2681 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2682 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2683 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2684 tcg_temp_free_i64(a2
);
2685 tcg_temp_free_i64(c1
);
2686 tcg_temp_free_i64(c2
);
2688 /* Write back the data from memory to Rs. */
2689 tcg_gen_mov_i64(s1
, d1
);
2690 tcg_gen_mov_i64(s2
, d2
);
2691 tcg_temp_free_i64(d1
);
2692 tcg_temp_free_i64(d2
);
2696 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2697 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2699 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2701 int opc0
= extract32(opc
, 0, 1);
2705 regsize
= opc0
? 32 : 64;
2707 regsize
= size
== 3 ? 64 : 32;
2709 return regsize
== 64;
2712 /* Load/store exclusive
2714 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2715 * +-----+-------------+----+---+----+------+----+-------+------+------+
2716 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2717 * +-----+-------------+----+---+----+------+----+-------+------+------+
2719 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2720 * L: 0 -> store, 1 -> load
2721 * o2: 0 -> exclusive, 1 -> not
2722 * o1: 0 -> single register, 1 -> register pair
2723 * o0: 1 -> load-acquire/store-release, 0 -> not
2725 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2727 int rt
= extract32(insn
, 0, 5);
2728 int rn
= extract32(insn
, 5, 5);
2729 int rt2
= extract32(insn
, 10, 5);
2730 int rs
= extract32(insn
, 16, 5);
2731 int is_lasr
= extract32(insn
, 15, 1);
2732 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2733 int size
= extract32(insn
, 30, 2);
2734 TCGv_i64 clean_addr
;
2736 switch (o2_L_o1_o0
) {
2737 case 0x0: /* STXR */
2738 case 0x1: /* STLXR */
2740 gen_check_sp_alignment(s
);
2743 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2745 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2746 true, rn
!= 31, size
);
2747 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2750 case 0x4: /* LDXR */
2751 case 0x5: /* LDAXR */
2753 gen_check_sp_alignment(s
);
2755 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2756 false, rn
!= 31, size
);
2758 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2760 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2764 case 0x8: /* STLLR */
2765 if (!dc_isar_feature(aa64_lor
, s
)) {
2768 /* StoreLORelease is the same as Store-Release for QEMU. */
2770 case 0x9: /* STLR */
2771 /* Generate ISS for non-exclusive accesses including LASR. */
2773 gen_check_sp_alignment(s
);
2775 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2776 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2777 true, rn
!= 31, size
);
2778 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2779 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2780 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2783 case 0xc: /* LDLAR */
2784 if (!dc_isar_feature(aa64_lor
, s
)) {
2787 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2789 case 0xd: /* LDAR */
2790 /* Generate ISS for non-exclusive accesses including LASR. */
2792 gen_check_sp_alignment(s
);
2794 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2795 false, rn
!= 31, size
);
2796 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2797 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2798 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2799 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2802 case 0x2: case 0x3: /* CASP / STXP */
2803 if (size
& 2) { /* STXP / STLXP */
2805 gen_check_sp_alignment(s
);
2808 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2810 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2811 true, rn
!= 31, size
);
2812 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2816 && ((rt
| rs
) & 1) == 0
2817 && dc_isar_feature(aa64_atomics
, s
)) {
2819 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2824 case 0x6: case 0x7: /* CASPA / LDXP */
2825 if (size
& 2) { /* LDXP / LDAXP */
2827 gen_check_sp_alignment(s
);
2829 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2830 false, rn
!= 31, size
);
2832 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2834 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2839 && ((rt
| rs
) & 1) == 0
2840 && dc_isar_feature(aa64_atomics
, s
)) {
2841 /* CASPA / CASPAL */
2842 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2848 case 0xb: /* CASL */
2849 case 0xe: /* CASA */
2850 case 0xf: /* CASAL */
2851 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2852 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2857 unallocated_encoding(s
);
2861 * Load register (literal)
2863 * 31 30 29 27 26 25 24 23 5 4 0
2864 * +-----+-------+---+-----+-------------------+-------+
2865 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2866 * +-----+-------+---+-----+-------------------+-------+
2868 * V: 1 -> vector (simd/fp)
2869 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2870 * 10-> 32 bit signed, 11 -> prefetch
2871 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2873 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2875 int rt
= extract32(insn
, 0, 5);
2876 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2877 bool is_vector
= extract32(insn
, 26, 1);
2878 int opc
= extract32(insn
, 30, 2);
2879 bool is_signed
= false;
2881 TCGv_i64 tcg_rt
, clean_addr
;
2885 unallocated_encoding(s
);
2889 if (!fp_access_check(s
)) {
2894 /* PRFM (literal) : prefetch */
2897 size
= 2 + extract32(opc
, 0, 1);
2898 is_signed
= extract32(opc
, 1, 1);
2901 tcg_rt
= cpu_reg(s
, rt
);
2903 clean_addr
= tcg_constant_i64(s
->pc_curr
+ imm
);
2905 do_fp_ld(s
, rt
, clean_addr
, size
);
2907 /* Only unsigned 32bit loads target 32bit registers. */
2908 bool iss_sf
= opc
!= 0;
2910 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2911 false, true, rt
, iss_sf
, false);
2916 * LDNP (Load Pair - non-temporal hint)
2917 * LDP (Load Pair - non vector)
2918 * LDPSW (Load Pair Signed Word - non vector)
2919 * STNP (Store Pair - non-temporal hint)
2920 * STP (Store Pair - non vector)
2921 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2922 * LDP (Load Pair of SIMD&FP)
2923 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2924 * STP (Store Pair of SIMD&FP)
2926 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2927 * +-----+-------+---+---+-------+---+-----------------------------+
2928 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2929 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2931 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2933 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2934 * V: 0 -> GPR, 1 -> Vector
2935 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2936 * 10 -> signed offset, 11 -> pre-index
2937 * L: 0 -> Store 1 -> Load
2939 * Rt, Rt2 = GPR or SIMD registers to be stored
2940 * Rn = general purpose register containing address
2941 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2943 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2945 int rt
= extract32(insn
, 0, 5);
2946 int rn
= extract32(insn
, 5, 5);
2947 int rt2
= extract32(insn
, 10, 5);
2948 uint64_t offset
= sextract64(insn
, 15, 7);
2949 int index
= extract32(insn
, 23, 2);
2950 bool is_vector
= extract32(insn
, 26, 1);
2951 bool is_load
= extract32(insn
, 22, 1);
2952 int opc
= extract32(insn
, 30, 2);
2954 bool is_signed
= false;
2955 bool postindex
= false;
2957 bool set_tag
= false;
2959 TCGv_i64 clean_addr
, dirty_addr
;
2964 unallocated_encoding(s
);
2970 } else if (opc
== 1 && !is_load
) {
2972 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2973 unallocated_encoding(s
);
2979 size
= 2 + extract32(opc
, 1, 1);
2980 is_signed
= extract32(opc
, 0, 1);
2981 if (!is_load
&& is_signed
) {
2982 unallocated_encoding(s
);
2988 case 1: /* post-index */
2993 /* signed offset with "non-temporal" hint. Since we don't emulate
2994 * caches we don't care about hints to the cache system about
2995 * data access patterns, and handle this identically to plain
2999 /* There is no non-temporal-hint version of LDPSW */
3000 unallocated_encoding(s
);
3005 case 2: /* signed offset, rn not updated */
3008 case 3: /* pre-index */
3014 if (is_vector
&& !fp_access_check(s
)) {
3018 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
3021 gen_check_sp_alignment(s
);
3024 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3026 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3032 * TODO: We could rely on the stores below, at least for
3033 * system mode, if we arrange to add MO_ALIGN_16.
3035 gen_helper_stg_stub(cpu_env
, dirty_addr
);
3036 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
3037 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
3039 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
3043 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
3044 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
3048 do_fp_ld(s
, rt
, clean_addr
, size
);
3050 do_fp_st(s
, rt
, clean_addr
, size
);
3052 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3054 do_fp_ld(s
, rt2
, clean_addr
, size
);
3056 do_fp_st(s
, rt2
, clean_addr
, size
);
3059 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3060 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
3063 TCGv_i64 tmp
= tcg_temp_new_i64();
3065 /* Do not modify tcg_rt before recognizing any exception
3066 * from the second load.
3068 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3069 false, false, 0, false, false);
3070 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3071 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3072 false, false, 0, false, false);
3074 tcg_gen_mov_i64(tcg_rt
, tmp
);
3075 tcg_temp_free_i64(tmp
);
3077 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3078 false, 0, false, false);
3079 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3080 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3081 false, 0, false, false);
3087 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3089 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3094 * Load/store (immediate post-indexed)
3095 * Load/store (immediate pre-indexed)
3096 * Load/store (unscaled immediate)
3098 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3099 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3100 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3101 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3103 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3105 * V = 0 -> non-vector
3106 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3107 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3109 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3115 int rn
= extract32(insn
, 5, 5);
3116 int imm9
= sextract32(insn
, 12, 9);
3117 int idx
= extract32(insn
, 10, 2);
3118 bool is_signed
= false;
3119 bool is_store
= false;
3120 bool is_extended
= false;
3121 bool is_unpriv
= (idx
== 2);
3127 TCGv_i64 clean_addr
, dirty_addr
;
3130 size
|= (opc
& 2) << 1;
3131 if (size
> 4 || is_unpriv
) {
3132 unallocated_encoding(s
);
3135 is_store
= ((opc
& 1) == 0);
3136 if (!fp_access_check(s
)) {
3140 if (size
== 3 && opc
== 2) {
3141 /* PRFM - prefetch */
3143 unallocated_encoding(s
);
3148 if (opc
== 3 && size
> 1) {
3149 unallocated_encoding(s
);
3152 is_store
= (opc
== 0);
3153 is_signed
= extract32(opc
, 1, 1);
3154 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3172 g_assert_not_reached();
3175 iss_valid
= !is_vector
&& !writeback
;
3178 gen_check_sp_alignment(s
);
3181 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3183 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3186 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3187 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3188 writeback
|| rn
!= 31,
3189 size
, is_unpriv
, memidx
);
3193 do_fp_st(s
, rt
, clean_addr
, size
);
3195 do_fp_ld(s
, rt
, clean_addr
, size
);
3198 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3199 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3202 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3203 iss_valid
, rt
, iss_sf
, false);
3205 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3206 is_extended
, memidx
,
3207 iss_valid
, rt
, iss_sf
, false);
3212 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3214 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3216 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3221 * Load/store (register offset)
3223 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3224 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3225 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3226 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3229 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3230 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3232 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3233 * opc<0>: 0 -> store, 1 -> load
3234 * V: 1 -> vector/simd
3235 * opt: extend encoding (see DecodeRegExtend)
3236 * S: if S=1 then scale (essentially index by sizeof(size))
3237 * Rt: register to transfer into/out of
3238 * Rn: address register or SP for base
3239 * Rm: offset register or ZR for offset
3241 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3247 int rn
= extract32(insn
, 5, 5);
3248 int shift
= extract32(insn
, 12, 1);
3249 int rm
= extract32(insn
, 16, 5);
3250 int opt
= extract32(insn
, 13, 3);
3251 bool is_signed
= false;
3252 bool is_store
= false;
3253 bool is_extended
= false;
3255 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3257 if (extract32(opt
, 1, 1) == 0) {
3258 unallocated_encoding(s
);
3263 size
|= (opc
& 2) << 1;
3265 unallocated_encoding(s
);
3268 is_store
= !extract32(opc
, 0, 1);
3269 if (!fp_access_check(s
)) {
3273 if (size
== 3 && opc
== 2) {
3274 /* PRFM - prefetch */
3277 if (opc
== 3 && size
> 1) {
3278 unallocated_encoding(s
);
3281 is_store
= (opc
== 0);
3282 is_signed
= extract32(opc
, 1, 1);
3283 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3287 gen_check_sp_alignment(s
);
3289 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3291 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3292 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3294 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3295 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3299 do_fp_st(s
, rt
, clean_addr
, size
);
3301 do_fp_ld(s
, rt
, clean_addr
, size
);
3304 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3305 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3307 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3308 true, rt
, iss_sf
, false);
3310 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3311 is_extended
, true, rt
, iss_sf
, false);
3317 * Load/store (unsigned immediate)
3319 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3320 * +----+-------+---+-----+-----+------------+-------+------+
3321 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3322 * +----+-------+---+-----+-----+------------+-------+------+
3325 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3326 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3328 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3329 * opc<0>: 0 -> store, 1 -> load
3330 * Rn: base address register (inc SP)
3331 * Rt: target register
3333 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3339 int rn
= extract32(insn
, 5, 5);
3340 unsigned int imm12
= extract32(insn
, 10, 12);
3341 unsigned int offset
;
3343 TCGv_i64 clean_addr
, dirty_addr
;
3346 bool is_signed
= false;
3347 bool is_extended
= false;
3350 size
|= (opc
& 2) << 1;
3352 unallocated_encoding(s
);
3355 is_store
= !extract32(opc
, 0, 1);
3356 if (!fp_access_check(s
)) {
3360 if (size
== 3 && opc
== 2) {
3361 /* PRFM - prefetch */
3364 if (opc
== 3 && size
> 1) {
3365 unallocated_encoding(s
);
3368 is_store
= (opc
== 0);
3369 is_signed
= extract32(opc
, 1, 1);
3370 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3374 gen_check_sp_alignment(s
);
3376 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3377 offset
= imm12
<< size
;
3378 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3379 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3383 do_fp_st(s
, rt
, clean_addr
, size
);
3385 do_fp_ld(s
, rt
, clean_addr
, size
);
3388 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3389 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3391 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3392 true, rt
, iss_sf
, false);
3394 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3395 is_extended
, true, rt
, iss_sf
, false);
3400 /* Atomic memory operations
3402 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3403 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3404 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3405 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3407 * Rt: the result register
3408 * Rn: base address or SP
3409 * Rs: the source register for the operation
3410 * V: vector flag (always 0 as of v8.3)
3414 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3415 int size
, int rt
, bool is_vector
)
3417 int rs
= extract32(insn
, 16, 5);
3418 int rn
= extract32(insn
, 5, 5);
3419 int o3_opc
= extract32(insn
, 12, 4);
3420 bool r
= extract32(insn
, 22, 1);
3421 bool a
= extract32(insn
, 23, 1);
3422 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3423 AtomicThreeOpFn
*fn
= NULL
;
3424 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3426 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3427 unallocated_encoding(s
);
3431 case 000: /* LDADD */
3432 fn
= tcg_gen_atomic_fetch_add_i64
;
3434 case 001: /* LDCLR */
3435 fn
= tcg_gen_atomic_fetch_and_i64
;
3437 case 002: /* LDEOR */
3438 fn
= tcg_gen_atomic_fetch_xor_i64
;
3440 case 003: /* LDSET */
3441 fn
= tcg_gen_atomic_fetch_or_i64
;
3443 case 004: /* LDSMAX */
3444 fn
= tcg_gen_atomic_fetch_smax_i64
;
3447 case 005: /* LDSMIN */
3448 fn
= tcg_gen_atomic_fetch_smin_i64
;
3451 case 006: /* LDUMAX */
3452 fn
= tcg_gen_atomic_fetch_umax_i64
;
3454 case 007: /* LDUMIN */
3455 fn
= tcg_gen_atomic_fetch_umin_i64
;
3458 fn
= tcg_gen_atomic_xchg_i64
;
3460 case 014: /* LDAPR, LDAPRH, LDAPRB */
3461 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3462 rs
!= 31 || a
!= 1 || r
!= 0) {
3463 unallocated_encoding(s
);
3468 unallocated_encoding(s
);
3473 gen_check_sp_alignment(s
);
3475 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3477 if (o3_opc
== 014) {
3479 * LDAPR* are a special case because they are a simple load, not a
3480 * fetch-and-do-something op.
3481 * The architectural consistency requirements here are weaker than
3482 * full load-acquire (we only need "load-acquire processor consistent"),
3483 * but we choose to implement them as full LDAQ.
3485 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3486 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3487 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3491 tcg_rs
= read_cpu_reg(s
, rs
, true);
3492 tcg_rt
= cpu_reg(s
, rt
);
3494 if (o3_opc
== 1) { /* LDCLR */
3495 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3498 /* The tcg atomic primitives are all full barriers. Therefore we
3499 * can ignore the Acquire and Release bits of this instruction.
3501 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3503 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3504 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3509 * PAC memory operations
3511 * 31 30 27 26 24 22 21 12 11 10 5 0
3512 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3513 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3514 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3516 * Rt: the result register
3517 * Rn: base address or SP
3518 * V: vector flag (always 0 as of v8.3)
3519 * M: clear for key DA, set for key DB
3520 * W: pre-indexing flag
3523 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3524 int size
, int rt
, bool is_vector
)
3526 int rn
= extract32(insn
, 5, 5);
3527 bool is_wback
= extract32(insn
, 11, 1);
3528 bool use_key_a
= !extract32(insn
, 23, 1);
3530 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3532 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3533 unallocated_encoding(s
);
3538 gen_check_sp_alignment(s
);
3540 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3542 if (s
->pauth_active
) {
3544 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3545 new_tmp_a64_zero(s
));
3547 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3548 new_tmp_a64_zero(s
));
3552 /* Form the 10-bit signed, scaled offset. */
3553 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3554 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3555 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3557 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3558 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3559 is_wback
|| rn
!= 31, size
);
3561 tcg_rt
= cpu_reg(s
, rt
);
3562 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3563 /* extend */ false, /* iss_valid */ !is_wback
,
3564 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3567 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3572 * LDAPR/STLR (unscaled immediate)
3574 * 31 30 24 22 21 12 10 5 0
3575 * +------+-------------+-----+---+--------+-----+----+-----+
3576 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3577 * +------+-------------+-----+---+--------+-----+----+-----+
3579 * Rt: source or destination register
3581 * imm9: unscaled immediate offset
3582 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3583 * size: size of load/store
3585 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3587 int rt
= extract32(insn
, 0, 5);
3588 int rn
= extract32(insn
, 5, 5);
3589 int offset
= sextract32(insn
, 12, 9);
3590 int opc
= extract32(insn
, 22, 2);
3591 int size
= extract32(insn
, 30, 2);
3592 TCGv_i64 clean_addr
, dirty_addr
;
3593 bool is_store
= false;
3594 bool extend
= false;
3598 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3599 unallocated_encoding(s
);
3603 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3604 mop
= size
| MO_ALIGN
;
3607 case 0: /* STLURB */
3610 case 1: /* LDAPUR* */
3612 case 2: /* LDAPURS* 64-bit variant */
3614 unallocated_encoding(s
);
3619 case 3: /* LDAPURS* 32-bit variant */
3621 unallocated_encoding(s
);
3625 extend
= true; /* zero-extend 32->64 after signed load */
3628 g_assert_not_reached();
3631 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3634 gen_check_sp_alignment(s
);
3637 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3638 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3639 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3642 /* Store-Release semantics */
3643 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3644 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3647 * Load-AcquirePC semantics; we implement as the slightly more
3648 * restrictive Load-Acquire.
3650 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3651 extend
, true, rt
, iss_sf
, true);
3652 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3656 /* Load/store register (all forms) */
3657 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3659 int rt
= extract32(insn
, 0, 5);
3660 int opc
= extract32(insn
, 22, 2);
3661 bool is_vector
= extract32(insn
, 26, 1);
3662 int size
= extract32(insn
, 30, 2);
3664 switch (extract32(insn
, 24, 2)) {
3666 if (extract32(insn
, 21, 1) == 0) {
3667 /* Load/store register (unscaled immediate)
3668 * Load/store immediate pre/post-indexed
3669 * Load/store register unprivileged
3671 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3674 switch (extract32(insn
, 10, 2)) {
3676 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3679 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3682 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3687 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3690 unallocated_encoding(s
);
3693 /* AdvSIMD load/store multiple structures
3695 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3696 * +---+---+---------------+---+-------------+--------+------+------+------+
3697 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3698 * +---+---+---------------+---+-------------+--------+------+------+------+
3700 * AdvSIMD load/store multiple structures (post-indexed)
3702 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3703 * +---+---+---------------+---+---+---------+--------+------+------+------+
3704 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3705 * +---+---+---------------+---+---+---------+--------+------+------+------+
3707 * Rt: first (or only) SIMD&FP register to be transferred
3708 * Rn: base address or SP
3709 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3711 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3713 int rt
= extract32(insn
, 0, 5);
3714 int rn
= extract32(insn
, 5, 5);
3715 int rm
= extract32(insn
, 16, 5);
3716 int size
= extract32(insn
, 10, 2);
3717 int opcode
= extract32(insn
, 12, 4);
3718 bool is_store
= !extract32(insn
, 22, 1);
3719 bool is_postidx
= extract32(insn
, 23, 1);
3720 bool is_q
= extract32(insn
, 30, 1);
3721 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3722 MemOp endian
, align
, mop
;
3724 int total
; /* total bytes */
3725 int elements
; /* elements per vector */
3726 int rpt
; /* num iterations */
3727 int selem
; /* structure elements */
3730 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3731 unallocated_encoding(s
);
3735 if (!is_postidx
&& rm
!= 0) {
3736 unallocated_encoding(s
);
3740 /* From the shared decode logic */
3771 unallocated_encoding(s
);
3775 if (size
== 3 && !is_q
&& selem
!= 1) {
3777 unallocated_encoding(s
);
3781 if (!fp_access_check(s
)) {
3786 gen_check_sp_alignment(s
);
3789 /* For our purposes, bytes are always little-endian. */
3790 endian
= s
->be_data
;
3795 total
= rpt
* selem
* (is_q
? 16 : 8);
3796 tcg_rn
= cpu_reg_sp(s
, rn
);
3799 * Issue the MTE check vs the logical repeat count, before we
3800 * promote consecutive little-endian elements below.
3802 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3806 * Consecutive little-endian elements from a single register
3807 * can be promoted to a larger little-endian operation.
3810 if (selem
== 1 && endian
== MO_LE
) {
3811 align
= pow2_align(size
);
3814 if (!s
->align_mem
) {
3817 mop
= endian
| size
| align
;
3819 elements
= (is_q
? 16 : 8) >> size
;
3820 tcg_ebytes
= tcg_constant_i64(1 << size
);
3821 for (r
= 0; r
< rpt
; r
++) {
3823 for (e
= 0; e
< elements
; e
++) {
3825 for (xs
= 0; xs
< selem
; xs
++) {
3826 int tt
= (rt
+ r
+ xs
) % 32;
3828 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3830 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3832 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3838 /* For non-quad operations, setting a slice of the low
3839 * 64 bits of the register clears the high 64 bits (in
3840 * the ARM ARM pseudocode this is implicit in the fact
3841 * that 'rval' is a 64 bit wide variable).
3842 * For quad operations, we might still need to zero the
3845 for (r
= 0; r
< rpt
* selem
; r
++) {
3846 int tt
= (rt
+ r
) % 32;
3847 clear_vec_high(s
, is_q
, tt
);
3853 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3855 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3860 /* AdvSIMD load/store single structure
3862 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3863 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3864 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3865 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3867 * AdvSIMD load/store single structure (post-indexed)
3869 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3870 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3871 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3872 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3874 * Rt: first (or only) SIMD&FP register to be transferred
3875 * Rn: base address or SP
3876 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3877 * index = encoded in Q:S:size dependent on size
3879 * lane_size = encoded in R, opc
3880 * transfer width = encoded in opc, S, size
3882 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3884 int rt
= extract32(insn
, 0, 5);
3885 int rn
= extract32(insn
, 5, 5);
3886 int rm
= extract32(insn
, 16, 5);
3887 int size
= extract32(insn
, 10, 2);
3888 int S
= extract32(insn
, 12, 1);
3889 int opc
= extract32(insn
, 13, 3);
3890 int R
= extract32(insn
, 21, 1);
3891 int is_load
= extract32(insn
, 22, 1);
3892 int is_postidx
= extract32(insn
, 23, 1);
3893 int is_q
= extract32(insn
, 30, 1);
3895 int scale
= extract32(opc
, 1, 2);
3896 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3897 bool replicate
= false;
3898 int index
= is_q
<< 3 | S
<< 2 | size
;
3900 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3903 if (extract32(insn
, 31, 1)) {
3904 unallocated_encoding(s
);
3907 if (!is_postidx
&& rm
!= 0) {
3908 unallocated_encoding(s
);
3914 if (!is_load
|| S
) {
3915 unallocated_encoding(s
);
3924 if (extract32(size
, 0, 1)) {
3925 unallocated_encoding(s
);
3931 if (extract32(size
, 1, 1)) {
3932 unallocated_encoding(s
);
3935 if (!extract32(size
, 0, 1)) {
3939 unallocated_encoding(s
);
3947 g_assert_not_reached();
3950 if (!fp_access_check(s
)) {
3955 gen_check_sp_alignment(s
);
3958 total
= selem
<< scale
;
3959 tcg_rn
= cpu_reg_sp(s
, rn
);
3961 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3963 mop
= finalize_memop(s
, scale
);
3965 tcg_ebytes
= tcg_constant_i64(1 << scale
);
3966 for (xs
= 0; xs
< selem
; xs
++) {
3968 /* Load and replicate to all elements */
3969 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3971 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3972 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3973 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3975 tcg_temp_free_i64(tcg_tmp
);
3977 /* Load/store one element per register */
3979 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3981 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3984 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3990 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3992 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3998 * Load/Store memory tags
4000 * 31 30 29 24 22 21 12 10 5 0
4001 * +-----+-------------+-----+---+------+-----+------+------+
4002 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
4003 * +-----+-------------+-----+---+------+-----+------+------+
4005 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
4007 int rt
= extract32(insn
, 0, 5);
4008 int rn
= extract32(insn
, 5, 5);
4009 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
4010 int op2
= extract32(insn
, 10, 2);
4011 int op1
= extract32(insn
, 22, 2);
4012 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
4014 TCGv_i64 addr
, clean_addr
, tcg_rt
;
4016 /* We checked insn bits [29:24,21] in the caller. */
4017 if (extract32(insn
, 30, 2) != 3) {
4018 goto do_unallocated
;
4022 * @index is a tri-state variable which has 3 states:
4023 * < 0 : post-index, writeback
4024 * = 0 : signed offset
4025 * > 0 : pre-index, writeback
4034 if (s
->current_el
== 0 || offset
!= 0) {
4035 goto do_unallocated
;
4037 is_mult
= is_zero
= true;
4057 if (s
->current_el
== 0 || offset
!= 0) {
4058 goto do_unallocated
;
4066 is_pair
= is_zero
= true;
4070 if (s
->current_el
== 0 || offset
!= 0) {
4071 goto do_unallocated
;
4073 is_mult
= is_load
= true;
4079 unallocated_encoding(s
);
4084 ? !dc_isar_feature(aa64_mte
, s
)
4085 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4086 goto do_unallocated
;
4090 gen_check_sp_alignment(s
);
4093 addr
= read_cpu_reg_sp(s
, rn
, true);
4095 /* pre-index or signed offset */
4096 tcg_gen_addi_i64(addr
, addr
, offset
);
4100 tcg_rt
= cpu_reg(s
, rt
);
4103 int size
= 4 << s
->dcz_blocksize
;
4106 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4109 * The non-tags portion of STZGM is mostly like DC_ZVA,
4110 * except the alignment happens before the access.
4112 clean_addr
= clean_data_tbi(s
, addr
);
4113 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4114 gen_helper_dc_zva(cpu_env
, clean_addr
);
4115 } else if (s
->ata
) {
4117 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4119 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4122 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4123 int size
= 4 << GMID_EL1_BS
;
4125 clean_addr
= clean_data_tbi(s
, addr
);
4126 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4127 gen_probe_access(s
, clean_addr
, acc
, size
);
4130 /* The result tags are zeros. */
4131 tcg_gen_movi_i64(tcg_rt
, 0);
4138 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4139 tcg_rt
= cpu_reg(s
, rt
);
4141 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4143 clean_addr
= clean_data_tbi(s
, addr
);
4144 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4145 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4148 tcg_rt
= cpu_reg_sp(s
, rt
);
4151 * For STG and ST2G, we need to check alignment and probe memory.
4152 * TODO: For STZG and STZ2G, we could rely on the stores below,
4153 * at least for system mode; user-only won't enforce alignment.
4156 gen_helper_st2g_stub(cpu_env
, addr
);
4158 gen_helper_stg_stub(cpu_env
, addr
);
4160 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4162 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4164 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4168 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4170 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4176 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4177 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
4178 int mem_index
= get_mem_index(s
);
4179 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4181 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4182 MO_UQ
| MO_ALIGN_16
);
4183 for (i
= 8; i
< n
; i
+= 8) {
4184 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4185 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_UQ
);
4190 /* pre-index or post-index */
4193 tcg_gen_addi_i64(addr
, addr
, offset
);
4195 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4199 /* Loads and stores */
4200 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4202 switch (extract32(insn
, 24, 6)) {
4203 case 0x08: /* Load/store exclusive */
4204 disas_ldst_excl(s
, insn
);
4206 case 0x18: case 0x1c: /* Load register (literal) */
4207 disas_ld_lit(s
, insn
);
4209 case 0x28: case 0x29:
4210 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4211 disas_ldst_pair(s
, insn
);
4213 case 0x38: case 0x39:
4214 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4215 disas_ldst_reg(s
, insn
);
4217 case 0x0c: /* AdvSIMD load/store multiple structures */
4218 disas_ldst_multiple_struct(s
, insn
);
4220 case 0x0d: /* AdvSIMD load/store single structure */
4221 disas_ldst_single_struct(s
, insn
);
4224 if (extract32(insn
, 21, 1) != 0) {
4225 disas_ldst_tag(s
, insn
);
4226 } else if (extract32(insn
, 10, 2) == 0) {
4227 disas_ldst_ldapr_stlr(s
, insn
);
4229 unallocated_encoding(s
);
4233 unallocated_encoding(s
);
4238 /* PC-rel. addressing
4239 * 31 30 29 28 24 23 5 4 0
4240 * +----+-------+-----------+-------------------+------+
4241 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4242 * +----+-------+-----------+-------------------+------+
4244 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4246 unsigned int page
, rd
;
4250 page
= extract32(insn
, 31, 1);
4251 /* SignExtend(immhi:immlo) -> offset */
4252 offset
= sextract64(insn
, 5, 19);
4253 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4254 rd
= extract32(insn
, 0, 5);
4258 /* ADRP (page based) */
4263 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4267 * Add/subtract (immediate)
4269 * 31 30 29 28 23 22 21 10 9 5 4 0
4270 * +--+--+--+-------------+--+-------------+-----+-----+
4271 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4272 * +--+--+--+-------------+--+-------------+-----+-----+
4274 * sf: 0 -> 32bit, 1 -> 64bit
4275 * op: 0 -> add , 1 -> sub
4277 * sh: 1 -> LSL imm by 12
4279 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4281 int rd
= extract32(insn
, 0, 5);
4282 int rn
= extract32(insn
, 5, 5);
4283 uint64_t imm
= extract32(insn
, 10, 12);
4284 bool shift
= extract32(insn
, 22, 1);
4285 bool setflags
= extract32(insn
, 29, 1);
4286 bool sub_op
= extract32(insn
, 30, 1);
4287 bool is_64bit
= extract32(insn
, 31, 1);
4289 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4290 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4291 TCGv_i64 tcg_result
;
4297 tcg_result
= tcg_temp_new_i64();
4300 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4302 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4305 TCGv_i64 tcg_imm
= tcg_constant_i64(imm
);
4307 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4309 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4314 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4316 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4319 tcg_temp_free_i64(tcg_result
);
4323 * Add/subtract (immediate, with tags)
4325 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4326 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4327 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4328 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4330 * op: 0 -> add, 1 -> sub
4332 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4334 int rd
= extract32(insn
, 0, 5);
4335 int rn
= extract32(insn
, 5, 5);
4336 int uimm4
= extract32(insn
, 10, 4);
4337 int uimm6
= extract32(insn
, 16, 6);
4338 bool sub_op
= extract32(insn
, 30, 1);
4339 TCGv_i64 tcg_rn
, tcg_rd
;
4342 /* Test all of sf=1, S=0, o2=0, o3=0. */
4343 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4344 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4345 unallocated_encoding(s
);
4349 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4354 tcg_rn
= cpu_reg_sp(s
, rn
);
4355 tcg_rd
= cpu_reg_sp(s
, rd
);
4358 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
,
4359 tcg_constant_i32(imm
),
4360 tcg_constant_i32(uimm4
));
4362 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4363 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4367 /* The input should be a value in the bottom e bits (with higher
4368 * bits zero); returns that value replicated into every element
4369 * of size e in a 64 bit integer.
4371 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4381 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4382 static inline uint64_t bitmask64(unsigned int length
)
4384 assert(length
> 0 && length
<= 64);
4385 return ~0ULL >> (64 - length
);
4388 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4389 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4390 * value (ie should cause a guest UNDEF exception), and true if they are
4391 * valid, in which case the decoded bit pattern is written to result.
4393 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4394 unsigned int imms
, unsigned int immr
)
4397 unsigned e
, levels
, s
, r
;
4400 assert(immn
< 2 && imms
< 64 && immr
< 64);
4402 /* The bit patterns we create here are 64 bit patterns which
4403 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4404 * 64 bits each. Each element contains the same value: a run
4405 * of between 1 and e-1 non-zero bits, rotated within the
4406 * element by between 0 and e-1 bits.
4408 * The element size and run length are encoded into immn (1 bit)
4409 * and imms (6 bits) as follows:
4410 * 64 bit elements: immn = 1, imms = <length of run - 1>
4411 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4412 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4413 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4414 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4415 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4416 * Notice that immn = 0, imms = 11111x is the only combination
4417 * not covered by one of the above options; this is reserved.
4418 * Further, <length of run - 1> all-ones is a reserved pattern.
4420 * In all cases the rotation is by immr % e (and immr is 6 bits).
4423 /* First determine the element size */
4424 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4426 /* This is the immn == 0, imms == 0x11111x case */
4436 /* <length of run - 1> mustn't be all-ones. */
4440 /* Create the value of one element: s+1 set bits rotated
4441 * by r within the element (which is e bits wide)...
4443 mask
= bitmask64(s
+ 1);
4445 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4446 mask
&= bitmask64(e
);
4448 /* ...then replicate the element over the whole 64 bit value */
4449 mask
= bitfield_replicate(mask
, e
);
4454 /* Logical (immediate)
4455 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4456 * +----+-----+-------------+---+------+------+------+------+
4457 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4458 * +----+-----+-------------+---+------+------+------+------+
4460 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4462 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4463 TCGv_i64 tcg_rd
, tcg_rn
;
4465 bool is_and
= false;
4467 sf
= extract32(insn
, 31, 1);
4468 opc
= extract32(insn
, 29, 2);
4469 is_n
= extract32(insn
, 22, 1);
4470 immr
= extract32(insn
, 16, 6);
4471 imms
= extract32(insn
, 10, 6);
4472 rn
= extract32(insn
, 5, 5);
4473 rd
= extract32(insn
, 0, 5);
4476 unallocated_encoding(s
);
4480 if (opc
== 0x3) { /* ANDS */
4481 tcg_rd
= cpu_reg(s
, rd
);
4483 tcg_rd
= cpu_reg_sp(s
, rd
);
4485 tcg_rn
= cpu_reg(s
, rn
);
4487 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4488 /* some immediate field values are reserved */
4489 unallocated_encoding(s
);
4494 wmask
&= 0xffffffff;
4498 case 0x3: /* ANDS */
4500 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4504 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4507 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4510 assert(FALSE
); /* must handle all above */
4514 if (!sf
&& !is_and
) {
4515 /* zero extend final result; we know we can skip this for AND
4516 * since the immediate had the high 32 bits clear.
4518 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4521 if (opc
== 3) { /* ANDS */
4522 gen_logic_CC(sf
, tcg_rd
);
4527 * Move wide (immediate)
4529 * 31 30 29 28 23 22 21 20 5 4 0
4530 * +--+-----+-------------+-----+----------------+------+
4531 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4532 * +--+-----+-------------+-----+----------------+------+
4534 * sf: 0 -> 32 bit, 1 -> 64 bit
4535 * opc: 00 -> N, 10 -> Z, 11 -> K
4536 * hw: shift/16 (0,16, and sf only 32, 48)
4538 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4540 int rd
= extract32(insn
, 0, 5);
4541 uint64_t imm
= extract32(insn
, 5, 16);
4542 int sf
= extract32(insn
, 31, 1);
4543 int opc
= extract32(insn
, 29, 2);
4544 int pos
= extract32(insn
, 21, 2) << 4;
4545 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4547 if (!sf
&& (pos
>= 32)) {
4548 unallocated_encoding(s
);
4562 tcg_gen_movi_i64(tcg_rd
, imm
);
4565 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_constant_i64(imm
), pos
, 16);
4567 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4571 unallocated_encoding(s
);
4577 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4578 * +----+-----+-------------+---+------+------+------+------+
4579 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4580 * +----+-----+-------------+---+------+------+------+------+
4582 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4584 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4585 TCGv_i64 tcg_rd
, tcg_tmp
;
4587 sf
= extract32(insn
, 31, 1);
4588 opc
= extract32(insn
, 29, 2);
4589 n
= extract32(insn
, 22, 1);
4590 ri
= extract32(insn
, 16, 6);
4591 si
= extract32(insn
, 10, 6);
4592 rn
= extract32(insn
, 5, 5);
4593 rd
= extract32(insn
, 0, 5);
4594 bitsize
= sf
? 64 : 32;
4596 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4597 unallocated_encoding(s
);
4601 tcg_rd
= cpu_reg(s
, rd
);
4603 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4604 to be smaller than bitsize, we'll never reference data outside the
4605 low 32-bits anyway. */
4606 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4608 /* Recognize simple(r) extractions. */
4610 /* Wd<s-r:0> = Wn<s:r> */
4611 len
= (si
- ri
) + 1;
4612 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4613 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4615 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4616 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4619 /* opc == 1, BFXIL fall through to deposit */
4620 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4623 /* Handle the ri > si case with a deposit
4624 * Wd<32+s-r,32-r> = Wn<s:0>
4627 pos
= (bitsize
- ri
) & (bitsize
- 1);
4630 if (opc
== 0 && len
< ri
) {
4631 /* SBFM: sign extend the destination field from len to fill
4632 the balance of the word. Let the deposit below insert all
4633 of those sign bits. */
4634 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4638 if (opc
== 1) { /* BFM, BFXIL */
4639 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4641 /* SBFM or UBFM: We start with zero, and we haven't modified
4642 any bits outside bitsize, therefore the zero-extension
4643 below is unneeded. */
4644 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4649 if (!sf
) { /* zero extend final result */
4650 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4655 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4656 * +----+------+-------------+---+----+------+--------+------+------+
4657 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4658 * +----+------+-------------+---+----+------+--------+------+------+
4660 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4662 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4664 sf
= extract32(insn
, 31, 1);
4665 n
= extract32(insn
, 22, 1);
4666 rm
= extract32(insn
, 16, 5);
4667 imm
= extract32(insn
, 10, 6);
4668 rn
= extract32(insn
, 5, 5);
4669 rd
= extract32(insn
, 0, 5);
4670 op21
= extract32(insn
, 29, 2);
4671 op0
= extract32(insn
, 21, 1);
4672 bitsize
= sf
? 64 : 32;
4674 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4675 unallocated_encoding(s
);
4677 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4679 tcg_rd
= cpu_reg(s
, rd
);
4681 if (unlikely(imm
== 0)) {
4682 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4683 * so an extract from bit 0 is a special case.
4686 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4688 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4691 tcg_rm
= cpu_reg(s
, rm
);
4692 tcg_rn
= cpu_reg(s
, rn
);
4695 /* Specialization to ROR happens in EXTRACT2. */
4696 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4698 TCGv_i32 t0
= tcg_temp_new_i32();
4700 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4702 tcg_gen_rotri_i32(t0
, t0
, imm
);
4704 TCGv_i32 t1
= tcg_temp_new_i32();
4705 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4706 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4707 tcg_temp_free_i32(t1
);
4709 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4710 tcg_temp_free_i32(t0
);
4716 /* Data processing - immediate */
4717 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4719 switch (extract32(insn
, 23, 6)) {
4720 case 0x20: case 0x21: /* PC-rel. addressing */
4721 disas_pc_rel_adr(s
, insn
);
4723 case 0x22: /* Add/subtract (immediate) */
4724 disas_add_sub_imm(s
, insn
);
4726 case 0x23: /* Add/subtract (immediate, with tags) */
4727 disas_add_sub_imm_with_tags(s
, insn
);
4729 case 0x24: /* Logical (immediate) */
4730 disas_logic_imm(s
, insn
);
4732 case 0x25: /* Move wide (immediate) */
4733 disas_movw_imm(s
, insn
);
4735 case 0x26: /* Bitfield */
4736 disas_bitfield(s
, insn
);
4738 case 0x27: /* Extract */
4739 disas_extract(s
, insn
);
4742 unallocated_encoding(s
);
4747 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4748 * Note that it is the caller's responsibility to ensure that the
4749 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4750 * mandated semantics for out of range shifts.
4752 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4753 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4755 switch (shift_type
) {
4756 case A64_SHIFT_TYPE_LSL
:
4757 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4759 case A64_SHIFT_TYPE_LSR
:
4760 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4762 case A64_SHIFT_TYPE_ASR
:
4764 tcg_gen_ext32s_i64(dst
, src
);
4766 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4768 case A64_SHIFT_TYPE_ROR
:
4770 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4773 t0
= tcg_temp_new_i32();
4774 t1
= tcg_temp_new_i32();
4775 tcg_gen_extrl_i64_i32(t0
, src
);
4776 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4777 tcg_gen_rotr_i32(t0
, t0
, t1
);
4778 tcg_gen_extu_i32_i64(dst
, t0
);
4779 tcg_temp_free_i32(t0
);
4780 tcg_temp_free_i32(t1
);
4784 assert(FALSE
); /* all shift types should be handled */
4788 if (!sf
) { /* zero extend final result */
4789 tcg_gen_ext32u_i64(dst
, dst
);
4793 /* Shift a TCGv src by immediate, put result in dst.
4794 * The shift amount must be in range (this should always be true as the
4795 * relevant instructions will UNDEF on bad shift immediates).
4797 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4798 enum a64_shift_type shift_type
, unsigned int shift_i
)
4800 assert(shift_i
< (sf
? 64 : 32));
4803 tcg_gen_mov_i64(dst
, src
);
4805 shift_reg(dst
, src
, sf
, shift_type
, tcg_constant_i64(shift_i
));
4809 /* Logical (shifted register)
4810 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4811 * +----+-----+-----------+-------+---+------+--------+------+------+
4812 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4813 * +----+-----+-----------+-------+---+------+--------+------+------+
4815 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4817 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4818 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4820 sf
= extract32(insn
, 31, 1);
4821 opc
= extract32(insn
, 29, 2);
4822 shift_type
= extract32(insn
, 22, 2);
4823 invert
= extract32(insn
, 21, 1);
4824 rm
= extract32(insn
, 16, 5);
4825 shift_amount
= extract32(insn
, 10, 6);
4826 rn
= extract32(insn
, 5, 5);
4827 rd
= extract32(insn
, 0, 5);
4829 if (!sf
&& (shift_amount
& (1 << 5))) {
4830 unallocated_encoding(s
);
4834 tcg_rd
= cpu_reg(s
, rd
);
4836 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4837 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4838 * register-register MOV and MVN, so it is worth special casing.
4840 tcg_rm
= cpu_reg(s
, rm
);
4842 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4844 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4848 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4850 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4856 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4859 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4862 tcg_rn
= cpu_reg(s
, rn
);
4864 switch (opc
| (invert
<< 2)) {
4867 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4870 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4873 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4877 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4880 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4883 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4891 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4895 gen_logic_CC(sf
, tcg_rd
);
4900 * Add/subtract (extended register)
4902 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4903 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4904 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4905 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4907 * sf: 0 -> 32bit, 1 -> 64bit
4908 * op: 0 -> add , 1 -> sub
4911 * option: extension type (see DecodeRegExtend)
4912 * imm3: optional shift to Rm
4914 * Rd = Rn + LSL(extend(Rm), amount)
4916 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4918 int rd
= extract32(insn
, 0, 5);
4919 int rn
= extract32(insn
, 5, 5);
4920 int imm3
= extract32(insn
, 10, 3);
4921 int option
= extract32(insn
, 13, 3);
4922 int rm
= extract32(insn
, 16, 5);
4923 int opt
= extract32(insn
, 22, 2);
4924 bool setflags
= extract32(insn
, 29, 1);
4925 bool sub_op
= extract32(insn
, 30, 1);
4926 bool sf
= extract32(insn
, 31, 1);
4928 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4930 TCGv_i64 tcg_result
;
4932 if (imm3
> 4 || opt
!= 0) {
4933 unallocated_encoding(s
);
4937 /* non-flag setting ops may use SP */
4939 tcg_rd
= cpu_reg_sp(s
, rd
);
4941 tcg_rd
= cpu_reg(s
, rd
);
4943 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4945 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4946 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4948 tcg_result
= tcg_temp_new_i64();
4952 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4954 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4958 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4960 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4965 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4967 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4970 tcg_temp_free_i64(tcg_result
);
4974 * Add/subtract (shifted register)
4976 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4977 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4978 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4979 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4981 * sf: 0 -> 32bit, 1 -> 64bit
4982 * op: 0 -> add , 1 -> sub
4984 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4985 * imm6: Shift amount to apply to Rm before the add/sub
4987 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4989 int rd
= extract32(insn
, 0, 5);
4990 int rn
= extract32(insn
, 5, 5);
4991 int imm6
= extract32(insn
, 10, 6);
4992 int rm
= extract32(insn
, 16, 5);
4993 int shift_type
= extract32(insn
, 22, 2);
4994 bool setflags
= extract32(insn
, 29, 1);
4995 bool sub_op
= extract32(insn
, 30, 1);
4996 bool sf
= extract32(insn
, 31, 1);
4998 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4999 TCGv_i64 tcg_rn
, tcg_rm
;
5000 TCGv_i64 tcg_result
;
5002 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
5003 unallocated_encoding(s
);
5007 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5008 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
5010 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
5012 tcg_result
= tcg_temp_new_i64();
5016 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
5018 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
5022 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
5024 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
5029 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
5031 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
5034 tcg_temp_free_i64(tcg_result
);
5037 /* Data-processing (3 source)
5039 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
5040 * +--+------+-----------+------+------+----+------+------+------+
5041 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
5042 * +--+------+-----------+------+------+----+------+------+------+
5044 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
5046 int rd
= extract32(insn
, 0, 5);
5047 int rn
= extract32(insn
, 5, 5);
5048 int ra
= extract32(insn
, 10, 5);
5049 int rm
= extract32(insn
, 16, 5);
5050 int op_id
= (extract32(insn
, 29, 3) << 4) |
5051 (extract32(insn
, 21, 3) << 1) |
5052 extract32(insn
, 15, 1);
5053 bool sf
= extract32(insn
, 31, 1);
5054 bool is_sub
= extract32(op_id
, 0, 1);
5055 bool is_high
= extract32(op_id
, 2, 1);
5056 bool is_signed
= false;
5061 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
5063 case 0x42: /* SMADDL */
5064 case 0x43: /* SMSUBL */
5065 case 0x44: /* SMULH */
5068 case 0x0: /* MADD (32bit) */
5069 case 0x1: /* MSUB (32bit) */
5070 case 0x40: /* MADD (64bit) */
5071 case 0x41: /* MSUB (64bit) */
5072 case 0x4a: /* UMADDL */
5073 case 0x4b: /* UMSUBL */
5074 case 0x4c: /* UMULH */
5077 unallocated_encoding(s
);
5082 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5083 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5084 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5085 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5088 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5090 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5093 tcg_temp_free_i64(low_bits
);
5097 tcg_op1
= tcg_temp_new_i64();
5098 tcg_op2
= tcg_temp_new_i64();
5099 tcg_tmp
= tcg_temp_new_i64();
5102 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5103 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5106 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5107 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5109 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5110 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5114 if (ra
== 31 && !is_sub
) {
5115 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5116 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5118 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5120 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5122 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5127 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5130 tcg_temp_free_i64(tcg_op1
);
5131 tcg_temp_free_i64(tcg_op2
);
5132 tcg_temp_free_i64(tcg_tmp
);
5135 /* Add/subtract (with carry)
5136 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5137 * +--+--+--+------------------------+------+-------------+------+-----+
5138 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5139 * +--+--+--+------------------------+------+-------------+------+-----+
5142 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5144 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5145 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5147 sf
= extract32(insn
, 31, 1);
5148 op
= extract32(insn
, 30, 1);
5149 setflags
= extract32(insn
, 29, 1);
5150 rm
= extract32(insn
, 16, 5);
5151 rn
= extract32(insn
, 5, 5);
5152 rd
= extract32(insn
, 0, 5);
5154 tcg_rd
= cpu_reg(s
, rd
);
5155 tcg_rn
= cpu_reg(s
, rn
);
5158 tcg_y
= new_tmp_a64(s
);
5159 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5161 tcg_y
= cpu_reg(s
, rm
);
5165 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5167 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5172 * Rotate right into flags
5173 * 31 30 29 21 15 10 5 4 0
5174 * +--+--+--+-----------------+--------+-----------+------+--+------+
5175 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5176 * +--+--+--+-----------------+--------+-----------+------+--+------+
5178 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5180 int mask
= extract32(insn
, 0, 4);
5181 int o2
= extract32(insn
, 4, 1);
5182 int rn
= extract32(insn
, 5, 5);
5183 int imm6
= extract32(insn
, 15, 6);
5184 int sf_op_s
= extract32(insn
, 29, 3);
5188 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5189 unallocated_encoding(s
);
5193 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5194 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5196 nzcv
= tcg_temp_new_i32();
5197 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5199 if (mask
& 8) { /* N */
5200 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5202 if (mask
& 4) { /* Z */
5203 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5204 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5206 if (mask
& 2) { /* C */
5207 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5209 if (mask
& 1) { /* V */
5210 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5213 tcg_temp_free_i32(nzcv
);
5217 * Evaluate into flags
5218 * 31 30 29 21 15 14 10 5 4 0
5219 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5220 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5221 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5223 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5225 int o3_mask
= extract32(insn
, 0, 5);
5226 int rn
= extract32(insn
, 5, 5);
5227 int o2
= extract32(insn
, 15, 6);
5228 int sz
= extract32(insn
, 14, 1);
5229 int sf_op_s
= extract32(insn
, 29, 3);
5233 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5234 !dc_isar_feature(aa64_condm_4
, s
)) {
5235 unallocated_encoding(s
);
5238 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5240 tmp
= tcg_temp_new_i32();
5241 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5242 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5243 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5244 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5245 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5246 tcg_temp_free_i32(tmp
);
5249 /* Conditional compare (immediate / register)
5250 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5251 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5252 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5253 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5256 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5258 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5259 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5260 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5263 if (!extract32(insn
, 29, 1)) {
5264 unallocated_encoding(s
);
5267 if (insn
& (1 << 10 | 1 << 4)) {
5268 unallocated_encoding(s
);
5271 sf
= extract32(insn
, 31, 1);
5272 op
= extract32(insn
, 30, 1);
5273 is_imm
= extract32(insn
, 11, 1);
5274 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5275 cond
= extract32(insn
, 12, 4);
5276 rn
= extract32(insn
, 5, 5);
5277 nzcv
= extract32(insn
, 0, 4);
5279 /* Set T0 = !COND. */
5280 tcg_t0
= tcg_temp_new_i32();
5281 arm_test_cc(&c
, cond
);
5282 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5285 /* Load the arguments for the new comparison. */
5287 tcg_y
= new_tmp_a64(s
);
5288 tcg_gen_movi_i64(tcg_y
, y
);
5290 tcg_y
= cpu_reg(s
, y
);
5292 tcg_rn
= cpu_reg(s
, rn
);
5294 /* Set the flags for the new comparison. */
5295 tcg_tmp
= tcg_temp_new_i64();
5297 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5299 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5301 tcg_temp_free_i64(tcg_tmp
);
5303 /* If COND was false, force the flags to #nzcv. Compute two masks
5304 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5305 * For tcg hosts that support ANDC, we can make do with just T1.
5306 * In either case, allow the tcg optimizer to delete any unused mask.
5308 tcg_t1
= tcg_temp_new_i32();
5309 tcg_t2
= tcg_temp_new_i32();
5310 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5311 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5313 if (nzcv
& 8) { /* N */
5314 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5316 if (TCG_TARGET_HAS_andc_i32
) {
5317 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5319 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5322 if (nzcv
& 4) { /* Z */
5323 if (TCG_TARGET_HAS_andc_i32
) {
5324 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5326 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5329 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5331 if (nzcv
& 2) { /* C */
5332 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5334 if (TCG_TARGET_HAS_andc_i32
) {
5335 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5337 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5340 if (nzcv
& 1) { /* V */
5341 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5343 if (TCG_TARGET_HAS_andc_i32
) {
5344 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5346 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5349 tcg_temp_free_i32(tcg_t0
);
5350 tcg_temp_free_i32(tcg_t1
);
5351 tcg_temp_free_i32(tcg_t2
);
5354 /* Conditional select
5355 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5356 * +----+----+---+-----------------+------+------+-----+------+------+
5357 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5358 * +----+----+---+-----------------+------+------+-----+------+------+
5360 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5362 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5363 TCGv_i64 tcg_rd
, zero
;
5366 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5367 /* S == 1 or op2<1> == 1 */
5368 unallocated_encoding(s
);
5371 sf
= extract32(insn
, 31, 1);
5372 else_inv
= extract32(insn
, 30, 1);
5373 rm
= extract32(insn
, 16, 5);
5374 cond
= extract32(insn
, 12, 4);
5375 else_inc
= extract32(insn
, 10, 1);
5376 rn
= extract32(insn
, 5, 5);
5377 rd
= extract32(insn
, 0, 5);
5379 tcg_rd
= cpu_reg(s
, rd
);
5381 a64_test_cc(&c
, cond
);
5382 zero
= tcg_constant_i64(0);
5384 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5386 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5388 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5391 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5392 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5393 if (else_inv
&& else_inc
) {
5394 tcg_gen_neg_i64(t_false
, t_false
);
5395 } else if (else_inv
) {
5396 tcg_gen_not_i64(t_false
, t_false
);
5397 } else if (else_inc
) {
5398 tcg_gen_addi_i64(t_false
, t_false
, 1);
5400 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5406 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5410 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5411 unsigned int rn
, unsigned int rd
)
5413 TCGv_i64 tcg_rd
, tcg_rn
;
5414 tcg_rd
= cpu_reg(s
, rd
);
5415 tcg_rn
= cpu_reg(s
, rn
);
5418 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5420 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5421 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5422 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5423 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5424 tcg_temp_free_i32(tcg_tmp32
);
5428 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5429 unsigned int rn
, unsigned int rd
)
5431 TCGv_i64 tcg_rd
, tcg_rn
;
5432 tcg_rd
= cpu_reg(s
, rd
);
5433 tcg_rn
= cpu_reg(s
, rn
);
5436 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5438 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5439 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5440 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5441 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5442 tcg_temp_free_i32(tcg_tmp32
);
5446 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5447 unsigned int rn
, unsigned int rd
)
5449 TCGv_i64 tcg_rd
, tcg_rn
;
5450 tcg_rd
= cpu_reg(s
, rd
);
5451 tcg_rn
= cpu_reg(s
, rn
);
5454 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5456 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5457 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5458 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5459 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5460 tcg_temp_free_i32(tcg_tmp32
);
5464 /* REV with sf==1, opcode==3 ("REV64") */
5465 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5466 unsigned int rn
, unsigned int rd
)
5469 unallocated_encoding(s
);
5472 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5475 /* REV with sf==0, opcode==2
5476 * REV32 (sf==1, opcode==2)
5478 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5479 unsigned int rn
, unsigned int rd
)
5481 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5482 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5485 tcg_gen_bswap64_i64(tcg_rd
, tcg_rn
);
5486 tcg_gen_rotri_i64(tcg_rd
, tcg_rd
, 32);
5488 tcg_gen_bswap32_i64(tcg_rd
, tcg_rn
, TCG_BSWAP_OZ
);
5492 /* REV16 (opcode==1) */
5493 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5494 unsigned int rn
, unsigned int rd
)
5496 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5497 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5498 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5499 TCGv_i64 mask
= tcg_constant_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5501 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5502 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5503 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5504 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5505 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5507 tcg_temp_free_i64(tcg_tmp
);
5510 /* Data-processing (1 source)
5511 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5512 * +----+---+---+-----------------+---------+--------+------+------+
5513 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5514 * +----+---+---+-----------------+---------+--------+------+------+
5516 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5518 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5521 if (extract32(insn
, 29, 1)) {
5522 unallocated_encoding(s
);
5526 sf
= extract32(insn
, 31, 1);
5527 opcode
= extract32(insn
, 10, 6);
5528 opcode2
= extract32(insn
, 16, 5);
5529 rn
= extract32(insn
, 5, 5);
5530 rd
= extract32(insn
, 0, 5);
5532 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5534 switch (MAP(sf
, opcode2
, opcode
)) {
5535 case MAP(0, 0x00, 0x00): /* RBIT */
5536 case MAP(1, 0x00, 0x00):
5537 handle_rbit(s
, sf
, rn
, rd
);
5539 case MAP(0, 0x00, 0x01): /* REV16 */
5540 case MAP(1, 0x00, 0x01):
5541 handle_rev16(s
, sf
, rn
, rd
);
5543 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5544 case MAP(1, 0x00, 0x02):
5545 handle_rev32(s
, sf
, rn
, rd
);
5547 case MAP(1, 0x00, 0x03): /* REV64 */
5548 handle_rev64(s
, sf
, rn
, rd
);
5550 case MAP(0, 0x00, 0x04): /* CLZ */
5551 case MAP(1, 0x00, 0x04):
5552 handle_clz(s
, sf
, rn
, rd
);
5554 case MAP(0, 0x00, 0x05): /* CLS */
5555 case MAP(1, 0x00, 0x05):
5556 handle_cls(s
, sf
, rn
, rd
);
5558 case MAP(1, 0x01, 0x00): /* PACIA */
5559 if (s
->pauth_active
) {
5560 tcg_rd
= cpu_reg(s
, rd
);
5561 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5562 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5563 goto do_unallocated
;
5566 case MAP(1, 0x01, 0x01): /* PACIB */
5567 if (s
->pauth_active
) {
5568 tcg_rd
= cpu_reg(s
, rd
);
5569 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5570 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5571 goto do_unallocated
;
5574 case MAP(1, 0x01, 0x02): /* PACDA */
5575 if (s
->pauth_active
) {
5576 tcg_rd
= cpu_reg(s
, rd
);
5577 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5578 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5579 goto do_unallocated
;
5582 case MAP(1, 0x01, 0x03): /* PACDB */
5583 if (s
->pauth_active
) {
5584 tcg_rd
= cpu_reg(s
, rd
);
5585 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5586 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5587 goto do_unallocated
;
5590 case MAP(1, 0x01, 0x04): /* AUTIA */
5591 if (s
->pauth_active
) {
5592 tcg_rd
= cpu_reg(s
, rd
);
5593 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5594 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5595 goto do_unallocated
;
5598 case MAP(1, 0x01, 0x05): /* AUTIB */
5599 if (s
->pauth_active
) {
5600 tcg_rd
= cpu_reg(s
, rd
);
5601 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5602 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5603 goto do_unallocated
;
5606 case MAP(1, 0x01, 0x06): /* AUTDA */
5607 if (s
->pauth_active
) {
5608 tcg_rd
= cpu_reg(s
, rd
);
5609 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5610 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5611 goto do_unallocated
;
5614 case MAP(1, 0x01, 0x07): /* AUTDB */
5615 if (s
->pauth_active
) {
5616 tcg_rd
= cpu_reg(s
, rd
);
5617 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5618 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5619 goto do_unallocated
;
5622 case MAP(1, 0x01, 0x08): /* PACIZA */
5623 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5624 goto do_unallocated
;
5625 } else if (s
->pauth_active
) {
5626 tcg_rd
= cpu_reg(s
, rd
);
5627 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5630 case MAP(1, 0x01, 0x09): /* PACIZB */
5631 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5632 goto do_unallocated
;
5633 } else if (s
->pauth_active
) {
5634 tcg_rd
= cpu_reg(s
, rd
);
5635 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5638 case MAP(1, 0x01, 0x0a): /* PACDZA */
5639 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5640 goto do_unallocated
;
5641 } else if (s
->pauth_active
) {
5642 tcg_rd
= cpu_reg(s
, rd
);
5643 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5646 case MAP(1, 0x01, 0x0b): /* PACDZB */
5647 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5648 goto do_unallocated
;
5649 } else if (s
->pauth_active
) {
5650 tcg_rd
= cpu_reg(s
, rd
);
5651 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5654 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5655 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5656 goto do_unallocated
;
5657 } else if (s
->pauth_active
) {
5658 tcg_rd
= cpu_reg(s
, rd
);
5659 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5662 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5663 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5664 goto do_unallocated
;
5665 } else if (s
->pauth_active
) {
5666 tcg_rd
= cpu_reg(s
, rd
);
5667 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5670 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5671 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5672 goto do_unallocated
;
5673 } else if (s
->pauth_active
) {
5674 tcg_rd
= cpu_reg(s
, rd
);
5675 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5678 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5679 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5680 goto do_unallocated
;
5681 } else if (s
->pauth_active
) {
5682 tcg_rd
= cpu_reg(s
, rd
);
5683 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5686 case MAP(1, 0x01, 0x10): /* XPACI */
5687 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5688 goto do_unallocated
;
5689 } else if (s
->pauth_active
) {
5690 tcg_rd
= cpu_reg(s
, rd
);
5691 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5694 case MAP(1, 0x01, 0x11): /* XPACD */
5695 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5696 goto do_unallocated
;
5697 } else if (s
->pauth_active
) {
5698 tcg_rd
= cpu_reg(s
, rd
);
5699 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5704 unallocated_encoding(s
);
5711 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5712 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5714 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5715 tcg_rd
= cpu_reg(s
, rd
);
5717 if (!sf
&& is_signed
) {
5718 tcg_n
= new_tmp_a64(s
);
5719 tcg_m
= new_tmp_a64(s
);
5720 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5721 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5723 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5724 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5728 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5730 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5733 if (!sf
) { /* zero extend final result */
5734 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5738 /* LSLV, LSRV, ASRV, RORV */
5739 static void handle_shift_reg(DisasContext
*s
,
5740 enum a64_shift_type shift_type
, unsigned int sf
,
5741 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5743 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5744 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5745 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5747 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5748 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5749 tcg_temp_free_i64(tcg_shift
);
5752 /* CRC32[BHWX], CRC32C[BHWX] */
5753 static void handle_crc32(DisasContext
*s
,
5754 unsigned int sf
, unsigned int sz
, bool crc32c
,
5755 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5757 TCGv_i64 tcg_acc
, tcg_val
;
5760 if (!dc_isar_feature(aa64_crc32
, s
)
5761 || (sf
== 1 && sz
!= 3)
5762 || (sf
== 0 && sz
== 3)) {
5763 unallocated_encoding(s
);
5768 tcg_val
= cpu_reg(s
, rm
);
5782 g_assert_not_reached();
5784 tcg_val
= new_tmp_a64(s
);
5785 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5788 tcg_acc
= cpu_reg(s
, rn
);
5789 tcg_bytes
= tcg_constant_i32(1 << sz
);
5792 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5794 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5798 /* Data-processing (2 source)
5799 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5800 * +----+---+---+-----------------+------+--------+------+------+
5801 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5802 * +----+---+---+-----------------+------+--------+------+------+
5804 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5806 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5807 sf
= extract32(insn
, 31, 1);
5808 setflag
= extract32(insn
, 29, 1);
5809 rm
= extract32(insn
, 16, 5);
5810 opcode
= extract32(insn
, 10, 6);
5811 rn
= extract32(insn
, 5, 5);
5812 rd
= extract32(insn
, 0, 5);
5814 if (setflag
&& opcode
!= 0) {
5815 unallocated_encoding(s
);
5820 case 0: /* SUBP(S) */
5821 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5822 goto do_unallocated
;
5824 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5826 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5827 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5828 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5829 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5830 tcg_d
= cpu_reg(s
, rd
);
5833 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5835 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5840 handle_div(s
, false, sf
, rm
, rn
, rd
);
5843 handle_div(s
, true, sf
, rm
, rn
, rd
);
5846 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5847 goto do_unallocated
;
5850 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5851 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5853 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5858 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5859 goto do_unallocated
;
5861 TCGv_i64 t
= tcg_temp_new_i64();
5863 tcg_gen_extract_i64(t
, cpu_reg_sp(s
, rn
), 56, 4);
5864 tcg_gen_shl_i64(t
, tcg_constant_i64(1), t
);
5865 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t
);
5867 tcg_temp_free_i64(t
);
5871 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5874 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5877 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5880 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5882 case 12: /* PACGA */
5883 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5884 goto do_unallocated
;
5886 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5887 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5896 case 23: /* CRC32 */
5898 int sz
= extract32(opcode
, 0, 2);
5899 bool crc32c
= extract32(opcode
, 2, 1);
5900 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5905 unallocated_encoding(s
);
5911 * Data processing - register
5912 * 31 30 29 28 25 21 20 16 10 0
5913 * +--+---+--+---+-------+-----+-------+-------+---------+
5914 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5915 * +--+---+--+---+-------+-----+-------+-------+---------+
5917 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5919 int op0
= extract32(insn
, 30, 1);
5920 int op1
= extract32(insn
, 28, 1);
5921 int op2
= extract32(insn
, 21, 4);
5922 int op3
= extract32(insn
, 10, 6);
5927 /* Add/sub (extended register) */
5928 disas_add_sub_ext_reg(s
, insn
);
5930 /* Add/sub (shifted register) */
5931 disas_add_sub_reg(s
, insn
);
5934 /* Logical (shifted register) */
5935 disas_logic_reg(s
, insn
);
5943 case 0x00: /* Add/subtract (with carry) */
5944 disas_adc_sbc(s
, insn
);
5947 case 0x01: /* Rotate right into flags */
5949 disas_rotate_right_into_flags(s
, insn
);
5952 case 0x02: /* Evaluate into flags */
5956 disas_evaluate_into_flags(s
, insn
);
5960 goto do_unallocated
;
5964 case 0x2: /* Conditional compare */
5965 disas_cc(s
, insn
); /* both imm and reg forms */
5968 case 0x4: /* Conditional select */
5969 disas_cond_select(s
, insn
);
5972 case 0x6: /* Data-processing */
5973 if (op0
) { /* (1 source) */
5974 disas_data_proc_1src(s
, insn
);
5975 } else { /* (2 source) */
5976 disas_data_proc_2src(s
, insn
);
5979 case 0x8 ... 0xf: /* (3 source) */
5980 disas_data_proc_3src(s
, insn
);
5985 unallocated_encoding(s
);
5990 static void handle_fp_compare(DisasContext
*s
, int size
,
5991 unsigned int rn
, unsigned int rm
,
5992 bool cmp_with_zero
, bool signal_all_nans
)
5994 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5995 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5997 if (size
== MO_64
) {
5998 TCGv_i64 tcg_vn
, tcg_vm
;
6000 tcg_vn
= read_fp_dreg(s
, rn
);
6001 if (cmp_with_zero
) {
6002 tcg_vm
= tcg_constant_i64(0);
6004 tcg_vm
= read_fp_dreg(s
, rm
);
6006 if (signal_all_nans
) {
6007 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6009 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6011 tcg_temp_free_i64(tcg_vn
);
6012 tcg_temp_free_i64(tcg_vm
);
6014 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
6015 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
6017 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
6018 if (cmp_with_zero
) {
6019 tcg_gen_movi_i32(tcg_vm
, 0);
6021 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
6026 if (signal_all_nans
) {
6027 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6029 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6033 if (signal_all_nans
) {
6034 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6036 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
6040 g_assert_not_reached();
6043 tcg_temp_free_i32(tcg_vn
);
6044 tcg_temp_free_i32(tcg_vm
);
6047 tcg_temp_free_ptr(fpst
);
6049 gen_set_nzcv(tcg_flags
);
6051 tcg_temp_free_i64(tcg_flags
);
6054 /* Floating point compare
6055 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
6056 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6057 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
6058 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
6060 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
6062 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6065 mos
= extract32(insn
, 29, 3);
6066 type
= extract32(insn
, 22, 2);
6067 rm
= extract32(insn
, 16, 5);
6068 op
= extract32(insn
, 14, 2);
6069 rn
= extract32(insn
, 5, 5);
6070 opc
= extract32(insn
, 3, 2);
6071 op2r
= extract32(insn
, 0, 3);
6073 if (mos
|| op
|| op2r
) {
6074 unallocated_encoding(s
);
6087 if (dc_isar_feature(aa64_fp16
, s
)) {
6092 unallocated_encoding(s
);
6096 if (!fp_access_check(s
)) {
6100 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6103 /* Floating point conditional compare
6104 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6105 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6106 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6107 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6109 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6111 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6112 TCGLabel
*label_continue
= NULL
;
6115 mos
= extract32(insn
, 29, 3);
6116 type
= extract32(insn
, 22, 2);
6117 rm
= extract32(insn
, 16, 5);
6118 cond
= extract32(insn
, 12, 4);
6119 rn
= extract32(insn
, 5, 5);
6120 op
= extract32(insn
, 4, 1);
6121 nzcv
= extract32(insn
, 0, 4);
6124 unallocated_encoding(s
);
6137 if (dc_isar_feature(aa64_fp16
, s
)) {
6142 unallocated_encoding(s
);
6146 if (!fp_access_check(s
)) {
6150 if (cond
< 0x0e) { /* not always */
6151 TCGLabel
*label_match
= gen_new_label();
6152 label_continue
= gen_new_label();
6153 arm_gen_test_cc(cond
, label_match
);
6155 gen_set_nzcv(tcg_constant_i64(nzcv
<< 28));
6156 tcg_gen_br(label_continue
);
6157 gen_set_label(label_match
);
6160 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6163 gen_set_label(label_continue
);
6167 /* Floating point conditional select
6168 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6169 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6170 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6171 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6173 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6175 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6176 TCGv_i64 t_true
, t_false
;
6180 mos
= extract32(insn
, 29, 3);
6181 type
= extract32(insn
, 22, 2);
6182 rm
= extract32(insn
, 16, 5);
6183 cond
= extract32(insn
, 12, 4);
6184 rn
= extract32(insn
, 5, 5);
6185 rd
= extract32(insn
, 0, 5);
6188 unallocated_encoding(s
);
6201 if (dc_isar_feature(aa64_fp16
, s
)) {
6206 unallocated_encoding(s
);
6210 if (!fp_access_check(s
)) {
6214 /* Zero extend sreg & hreg inputs to 64 bits now. */
6215 t_true
= tcg_temp_new_i64();
6216 t_false
= tcg_temp_new_i64();
6217 read_vec_element(s
, t_true
, rn
, 0, sz
);
6218 read_vec_element(s
, t_false
, rm
, 0, sz
);
6220 a64_test_cc(&c
, cond
);
6221 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, tcg_constant_i64(0),
6223 tcg_temp_free_i64(t_false
);
6226 /* Note that sregs & hregs write back zeros to the high bits,
6227 and we've already done the zero-extension. */
6228 write_fp_dreg(s
, rd
, t_true
);
6229 tcg_temp_free_i64(t_true
);
6232 /* Floating-point data-processing (1 source) - half precision */
6233 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6235 TCGv_ptr fpst
= NULL
;
6236 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6237 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6240 case 0x0: /* FMOV */
6241 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6243 case 0x1: /* FABS */
6244 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6246 case 0x2: /* FNEG */
6247 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6249 case 0x3: /* FSQRT */
6250 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6251 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6253 case 0x8: /* FRINTN */
6254 case 0x9: /* FRINTP */
6255 case 0xa: /* FRINTM */
6256 case 0xb: /* FRINTZ */
6257 case 0xc: /* FRINTA */
6259 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6260 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6262 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6263 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6265 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6266 tcg_temp_free_i32(tcg_rmode
);
6269 case 0xe: /* FRINTX */
6270 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6271 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6273 case 0xf: /* FRINTI */
6274 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6275 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6278 g_assert_not_reached();
6281 write_fp_sreg(s
, rd
, tcg_res
);
6284 tcg_temp_free_ptr(fpst
);
6286 tcg_temp_free_i32(tcg_op
);
6287 tcg_temp_free_i32(tcg_res
);
6290 /* Floating-point data-processing (1 source) - single precision */
6291 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6293 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6294 TCGv_i32 tcg_op
, tcg_res
;
6298 tcg_op
= read_fp_sreg(s
, rn
);
6299 tcg_res
= tcg_temp_new_i32();
6302 case 0x0: /* FMOV */
6303 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6305 case 0x1: /* FABS */
6306 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6308 case 0x2: /* FNEG */
6309 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6311 case 0x3: /* FSQRT */
6312 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6314 case 0x6: /* BFCVT */
6315 gen_fpst
= gen_helper_bfcvt
;
6317 case 0x8: /* FRINTN */
6318 case 0x9: /* FRINTP */
6319 case 0xa: /* FRINTM */
6320 case 0xb: /* FRINTZ */
6321 case 0xc: /* FRINTA */
6322 rmode
= arm_rmode_to_sf(opcode
& 7);
6323 gen_fpst
= gen_helper_rints
;
6325 case 0xe: /* FRINTX */
6326 gen_fpst
= gen_helper_rints_exact
;
6328 case 0xf: /* FRINTI */
6329 gen_fpst
= gen_helper_rints
;
6331 case 0x10: /* FRINT32Z */
6332 rmode
= float_round_to_zero
;
6333 gen_fpst
= gen_helper_frint32_s
;
6335 case 0x11: /* FRINT32X */
6336 gen_fpst
= gen_helper_frint32_s
;
6338 case 0x12: /* FRINT64Z */
6339 rmode
= float_round_to_zero
;
6340 gen_fpst
= gen_helper_frint64_s
;
6342 case 0x13: /* FRINT64X */
6343 gen_fpst
= gen_helper_frint64_s
;
6346 g_assert_not_reached();
6349 fpst
= fpstatus_ptr(FPST_FPCR
);
6351 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6352 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6353 gen_fpst(tcg_res
, tcg_op
, fpst
);
6354 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6355 tcg_temp_free_i32(tcg_rmode
);
6357 gen_fpst(tcg_res
, tcg_op
, fpst
);
6359 tcg_temp_free_ptr(fpst
);
6362 write_fp_sreg(s
, rd
, tcg_res
);
6363 tcg_temp_free_i32(tcg_op
);
6364 tcg_temp_free_i32(tcg_res
);
6367 /* Floating-point data-processing (1 source) - double precision */
6368 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6370 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6371 TCGv_i64 tcg_op
, tcg_res
;
6376 case 0x0: /* FMOV */
6377 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6381 tcg_op
= read_fp_dreg(s
, rn
);
6382 tcg_res
= tcg_temp_new_i64();
6385 case 0x1: /* FABS */
6386 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6388 case 0x2: /* FNEG */
6389 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6391 case 0x3: /* FSQRT */
6392 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6394 case 0x8: /* FRINTN */
6395 case 0x9: /* FRINTP */
6396 case 0xa: /* FRINTM */
6397 case 0xb: /* FRINTZ */
6398 case 0xc: /* FRINTA */
6399 rmode
= arm_rmode_to_sf(opcode
& 7);
6400 gen_fpst
= gen_helper_rintd
;
6402 case 0xe: /* FRINTX */
6403 gen_fpst
= gen_helper_rintd_exact
;
6405 case 0xf: /* FRINTI */
6406 gen_fpst
= gen_helper_rintd
;
6408 case 0x10: /* FRINT32Z */
6409 rmode
= float_round_to_zero
;
6410 gen_fpst
= gen_helper_frint32_d
;
6412 case 0x11: /* FRINT32X */
6413 gen_fpst
= gen_helper_frint32_d
;
6415 case 0x12: /* FRINT64Z */
6416 rmode
= float_round_to_zero
;
6417 gen_fpst
= gen_helper_frint64_d
;
6419 case 0x13: /* FRINT64X */
6420 gen_fpst
= gen_helper_frint64_d
;
6423 g_assert_not_reached();
6426 fpst
= fpstatus_ptr(FPST_FPCR
);
6428 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6429 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6430 gen_fpst(tcg_res
, tcg_op
, fpst
);
6431 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6432 tcg_temp_free_i32(tcg_rmode
);
6434 gen_fpst(tcg_res
, tcg_op
, fpst
);
6436 tcg_temp_free_ptr(fpst
);
6439 write_fp_dreg(s
, rd
, tcg_res
);
6440 tcg_temp_free_i64(tcg_op
);
6441 tcg_temp_free_i64(tcg_res
);
6444 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6445 int rd
, int rn
, int dtype
, int ntype
)
6450 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6452 /* Single to double */
6453 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6454 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6455 write_fp_dreg(s
, rd
, tcg_rd
);
6456 tcg_temp_free_i64(tcg_rd
);
6458 /* Single to half */
6459 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6460 TCGv_i32 ahp
= get_ahp_flag();
6461 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6463 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6464 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6465 write_fp_sreg(s
, rd
, tcg_rd
);
6466 tcg_temp_free_i32(tcg_rd
);
6467 tcg_temp_free_i32(ahp
);
6468 tcg_temp_free_ptr(fpst
);
6470 tcg_temp_free_i32(tcg_rn
);
6475 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6476 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6478 /* Double to single */
6479 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6481 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6482 TCGv_i32 ahp
= get_ahp_flag();
6483 /* Double to half */
6484 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6485 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6486 tcg_temp_free_ptr(fpst
);
6487 tcg_temp_free_i32(ahp
);
6489 write_fp_sreg(s
, rd
, tcg_rd
);
6490 tcg_temp_free_i32(tcg_rd
);
6491 tcg_temp_free_i64(tcg_rn
);
6496 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6497 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6498 TCGv_i32 tcg_ahp
= get_ahp_flag();
6499 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6501 /* Half to single */
6502 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6503 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6504 write_fp_sreg(s
, rd
, tcg_rd
);
6505 tcg_temp_free_i32(tcg_rd
);
6507 /* Half to double */
6508 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6509 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6510 write_fp_dreg(s
, rd
, tcg_rd
);
6511 tcg_temp_free_i64(tcg_rd
);
6513 tcg_temp_free_i32(tcg_rn
);
6514 tcg_temp_free_ptr(tcg_fpst
);
6515 tcg_temp_free_i32(tcg_ahp
);
6519 g_assert_not_reached();
6523 /* Floating point data-processing (1 source)
6524 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6525 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6526 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6527 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6529 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6531 int mos
= extract32(insn
, 29, 3);
6532 int type
= extract32(insn
, 22, 2);
6533 int opcode
= extract32(insn
, 15, 6);
6534 int rn
= extract32(insn
, 5, 5);
6535 int rd
= extract32(insn
, 0, 5);
6538 goto do_unallocated
;
6542 case 0x4: case 0x5: case 0x7:
6544 /* FCVT between half, single and double precision */
6545 int dtype
= extract32(opcode
, 0, 2);
6546 if (type
== 2 || dtype
== type
) {
6547 goto do_unallocated
;
6549 if (!fp_access_check(s
)) {
6553 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6557 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6558 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6559 goto do_unallocated
;
6565 /* 32-to-32 and 64-to-64 ops */
6568 if (!fp_access_check(s
)) {
6571 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6574 if (!fp_access_check(s
)) {
6577 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6580 if (!dc_isar_feature(aa64_fp16
, s
)) {
6581 goto do_unallocated
;
6584 if (!fp_access_check(s
)) {
6587 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6590 goto do_unallocated
;
6597 if (!dc_isar_feature(aa64_bf16
, s
)) {
6598 goto do_unallocated
;
6600 if (!fp_access_check(s
)) {
6603 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6606 goto do_unallocated
;
6612 unallocated_encoding(s
);
6617 /* Floating-point data-processing (2 source) - single precision */
6618 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6619 int rd
, int rn
, int rm
)
6626 tcg_res
= tcg_temp_new_i32();
6627 fpst
= fpstatus_ptr(FPST_FPCR
);
6628 tcg_op1
= read_fp_sreg(s
, rn
);
6629 tcg_op2
= read_fp_sreg(s
, rm
);
6632 case 0x0: /* FMUL */
6633 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6635 case 0x1: /* FDIV */
6636 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6638 case 0x2: /* FADD */
6639 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6641 case 0x3: /* FSUB */
6642 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6644 case 0x4: /* FMAX */
6645 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6647 case 0x5: /* FMIN */
6648 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6650 case 0x6: /* FMAXNM */
6651 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 case 0x7: /* FMINNM */
6654 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6656 case 0x8: /* FNMUL */
6657 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6658 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6662 write_fp_sreg(s
, rd
, tcg_res
);
6664 tcg_temp_free_ptr(fpst
);
6665 tcg_temp_free_i32(tcg_op1
);
6666 tcg_temp_free_i32(tcg_op2
);
6667 tcg_temp_free_i32(tcg_res
);
6670 /* Floating-point data-processing (2 source) - double precision */
6671 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6672 int rd
, int rn
, int rm
)
6679 tcg_res
= tcg_temp_new_i64();
6680 fpst
= fpstatus_ptr(FPST_FPCR
);
6681 tcg_op1
= read_fp_dreg(s
, rn
);
6682 tcg_op2
= read_fp_dreg(s
, rm
);
6685 case 0x0: /* FMUL */
6686 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6688 case 0x1: /* FDIV */
6689 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6691 case 0x2: /* FADD */
6692 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6694 case 0x3: /* FSUB */
6695 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6697 case 0x4: /* FMAX */
6698 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6700 case 0x5: /* FMIN */
6701 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6703 case 0x6: /* FMAXNM */
6704 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6706 case 0x7: /* FMINNM */
6707 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6709 case 0x8: /* FNMUL */
6710 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6711 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6715 write_fp_dreg(s
, rd
, tcg_res
);
6717 tcg_temp_free_ptr(fpst
);
6718 tcg_temp_free_i64(tcg_op1
);
6719 tcg_temp_free_i64(tcg_op2
);
6720 tcg_temp_free_i64(tcg_res
);
6723 /* Floating-point data-processing (2 source) - half precision */
6724 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6725 int rd
, int rn
, int rm
)
6732 tcg_res
= tcg_temp_new_i32();
6733 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6734 tcg_op1
= read_fp_hreg(s
, rn
);
6735 tcg_op2
= read_fp_hreg(s
, rm
);
6738 case 0x0: /* FMUL */
6739 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6741 case 0x1: /* FDIV */
6742 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6744 case 0x2: /* FADD */
6745 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6747 case 0x3: /* FSUB */
6748 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6750 case 0x4: /* FMAX */
6751 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6753 case 0x5: /* FMIN */
6754 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6756 case 0x6: /* FMAXNM */
6757 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6759 case 0x7: /* FMINNM */
6760 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6762 case 0x8: /* FNMUL */
6763 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6764 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6767 g_assert_not_reached();
6770 write_fp_sreg(s
, rd
, tcg_res
);
6772 tcg_temp_free_ptr(fpst
);
6773 tcg_temp_free_i32(tcg_op1
);
6774 tcg_temp_free_i32(tcg_op2
);
6775 tcg_temp_free_i32(tcg_res
);
6778 /* Floating point data-processing (2 source)
6779 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6780 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6781 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6782 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6784 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6786 int mos
= extract32(insn
, 29, 3);
6787 int type
= extract32(insn
, 22, 2);
6788 int rd
= extract32(insn
, 0, 5);
6789 int rn
= extract32(insn
, 5, 5);
6790 int rm
= extract32(insn
, 16, 5);
6791 int opcode
= extract32(insn
, 12, 4);
6793 if (opcode
> 8 || mos
) {
6794 unallocated_encoding(s
);
6800 if (!fp_access_check(s
)) {
6803 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6806 if (!fp_access_check(s
)) {
6809 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6812 if (!dc_isar_feature(aa64_fp16
, s
)) {
6813 unallocated_encoding(s
);
6816 if (!fp_access_check(s
)) {
6819 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6822 unallocated_encoding(s
);
6826 /* Floating-point data-processing (3 source) - single precision */
6827 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6828 int rd
, int rn
, int rm
, int ra
)
6830 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6831 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6832 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6834 tcg_op1
= read_fp_sreg(s
, rn
);
6835 tcg_op2
= read_fp_sreg(s
, rm
);
6836 tcg_op3
= read_fp_sreg(s
, ra
);
6838 /* These are fused multiply-add, and must be done as one
6839 * floating point operation with no rounding between the
6840 * multiplication and addition steps.
6841 * NB that doing the negations here as separate steps is
6842 * correct : an input NaN should come out with its sign bit
6843 * flipped if it is a negated-input.
6846 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6850 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6853 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6855 write_fp_sreg(s
, rd
, tcg_res
);
6857 tcg_temp_free_ptr(fpst
);
6858 tcg_temp_free_i32(tcg_op1
);
6859 tcg_temp_free_i32(tcg_op2
);
6860 tcg_temp_free_i32(tcg_op3
);
6861 tcg_temp_free_i32(tcg_res
);
6864 /* Floating-point data-processing (3 source) - double precision */
6865 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6866 int rd
, int rn
, int rm
, int ra
)
6868 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6869 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6870 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6872 tcg_op1
= read_fp_dreg(s
, rn
);
6873 tcg_op2
= read_fp_dreg(s
, rm
);
6874 tcg_op3
= read_fp_dreg(s
, ra
);
6876 /* These are fused multiply-add, and must be done as one
6877 * floating point operation with no rounding between the
6878 * multiplication and addition steps.
6879 * NB that doing the negations here as separate steps is
6880 * correct : an input NaN should come out with its sign bit
6881 * flipped if it is a negated-input.
6884 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6888 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6891 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6893 write_fp_dreg(s
, rd
, tcg_res
);
6895 tcg_temp_free_ptr(fpst
);
6896 tcg_temp_free_i64(tcg_op1
);
6897 tcg_temp_free_i64(tcg_op2
);
6898 tcg_temp_free_i64(tcg_op3
);
6899 tcg_temp_free_i64(tcg_res
);
6902 /* Floating-point data-processing (3 source) - half precision */
6903 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6904 int rd
, int rn
, int rm
, int ra
)
6906 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6907 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6908 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6910 tcg_op1
= read_fp_hreg(s
, rn
);
6911 tcg_op2
= read_fp_hreg(s
, rm
);
6912 tcg_op3
= read_fp_hreg(s
, ra
);
6914 /* These are fused multiply-add, and must be done as one
6915 * floating point operation with no rounding between the
6916 * multiplication and addition steps.
6917 * NB that doing the negations here as separate steps is
6918 * correct : an input NaN should come out with its sign bit
6919 * flipped if it is a negated-input.
6922 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6926 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6929 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6931 write_fp_sreg(s
, rd
, tcg_res
);
6933 tcg_temp_free_ptr(fpst
);
6934 tcg_temp_free_i32(tcg_op1
);
6935 tcg_temp_free_i32(tcg_op2
);
6936 tcg_temp_free_i32(tcg_op3
);
6937 tcg_temp_free_i32(tcg_res
);
6940 /* Floating point data-processing (3 source)
6941 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6942 * +---+---+---+-----------+------+----+------+----+------+------+------+
6943 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6944 * +---+---+---+-----------+------+----+------+----+------+------+------+
6946 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6948 int mos
= extract32(insn
, 29, 3);
6949 int type
= extract32(insn
, 22, 2);
6950 int rd
= extract32(insn
, 0, 5);
6951 int rn
= extract32(insn
, 5, 5);
6952 int ra
= extract32(insn
, 10, 5);
6953 int rm
= extract32(insn
, 16, 5);
6954 bool o0
= extract32(insn
, 15, 1);
6955 bool o1
= extract32(insn
, 21, 1);
6958 unallocated_encoding(s
);
6964 if (!fp_access_check(s
)) {
6967 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6970 if (!fp_access_check(s
)) {
6973 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6976 if (!dc_isar_feature(aa64_fp16
, s
)) {
6977 unallocated_encoding(s
);
6980 if (!fp_access_check(s
)) {
6983 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6986 unallocated_encoding(s
);
6990 /* Floating point immediate
6991 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6992 * +---+---+---+-----------+------+---+------------+-------+------+------+
6993 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6994 * +---+---+---+-----------+------+---+------------+-------+------+------+
6996 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6998 int rd
= extract32(insn
, 0, 5);
6999 int imm5
= extract32(insn
, 5, 5);
7000 int imm8
= extract32(insn
, 13, 8);
7001 int type
= extract32(insn
, 22, 2);
7002 int mos
= extract32(insn
, 29, 3);
7007 unallocated_encoding(s
);
7020 if (dc_isar_feature(aa64_fp16
, s
)) {
7025 unallocated_encoding(s
);
7029 if (!fp_access_check(s
)) {
7033 imm
= vfp_expand_imm(sz
, imm8
);
7034 write_fp_dreg(s
, rd
, tcg_constant_i64(imm
));
7037 /* Handle floating point <=> fixed point conversions. Note that we can
7038 * also deal with fp <=> integer conversions as a special case (scale == 64)
7039 * OPTME: consider handling that special case specially or at least skipping
7040 * the call to scalbn in the helpers for zero shifts.
7042 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
7043 bool itof
, int rmode
, int scale
, int sf
, int type
)
7045 bool is_signed
= !(opcode
& 1);
7046 TCGv_ptr tcg_fpstatus
;
7047 TCGv_i32 tcg_shift
, tcg_single
;
7048 TCGv_i64 tcg_double
;
7050 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
7052 tcg_shift
= tcg_constant_i32(64 - scale
);
7055 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
7057 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
7060 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
7062 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
7065 tcg_int
= tcg_extend
;
7069 case 1: /* float64 */
7070 tcg_double
= tcg_temp_new_i64();
7072 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7073 tcg_shift
, tcg_fpstatus
);
7075 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7076 tcg_shift
, tcg_fpstatus
);
7078 write_fp_dreg(s
, rd
, tcg_double
);
7079 tcg_temp_free_i64(tcg_double
);
7082 case 0: /* float32 */
7083 tcg_single
= tcg_temp_new_i32();
7085 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7086 tcg_shift
, tcg_fpstatus
);
7088 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7089 tcg_shift
, tcg_fpstatus
);
7091 write_fp_sreg(s
, rd
, tcg_single
);
7092 tcg_temp_free_i32(tcg_single
);
7095 case 3: /* float16 */
7096 tcg_single
= tcg_temp_new_i32();
7098 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7099 tcg_shift
, tcg_fpstatus
);
7101 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7102 tcg_shift
, tcg_fpstatus
);
7104 write_fp_sreg(s
, rd
, tcg_single
);
7105 tcg_temp_free_i32(tcg_single
);
7109 g_assert_not_reached();
7112 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7115 if (extract32(opcode
, 2, 1)) {
7116 /* There are too many rounding modes to all fit into rmode,
7117 * so FCVTA[US] is a special case.
7119 rmode
= FPROUNDING_TIEAWAY
;
7122 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7124 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7127 case 1: /* float64 */
7128 tcg_double
= read_fp_dreg(s
, rn
);
7131 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7132 tcg_shift
, tcg_fpstatus
);
7134 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7135 tcg_shift
, tcg_fpstatus
);
7139 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7140 tcg_shift
, tcg_fpstatus
);
7142 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7143 tcg_shift
, tcg_fpstatus
);
7147 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7149 tcg_temp_free_i64(tcg_double
);
7152 case 0: /* float32 */
7153 tcg_single
= read_fp_sreg(s
, rn
);
7156 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7157 tcg_shift
, tcg_fpstatus
);
7159 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7160 tcg_shift
, tcg_fpstatus
);
7163 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7165 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7166 tcg_shift
, tcg_fpstatus
);
7168 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7169 tcg_shift
, tcg_fpstatus
);
7171 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7172 tcg_temp_free_i32(tcg_dest
);
7174 tcg_temp_free_i32(tcg_single
);
7177 case 3: /* float16 */
7178 tcg_single
= read_fp_sreg(s
, rn
);
7181 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7182 tcg_shift
, tcg_fpstatus
);
7184 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7185 tcg_shift
, tcg_fpstatus
);
7188 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7190 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7191 tcg_shift
, tcg_fpstatus
);
7193 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7194 tcg_shift
, tcg_fpstatus
);
7196 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7197 tcg_temp_free_i32(tcg_dest
);
7199 tcg_temp_free_i32(tcg_single
);
7203 g_assert_not_reached();
7206 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7207 tcg_temp_free_i32(tcg_rmode
);
7210 tcg_temp_free_ptr(tcg_fpstatus
);
7213 /* Floating point <-> fixed point conversions
7214 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7215 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7216 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7217 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7219 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7221 int rd
= extract32(insn
, 0, 5);
7222 int rn
= extract32(insn
, 5, 5);
7223 int scale
= extract32(insn
, 10, 6);
7224 int opcode
= extract32(insn
, 16, 3);
7225 int rmode
= extract32(insn
, 19, 2);
7226 int type
= extract32(insn
, 22, 2);
7227 bool sbit
= extract32(insn
, 29, 1);
7228 bool sf
= extract32(insn
, 31, 1);
7231 if (sbit
|| (!sf
&& scale
< 32)) {
7232 unallocated_encoding(s
);
7237 case 0: /* float32 */
7238 case 1: /* float64 */
7240 case 3: /* float16 */
7241 if (dc_isar_feature(aa64_fp16
, s
)) {
7246 unallocated_encoding(s
);
7250 switch ((rmode
<< 3) | opcode
) {
7251 case 0x2: /* SCVTF */
7252 case 0x3: /* UCVTF */
7255 case 0x18: /* FCVTZS */
7256 case 0x19: /* FCVTZU */
7260 unallocated_encoding(s
);
7264 if (!fp_access_check(s
)) {
7268 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7271 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7273 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7274 * without conversion.
7278 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7284 tmp
= tcg_temp_new_i64();
7285 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7286 write_fp_dreg(s
, rd
, tmp
);
7287 tcg_temp_free_i64(tmp
);
7291 write_fp_dreg(s
, rd
, tcg_rn
);
7294 /* 64 bit to top half. */
7295 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7296 clear_vec_high(s
, true, rd
);
7300 tmp
= tcg_temp_new_i64();
7301 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7302 write_fp_dreg(s
, rd
, tmp
);
7303 tcg_temp_free_i64(tmp
);
7306 g_assert_not_reached();
7309 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7314 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7318 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7321 /* 64 bits from top half */
7322 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7326 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7329 g_assert_not_reached();
7334 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7336 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7337 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7339 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7341 tcg_temp_free_ptr(fpstatus
);
7343 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7344 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7345 tcg_gen_movi_i32(cpu_CF
, 0);
7346 tcg_gen_movi_i32(cpu_NF
, 0);
7347 tcg_gen_movi_i32(cpu_VF
, 0);
7349 tcg_temp_free_i64(t
);
7352 /* Floating point <-> integer conversions
7353 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7354 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7355 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7356 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7358 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7360 int rd
= extract32(insn
, 0, 5);
7361 int rn
= extract32(insn
, 5, 5);
7362 int opcode
= extract32(insn
, 16, 3);
7363 int rmode
= extract32(insn
, 19, 2);
7364 int type
= extract32(insn
, 22, 2);
7365 bool sbit
= extract32(insn
, 29, 1);
7366 bool sf
= extract32(insn
, 31, 1);
7370 goto do_unallocated
;
7378 case 4: /* FCVTAS */
7379 case 5: /* FCVTAU */
7381 goto do_unallocated
;
7384 case 0: /* FCVT[NPMZ]S */
7385 case 1: /* FCVT[NPMZ]U */
7387 case 0: /* float32 */
7388 case 1: /* float64 */
7390 case 3: /* float16 */
7391 if (!dc_isar_feature(aa64_fp16
, s
)) {
7392 goto do_unallocated
;
7396 goto do_unallocated
;
7398 if (!fp_access_check(s
)) {
7401 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7405 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7406 case 0b01100110: /* FMOV half <-> 32-bit int */
7408 case 0b11100110: /* FMOV half <-> 64-bit int */
7410 if (!dc_isar_feature(aa64_fp16
, s
)) {
7411 goto do_unallocated
;
7414 case 0b00000110: /* FMOV 32-bit */
7416 case 0b10100110: /* FMOV 64-bit */
7418 case 0b11001110: /* FMOV top half of 128-bit */
7420 if (!fp_access_check(s
)) {
7424 handle_fmov(s
, rd
, rn
, type
, itof
);
7427 case 0b00111110: /* FJCVTZS */
7428 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7429 goto do_unallocated
;
7430 } else if (fp_access_check(s
)) {
7431 handle_fjcvtzs(s
, rd
, rn
);
7437 unallocated_encoding(s
);
7444 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7445 * 31 30 29 28 25 24 0
7446 * +---+---+---+---------+-----------------------------+
7447 * | | 0 | | 1 1 1 1 | |
7448 * +---+---+---+---------+-----------------------------+
7450 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7452 if (extract32(insn
, 24, 1)) {
7453 /* Floating point data-processing (3 source) */
7454 disas_fp_3src(s
, insn
);
7455 } else if (extract32(insn
, 21, 1) == 0) {
7456 /* Floating point to fixed point conversions */
7457 disas_fp_fixed_conv(s
, insn
);
7459 switch (extract32(insn
, 10, 2)) {
7461 /* Floating point conditional compare */
7462 disas_fp_ccomp(s
, insn
);
7465 /* Floating point data-processing (2 source) */
7466 disas_fp_2src(s
, insn
);
7469 /* Floating point conditional select */
7470 disas_fp_csel(s
, insn
);
7473 switch (ctz32(extract32(insn
, 12, 4))) {
7474 case 0: /* [15:12] == xxx1 */
7475 /* Floating point immediate */
7476 disas_fp_imm(s
, insn
);
7478 case 1: /* [15:12] == xx10 */
7479 /* Floating point compare */
7480 disas_fp_compare(s
, insn
);
7482 case 2: /* [15:12] == x100 */
7483 /* Floating point data-processing (1 source) */
7484 disas_fp_1src(s
, insn
);
7486 case 3: /* [15:12] == 1000 */
7487 unallocated_encoding(s
);
7489 default: /* [15:12] == 0000 */
7490 /* Floating point <-> integer conversions */
7491 disas_fp_int_conv(s
, insn
);
7499 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7502 /* Extract 64 bits from the middle of two concatenated 64 bit
7503 * vector register slices left:right. The extracted bits start
7504 * at 'pos' bits into the right (least significant) side.
7505 * We return the result in tcg_right, and guarantee not to
7508 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7509 assert(pos
> 0 && pos
< 64);
7511 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7512 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7513 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7515 tcg_temp_free_i64(tcg_tmp
);
7519 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7520 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7521 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7522 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7524 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7526 int is_q
= extract32(insn
, 30, 1);
7527 int op2
= extract32(insn
, 22, 2);
7528 int imm4
= extract32(insn
, 11, 4);
7529 int rm
= extract32(insn
, 16, 5);
7530 int rn
= extract32(insn
, 5, 5);
7531 int rd
= extract32(insn
, 0, 5);
7532 int pos
= imm4
<< 3;
7533 TCGv_i64 tcg_resl
, tcg_resh
;
7535 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7536 unallocated_encoding(s
);
7540 if (!fp_access_check(s
)) {
7544 tcg_resh
= tcg_temp_new_i64();
7545 tcg_resl
= tcg_temp_new_i64();
7547 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7548 * either extracting 128 bits from a 128:128 concatenation, or
7549 * extracting 64 bits from a 64:64 concatenation.
7552 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7554 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7555 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7563 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7564 EltPosns
*elt
= eltposns
;
7571 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7573 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7576 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7577 tcg_hh
= tcg_temp_new_i64();
7578 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7579 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7580 tcg_temp_free_i64(tcg_hh
);
7584 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7585 tcg_temp_free_i64(tcg_resl
);
7587 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7589 tcg_temp_free_i64(tcg_resh
);
7590 clear_vec_high(s
, is_q
, rd
);
7594 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7595 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7596 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7597 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7599 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7601 int op2
= extract32(insn
, 22, 2);
7602 int is_q
= extract32(insn
, 30, 1);
7603 int rm
= extract32(insn
, 16, 5);
7604 int rn
= extract32(insn
, 5, 5);
7605 int rd
= extract32(insn
, 0, 5);
7606 int is_tbx
= extract32(insn
, 12, 1);
7607 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7610 unallocated_encoding(s
);
7614 if (!fp_access_check(s
)) {
7618 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7619 vec_full_reg_offset(s
, rm
), cpu_env
,
7620 is_q
? 16 : 8, vec_full_reg_size(s
),
7621 (len
<< 6) | (is_tbx
<< 5) | rn
,
7622 gen_helper_simd_tblx
);
7626 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7627 * +---+---+-------------+------+---+------+---+------------------+------+
7628 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7629 * +---+---+-------------+------+---+------+---+------------------+------+
7631 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7633 int rd
= extract32(insn
, 0, 5);
7634 int rn
= extract32(insn
, 5, 5);
7635 int rm
= extract32(insn
, 16, 5);
7636 int size
= extract32(insn
, 22, 2);
7637 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7638 * bit 2 indicates 1 vs 2 variant of the insn.
7640 int opcode
= extract32(insn
, 12, 2);
7641 bool part
= extract32(insn
, 14, 1);
7642 bool is_q
= extract32(insn
, 30, 1);
7643 int esize
= 8 << size
;
7645 int datasize
= is_q
? 128 : 64;
7646 int elements
= datasize
/ esize
;
7647 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7649 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7650 unallocated_encoding(s
);
7654 if (!fp_access_check(s
)) {
7658 tcg_resl
= tcg_const_i64(0);
7659 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7660 tcg_res
= tcg_temp_new_i64();
7662 for (i
= 0; i
< elements
; i
++) {
7664 case 1: /* UZP1/2 */
7666 int midpoint
= elements
/ 2;
7668 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7670 read_vec_element(s
, tcg_res
, rm
,
7671 2 * (i
- midpoint
) + part
, size
);
7675 case 2: /* TRN1/2 */
7677 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7679 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7682 case 3: /* ZIP1/2 */
7684 int base
= part
* elements
/ 2;
7686 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7688 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7693 g_assert_not_reached();
7698 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7699 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7701 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7702 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7706 tcg_temp_free_i64(tcg_res
);
7708 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7709 tcg_temp_free_i64(tcg_resl
);
7712 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7713 tcg_temp_free_i64(tcg_resh
);
7715 clear_vec_high(s
, is_q
, rd
);
7719 * do_reduction_op helper
7721 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7722 * important for correct NaN propagation that we do these
7723 * operations in exactly the order specified by the pseudocode.
7725 * This is a recursive function, TCG temps should be freed by the
7726 * calling function once it is done with the values.
7728 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7729 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7731 if (esize
== size
) {
7733 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7736 /* We should have one register left here */
7737 assert(ctpop8(vmap
) == 1);
7738 element
= ctz32(vmap
);
7739 assert(element
< 8);
7741 tcg_elem
= tcg_temp_new_i32();
7742 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7745 int bits
= size
/ 2;
7746 int shift
= ctpop8(vmap
) / 2;
7747 int vmap_lo
= (vmap
>> shift
) & vmap
;
7748 int vmap_hi
= (vmap
& ~vmap_lo
);
7749 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7751 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7752 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7753 tcg_res
= tcg_temp_new_i32();
7756 case 0x0c: /* fmaxnmv half-precision */
7757 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7759 case 0x0f: /* fmaxv half-precision */
7760 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7762 case 0x1c: /* fminnmv half-precision */
7763 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7765 case 0x1f: /* fminv half-precision */
7766 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7768 case 0x2c: /* fmaxnmv */
7769 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7771 case 0x2f: /* fmaxv */
7772 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7774 case 0x3c: /* fminnmv */
7775 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7777 case 0x3f: /* fminv */
7778 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7781 g_assert_not_reached();
7784 tcg_temp_free_i32(tcg_hi
);
7785 tcg_temp_free_i32(tcg_lo
);
7790 /* AdvSIMD across lanes
7791 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7792 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7793 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7794 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7796 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7798 int rd
= extract32(insn
, 0, 5);
7799 int rn
= extract32(insn
, 5, 5);
7800 int size
= extract32(insn
, 22, 2);
7801 int opcode
= extract32(insn
, 12, 5);
7802 bool is_q
= extract32(insn
, 30, 1);
7803 bool is_u
= extract32(insn
, 29, 1);
7805 bool is_min
= false;
7809 TCGv_i64 tcg_res
, tcg_elt
;
7812 case 0x1b: /* ADDV */
7814 unallocated_encoding(s
);
7818 case 0x3: /* SADDLV, UADDLV */
7819 case 0xa: /* SMAXV, UMAXV */
7820 case 0x1a: /* SMINV, UMINV */
7821 if (size
== 3 || (size
== 2 && !is_q
)) {
7822 unallocated_encoding(s
);
7826 case 0xc: /* FMAXNMV, FMINNMV */
7827 case 0xf: /* FMAXV, FMINV */
7828 /* Bit 1 of size field encodes min vs max and the actual size
7829 * depends on the encoding of the U bit. If not set (and FP16
7830 * enabled) then we do half-precision float instead of single
7833 is_min
= extract32(size
, 1, 1);
7835 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7837 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7838 unallocated_encoding(s
);
7845 unallocated_encoding(s
);
7849 if (!fp_access_check(s
)) {
7854 elements
= (is_q
? 128 : 64) / esize
;
7856 tcg_res
= tcg_temp_new_i64();
7857 tcg_elt
= tcg_temp_new_i64();
7859 /* These instructions operate across all lanes of a vector
7860 * to produce a single result. We can guarantee that a 64
7861 * bit intermediate is sufficient:
7862 * + for [US]ADDLV the maximum element size is 32 bits, and
7863 * the result type is 64 bits
7864 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7865 * same as the element size, which is 32 bits at most
7866 * For the integer operations we can choose to work at 64
7867 * or 32 bits and truncate at the end; for simplicity
7868 * we use 64 bits always. The floating point
7869 * ops do require 32 bit intermediates, though.
7872 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7874 for (i
= 1; i
< elements
; i
++) {
7875 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7878 case 0x03: /* SADDLV / UADDLV */
7879 case 0x1b: /* ADDV */
7880 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7882 case 0x0a: /* SMAXV / UMAXV */
7884 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7886 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7889 case 0x1a: /* SMINV / UMINV */
7891 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7893 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7897 g_assert_not_reached();
7902 /* Floating point vector reduction ops which work across 32
7903 * bit (single) or 16 bit (half-precision) intermediates.
7904 * Note that correct NaN propagation requires that we do these
7905 * operations in exactly the order specified by the pseudocode.
7907 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7908 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7909 int vmap
= (1 << elements
) - 1;
7910 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7911 (is_q
? 128 : 64), vmap
, fpst
);
7912 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7913 tcg_temp_free_i32(tcg_res32
);
7914 tcg_temp_free_ptr(fpst
);
7917 tcg_temp_free_i64(tcg_elt
);
7919 /* Now truncate the result to the width required for the final output */
7920 if (opcode
== 0x03) {
7921 /* SADDLV, UADDLV: result is 2*esize */
7927 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7930 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7933 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7938 g_assert_not_reached();
7941 write_fp_dreg(s
, rd
, tcg_res
);
7942 tcg_temp_free_i64(tcg_res
);
7945 /* DUP (Element, Vector)
7947 * 31 30 29 21 20 16 15 10 9 5 4 0
7948 * +---+---+-------------------+--------+-------------+------+------+
7949 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7950 * +---+---+-------------------+--------+-------------+------+------+
7952 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7954 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7957 int size
= ctz32(imm5
);
7960 if (size
> 3 || (size
== 3 && !is_q
)) {
7961 unallocated_encoding(s
);
7965 if (!fp_access_check(s
)) {
7969 index
= imm5
>> (size
+ 1);
7970 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7971 vec_reg_offset(s
, rn
, index
, size
),
7972 is_q
? 16 : 8, vec_full_reg_size(s
));
7975 /* DUP (element, scalar)
7976 * 31 21 20 16 15 10 9 5 4 0
7977 * +-----------------------+--------+-------------+------+------+
7978 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7979 * +-----------------------+--------+-------------+------+------+
7981 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7984 int size
= ctz32(imm5
);
7989 unallocated_encoding(s
);
7993 if (!fp_access_check(s
)) {
7997 index
= imm5
>> (size
+ 1);
7999 /* This instruction just extracts the specified element and
8000 * zero-extends it into the bottom of the destination register.
8002 tmp
= tcg_temp_new_i64();
8003 read_vec_element(s
, tmp
, rn
, index
, size
);
8004 write_fp_dreg(s
, rd
, tmp
);
8005 tcg_temp_free_i64(tmp
);
8010 * 31 30 29 21 20 16 15 10 9 5 4 0
8011 * +---+---+-------------------+--------+-------------+------+------+
8012 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
8013 * +---+---+-------------------+--------+-------------+------+------+
8015 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8017 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
8020 int size
= ctz32(imm5
);
8021 uint32_t dofs
, oprsz
, maxsz
;
8023 if (size
> 3 || ((size
== 3) && !is_q
)) {
8024 unallocated_encoding(s
);
8028 if (!fp_access_check(s
)) {
8032 dofs
= vec_full_reg_offset(s
, rd
);
8033 oprsz
= is_q
? 16 : 8;
8034 maxsz
= vec_full_reg_size(s
);
8036 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
8041 * 31 21 20 16 15 14 11 10 9 5 4 0
8042 * +-----------------------+--------+------------+---+------+------+
8043 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8044 * +-----------------------+--------+------------+---+------+------+
8046 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8047 * index: encoded in imm5<4:size+1>
8049 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
8052 int size
= ctz32(imm5
);
8053 int src_index
, dst_index
;
8057 unallocated_encoding(s
);
8061 if (!fp_access_check(s
)) {
8065 dst_index
= extract32(imm5
, 1+size
, 5);
8066 src_index
= extract32(imm4
, size
, 4);
8068 tmp
= tcg_temp_new_i64();
8070 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8071 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8073 tcg_temp_free_i64(tmp
);
8075 /* INS is considered a 128-bit write for SVE. */
8076 clear_vec_high(s
, true, rd
);
8082 * 31 21 20 16 15 10 9 5 4 0
8083 * +-----------------------+--------+-------------+------+------+
8084 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8085 * +-----------------------+--------+-------------+------+------+
8087 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8088 * index: encoded in imm5<4:size+1>
8090 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8092 int size
= ctz32(imm5
);
8096 unallocated_encoding(s
);
8100 if (!fp_access_check(s
)) {
8104 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8105 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8107 /* INS is considered a 128-bit write for SVE. */
8108 clear_vec_high(s
, true, rd
);
8115 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8116 * +---+---+-------------------+--------+-------------+------+------+
8117 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8118 * +---+---+-------------------+--------+-------------+------+------+
8120 * U: unsigned when set
8121 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8123 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8124 int rn
, int rd
, int imm5
)
8126 int size
= ctz32(imm5
);
8130 /* Check for UnallocatedEncodings */
8132 if (size
> 2 || (size
== 2 && !is_q
)) {
8133 unallocated_encoding(s
);
8138 || (size
< 3 && is_q
)
8139 || (size
== 3 && !is_q
)) {
8140 unallocated_encoding(s
);
8145 if (!fp_access_check(s
)) {
8149 element
= extract32(imm5
, 1+size
, 4);
8151 tcg_rd
= cpu_reg(s
, rd
);
8152 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8153 if (is_signed
&& !is_q
) {
8154 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8159 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8160 * +---+---+----+-----------------+------+---+------+---+------+------+
8161 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8162 * +---+---+----+-----------------+------+---+------+---+------+------+
8164 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8166 int rd
= extract32(insn
, 0, 5);
8167 int rn
= extract32(insn
, 5, 5);
8168 int imm4
= extract32(insn
, 11, 4);
8169 int op
= extract32(insn
, 29, 1);
8170 int is_q
= extract32(insn
, 30, 1);
8171 int imm5
= extract32(insn
, 16, 5);
8176 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8178 unallocated_encoding(s
);
8183 /* DUP (element - vector) */
8184 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8188 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8193 handle_simd_insg(s
, rd
, rn
, imm5
);
8195 unallocated_encoding(s
);
8200 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8201 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8204 unallocated_encoding(s
);
8210 /* AdvSIMD modified immediate
8211 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8212 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8213 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8214 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8216 * There are a number of operations that can be carried out here:
8217 * MOVI - move (shifted) imm into register
8218 * MVNI - move inverted (shifted) imm into register
8219 * ORR - bitwise OR of (shifted) imm with register
8220 * BIC - bitwise clear of (shifted) imm with register
8221 * With ARMv8.2 we also have:
8222 * FMOV half-precision
8224 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8226 int rd
= extract32(insn
, 0, 5);
8227 int cmode
= extract32(insn
, 12, 4);
8228 int o2
= extract32(insn
, 11, 1);
8229 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8230 bool is_neg
= extract32(insn
, 29, 1);
8231 bool is_q
= extract32(insn
, 30, 1);
8234 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8235 /* Check for FMOV (vector, immediate) - half-precision */
8236 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8237 unallocated_encoding(s
);
8242 if (!fp_access_check(s
)) {
8246 if (cmode
== 15 && o2
&& !is_neg
) {
8247 /* FMOV (vector, immediate) - half-precision */
8248 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8249 /* now duplicate across the lanes */
8250 imm
= dup_const(MO_16
, imm
);
8252 imm
= asimd_imm_const(abcdefgh
, cmode
, is_neg
);
8255 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8256 /* MOVI or MVNI, with MVNI negation handled above. */
8257 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8258 vec_full_reg_size(s
), imm
);
8260 /* ORR or BIC, with BIC negation to AND handled above. */
8262 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8264 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8269 /* AdvSIMD scalar copy
8270 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8271 * +-----+----+-----------------+------+---+------+---+------+------+
8272 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8273 * +-----+----+-----------------+------+---+------+---+------+------+
8275 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8277 int rd
= extract32(insn
, 0, 5);
8278 int rn
= extract32(insn
, 5, 5);
8279 int imm4
= extract32(insn
, 11, 4);
8280 int imm5
= extract32(insn
, 16, 5);
8281 int op
= extract32(insn
, 29, 1);
8283 if (op
!= 0 || imm4
!= 0) {
8284 unallocated_encoding(s
);
8288 /* DUP (element, scalar) */
8289 handle_simd_dupes(s
, rd
, rn
, imm5
);
8292 /* AdvSIMD scalar pairwise
8293 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8294 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8295 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8296 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8298 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8300 int u
= extract32(insn
, 29, 1);
8301 int size
= extract32(insn
, 22, 2);
8302 int opcode
= extract32(insn
, 12, 5);
8303 int rn
= extract32(insn
, 5, 5);
8304 int rd
= extract32(insn
, 0, 5);
8307 /* For some ops (the FP ones), size[1] is part of the encoding.
8308 * For ADDP strictly it is not but size[1] is always 1 for valid
8311 opcode
|= (extract32(size
, 1, 1) << 5);
8314 case 0x3b: /* ADDP */
8315 if (u
|| size
!= 3) {
8316 unallocated_encoding(s
);
8319 if (!fp_access_check(s
)) {
8325 case 0xc: /* FMAXNMP */
8326 case 0xd: /* FADDP */
8327 case 0xf: /* FMAXP */
8328 case 0x2c: /* FMINNMP */
8329 case 0x2f: /* FMINP */
8330 /* FP op, size[0] is 32 or 64 bit*/
8332 if (!dc_isar_feature(aa64_fp16
, s
)) {
8333 unallocated_encoding(s
);
8339 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8342 if (!fp_access_check(s
)) {
8346 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8349 unallocated_encoding(s
);
8353 if (size
== MO_64
) {
8354 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8355 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8356 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8358 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8359 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8362 case 0x3b: /* ADDP */
8363 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8365 case 0xc: /* FMAXNMP */
8366 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8368 case 0xd: /* FADDP */
8369 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8371 case 0xf: /* FMAXP */
8372 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8374 case 0x2c: /* FMINNMP */
8375 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8377 case 0x2f: /* FMINP */
8378 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8381 g_assert_not_reached();
8384 write_fp_dreg(s
, rd
, tcg_res
);
8386 tcg_temp_free_i64(tcg_op1
);
8387 tcg_temp_free_i64(tcg_op2
);
8388 tcg_temp_free_i64(tcg_res
);
8390 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8391 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8392 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8394 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8395 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8397 if (size
== MO_16
) {
8399 case 0xc: /* FMAXNMP */
8400 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8402 case 0xd: /* FADDP */
8403 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8405 case 0xf: /* FMAXP */
8406 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8408 case 0x2c: /* FMINNMP */
8409 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8411 case 0x2f: /* FMINP */
8412 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8415 g_assert_not_reached();
8419 case 0xc: /* FMAXNMP */
8420 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8422 case 0xd: /* FADDP */
8423 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8425 case 0xf: /* FMAXP */
8426 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8428 case 0x2c: /* FMINNMP */
8429 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8431 case 0x2f: /* FMINP */
8432 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8435 g_assert_not_reached();
8439 write_fp_sreg(s
, rd
, tcg_res
);
8441 tcg_temp_free_i32(tcg_op1
);
8442 tcg_temp_free_i32(tcg_op2
);
8443 tcg_temp_free_i32(tcg_res
);
8447 tcg_temp_free_ptr(fpst
);
8452 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8454 * This code is handles the common shifting code and is used by both
8455 * the vector and scalar code.
8457 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8458 TCGv_i64 tcg_rnd
, bool accumulate
,
8459 bool is_u
, int size
, int shift
)
8461 bool extended_result
= false;
8462 bool round
= tcg_rnd
!= NULL
;
8464 TCGv_i64 tcg_src_hi
;
8466 if (round
&& size
== 3) {
8467 extended_result
= true;
8468 ext_lshift
= 64 - shift
;
8469 tcg_src_hi
= tcg_temp_new_i64();
8470 } else if (shift
== 64) {
8471 if (!accumulate
&& is_u
) {
8472 /* result is zero */
8473 tcg_gen_movi_i64(tcg_res
, 0);
8478 /* Deal with the rounding step */
8480 if (extended_result
) {
8481 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
8483 /* take care of sign extending tcg_res */
8484 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8485 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8486 tcg_src
, tcg_src_hi
,
8489 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8494 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8498 /* Now do the shift right */
8499 if (round
&& extended_result
) {
8500 /* extended case, >64 bit precision required */
8501 if (ext_lshift
== 0) {
8502 /* special case, only high bits matter */
8503 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8505 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8506 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8507 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8512 /* essentially shifting in 64 zeros */
8513 tcg_gen_movi_i64(tcg_src
, 0);
8515 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8519 /* effectively extending the sign-bit */
8520 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8522 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8528 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8530 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8533 if (extended_result
) {
8534 tcg_temp_free_i64(tcg_src_hi
);
8538 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8539 static void handle_scalar_simd_shri(DisasContext
*s
,
8540 bool is_u
, int immh
, int immb
,
8541 int opcode
, int rn
, int rd
)
8544 int immhb
= immh
<< 3 | immb
;
8545 int shift
= 2 * (8 << size
) - immhb
;
8546 bool accumulate
= false;
8548 bool insert
= false;
8553 if (!extract32(immh
, 3, 1)) {
8554 unallocated_encoding(s
);
8558 if (!fp_access_check(s
)) {
8563 case 0x02: /* SSRA / USRA (accumulate) */
8566 case 0x04: /* SRSHR / URSHR (rounding) */
8569 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8570 accumulate
= round
= true;
8572 case 0x08: /* SRI */
8578 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8583 tcg_rn
= read_fp_dreg(s
, rn
);
8584 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8587 /* shift count same as element size is valid but does nothing;
8588 * special case to avoid potential shift by 64.
8590 int esize
= 8 << size
;
8591 if (shift
!= esize
) {
8592 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8593 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8596 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8597 accumulate
, is_u
, size
, shift
);
8600 write_fp_dreg(s
, rd
, tcg_rd
);
8602 tcg_temp_free_i64(tcg_rn
);
8603 tcg_temp_free_i64(tcg_rd
);
8606 /* SHL/SLI - Scalar shift left */
8607 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8608 int immh
, int immb
, int opcode
,
8611 int size
= 32 - clz32(immh
) - 1;
8612 int immhb
= immh
<< 3 | immb
;
8613 int shift
= immhb
- (8 << size
);
8617 if (!extract32(immh
, 3, 1)) {
8618 unallocated_encoding(s
);
8622 if (!fp_access_check(s
)) {
8626 tcg_rn
= read_fp_dreg(s
, rn
);
8627 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8630 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8632 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8635 write_fp_dreg(s
, rd
, tcg_rd
);
8637 tcg_temp_free_i64(tcg_rn
);
8638 tcg_temp_free_i64(tcg_rd
);
8641 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8642 * (signed/unsigned) narrowing */
8643 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8644 bool is_u_shift
, bool is_u_narrow
,
8645 int immh
, int immb
, int opcode
,
8648 int immhb
= immh
<< 3 | immb
;
8649 int size
= 32 - clz32(immh
) - 1;
8650 int esize
= 8 << size
;
8651 int shift
= (2 * esize
) - immhb
;
8652 int elements
= is_scalar
? 1 : (64 / esize
);
8653 bool round
= extract32(opcode
, 0, 1);
8654 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8655 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8656 TCGv_i32 tcg_rd_narrowed
;
8659 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8660 { gen_helper_neon_narrow_sat_s8
,
8661 gen_helper_neon_unarrow_sat8
},
8662 { gen_helper_neon_narrow_sat_s16
,
8663 gen_helper_neon_unarrow_sat16
},
8664 { gen_helper_neon_narrow_sat_s32
,
8665 gen_helper_neon_unarrow_sat32
},
8668 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8669 gen_helper_neon_narrow_sat_u8
,
8670 gen_helper_neon_narrow_sat_u16
,
8671 gen_helper_neon_narrow_sat_u32
,
8674 NeonGenNarrowEnvFn
*narrowfn
;
8680 if (extract32(immh
, 3, 1)) {
8681 unallocated_encoding(s
);
8685 if (!fp_access_check(s
)) {
8690 narrowfn
= unsigned_narrow_fns
[size
];
8692 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8695 tcg_rn
= tcg_temp_new_i64();
8696 tcg_rd
= tcg_temp_new_i64();
8697 tcg_rd_narrowed
= tcg_temp_new_i32();
8698 tcg_final
= tcg_const_i64(0);
8701 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8706 for (i
= 0; i
< elements
; i
++) {
8707 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8708 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8709 false, is_u_shift
, size
+1, shift
);
8710 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8711 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8712 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8716 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8718 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8721 tcg_temp_free_i64(tcg_rn
);
8722 tcg_temp_free_i64(tcg_rd
);
8723 tcg_temp_free_i32(tcg_rd_narrowed
);
8724 tcg_temp_free_i64(tcg_final
);
8726 clear_vec_high(s
, is_q
, rd
);
8729 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8730 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8731 bool src_unsigned
, bool dst_unsigned
,
8732 int immh
, int immb
, int rn
, int rd
)
8734 int immhb
= immh
<< 3 | immb
;
8735 int size
= 32 - clz32(immh
) - 1;
8736 int shift
= immhb
- (8 << size
);
8740 assert(!(scalar
&& is_q
));
8743 if (!is_q
&& extract32(immh
, 3, 1)) {
8744 unallocated_encoding(s
);
8748 /* Since we use the variable-shift helpers we must
8749 * replicate the shift count into each element of
8750 * the tcg_shift value.
8754 shift
|= shift
<< 8;
8757 shift
|= shift
<< 16;
8763 g_assert_not_reached();
8767 if (!fp_access_check(s
)) {
8772 TCGv_i64 tcg_shift
= tcg_constant_i64(shift
);
8773 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8774 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8775 { NULL
, gen_helper_neon_qshl_u64
},
8777 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8778 int maxpass
= is_q
? 2 : 1;
8780 for (pass
= 0; pass
< maxpass
; pass
++) {
8781 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8783 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8784 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8785 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8787 tcg_temp_free_i64(tcg_op
);
8789 clear_vec_high(s
, is_q
, rd
);
8791 TCGv_i32 tcg_shift
= tcg_constant_i32(shift
);
8792 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8794 { gen_helper_neon_qshl_s8
,
8795 gen_helper_neon_qshl_s16
,
8796 gen_helper_neon_qshl_s32
},
8797 { gen_helper_neon_qshlu_s8
,
8798 gen_helper_neon_qshlu_s16
,
8799 gen_helper_neon_qshlu_s32
}
8801 { NULL
, NULL
, NULL
},
8802 { gen_helper_neon_qshl_u8
,
8803 gen_helper_neon_qshl_u16
,
8804 gen_helper_neon_qshl_u32
}
8807 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8808 MemOp memop
= scalar
? size
: MO_32
;
8809 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8811 for (pass
= 0; pass
< maxpass
; pass
++) {
8812 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8814 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8815 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8819 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8822 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8827 g_assert_not_reached();
8829 write_fp_sreg(s
, rd
, tcg_op
);
8831 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8834 tcg_temp_free_i32(tcg_op
);
8838 clear_vec_high(s
, is_q
, rd
);
8843 /* Common vector code for handling integer to FP conversion */
8844 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8845 int elements
, int is_signed
,
8846 int fracbits
, int size
)
8848 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8849 TCGv_i32 tcg_shift
= NULL
;
8851 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8854 if (fracbits
|| size
== MO_64
) {
8855 tcg_shift
= tcg_constant_i32(fracbits
);
8858 if (size
== MO_64
) {
8859 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8860 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8862 for (pass
= 0; pass
< elements
; pass
++) {
8863 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8866 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8867 tcg_shift
, tcg_fpst
);
8869 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8870 tcg_shift
, tcg_fpst
);
8872 if (elements
== 1) {
8873 write_fp_dreg(s
, rd
, tcg_double
);
8875 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8879 tcg_temp_free_i64(tcg_int64
);
8880 tcg_temp_free_i64(tcg_double
);
8883 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8884 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8886 for (pass
= 0; pass
< elements
; pass
++) {
8887 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8893 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8894 tcg_shift
, tcg_fpst
);
8896 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8897 tcg_shift
, tcg_fpst
);
8901 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8903 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8910 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8911 tcg_shift
, tcg_fpst
);
8913 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8914 tcg_shift
, tcg_fpst
);
8918 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8920 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8925 g_assert_not_reached();
8928 if (elements
== 1) {
8929 write_fp_sreg(s
, rd
, tcg_float
);
8931 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8935 tcg_temp_free_i32(tcg_int32
);
8936 tcg_temp_free_i32(tcg_float
);
8939 tcg_temp_free_ptr(tcg_fpst
);
8941 clear_vec_high(s
, elements
<< size
== 16, rd
);
8944 /* UCVTF/SCVTF - Integer to FP conversion */
8945 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8946 bool is_q
, bool is_u
,
8947 int immh
, int immb
, int opcode
,
8950 int size
, elements
, fracbits
;
8951 int immhb
= immh
<< 3 | immb
;
8955 if (!is_scalar
&& !is_q
) {
8956 unallocated_encoding(s
);
8959 } else if (immh
& 4) {
8961 } else if (immh
& 2) {
8963 if (!dc_isar_feature(aa64_fp16
, s
)) {
8964 unallocated_encoding(s
);
8968 /* immh == 0 would be a failure of the decode logic */
8969 g_assert(immh
== 1);
8970 unallocated_encoding(s
);
8977 elements
= (8 << is_q
) >> size
;
8979 fracbits
= (16 << size
) - immhb
;
8981 if (!fp_access_check(s
)) {
8985 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8988 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8989 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8990 bool is_q
, bool is_u
,
8991 int immh
, int immb
, int rn
, int rd
)
8993 int immhb
= immh
<< 3 | immb
;
8994 int pass
, size
, fracbits
;
8995 TCGv_ptr tcg_fpstatus
;
8996 TCGv_i32 tcg_rmode
, tcg_shift
;
9000 if (!is_scalar
&& !is_q
) {
9001 unallocated_encoding(s
);
9004 } else if (immh
& 0x4) {
9006 } else if (immh
& 0x2) {
9008 if (!dc_isar_feature(aa64_fp16
, s
)) {
9009 unallocated_encoding(s
);
9013 /* Should have split out AdvSIMD modified immediate earlier. */
9015 unallocated_encoding(s
);
9019 if (!fp_access_check(s
)) {
9023 assert(!(is_scalar
&& is_q
));
9025 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9026 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9027 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9028 fracbits
= (16 << size
) - immhb
;
9029 tcg_shift
= tcg_constant_i32(fracbits
);
9031 if (size
== MO_64
) {
9032 int maxpass
= is_scalar
? 1 : 2;
9034 for (pass
= 0; pass
< maxpass
; pass
++) {
9035 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9037 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9039 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9041 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9043 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9044 tcg_temp_free_i64(tcg_op
);
9046 clear_vec_high(s
, is_q
, rd
);
9048 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9049 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9054 fn
= gen_helper_vfp_touhh
;
9056 fn
= gen_helper_vfp_toshh
;
9061 fn
= gen_helper_vfp_touls
;
9063 fn
= gen_helper_vfp_tosls
;
9067 g_assert_not_reached();
9070 for (pass
= 0; pass
< maxpass
; pass
++) {
9071 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9073 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9074 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9076 write_fp_sreg(s
, rd
, tcg_op
);
9078 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9080 tcg_temp_free_i32(tcg_op
);
9083 clear_vec_high(s
, is_q
, rd
);
9087 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9088 tcg_temp_free_ptr(tcg_fpstatus
);
9089 tcg_temp_free_i32(tcg_rmode
);
9092 /* AdvSIMD scalar shift by immediate
9093 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9094 * +-----+---+-------------+------+------+--------+---+------+------+
9095 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9096 * +-----+---+-------------+------+------+--------+---+------+------+
9098 * This is the scalar version so it works on a fixed sized registers
9100 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9102 int rd
= extract32(insn
, 0, 5);
9103 int rn
= extract32(insn
, 5, 5);
9104 int opcode
= extract32(insn
, 11, 5);
9105 int immb
= extract32(insn
, 16, 3);
9106 int immh
= extract32(insn
, 19, 4);
9107 bool is_u
= extract32(insn
, 29, 1);
9110 unallocated_encoding(s
);
9115 case 0x08: /* SRI */
9117 unallocated_encoding(s
);
9121 case 0x00: /* SSHR / USHR */
9122 case 0x02: /* SSRA / USRA */
9123 case 0x04: /* SRSHR / URSHR */
9124 case 0x06: /* SRSRA / URSRA */
9125 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9127 case 0x0a: /* SHL / SLI */
9128 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9130 case 0x1c: /* SCVTF, UCVTF */
9131 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9134 case 0x10: /* SQSHRUN, SQSHRUN2 */
9135 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9137 unallocated_encoding(s
);
9140 handle_vec_simd_sqshrn(s
, true, false, false, true,
9141 immh
, immb
, opcode
, rn
, rd
);
9143 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9144 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9145 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9146 immh
, immb
, opcode
, rn
, rd
);
9148 case 0xc: /* SQSHLU */
9150 unallocated_encoding(s
);
9153 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9155 case 0xe: /* SQSHL, UQSHL */
9156 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9158 case 0x1f: /* FCVTZS, FCVTZU */
9159 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9162 unallocated_encoding(s
);
9167 /* AdvSIMD scalar three different
9168 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9169 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9170 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9171 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9173 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9175 bool is_u
= extract32(insn
, 29, 1);
9176 int size
= extract32(insn
, 22, 2);
9177 int opcode
= extract32(insn
, 12, 4);
9178 int rm
= extract32(insn
, 16, 5);
9179 int rn
= extract32(insn
, 5, 5);
9180 int rd
= extract32(insn
, 0, 5);
9183 unallocated_encoding(s
);
9188 case 0x9: /* SQDMLAL, SQDMLAL2 */
9189 case 0xb: /* SQDMLSL, SQDMLSL2 */
9190 case 0xd: /* SQDMULL, SQDMULL2 */
9191 if (size
== 0 || size
== 3) {
9192 unallocated_encoding(s
);
9197 unallocated_encoding(s
);
9201 if (!fp_access_check(s
)) {
9206 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9207 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9208 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9210 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9211 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9213 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9214 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9217 case 0xd: /* SQDMULL, SQDMULL2 */
9219 case 0xb: /* SQDMLSL, SQDMLSL2 */
9220 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9222 case 0x9: /* SQDMLAL, SQDMLAL2 */
9223 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9224 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9228 g_assert_not_reached();
9231 write_fp_dreg(s
, rd
, tcg_res
);
9233 tcg_temp_free_i64(tcg_op1
);
9234 tcg_temp_free_i64(tcg_op2
);
9235 tcg_temp_free_i64(tcg_res
);
9237 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9238 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9239 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9241 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9242 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9245 case 0xd: /* SQDMULL, SQDMULL2 */
9247 case 0xb: /* SQDMLSL, SQDMLSL2 */
9248 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9250 case 0x9: /* SQDMLAL, SQDMLAL2 */
9252 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9253 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9254 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9256 tcg_temp_free_i64(tcg_op3
);
9260 g_assert_not_reached();
9263 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9264 write_fp_dreg(s
, rd
, tcg_res
);
9266 tcg_temp_free_i32(tcg_op1
);
9267 tcg_temp_free_i32(tcg_op2
);
9268 tcg_temp_free_i64(tcg_res
);
9272 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9273 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9275 /* Handle 64x64->64 opcodes which are shared between the scalar
9276 * and vector 3-same groups. We cover every opcode where size == 3
9277 * is valid in either the three-reg-same (integer, not pairwise)
9278 * or scalar-three-reg-same groups.
9283 case 0x1: /* SQADD */
9285 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9287 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9290 case 0x5: /* SQSUB */
9292 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9294 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9297 case 0x6: /* CMGT, CMHI */
9298 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9299 * We implement this using setcond (test) and then negating.
9301 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9303 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9304 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9306 case 0x7: /* CMGE, CMHS */
9307 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9309 case 0x11: /* CMTST, CMEQ */
9314 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9316 case 0x8: /* SSHL, USHL */
9318 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9320 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9323 case 0x9: /* SQSHL, UQSHL */
9325 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9327 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9330 case 0xa: /* SRSHL, URSHL */
9332 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9334 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9337 case 0xb: /* SQRSHL, UQRSHL */
9339 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9341 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9344 case 0x10: /* ADD, SUB */
9346 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9348 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9352 g_assert_not_reached();
9356 /* Handle the 3-same-operands float operations; shared by the scalar
9357 * and vector encodings. The caller must filter out any encodings
9358 * not allocated for the encoding it is dealing with.
9360 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9361 int fpopcode
, int rd
, int rn
, int rm
)
9364 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9366 for (pass
= 0; pass
< elements
; pass
++) {
9369 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9370 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9371 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9373 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9374 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9377 case 0x39: /* FMLS */
9378 /* As usual for ARM, separate negation for fused multiply-add */
9379 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9381 case 0x19: /* FMLA */
9382 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9383 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9386 case 0x18: /* FMAXNM */
9387 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9389 case 0x1a: /* FADD */
9390 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9392 case 0x1b: /* FMULX */
9393 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9395 case 0x1c: /* FCMEQ */
9396 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9398 case 0x1e: /* FMAX */
9399 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9401 case 0x1f: /* FRECPS */
9402 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9404 case 0x38: /* FMINNM */
9405 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9407 case 0x3a: /* FSUB */
9408 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9410 case 0x3e: /* FMIN */
9411 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9413 case 0x3f: /* FRSQRTS */
9414 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9416 case 0x5b: /* FMUL */
9417 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9419 case 0x5c: /* FCMGE */
9420 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9422 case 0x5d: /* FACGE */
9423 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9425 case 0x5f: /* FDIV */
9426 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9428 case 0x7a: /* FABD */
9429 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9430 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9432 case 0x7c: /* FCMGT */
9433 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9435 case 0x7d: /* FACGT */
9436 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9439 g_assert_not_reached();
9442 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9444 tcg_temp_free_i64(tcg_res
);
9445 tcg_temp_free_i64(tcg_op1
);
9446 tcg_temp_free_i64(tcg_op2
);
9449 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9450 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9451 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9453 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9454 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9457 case 0x39: /* FMLS */
9458 /* As usual for ARM, separate negation for fused multiply-add */
9459 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9461 case 0x19: /* FMLA */
9462 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9463 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9466 case 0x1a: /* FADD */
9467 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9469 case 0x1b: /* FMULX */
9470 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9472 case 0x1c: /* FCMEQ */
9473 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9475 case 0x1e: /* FMAX */
9476 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9478 case 0x1f: /* FRECPS */
9479 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9481 case 0x18: /* FMAXNM */
9482 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9484 case 0x38: /* FMINNM */
9485 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9487 case 0x3a: /* FSUB */
9488 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9490 case 0x3e: /* FMIN */
9491 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9493 case 0x3f: /* FRSQRTS */
9494 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9496 case 0x5b: /* FMUL */
9497 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9499 case 0x5c: /* FCMGE */
9500 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9502 case 0x5d: /* FACGE */
9503 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9505 case 0x5f: /* FDIV */
9506 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9508 case 0x7a: /* FABD */
9509 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9510 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9512 case 0x7c: /* FCMGT */
9513 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9515 case 0x7d: /* FACGT */
9516 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9519 g_assert_not_reached();
9522 if (elements
== 1) {
9523 /* scalar single so clear high part */
9524 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9526 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9527 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9528 tcg_temp_free_i64(tcg_tmp
);
9530 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9533 tcg_temp_free_i32(tcg_res
);
9534 tcg_temp_free_i32(tcg_op1
);
9535 tcg_temp_free_i32(tcg_op2
);
9539 tcg_temp_free_ptr(fpst
);
9541 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9544 /* AdvSIMD scalar three same
9545 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9546 * +-----+---+-----------+------+---+------+--------+---+------+------+
9547 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9548 * +-----+---+-----------+------+---+------+--------+---+------+------+
9550 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9552 int rd
= extract32(insn
, 0, 5);
9553 int rn
= extract32(insn
, 5, 5);
9554 int opcode
= extract32(insn
, 11, 5);
9555 int rm
= extract32(insn
, 16, 5);
9556 int size
= extract32(insn
, 22, 2);
9557 bool u
= extract32(insn
, 29, 1);
9560 if (opcode
>= 0x18) {
9561 /* Floating point: U, size[1] and opcode indicate operation */
9562 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9564 case 0x1b: /* FMULX */
9565 case 0x1f: /* FRECPS */
9566 case 0x3f: /* FRSQRTS */
9567 case 0x5d: /* FACGE */
9568 case 0x7d: /* FACGT */
9569 case 0x1c: /* FCMEQ */
9570 case 0x5c: /* FCMGE */
9571 case 0x7c: /* FCMGT */
9572 case 0x7a: /* FABD */
9575 unallocated_encoding(s
);
9579 if (!fp_access_check(s
)) {
9583 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9588 case 0x1: /* SQADD, UQADD */
9589 case 0x5: /* SQSUB, UQSUB */
9590 case 0x9: /* SQSHL, UQSHL */
9591 case 0xb: /* SQRSHL, UQRSHL */
9593 case 0x8: /* SSHL, USHL */
9594 case 0xa: /* SRSHL, URSHL */
9595 case 0x6: /* CMGT, CMHI */
9596 case 0x7: /* CMGE, CMHS */
9597 case 0x11: /* CMTST, CMEQ */
9598 case 0x10: /* ADD, SUB (vector) */
9600 unallocated_encoding(s
);
9604 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9605 if (size
!= 1 && size
!= 2) {
9606 unallocated_encoding(s
);
9611 unallocated_encoding(s
);
9615 if (!fp_access_check(s
)) {
9619 tcg_rd
= tcg_temp_new_i64();
9622 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9623 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9625 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9626 tcg_temp_free_i64(tcg_rn
);
9627 tcg_temp_free_i64(tcg_rm
);
9629 /* Do a single operation on the lowest element in the vector.
9630 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9631 * no side effects for all these operations.
9632 * OPTME: special-purpose helpers would avoid doing some
9633 * unnecessary work in the helper for the 8 and 16 bit cases.
9635 NeonGenTwoOpEnvFn
*genenvfn
;
9636 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9637 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9638 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9640 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9641 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9644 case 0x1: /* SQADD, UQADD */
9646 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9647 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9648 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9649 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9651 genenvfn
= fns
[size
][u
];
9654 case 0x5: /* SQSUB, UQSUB */
9656 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9657 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9658 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9659 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9661 genenvfn
= fns
[size
][u
];
9664 case 0x9: /* SQSHL, UQSHL */
9666 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9667 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9668 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9669 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9671 genenvfn
= fns
[size
][u
];
9674 case 0xb: /* SQRSHL, UQRSHL */
9676 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9677 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9678 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9679 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9681 genenvfn
= fns
[size
][u
];
9684 case 0x16: /* SQDMULH, SQRDMULH */
9686 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9687 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9688 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9690 assert(size
== 1 || size
== 2);
9691 genenvfn
= fns
[size
- 1][u
];
9695 g_assert_not_reached();
9698 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9699 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9700 tcg_temp_free_i32(tcg_rd32
);
9701 tcg_temp_free_i32(tcg_rn
);
9702 tcg_temp_free_i32(tcg_rm
);
9705 write_fp_dreg(s
, rd
, tcg_rd
);
9707 tcg_temp_free_i64(tcg_rd
);
9710 /* AdvSIMD scalar three same FP16
9711 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9712 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9713 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9714 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9715 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9716 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9718 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9721 int rd
= extract32(insn
, 0, 5);
9722 int rn
= extract32(insn
, 5, 5);
9723 int opcode
= extract32(insn
, 11, 3);
9724 int rm
= extract32(insn
, 16, 5);
9725 bool u
= extract32(insn
, 29, 1);
9726 bool a
= extract32(insn
, 23, 1);
9727 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9734 case 0x03: /* FMULX */
9735 case 0x04: /* FCMEQ (reg) */
9736 case 0x07: /* FRECPS */
9737 case 0x0f: /* FRSQRTS */
9738 case 0x14: /* FCMGE (reg) */
9739 case 0x15: /* FACGE */
9740 case 0x1a: /* FABD */
9741 case 0x1c: /* FCMGT (reg) */
9742 case 0x1d: /* FACGT */
9745 unallocated_encoding(s
);
9749 if (!dc_isar_feature(aa64_fp16
, s
)) {
9750 unallocated_encoding(s
);
9753 if (!fp_access_check(s
)) {
9757 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9759 tcg_op1
= read_fp_hreg(s
, rn
);
9760 tcg_op2
= read_fp_hreg(s
, rm
);
9761 tcg_res
= tcg_temp_new_i32();
9764 case 0x03: /* FMULX */
9765 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9767 case 0x04: /* FCMEQ (reg) */
9768 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9770 case 0x07: /* FRECPS */
9771 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9773 case 0x0f: /* FRSQRTS */
9774 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9776 case 0x14: /* FCMGE (reg) */
9777 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9779 case 0x15: /* FACGE */
9780 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9782 case 0x1a: /* FABD */
9783 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9784 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9786 case 0x1c: /* FCMGT (reg) */
9787 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9789 case 0x1d: /* FACGT */
9790 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9793 g_assert_not_reached();
9796 write_fp_sreg(s
, rd
, tcg_res
);
9799 tcg_temp_free_i32(tcg_res
);
9800 tcg_temp_free_i32(tcg_op1
);
9801 tcg_temp_free_i32(tcg_op2
);
9802 tcg_temp_free_ptr(fpst
);
9805 /* AdvSIMD scalar three same extra
9806 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9807 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9808 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9809 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9811 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9814 int rd
= extract32(insn
, 0, 5);
9815 int rn
= extract32(insn
, 5, 5);
9816 int opcode
= extract32(insn
, 11, 4);
9817 int rm
= extract32(insn
, 16, 5);
9818 int size
= extract32(insn
, 22, 2);
9819 bool u
= extract32(insn
, 29, 1);
9820 TCGv_i32 ele1
, ele2
, ele3
;
9824 switch (u
* 16 + opcode
) {
9825 case 0x10: /* SQRDMLAH (vector) */
9826 case 0x11: /* SQRDMLSH (vector) */
9827 if (size
!= 1 && size
!= 2) {
9828 unallocated_encoding(s
);
9831 feature
= dc_isar_feature(aa64_rdm
, s
);
9834 unallocated_encoding(s
);
9838 unallocated_encoding(s
);
9841 if (!fp_access_check(s
)) {
9845 /* Do a single operation on the lowest element in the vector.
9846 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9847 * with no side effects for all these operations.
9848 * OPTME: special-purpose helpers would avoid doing some
9849 * unnecessary work in the helper for the 16 bit cases.
9851 ele1
= tcg_temp_new_i32();
9852 ele2
= tcg_temp_new_i32();
9853 ele3
= tcg_temp_new_i32();
9855 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9856 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9857 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9860 case 0x0: /* SQRDMLAH */
9862 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9864 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9867 case 0x1: /* SQRDMLSH */
9869 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9871 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9875 g_assert_not_reached();
9877 tcg_temp_free_i32(ele1
);
9878 tcg_temp_free_i32(ele2
);
9880 res
= tcg_temp_new_i64();
9881 tcg_gen_extu_i32_i64(res
, ele3
);
9882 tcg_temp_free_i32(ele3
);
9884 write_fp_dreg(s
, rd
, res
);
9885 tcg_temp_free_i64(res
);
9888 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9889 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9890 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9892 /* Handle 64->64 opcodes which are shared between the scalar and
9893 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9894 * is valid in either group and also the double-precision fp ops.
9895 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9901 case 0x4: /* CLS, CLZ */
9903 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9905 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9909 /* This opcode is shared with CNT and RBIT but we have earlier
9910 * enforced that size == 3 if and only if this is the NOT insn.
9912 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9914 case 0x7: /* SQABS, SQNEG */
9916 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9918 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9921 case 0xa: /* CMLT */
9922 /* 64 bit integer comparison against zero, result is
9923 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9928 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9929 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9931 case 0x8: /* CMGT, CMGE */
9932 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9934 case 0x9: /* CMEQ, CMLE */
9935 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9937 case 0xb: /* ABS, NEG */
9939 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9941 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9944 case 0x2f: /* FABS */
9945 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9947 case 0x6f: /* FNEG */
9948 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9950 case 0x7f: /* FSQRT */
9951 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9953 case 0x1a: /* FCVTNS */
9954 case 0x1b: /* FCVTMS */
9955 case 0x1c: /* FCVTAS */
9956 case 0x3a: /* FCVTPS */
9957 case 0x3b: /* FCVTZS */
9958 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9960 case 0x5a: /* FCVTNU */
9961 case 0x5b: /* FCVTMU */
9962 case 0x5c: /* FCVTAU */
9963 case 0x7a: /* FCVTPU */
9964 case 0x7b: /* FCVTZU */
9965 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9967 case 0x18: /* FRINTN */
9968 case 0x19: /* FRINTM */
9969 case 0x38: /* FRINTP */
9970 case 0x39: /* FRINTZ */
9971 case 0x58: /* FRINTA */
9972 case 0x79: /* FRINTI */
9973 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9975 case 0x59: /* FRINTX */
9976 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9978 case 0x1e: /* FRINT32Z */
9979 case 0x5e: /* FRINT32X */
9980 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9982 case 0x1f: /* FRINT64Z */
9983 case 0x5f: /* FRINT64X */
9984 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9987 g_assert_not_reached();
9991 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9992 bool is_scalar
, bool is_u
, bool is_q
,
9993 int size
, int rn
, int rd
)
9995 bool is_double
= (size
== MO_64
);
9998 if (!fp_access_check(s
)) {
10002 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
10005 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10006 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
10007 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10008 NeonGenTwoDoubleOpFn
*genfn
;
10013 case 0x2e: /* FCMLT (zero) */
10016 case 0x2c: /* FCMGT (zero) */
10017 genfn
= gen_helper_neon_cgt_f64
;
10019 case 0x2d: /* FCMEQ (zero) */
10020 genfn
= gen_helper_neon_ceq_f64
;
10022 case 0x6d: /* FCMLE (zero) */
10025 case 0x6c: /* FCMGE (zero) */
10026 genfn
= gen_helper_neon_cge_f64
;
10029 g_assert_not_reached();
10032 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10033 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10035 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10037 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10039 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10041 tcg_temp_free_i64(tcg_res
);
10042 tcg_temp_free_i64(tcg_op
);
10044 clear_vec_high(s
, !is_scalar
, rd
);
10046 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10047 TCGv_i32 tcg_zero
= tcg_constant_i32(0);
10048 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10049 NeonGenTwoSingleOpFn
*genfn
;
10051 int pass
, maxpasses
;
10053 if (size
== MO_16
) {
10055 case 0x2e: /* FCMLT (zero) */
10058 case 0x2c: /* FCMGT (zero) */
10059 genfn
= gen_helper_advsimd_cgt_f16
;
10061 case 0x2d: /* FCMEQ (zero) */
10062 genfn
= gen_helper_advsimd_ceq_f16
;
10064 case 0x6d: /* FCMLE (zero) */
10067 case 0x6c: /* FCMGE (zero) */
10068 genfn
= gen_helper_advsimd_cge_f16
;
10071 g_assert_not_reached();
10075 case 0x2e: /* FCMLT (zero) */
10078 case 0x2c: /* FCMGT (zero) */
10079 genfn
= gen_helper_neon_cgt_f32
;
10081 case 0x2d: /* FCMEQ (zero) */
10082 genfn
= gen_helper_neon_ceq_f32
;
10084 case 0x6d: /* FCMLE (zero) */
10087 case 0x6c: /* FCMGE (zero) */
10088 genfn
= gen_helper_neon_cge_f32
;
10091 g_assert_not_reached();
10098 int vector_size
= 8 << is_q
;
10099 maxpasses
= vector_size
>> size
;
10102 for (pass
= 0; pass
< maxpasses
; pass
++) {
10103 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10105 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10107 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10110 write_fp_sreg(s
, rd
, tcg_res
);
10112 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10115 tcg_temp_free_i32(tcg_res
);
10116 tcg_temp_free_i32(tcg_op
);
10118 clear_vec_high(s
, is_q
, rd
);
10122 tcg_temp_free_ptr(fpst
);
10125 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10126 bool is_scalar
, bool is_u
, bool is_q
,
10127 int size
, int rn
, int rd
)
10129 bool is_double
= (size
== 3);
10130 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10133 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10134 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10137 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10138 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10140 case 0x3d: /* FRECPE */
10141 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10143 case 0x3f: /* FRECPX */
10144 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10146 case 0x7d: /* FRSQRTE */
10147 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10150 g_assert_not_reached();
10152 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10154 tcg_temp_free_i64(tcg_res
);
10155 tcg_temp_free_i64(tcg_op
);
10156 clear_vec_high(s
, !is_scalar
, rd
);
10158 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10159 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10160 int pass
, maxpasses
;
10165 maxpasses
= is_q
? 4 : 2;
10168 for (pass
= 0; pass
< maxpasses
; pass
++) {
10169 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10172 case 0x3c: /* URECPE */
10173 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10175 case 0x3d: /* FRECPE */
10176 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10178 case 0x3f: /* FRECPX */
10179 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10181 case 0x7d: /* FRSQRTE */
10182 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10185 g_assert_not_reached();
10189 write_fp_sreg(s
, rd
, tcg_res
);
10191 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10194 tcg_temp_free_i32(tcg_res
);
10195 tcg_temp_free_i32(tcg_op
);
10197 clear_vec_high(s
, is_q
, rd
);
10200 tcg_temp_free_ptr(fpst
);
10203 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10204 int opcode
, bool u
, bool is_q
,
10205 int size
, int rn
, int rd
)
10207 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10208 * in the source becomes a size element in the destination).
10211 TCGv_i32 tcg_res
[2];
10212 int destelt
= is_q
? 2 : 0;
10213 int passes
= scalar
? 1 : 2;
10216 tcg_res
[1] = tcg_constant_i32(0);
10219 for (pass
= 0; pass
< passes
; pass
++) {
10220 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10221 NeonGenNarrowFn
*genfn
= NULL
;
10222 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10225 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10227 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10229 tcg_res
[pass
] = tcg_temp_new_i32();
10232 case 0x12: /* XTN, SQXTUN */
10234 static NeonGenNarrowFn
* const xtnfns
[3] = {
10235 gen_helper_neon_narrow_u8
,
10236 gen_helper_neon_narrow_u16
,
10237 tcg_gen_extrl_i64_i32
,
10239 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10240 gen_helper_neon_unarrow_sat8
,
10241 gen_helper_neon_unarrow_sat16
,
10242 gen_helper_neon_unarrow_sat32
,
10245 genenvfn
= sqxtunfns
[size
];
10247 genfn
= xtnfns
[size
];
10251 case 0x14: /* SQXTN, UQXTN */
10253 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10254 { gen_helper_neon_narrow_sat_s8
,
10255 gen_helper_neon_narrow_sat_u8
},
10256 { gen_helper_neon_narrow_sat_s16
,
10257 gen_helper_neon_narrow_sat_u16
},
10258 { gen_helper_neon_narrow_sat_s32
,
10259 gen_helper_neon_narrow_sat_u32
},
10261 genenvfn
= fns
[size
][u
];
10264 case 0x16: /* FCVTN, FCVTN2 */
10265 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10267 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10269 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10270 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10271 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10272 TCGv_i32 ahp
= get_ahp_flag();
10274 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10275 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10276 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10277 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10278 tcg_temp_free_i32(tcg_lo
);
10279 tcg_temp_free_i32(tcg_hi
);
10280 tcg_temp_free_ptr(fpst
);
10281 tcg_temp_free_i32(ahp
);
10284 case 0x36: /* BFCVTN, BFCVTN2 */
10286 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10287 gen_helper_bfcvt_pair(tcg_res
[pass
], tcg_op
, fpst
);
10288 tcg_temp_free_ptr(fpst
);
10291 case 0x56: /* FCVTXN, FCVTXN2 */
10292 /* 64 bit to 32 bit float conversion
10293 * with von Neumann rounding (round to odd)
10296 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10299 g_assert_not_reached();
10303 genfn(tcg_res
[pass
], tcg_op
);
10304 } else if (genenvfn
) {
10305 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10308 tcg_temp_free_i64(tcg_op
);
10311 for (pass
= 0; pass
< 2; pass
++) {
10312 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10313 tcg_temp_free_i32(tcg_res
[pass
]);
10315 clear_vec_high(s
, is_q
, rd
);
10318 /* Remaining saturating accumulating ops */
10319 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10320 bool is_q
, int size
, int rn
, int rd
)
10322 bool is_double
= (size
== 3);
10325 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10326 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10329 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10330 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10331 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10333 if (is_u
) { /* USQADD */
10334 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10335 } else { /* SUQADD */
10336 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10338 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10340 tcg_temp_free_i64(tcg_rd
);
10341 tcg_temp_free_i64(tcg_rn
);
10342 clear_vec_high(s
, !is_scalar
, rd
);
10344 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10345 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10346 int pass
, maxpasses
;
10351 maxpasses
= is_q
? 4 : 2;
10354 for (pass
= 0; pass
< maxpasses
; pass
++) {
10356 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10357 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10359 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10360 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10363 if (is_u
) { /* USQADD */
10366 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10369 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10372 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10375 g_assert_not_reached();
10377 } else { /* SUQADD */
10380 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10383 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10386 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10389 g_assert_not_reached();
10394 write_vec_element(s
, tcg_constant_i64(0), rd
, 0, MO_64
);
10396 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10398 tcg_temp_free_i32(tcg_rd
);
10399 tcg_temp_free_i32(tcg_rn
);
10400 clear_vec_high(s
, is_q
, rd
);
10404 /* AdvSIMD scalar two reg misc
10405 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10406 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10407 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10408 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10410 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10412 int rd
= extract32(insn
, 0, 5);
10413 int rn
= extract32(insn
, 5, 5);
10414 int opcode
= extract32(insn
, 12, 5);
10415 int size
= extract32(insn
, 22, 2);
10416 bool u
= extract32(insn
, 29, 1);
10417 bool is_fcvt
= false;
10419 TCGv_i32 tcg_rmode
;
10420 TCGv_ptr tcg_fpstatus
;
10423 case 0x3: /* USQADD / SUQADD*/
10424 if (!fp_access_check(s
)) {
10427 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10429 case 0x7: /* SQABS / SQNEG */
10431 case 0xa: /* CMLT */
10433 unallocated_encoding(s
);
10437 case 0x8: /* CMGT, CMGE */
10438 case 0x9: /* CMEQ, CMLE */
10439 case 0xb: /* ABS, NEG */
10441 unallocated_encoding(s
);
10445 case 0x12: /* SQXTUN */
10447 unallocated_encoding(s
);
10451 case 0x14: /* SQXTN, UQXTN */
10453 unallocated_encoding(s
);
10456 if (!fp_access_check(s
)) {
10459 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10462 case 0x16 ... 0x1d:
10464 /* Floating point: U, size[1] and opcode indicate operation;
10465 * size[0] indicates single or double precision.
10467 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10468 size
= extract32(size
, 0, 1) ? 3 : 2;
10470 case 0x2c: /* FCMGT (zero) */
10471 case 0x2d: /* FCMEQ (zero) */
10472 case 0x2e: /* FCMLT (zero) */
10473 case 0x6c: /* FCMGE (zero) */
10474 case 0x6d: /* FCMLE (zero) */
10475 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10477 case 0x1d: /* SCVTF */
10478 case 0x5d: /* UCVTF */
10480 bool is_signed
= (opcode
== 0x1d);
10481 if (!fp_access_check(s
)) {
10484 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10487 case 0x3d: /* FRECPE */
10488 case 0x3f: /* FRECPX */
10489 case 0x7d: /* FRSQRTE */
10490 if (!fp_access_check(s
)) {
10493 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10495 case 0x1a: /* FCVTNS */
10496 case 0x1b: /* FCVTMS */
10497 case 0x3a: /* FCVTPS */
10498 case 0x3b: /* FCVTZS */
10499 case 0x5a: /* FCVTNU */
10500 case 0x5b: /* FCVTMU */
10501 case 0x7a: /* FCVTPU */
10502 case 0x7b: /* FCVTZU */
10504 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10506 case 0x1c: /* FCVTAS */
10507 case 0x5c: /* FCVTAU */
10508 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10510 rmode
= FPROUNDING_TIEAWAY
;
10512 case 0x56: /* FCVTXN, FCVTXN2 */
10514 unallocated_encoding(s
);
10517 if (!fp_access_check(s
)) {
10520 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10523 unallocated_encoding(s
);
10528 unallocated_encoding(s
);
10532 if (!fp_access_check(s
)) {
10537 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10538 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10539 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10542 tcg_fpstatus
= NULL
;
10546 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10547 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10549 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10550 write_fp_dreg(s
, rd
, tcg_rd
);
10551 tcg_temp_free_i64(tcg_rd
);
10552 tcg_temp_free_i64(tcg_rn
);
10554 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10555 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10557 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10560 case 0x7: /* SQABS, SQNEG */
10562 NeonGenOneOpEnvFn
*genfn
;
10563 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10564 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10565 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10566 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10568 genfn
= fns
[size
][u
];
10569 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10572 case 0x1a: /* FCVTNS */
10573 case 0x1b: /* FCVTMS */
10574 case 0x1c: /* FCVTAS */
10575 case 0x3a: /* FCVTPS */
10576 case 0x3b: /* FCVTZS */
10577 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10580 case 0x5a: /* FCVTNU */
10581 case 0x5b: /* FCVTMU */
10582 case 0x5c: /* FCVTAU */
10583 case 0x7a: /* FCVTPU */
10584 case 0x7b: /* FCVTZU */
10585 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10589 g_assert_not_reached();
10592 write_fp_sreg(s
, rd
, tcg_rd
);
10593 tcg_temp_free_i32(tcg_rd
);
10594 tcg_temp_free_i32(tcg_rn
);
10598 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10599 tcg_temp_free_i32(tcg_rmode
);
10600 tcg_temp_free_ptr(tcg_fpstatus
);
10604 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10605 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10606 int immh
, int immb
, int opcode
, int rn
, int rd
)
10608 int size
= 32 - clz32(immh
) - 1;
10609 int immhb
= immh
<< 3 | immb
;
10610 int shift
= 2 * (8 << size
) - immhb
;
10611 GVecGen2iFn
*gvec_fn
;
10613 if (extract32(immh
, 3, 1) && !is_q
) {
10614 unallocated_encoding(s
);
10617 tcg_debug_assert(size
<= 3);
10619 if (!fp_access_check(s
)) {
10624 case 0x02: /* SSRA / USRA (accumulate) */
10625 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10628 case 0x08: /* SRI */
10629 gvec_fn
= gen_gvec_sri
;
10632 case 0x00: /* SSHR / USHR */
10634 if (shift
== 8 << size
) {
10635 /* Shift count the same size as element size produces zero. */
10636 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10637 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10640 gvec_fn
= tcg_gen_gvec_shri
;
10642 /* Shift count the same size as element size produces all sign. */
10643 if (shift
== 8 << size
) {
10646 gvec_fn
= tcg_gen_gvec_sari
;
10650 case 0x04: /* SRSHR / URSHR (rounding) */
10651 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10654 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10655 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10659 g_assert_not_reached();
10662 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10665 /* SHL/SLI - Vector shift left */
10666 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10667 int immh
, int immb
, int opcode
, int rn
, int rd
)
10669 int size
= 32 - clz32(immh
) - 1;
10670 int immhb
= immh
<< 3 | immb
;
10671 int shift
= immhb
- (8 << size
);
10673 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10674 assert(size
>= 0 && size
<= 3);
10676 if (extract32(immh
, 3, 1) && !is_q
) {
10677 unallocated_encoding(s
);
10681 if (!fp_access_check(s
)) {
10686 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10688 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10692 /* USHLL/SHLL - Vector shift left with widening */
10693 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10694 int immh
, int immb
, int opcode
, int rn
, int rd
)
10696 int size
= 32 - clz32(immh
) - 1;
10697 int immhb
= immh
<< 3 | immb
;
10698 int shift
= immhb
- (8 << size
);
10700 int esize
= 8 << size
;
10701 int elements
= dsize
/esize
;
10702 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10703 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10707 unallocated_encoding(s
);
10711 if (!fp_access_check(s
)) {
10715 /* For the LL variants the store is larger than the load,
10716 * so if rd == rn we would overwrite parts of our input.
10717 * So load everything right now and use shifts in the main loop.
10719 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10721 for (i
= 0; i
< elements
; i
++) {
10722 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10723 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10724 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10725 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10729 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10730 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10731 int immh
, int immb
, int opcode
, int rn
, int rd
)
10733 int immhb
= immh
<< 3 | immb
;
10734 int size
= 32 - clz32(immh
) - 1;
10736 int esize
= 8 << size
;
10737 int elements
= dsize
/esize
;
10738 int shift
= (2 * esize
) - immhb
;
10739 bool round
= extract32(opcode
, 0, 1);
10740 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10741 TCGv_i64 tcg_round
;
10744 if (extract32(immh
, 3, 1)) {
10745 unallocated_encoding(s
);
10749 if (!fp_access_check(s
)) {
10753 tcg_rn
= tcg_temp_new_i64();
10754 tcg_rd
= tcg_temp_new_i64();
10755 tcg_final
= tcg_temp_new_i64();
10756 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10759 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
10764 for (i
= 0; i
< elements
; i
++) {
10765 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10766 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10767 false, true, size
+1, shift
);
10769 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10773 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10775 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10777 tcg_temp_free_i64(tcg_rn
);
10778 tcg_temp_free_i64(tcg_rd
);
10779 tcg_temp_free_i64(tcg_final
);
10781 clear_vec_high(s
, is_q
, rd
);
10785 /* AdvSIMD shift by immediate
10786 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10787 * +---+---+---+-------------+------+------+--------+---+------+------+
10788 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10789 * +---+---+---+-------------+------+------+--------+---+------+------+
10791 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10793 int rd
= extract32(insn
, 0, 5);
10794 int rn
= extract32(insn
, 5, 5);
10795 int opcode
= extract32(insn
, 11, 5);
10796 int immb
= extract32(insn
, 16, 3);
10797 int immh
= extract32(insn
, 19, 4);
10798 bool is_u
= extract32(insn
, 29, 1);
10799 bool is_q
= extract32(insn
, 30, 1);
10801 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10805 case 0x08: /* SRI */
10807 unallocated_encoding(s
);
10811 case 0x00: /* SSHR / USHR */
10812 case 0x02: /* SSRA / USRA (accumulate) */
10813 case 0x04: /* SRSHR / URSHR (rounding) */
10814 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10815 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10817 case 0x0a: /* SHL / SLI */
10818 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10820 case 0x10: /* SHRN */
10821 case 0x11: /* RSHRN / SQRSHRUN */
10823 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10826 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10829 case 0x12: /* SQSHRN / UQSHRN */
10830 case 0x13: /* SQRSHRN / UQRSHRN */
10831 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10834 case 0x14: /* SSHLL / USHLL */
10835 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10837 case 0x1c: /* SCVTF / UCVTF */
10838 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10841 case 0xc: /* SQSHLU */
10843 unallocated_encoding(s
);
10846 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10848 case 0xe: /* SQSHL, UQSHL */
10849 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10851 case 0x1f: /* FCVTZS/ FCVTZU */
10852 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10855 unallocated_encoding(s
);
10860 /* Generate code to do a "long" addition or subtraction, ie one done in
10861 * TCGv_i64 on vector lanes twice the width specified by size.
10863 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10864 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10866 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10867 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10868 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10869 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10871 NeonGenTwo64OpFn
*genfn
;
10874 genfn
= fns
[size
][is_sub
];
10875 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10878 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10879 int opcode
, int rd
, int rn
, int rm
)
10881 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10882 TCGv_i64 tcg_res
[2];
10885 tcg_res
[0] = tcg_temp_new_i64();
10886 tcg_res
[1] = tcg_temp_new_i64();
10888 /* Does this op do an adding accumulate, a subtracting accumulate,
10889 * or no accumulate at all?
10907 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10908 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10911 /* size == 2 means two 32x32->64 operations; this is worth special
10912 * casing because we can generally handle it inline.
10915 for (pass
= 0; pass
< 2; pass
++) {
10916 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10917 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10918 TCGv_i64 tcg_passres
;
10919 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10921 int elt
= pass
+ is_q
* 2;
10923 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10924 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10927 tcg_passres
= tcg_res
[pass
];
10929 tcg_passres
= tcg_temp_new_i64();
10933 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10934 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10936 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10937 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10939 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10940 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10942 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10943 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10945 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10946 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10947 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10949 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10950 tcg_temp_free_i64(tcg_tmp1
);
10951 tcg_temp_free_i64(tcg_tmp2
);
10954 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10955 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10956 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10957 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10959 case 9: /* SQDMLAL, SQDMLAL2 */
10960 case 11: /* SQDMLSL, SQDMLSL2 */
10961 case 13: /* SQDMULL, SQDMULL2 */
10962 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10963 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10964 tcg_passres
, tcg_passres
);
10967 g_assert_not_reached();
10970 if (opcode
== 9 || opcode
== 11) {
10971 /* saturating accumulate ops */
10973 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10975 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10976 tcg_res
[pass
], tcg_passres
);
10977 } else if (accop
> 0) {
10978 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10979 } else if (accop
< 0) {
10980 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10984 tcg_temp_free_i64(tcg_passres
);
10987 tcg_temp_free_i64(tcg_op1
);
10988 tcg_temp_free_i64(tcg_op2
);
10991 /* size 0 or 1, generally helper functions */
10992 for (pass
= 0; pass
< 2; pass
++) {
10993 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10994 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10995 TCGv_i64 tcg_passres
;
10996 int elt
= pass
+ is_q
* 2;
10998 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10999 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11002 tcg_passres
= tcg_res
[pass
];
11004 tcg_passres
= tcg_temp_new_i64();
11008 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11009 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11011 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11012 static NeonGenWidenFn
* const widenfns
[2][2] = {
11013 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11014 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11016 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11018 widenfn(tcg_op2_64
, tcg_op2
);
11019 widenfn(tcg_passres
, tcg_op1
);
11020 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11021 tcg_passres
, tcg_op2_64
);
11022 tcg_temp_free_i64(tcg_op2_64
);
11025 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11026 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11029 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11031 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11035 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11037 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11041 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11042 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11043 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11046 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11048 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11052 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11054 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11058 case 9: /* SQDMLAL, SQDMLAL2 */
11059 case 11: /* SQDMLSL, SQDMLSL2 */
11060 case 13: /* SQDMULL, SQDMULL2 */
11062 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11063 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11064 tcg_passres
, tcg_passres
);
11067 g_assert_not_reached();
11069 tcg_temp_free_i32(tcg_op1
);
11070 tcg_temp_free_i32(tcg_op2
);
11073 if (opcode
== 9 || opcode
== 11) {
11074 /* saturating accumulate ops */
11076 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11078 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11082 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11083 tcg_res
[pass
], tcg_passres
);
11085 tcg_temp_free_i64(tcg_passres
);
11090 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11091 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11092 tcg_temp_free_i64(tcg_res
[0]);
11093 tcg_temp_free_i64(tcg_res
[1]);
11096 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11097 int opcode
, int rd
, int rn
, int rm
)
11099 TCGv_i64 tcg_res
[2];
11100 int part
= is_q
? 2 : 0;
11103 for (pass
= 0; pass
< 2; pass
++) {
11104 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11105 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11106 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11107 static NeonGenWidenFn
* const widenfns
[3][2] = {
11108 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11109 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11110 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11112 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11114 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11115 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11116 widenfn(tcg_op2_wide
, tcg_op2
);
11117 tcg_temp_free_i32(tcg_op2
);
11118 tcg_res
[pass
] = tcg_temp_new_i64();
11119 gen_neon_addl(size
, (opcode
== 3),
11120 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11121 tcg_temp_free_i64(tcg_op1
);
11122 tcg_temp_free_i64(tcg_op2_wide
);
11125 for (pass
= 0; pass
< 2; pass
++) {
11126 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11127 tcg_temp_free_i64(tcg_res
[pass
]);
11131 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11133 tcg_gen_addi_i64(in
, in
, 1U << 31);
11134 tcg_gen_extrh_i64_i32(res
, in
);
11137 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11138 int opcode
, int rd
, int rn
, int rm
)
11140 TCGv_i32 tcg_res
[2];
11141 int part
= is_q
? 2 : 0;
11144 for (pass
= 0; pass
< 2; pass
++) {
11145 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11146 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11147 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11148 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11149 { gen_helper_neon_narrow_high_u8
,
11150 gen_helper_neon_narrow_round_high_u8
},
11151 { gen_helper_neon_narrow_high_u16
,
11152 gen_helper_neon_narrow_round_high_u16
},
11153 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11155 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11157 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11158 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11160 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11162 tcg_temp_free_i64(tcg_op1
);
11163 tcg_temp_free_i64(tcg_op2
);
11165 tcg_res
[pass
] = tcg_temp_new_i32();
11166 gennarrow(tcg_res
[pass
], tcg_wideres
);
11167 tcg_temp_free_i64(tcg_wideres
);
11170 for (pass
= 0; pass
< 2; pass
++) {
11171 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11172 tcg_temp_free_i32(tcg_res
[pass
]);
11174 clear_vec_high(s
, is_q
, rd
);
11177 /* AdvSIMD three different
11178 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11179 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11180 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11181 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11183 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11185 /* Instructions in this group fall into three basic classes
11186 * (in each case with the operation working on each element in
11187 * the input vectors):
11188 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11190 * (2) wide 64 x 128 -> 128
11191 * (3) narrowing 128 x 128 -> 64
11192 * Here we do initial decode, catch unallocated cases and
11193 * dispatch to separate functions for each class.
11195 int is_q
= extract32(insn
, 30, 1);
11196 int is_u
= extract32(insn
, 29, 1);
11197 int size
= extract32(insn
, 22, 2);
11198 int opcode
= extract32(insn
, 12, 4);
11199 int rm
= extract32(insn
, 16, 5);
11200 int rn
= extract32(insn
, 5, 5);
11201 int rd
= extract32(insn
, 0, 5);
11204 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11205 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11206 /* 64 x 128 -> 128 */
11208 unallocated_encoding(s
);
11211 if (!fp_access_check(s
)) {
11214 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11216 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11217 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11218 /* 128 x 128 -> 64 */
11220 unallocated_encoding(s
);
11223 if (!fp_access_check(s
)) {
11226 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11228 case 14: /* PMULL, PMULL2 */
11230 unallocated_encoding(s
);
11234 case 0: /* PMULL.P8 */
11235 if (!fp_access_check(s
)) {
11238 /* The Q field specifies lo/hi half input for this insn. */
11239 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11240 gen_helper_neon_pmull_h
);
11243 case 3: /* PMULL.P64 */
11244 if (!dc_isar_feature(aa64_pmull
, s
)) {
11245 unallocated_encoding(s
);
11248 if (!fp_access_check(s
)) {
11251 /* The Q field specifies lo/hi half input for this insn. */
11252 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11253 gen_helper_gvec_pmull_q
);
11257 unallocated_encoding(s
);
11261 case 9: /* SQDMLAL, SQDMLAL2 */
11262 case 11: /* SQDMLSL, SQDMLSL2 */
11263 case 13: /* SQDMULL, SQDMULL2 */
11264 if (is_u
|| size
== 0) {
11265 unallocated_encoding(s
);
11269 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11270 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11271 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11272 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11273 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11274 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11275 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11276 /* 64 x 64 -> 128 */
11278 unallocated_encoding(s
);
11281 if (!fp_access_check(s
)) {
11285 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11288 /* opcode 15 not allocated */
11289 unallocated_encoding(s
);
11294 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11295 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11297 int rd
= extract32(insn
, 0, 5);
11298 int rn
= extract32(insn
, 5, 5);
11299 int rm
= extract32(insn
, 16, 5);
11300 int size
= extract32(insn
, 22, 2);
11301 bool is_u
= extract32(insn
, 29, 1);
11302 bool is_q
= extract32(insn
, 30, 1);
11304 if (!fp_access_check(s
)) {
11308 switch (size
+ 4 * is_u
) {
11310 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11313 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11316 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11319 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11322 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11325 case 5: /* BSL bitwise select */
11326 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11328 case 6: /* BIT, bitwise insert if true */
11329 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11331 case 7: /* BIF, bitwise insert if false */
11332 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11336 g_assert_not_reached();
11340 /* Pairwise op subgroup of C3.6.16.
11342 * This is called directly or via the handle_3same_float for float pairwise
11343 * operations where the opcode and size are calculated differently.
11345 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11346 int size
, int rn
, int rm
, int rd
)
11351 /* Floating point operations need fpst */
11352 if (opcode
>= 0x58) {
11353 fpst
= fpstatus_ptr(FPST_FPCR
);
11358 if (!fp_access_check(s
)) {
11362 /* These operations work on the concatenated rm:rn, with each pair of
11363 * adjacent elements being operated on to produce an element in the result.
11366 TCGv_i64 tcg_res
[2];
11368 for (pass
= 0; pass
< 2; pass
++) {
11369 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11370 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11371 int passreg
= (pass
== 0) ? rn
: rm
;
11373 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11374 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11375 tcg_res
[pass
] = tcg_temp_new_i64();
11378 case 0x17: /* ADDP */
11379 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11381 case 0x58: /* FMAXNMP */
11382 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11384 case 0x5a: /* FADDP */
11385 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11387 case 0x5e: /* FMAXP */
11388 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11390 case 0x78: /* FMINNMP */
11391 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11393 case 0x7e: /* FMINP */
11394 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11397 g_assert_not_reached();
11400 tcg_temp_free_i64(tcg_op1
);
11401 tcg_temp_free_i64(tcg_op2
);
11404 for (pass
= 0; pass
< 2; pass
++) {
11405 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11406 tcg_temp_free_i64(tcg_res
[pass
]);
11409 int maxpass
= is_q
? 4 : 2;
11410 TCGv_i32 tcg_res
[4];
11412 for (pass
= 0; pass
< maxpass
; pass
++) {
11413 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11414 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11415 NeonGenTwoOpFn
*genfn
= NULL
;
11416 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11417 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11419 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11420 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11421 tcg_res
[pass
] = tcg_temp_new_i32();
11424 case 0x17: /* ADDP */
11426 static NeonGenTwoOpFn
* const fns
[3] = {
11427 gen_helper_neon_padd_u8
,
11428 gen_helper_neon_padd_u16
,
11434 case 0x14: /* SMAXP, UMAXP */
11436 static NeonGenTwoOpFn
* const fns
[3][2] = {
11437 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11438 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11439 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11441 genfn
= fns
[size
][u
];
11444 case 0x15: /* SMINP, UMINP */
11446 static NeonGenTwoOpFn
* const fns
[3][2] = {
11447 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11448 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11449 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11451 genfn
= fns
[size
][u
];
11454 /* The FP operations are all on single floats (32 bit) */
11455 case 0x58: /* FMAXNMP */
11456 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11458 case 0x5a: /* FADDP */
11459 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11461 case 0x5e: /* FMAXP */
11462 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11464 case 0x78: /* FMINNMP */
11465 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11467 case 0x7e: /* FMINP */
11468 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11471 g_assert_not_reached();
11474 /* FP ops called directly, otherwise call now */
11476 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11479 tcg_temp_free_i32(tcg_op1
);
11480 tcg_temp_free_i32(tcg_op2
);
11483 for (pass
= 0; pass
< maxpass
; pass
++) {
11484 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11485 tcg_temp_free_i32(tcg_res
[pass
]);
11487 clear_vec_high(s
, is_q
, rd
);
11491 tcg_temp_free_ptr(fpst
);
11495 /* Floating point op subgroup of C3.6.16. */
11496 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11498 /* For floating point ops, the U, size[1] and opcode bits
11499 * together indicate the operation. size[0] indicates single
11502 int fpopcode
= extract32(insn
, 11, 5)
11503 | (extract32(insn
, 23, 1) << 5)
11504 | (extract32(insn
, 29, 1) << 6);
11505 int is_q
= extract32(insn
, 30, 1);
11506 int size
= extract32(insn
, 22, 1);
11507 int rm
= extract32(insn
, 16, 5);
11508 int rn
= extract32(insn
, 5, 5);
11509 int rd
= extract32(insn
, 0, 5);
11511 int datasize
= is_q
? 128 : 64;
11512 int esize
= 32 << size
;
11513 int elements
= datasize
/ esize
;
11515 if (size
== 1 && !is_q
) {
11516 unallocated_encoding(s
);
11520 switch (fpopcode
) {
11521 case 0x58: /* FMAXNMP */
11522 case 0x5a: /* FADDP */
11523 case 0x5e: /* FMAXP */
11524 case 0x78: /* FMINNMP */
11525 case 0x7e: /* FMINP */
11526 if (size
&& !is_q
) {
11527 unallocated_encoding(s
);
11530 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11533 case 0x1b: /* FMULX */
11534 case 0x1f: /* FRECPS */
11535 case 0x3f: /* FRSQRTS */
11536 case 0x5d: /* FACGE */
11537 case 0x7d: /* FACGT */
11538 case 0x19: /* FMLA */
11539 case 0x39: /* FMLS */
11540 case 0x18: /* FMAXNM */
11541 case 0x1a: /* FADD */
11542 case 0x1c: /* FCMEQ */
11543 case 0x1e: /* FMAX */
11544 case 0x38: /* FMINNM */
11545 case 0x3a: /* FSUB */
11546 case 0x3e: /* FMIN */
11547 case 0x5b: /* FMUL */
11548 case 0x5c: /* FCMGE */
11549 case 0x5f: /* FDIV */
11550 case 0x7a: /* FABD */
11551 case 0x7c: /* FCMGT */
11552 if (!fp_access_check(s
)) {
11555 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11558 case 0x1d: /* FMLAL */
11559 case 0x3d: /* FMLSL */
11560 case 0x59: /* FMLAL2 */
11561 case 0x79: /* FMLSL2 */
11562 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11563 unallocated_encoding(s
);
11566 if (fp_access_check(s
)) {
11567 int is_s
= extract32(insn
, 23, 1);
11568 int is_2
= extract32(insn
, 29, 1);
11569 int data
= (is_2
<< 1) | is_s
;
11570 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11571 vec_full_reg_offset(s
, rn
),
11572 vec_full_reg_offset(s
, rm
), cpu_env
,
11573 is_q
? 16 : 8, vec_full_reg_size(s
),
11574 data
, gen_helper_gvec_fmlal_a64
);
11579 unallocated_encoding(s
);
11584 /* Integer op subgroup of C3.6.16. */
11585 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11587 int is_q
= extract32(insn
, 30, 1);
11588 int u
= extract32(insn
, 29, 1);
11589 int size
= extract32(insn
, 22, 2);
11590 int opcode
= extract32(insn
, 11, 5);
11591 int rm
= extract32(insn
, 16, 5);
11592 int rn
= extract32(insn
, 5, 5);
11593 int rd
= extract32(insn
, 0, 5);
11598 case 0x13: /* MUL, PMUL */
11599 if (u
&& size
!= 0) {
11600 unallocated_encoding(s
);
11604 case 0x0: /* SHADD, UHADD */
11605 case 0x2: /* SRHADD, URHADD */
11606 case 0x4: /* SHSUB, UHSUB */
11607 case 0xc: /* SMAX, UMAX */
11608 case 0xd: /* SMIN, UMIN */
11609 case 0xe: /* SABD, UABD */
11610 case 0xf: /* SABA, UABA */
11611 case 0x12: /* MLA, MLS */
11613 unallocated_encoding(s
);
11617 case 0x16: /* SQDMULH, SQRDMULH */
11618 if (size
== 0 || size
== 3) {
11619 unallocated_encoding(s
);
11624 if (size
== 3 && !is_q
) {
11625 unallocated_encoding(s
);
11631 if (!fp_access_check(s
)) {
11636 case 0x01: /* SQADD, UQADD */
11638 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11640 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11643 case 0x05: /* SQSUB, UQSUB */
11645 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11647 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11650 case 0x08: /* SSHL, USHL */
11652 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11654 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11657 case 0x0c: /* SMAX, UMAX */
11659 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11661 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11664 case 0x0d: /* SMIN, UMIN */
11666 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11668 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11671 case 0xe: /* SABD, UABD */
11673 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11675 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11678 case 0xf: /* SABA, UABA */
11680 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11682 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11685 case 0x10: /* ADD, SUB */
11687 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11689 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11692 case 0x13: /* MUL, PMUL */
11693 if (!u
) { /* MUL */
11694 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11695 } else { /* PMUL */
11696 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11699 case 0x12: /* MLA, MLS */
11701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11703 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11706 case 0x16: /* SQDMULH, SQRDMULH */
11708 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11709 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11710 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11712 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11716 if (!u
) { /* CMTST */
11717 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11721 cond
= TCG_COND_EQ
;
11723 case 0x06: /* CMGT, CMHI */
11724 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11726 case 0x07: /* CMGE, CMHS */
11727 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11729 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11730 vec_full_reg_offset(s
, rn
),
11731 vec_full_reg_offset(s
, rm
),
11732 is_q
? 16 : 8, vec_full_reg_size(s
));
11738 for (pass
= 0; pass
< 2; pass
++) {
11739 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11740 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11741 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11743 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11744 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11746 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11748 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11750 tcg_temp_free_i64(tcg_res
);
11751 tcg_temp_free_i64(tcg_op1
);
11752 tcg_temp_free_i64(tcg_op2
);
11755 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11756 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11757 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11758 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11759 NeonGenTwoOpFn
*genfn
= NULL
;
11760 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11762 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11763 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11766 case 0x0: /* SHADD, UHADD */
11768 static NeonGenTwoOpFn
* const fns
[3][2] = {
11769 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11770 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11771 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11773 genfn
= fns
[size
][u
];
11776 case 0x2: /* SRHADD, URHADD */
11778 static NeonGenTwoOpFn
* const fns
[3][2] = {
11779 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11780 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11781 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11783 genfn
= fns
[size
][u
];
11786 case 0x4: /* SHSUB, UHSUB */
11788 static NeonGenTwoOpFn
* const fns
[3][2] = {
11789 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11790 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11791 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11793 genfn
= fns
[size
][u
];
11796 case 0x9: /* SQSHL, UQSHL */
11798 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11799 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11800 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11801 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11803 genenvfn
= fns
[size
][u
];
11806 case 0xa: /* SRSHL, URSHL */
11808 static NeonGenTwoOpFn
* const fns
[3][2] = {
11809 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11810 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11811 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11813 genfn
= fns
[size
][u
];
11816 case 0xb: /* SQRSHL, UQRSHL */
11818 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11819 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11820 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11821 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11823 genenvfn
= fns
[size
][u
];
11827 g_assert_not_reached();
11831 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11833 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11836 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11838 tcg_temp_free_i32(tcg_res
);
11839 tcg_temp_free_i32(tcg_op1
);
11840 tcg_temp_free_i32(tcg_op2
);
11843 clear_vec_high(s
, is_q
, rd
);
11846 /* AdvSIMD three same
11847 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11848 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11849 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11850 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11852 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11854 int opcode
= extract32(insn
, 11, 5);
11857 case 0x3: /* logic ops */
11858 disas_simd_3same_logic(s
, insn
);
11860 case 0x17: /* ADDP */
11861 case 0x14: /* SMAXP, UMAXP */
11862 case 0x15: /* SMINP, UMINP */
11864 /* Pairwise operations */
11865 int is_q
= extract32(insn
, 30, 1);
11866 int u
= extract32(insn
, 29, 1);
11867 int size
= extract32(insn
, 22, 2);
11868 int rm
= extract32(insn
, 16, 5);
11869 int rn
= extract32(insn
, 5, 5);
11870 int rd
= extract32(insn
, 0, 5);
11871 if (opcode
== 0x17) {
11872 if (u
|| (size
== 3 && !is_q
)) {
11873 unallocated_encoding(s
);
11878 unallocated_encoding(s
);
11882 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11885 case 0x18 ... 0x31:
11886 /* floating point ops, sz[1] and U are part of opcode */
11887 disas_simd_3same_float(s
, insn
);
11890 disas_simd_3same_int(s
, insn
);
11896 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11898 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11899 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11900 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11901 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11903 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11904 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11907 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11909 int opcode
= extract32(insn
, 11, 3);
11910 int u
= extract32(insn
, 29, 1);
11911 int a
= extract32(insn
, 23, 1);
11912 int is_q
= extract32(insn
, 30, 1);
11913 int rm
= extract32(insn
, 16, 5);
11914 int rn
= extract32(insn
, 5, 5);
11915 int rd
= extract32(insn
, 0, 5);
11917 * For these floating point ops, the U, a and opcode bits
11918 * together indicate the operation.
11920 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11921 int datasize
= is_q
? 128 : 64;
11922 int elements
= datasize
/ 16;
11927 switch (fpopcode
) {
11928 case 0x0: /* FMAXNM */
11929 case 0x1: /* FMLA */
11930 case 0x2: /* FADD */
11931 case 0x3: /* FMULX */
11932 case 0x4: /* FCMEQ */
11933 case 0x6: /* FMAX */
11934 case 0x7: /* FRECPS */
11935 case 0x8: /* FMINNM */
11936 case 0x9: /* FMLS */
11937 case 0xa: /* FSUB */
11938 case 0xe: /* FMIN */
11939 case 0xf: /* FRSQRTS */
11940 case 0x13: /* FMUL */
11941 case 0x14: /* FCMGE */
11942 case 0x15: /* FACGE */
11943 case 0x17: /* FDIV */
11944 case 0x1a: /* FABD */
11945 case 0x1c: /* FCMGT */
11946 case 0x1d: /* FACGT */
11949 case 0x10: /* FMAXNMP */
11950 case 0x12: /* FADDP */
11951 case 0x16: /* FMAXP */
11952 case 0x18: /* FMINNMP */
11953 case 0x1e: /* FMINP */
11957 unallocated_encoding(s
);
11961 if (!dc_isar_feature(aa64_fp16
, s
)) {
11962 unallocated_encoding(s
);
11966 if (!fp_access_check(s
)) {
11970 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11973 int maxpass
= is_q
? 8 : 4;
11974 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11975 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11976 TCGv_i32 tcg_res
[8];
11978 for (pass
= 0; pass
< maxpass
; pass
++) {
11979 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11980 int passelt
= (pass
<< 1) & (maxpass
- 1);
11982 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11983 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11984 tcg_res
[pass
] = tcg_temp_new_i32();
11986 switch (fpopcode
) {
11987 case 0x10: /* FMAXNMP */
11988 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11991 case 0x12: /* FADDP */
11992 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11994 case 0x16: /* FMAXP */
11995 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11997 case 0x18: /* FMINNMP */
11998 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12001 case 0x1e: /* FMINP */
12002 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12005 g_assert_not_reached();
12009 for (pass
= 0; pass
< maxpass
; pass
++) {
12010 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12011 tcg_temp_free_i32(tcg_res
[pass
]);
12014 tcg_temp_free_i32(tcg_op1
);
12015 tcg_temp_free_i32(tcg_op2
);
12018 for (pass
= 0; pass
< elements
; pass
++) {
12019 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12020 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12021 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12023 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12024 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12026 switch (fpopcode
) {
12027 case 0x0: /* FMAXNM */
12028 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12030 case 0x1: /* FMLA */
12031 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12032 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12035 case 0x2: /* FADD */
12036 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12038 case 0x3: /* FMULX */
12039 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12041 case 0x4: /* FCMEQ */
12042 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12044 case 0x6: /* FMAX */
12045 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12047 case 0x7: /* FRECPS */
12048 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12050 case 0x8: /* FMINNM */
12051 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12053 case 0x9: /* FMLS */
12054 /* As usual for ARM, separate negation for fused multiply-add */
12055 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12056 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12057 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12060 case 0xa: /* FSUB */
12061 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12063 case 0xe: /* FMIN */
12064 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12066 case 0xf: /* FRSQRTS */
12067 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12069 case 0x13: /* FMUL */
12070 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12072 case 0x14: /* FCMGE */
12073 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12075 case 0x15: /* FACGE */
12076 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12078 case 0x17: /* FDIV */
12079 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12081 case 0x1a: /* FABD */
12082 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12083 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12085 case 0x1c: /* FCMGT */
12086 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12088 case 0x1d: /* FACGT */
12089 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12092 g_assert_not_reached();
12095 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12096 tcg_temp_free_i32(tcg_res
);
12097 tcg_temp_free_i32(tcg_op1
);
12098 tcg_temp_free_i32(tcg_op2
);
12102 tcg_temp_free_ptr(fpst
);
12104 clear_vec_high(s
, is_q
, rd
);
12107 /* AdvSIMD three same extra
12108 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12109 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12110 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12111 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12113 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12115 int rd
= extract32(insn
, 0, 5);
12116 int rn
= extract32(insn
, 5, 5);
12117 int opcode
= extract32(insn
, 11, 4);
12118 int rm
= extract32(insn
, 16, 5);
12119 int size
= extract32(insn
, 22, 2);
12120 bool u
= extract32(insn
, 29, 1);
12121 bool is_q
= extract32(insn
, 30, 1);
12125 switch (u
* 16 + opcode
) {
12126 case 0x10: /* SQRDMLAH (vector) */
12127 case 0x11: /* SQRDMLSH (vector) */
12128 if (size
!= 1 && size
!= 2) {
12129 unallocated_encoding(s
);
12132 feature
= dc_isar_feature(aa64_rdm
, s
);
12134 case 0x02: /* SDOT (vector) */
12135 case 0x12: /* UDOT (vector) */
12136 if (size
!= MO_32
) {
12137 unallocated_encoding(s
);
12140 feature
= dc_isar_feature(aa64_dp
, s
);
12142 case 0x03: /* USDOT */
12143 if (size
!= MO_32
) {
12144 unallocated_encoding(s
);
12147 feature
= dc_isar_feature(aa64_i8mm
, s
);
12149 case 0x04: /* SMMLA */
12150 case 0x14: /* UMMLA */
12151 case 0x05: /* USMMLA */
12152 if (!is_q
|| size
!= MO_32
) {
12153 unallocated_encoding(s
);
12156 feature
= dc_isar_feature(aa64_i8mm
, s
);
12158 case 0x18: /* FCMLA, #0 */
12159 case 0x19: /* FCMLA, #90 */
12160 case 0x1a: /* FCMLA, #180 */
12161 case 0x1b: /* FCMLA, #270 */
12162 case 0x1c: /* FCADD, #90 */
12163 case 0x1e: /* FCADD, #270 */
12165 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12166 || (size
== 3 && !is_q
)) {
12167 unallocated_encoding(s
);
12170 feature
= dc_isar_feature(aa64_fcma
, s
);
12172 case 0x1d: /* BFMMLA */
12173 if (size
!= MO_16
|| !is_q
) {
12174 unallocated_encoding(s
);
12177 feature
= dc_isar_feature(aa64_bf16
, s
);
12181 case 1: /* BFDOT */
12182 case 3: /* BFMLAL{B,T} */
12183 feature
= dc_isar_feature(aa64_bf16
, s
);
12186 unallocated_encoding(s
);
12191 unallocated_encoding(s
);
12195 unallocated_encoding(s
);
12198 if (!fp_access_check(s
)) {
12203 case 0x0: /* SQRDMLAH (vector) */
12204 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12207 case 0x1: /* SQRDMLSH (vector) */
12208 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12211 case 0x2: /* SDOT / UDOT */
12212 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
12213 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12216 case 0x3: /* USDOT */
12217 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
12220 case 0x04: /* SMMLA, UMMLA */
12221 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
12222 u
? gen_helper_gvec_ummla_b
12223 : gen_helper_gvec_smmla_b
);
12225 case 0x05: /* USMMLA */
12226 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
12229 case 0x8: /* FCMLA, #0 */
12230 case 0x9: /* FCMLA, #90 */
12231 case 0xa: /* FCMLA, #180 */
12232 case 0xb: /* FCMLA, #270 */
12233 rot
= extract32(opcode
, 0, 2);
12236 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
12237 gen_helper_gvec_fcmlah
);
12240 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12241 gen_helper_gvec_fcmlas
);
12244 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12245 gen_helper_gvec_fcmlad
);
12248 g_assert_not_reached();
12252 case 0xc: /* FCADD, #90 */
12253 case 0xe: /* FCADD, #270 */
12254 rot
= extract32(opcode
, 1, 1);
12257 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12258 gen_helper_gvec_fcaddh
);
12261 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12262 gen_helper_gvec_fcadds
);
12265 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12266 gen_helper_gvec_fcaddd
);
12269 g_assert_not_reached();
12273 case 0xd: /* BFMMLA */
12274 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfmmla
);
12278 case 1: /* BFDOT */
12279 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfdot
);
12281 case 3: /* BFMLAL{B,T} */
12282 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, false, is_q
,
12283 gen_helper_gvec_bfmlal
);
12286 g_assert_not_reached();
12291 g_assert_not_reached();
12295 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12296 int size
, int rn
, int rd
)
12298 /* Handle 2-reg-misc ops which are widening (so each size element
12299 * in the source becomes a 2*size element in the destination.
12300 * The only instruction like this is FCVTL.
12305 /* 32 -> 64 bit fp conversion */
12306 TCGv_i64 tcg_res
[2];
12307 int srcelt
= is_q
? 2 : 0;
12309 for (pass
= 0; pass
< 2; pass
++) {
12310 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12311 tcg_res
[pass
] = tcg_temp_new_i64();
12313 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12314 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12315 tcg_temp_free_i32(tcg_op
);
12317 for (pass
= 0; pass
< 2; pass
++) {
12318 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12319 tcg_temp_free_i64(tcg_res
[pass
]);
12322 /* 16 -> 32 bit fp conversion */
12323 int srcelt
= is_q
? 4 : 0;
12324 TCGv_i32 tcg_res
[4];
12325 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12326 TCGv_i32 ahp
= get_ahp_flag();
12328 for (pass
= 0; pass
< 4; pass
++) {
12329 tcg_res
[pass
] = tcg_temp_new_i32();
12331 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12332 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12335 for (pass
= 0; pass
< 4; pass
++) {
12336 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12337 tcg_temp_free_i32(tcg_res
[pass
]);
12340 tcg_temp_free_ptr(fpst
);
12341 tcg_temp_free_i32(ahp
);
12345 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12346 bool is_q
, int size
, int rn
, int rd
)
12348 int op
= (opcode
<< 1) | u
;
12349 int opsz
= op
+ size
;
12350 int grp_size
= 3 - opsz
;
12351 int dsize
= is_q
? 128 : 64;
12355 unallocated_encoding(s
);
12359 if (!fp_access_check(s
)) {
12364 /* Special case bytes, use bswap op on each group of elements */
12365 int groups
= dsize
/ (8 << grp_size
);
12367 for (i
= 0; i
< groups
; i
++) {
12368 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12370 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12371 switch (grp_size
) {
12373 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12376 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12379 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12382 g_assert_not_reached();
12384 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12385 tcg_temp_free_i64(tcg_tmp
);
12387 clear_vec_high(s
, is_q
, rd
);
12389 int revmask
= (1 << grp_size
) - 1;
12390 int esize
= 8 << size
;
12391 int elements
= dsize
/ esize
;
12392 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12393 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12394 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12396 for (i
= 0; i
< elements
; i
++) {
12397 int e_rev
= (i
& 0xf) ^ revmask
;
12398 int off
= e_rev
* esize
;
12399 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12401 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12402 tcg_rn
, off
- 64, esize
);
12404 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12407 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12408 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12410 tcg_temp_free_i64(tcg_rd_hi
);
12411 tcg_temp_free_i64(tcg_rd
);
12412 tcg_temp_free_i64(tcg_rn
);
12416 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12417 bool is_q
, int size
, int rn
, int rd
)
12419 /* Implement the pairwise operations from 2-misc:
12420 * SADDLP, UADDLP, SADALP, UADALP.
12421 * These all add pairs of elements in the input to produce a
12422 * double-width result element in the output (possibly accumulating).
12424 bool accum
= (opcode
== 0x6);
12425 int maxpass
= is_q
? 2 : 1;
12427 TCGv_i64 tcg_res
[2];
12430 /* 32 + 32 -> 64 op */
12431 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12433 for (pass
= 0; pass
< maxpass
; pass
++) {
12434 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12435 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12437 tcg_res
[pass
] = tcg_temp_new_i64();
12439 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12440 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12441 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12443 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12444 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12447 tcg_temp_free_i64(tcg_op1
);
12448 tcg_temp_free_i64(tcg_op2
);
12451 for (pass
= 0; pass
< maxpass
; pass
++) {
12452 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12453 NeonGenOne64OpFn
*genfn
;
12454 static NeonGenOne64OpFn
* const fns
[2][2] = {
12455 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12456 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12459 genfn
= fns
[size
][u
];
12461 tcg_res
[pass
] = tcg_temp_new_i64();
12463 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12464 genfn(tcg_res
[pass
], tcg_op
);
12467 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12469 gen_helper_neon_addl_u16(tcg_res
[pass
],
12470 tcg_res
[pass
], tcg_op
);
12472 gen_helper_neon_addl_u32(tcg_res
[pass
],
12473 tcg_res
[pass
], tcg_op
);
12476 tcg_temp_free_i64(tcg_op
);
12480 tcg_res
[1] = tcg_constant_i64(0);
12482 for (pass
= 0; pass
< 2; pass
++) {
12483 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12484 tcg_temp_free_i64(tcg_res
[pass
]);
12488 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12490 /* Implement SHLL and SHLL2 */
12492 int part
= is_q
? 2 : 0;
12493 TCGv_i64 tcg_res
[2];
12495 for (pass
= 0; pass
< 2; pass
++) {
12496 static NeonGenWidenFn
* const widenfns
[3] = {
12497 gen_helper_neon_widen_u8
,
12498 gen_helper_neon_widen_u16
,
12499 tcg_gen_extu_i32_i64
,
12501 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12502 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12504 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12505 tcg_res
[pass
] = tcg_temp_new_i64();
12506 widenfn(tcg_res
[pass
], tcg_op
);
12507 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12509 tcg_temp_free_i32(tcg_op
);
12512 for (pass
= 0; pass
< 2; pass
++) {
12513 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12514 tcg_temp_free_i64(tcg_res
[pass
]);
12518 /* AdvSIMD two reg misc
12519 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12520 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12521 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12522 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12524 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12526 int size
= extract32(insn
, 22, 2);
12527 int opcode
= extract32(insn
, 12, 5);
12528 bool u
= extract32(insn
, 29, 1);
12529 bool is_q
= extract32(insn
, 30, 1);
12530 int rn
= extract32(insn
, 5, 5);
12531 int rd
= extract32(insn
, 0, 5);
12532 bool need_fpstatus
= false;
12533 bool need_rmode
= false;
12535 TCGv_i32 tcg_rmode
;
12536 TCGv_ptr tcg_fpstatus
;
12539 case 0x0: /* REV64, REV32 */
12540 case 0x1: /* REV16 */
12541 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12543 case 0x5: /* CNT, NOT, RBIT */
12544 if (u
&& size
== 0) {
12547 } else if (u
&& size
== 1) {
12550 } else if (!u
&& size
== 0) {
12554 unallocated_encoding(s
);
12556 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12557 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12559 unallocated_encoding(s
);
12562 if (!fp_access_check(s
)) {
12566 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12568 case 0x4: /* CLS, CLZ */
12570 unallocated_encoding(s
);
12574 case 0x2: /* SADDLP, UADDLP */
12575 case 0x6: /* SADALP, UADALP */
12577 unallocated_encoding(s
);
12580 if (!fp_access_check(s
)) {
12583 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12585 case 0x13: /* SHLL, SHLL2 */
12586 if (u
== 0 || size
== 3) {
12587 unallocated_encoding(s
);
12590 if (!fp_access_check(s
)) {
12593 handle_shll(s
, is_q
, size
, rn
, rd
);
12595 case 0xa: /* CMLT */
12597 unallocated_encoding(s
);
12601 case 0x8: /* CMGT, CMGE */
12602 case 0x9: /* CMEQ, CMLE */
12603 case 0xb: /* ABS, NEG */
12604 if (size
== 3 && !is_q
) {
12605 unallocated_encoding(s
);
12609 case 0x3: /* SUQADD, USQADD */
12610 if (size
== 3 && !is_q
) {
12611 unallocated_encoding(s
);
12614 if (!fp_access_check(s
)) {
12617 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12619 case 0x7: /* SQABS, SQNEG */
12620 if (size
== 3 && !is_q
) {
12621 unallocated_encoding(s
);
12626 case 0x16 ... 0x1f:
12628 /* Floating point: U, size[1] and opcode indicate operation;
12629 * size[0] indicates single or double precision.
12631 int is_double
= extract32(size
, 0, 1);
12632 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12633 size
= is_double
? 3 : 2;
12635 case 0x2f: /* FABS */
12636 case 0x6f: /* FNEG */
12637 if (size
== 3 && !is_q
) {
12638 unallocated_encoding(s
);
12642 case 0x1d: /* SCVTF */
12643 case 0x5d: /* UCVTF */
12645 bool is_signed
= (opcode
== 0x1d) ? true : false;
12646 int elements
= is_double
? 2 : is_q
? 4 : 2;
12647 if (is_double
&& !is_q
) {
12648 unallocated_encoding(s
);
12651 if (!fp_access_check(s
)) {
12654 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12657 case 0x2c: /* FCMGT (zero) */
12658 case 0x2d: /* FCMEQ (zero) */
12659 case 0x2e: /* FCMLT (zero) */
12660 case 0x6c: /* FCMGE (zero) */
12661 case 0x6d: /* FCMLE (zero) */
12662 if (size
== 3 && !is_q
) {
12663 unallocated_encoding(s
);
12666 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12668 case 0x7f: /* FSQRT */
12669 if (size
== 3 && !is_q
) {
12670 unallocated_encoding(s
);
12674 case 0x1a: /* FCVTNS */
12675 case 0x1b: /* FCVTMS */
12676 case 0x3a: /* FCVTPS */
12677 case 0x3b: /* FCVTZS */
12678 case 0x5a: /* FCVTNU */
12679 case 0x5b: /* FCVTMU */
12680 case 0x7a: /* FCVTPU */
12681 case 0x7b: /* FCVTZU */
12682 need_fpstatus
= true;
12684 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12685 if (size
== 3 && !is_q
) {
12686 unallocated_encoding(s
);
12690 case 0x5c: /* FCVTAU */
12691 case 0x1c: /* FCVTAS */
12692 need_fpstatus
= true;
12694 rmode
= FPROUNDING_TIEAWAY
;
12695 if (size
== 3 && !is_q
) {
12696 unallocated_encoding(s
);
12700 case 0x3c: /* URECPE */
12702 unallocated_encoding(s
);
12706 case 0x3d: /* FRECPE */
12707 case 0x7d: /* FRSQRTE */
12708 if (size
== 3 && !is_q
) {
12709 unallocated_encoding(s
);
12712 if (!fp_access_check(s
)) {
12715 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12717 case 0x56: /* FCVTXN, FCVTXN2 */
12719 unallocated_encoding(s
);
12723 case 0x16: /* FCVTN, FCVTN2 */
12724 /* handle_2misc_narrow does a 2*size -> size operation, but these
12725 * instructions encode the source size rather than dest size.
12727 if (!fp_access_check(s
)) {
12730 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12732 case 0x36: /* BFCVTN, BFCVTN2 */
12733 if (!dc_isar_feature(aa64_bf16
, s
) || size
!= 2) {
12734 unallocated_encoding(s
);
12737 if (!fp_access_check(s
)) {
12740 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12742 case 0x17: /* FCVTL, FCVTL2 */
12743 if (!fp_access_check(s
)) {
12746 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12748 case 0x18: /* FRINTN */
12749 case 0x19: /* FRINTM */
12750 case 0x38: /* FRINTP */
12751 case 0x39: /* FRINTZ */
12753 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12755 case 0x59: /* FRINTX */
12756 case 0x79: /* FRINTI */
12757 need_fpstatus
= true;
12758 if (size
== 3 && !is_q
) {
12759 unallocated_encoding(s
);
12763 case 0x58: /* FRINTA */
12765 rmode
= FPROUNDING_TIEAWAY
;
12766 need_fpstatus
= true;
12767 if (size
== 3 && !is_q
) {
12768 unallocated_encoding(s
);
12772 case 0x7c: /* URSQRTE */
12774 unallocated_encoding(s
);
12778 case 0x1e: /* FRINT32Z */
12779 case 0x1f: /* FRINT64Z */
12781 rmode
= FPROUNDING_ZERO
;
12783 case 0x5e: /* FRINT32X */
12784 case 0x5f: /* FRINT64X */
12785 need_fpstatus
= true;
12786 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12787 unallocated_encoding(s
);
12792 unallocated_encoding(s
);
12798 unallocated_encoding(s
);
12802 if (!fp_access_check(s
)) {
12806 if (need_fpstatus
|| need_rmode
) {
12807 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12809 tcg_fpstatus
= NULL
;
12812 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12813 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12820 if (u
&& size
== 0) { /* NOT */
12821 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12825 case 0x8: /* CMGT, CMGE */
12827 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12829 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12832 case 0x9: /* CMEQ, CMLE */
12834 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12836 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12839 case 0xa: /* CMLT */
12840 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12843 if (u
) { /* ABS, NEG */
12844 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12846 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12852 /* All 64-bit element operations can be shared with scalar 2misc */
12855 /* Coverity claims (size == 3 && !is_q) has been eliminated
12856 * from all paths leading to here.
12858 tcg_debug_assert(is_q
);
12859 for (pass
= 0; pass
< 2; pass
++) {
12860 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12861 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12863 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12865 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12866 tcg_rmode
, tcg_fpstatus
);
12868 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12870 tcg_temp_free_i64(tcg_res
);
12871 tcg_temp_free_i64(tcg_op
);
12876 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12877 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12878 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12880 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12883 /* Special cases for 32 bit elements */
12885 case 0x4: /* CLS */
12887 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12889 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12892 case 0x7: /* SQABS, SQNEG */
12894 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12896 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12899 case 0x2f: /* FABS */
12900 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12902 case 0x6f: /* FNEG */
12903 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12905 case 0x7f: /* FSQRT */
12906 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12908 case 0x1a: /* FCVTNS */
12909 case 0x1b: /* FCVTMS */
12910 case 0x1c: /* FCVTAS */
12911 case 0x3a: /* FCVTPS */
12912 case 0x3b: /* FCVTZS */
12913 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12914 tcg_constant_i32(0), tcg_fpstatus
);
12916 case 0x5a: /* FCVTNU */
12917 case 0x5b: /* FCVTMU */
12918 case 0x5c: /* FCVTAU */
12919 case 0x7a: /* FCVTPU */
12920 case 0x7b: /* FCVTZU */
12921 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12922 tcg_constant_i32(0), tcg_fpstatus
);
12924 case 0x18: /* FRINTN */
12925 case 0x19: /* FRINTM */
12926 case 0x38: /* FRINTP */
12927 case 0x39: /* FRINTZ */
12928 case 0x58: /* FRINTA */
12929 case 0x79: /* FRINTI */
12930 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12932 case 0x59: /* FRINTX */
12933 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12935 case 0x7c: /* URSQRTE */
12936 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12938 case 0x1e: /* FRINT32Z */
12939 case 0x5e: /* FRINT32X */
12940 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12942 case 0x1f: /* FRINT64Z */
12943 case 0x5f: /* FRINT64X */
12944 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12947 g_assert_not_reached();
12950 /* Use helpers for 8 and 16 bit elements */
12952 case 0x5: /* CNT, RBIT */
12953 /* For these two insns size is part of the opcode specifier
12954 * (handled earlier); they always operate on byte elements.
12957 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12959 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12962 case 0x7: /* SQABS, SQNEG */
12964 NeonGenOneOpEnvFn
*genfn
;
12965 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12966 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12967 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12969 genfn
= fns
[size
][u
];
12970 genfn(tcg_res
, cpu_env
, tcg_op
);
12973 case 0x4: /* CLS, CLZ */
12976 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12978 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12982 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12984 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12989 g_assert_not_reached();
12993 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12995 tcg_temp_free_i32(tcg_res
);
12996 tcg_temp_free_i32(tcg_op
);
12999 clear_vec_high(s
, is_q
, rd
);
13002 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13003 tcg_temp_free_i32(tcg_rmode
);
13005 if (need_fpstatus
) {
13006 tcg_temp_free_ptr(tcg_fpstatus
);
13010 /* AdvSIMD [scalar] two register miscellaneous (FP16)
13012 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
13013 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13014 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
13015 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13016 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
13017 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
13019 * This actually covers two groups where scalar access is governed by
13020 * bit 28. A bunch of the instructions (float to integral) only exist
13021 * in the vector form and are un-allocated for the scalar decode. Also
13022 * in the scalar decode Q is always 1.
13024 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
13026 int fpop
, opcode
, a
, u
;
13030 bool only_in_vector
= false;
13033 TCGv_i32 tcg_rmode
= NULL
;
13034 TCGv_ptr tcg_fpstatus
= NULL
;
13035 bool need_rmode
= false;
13036 bool need_fpst
= true;
13039 if (!dc_isar_feature(aa64_fp16
, s
)) {
13040 unallocated_encoding(s
);
13044 rd
= extract32(insn
, 0, 5);
13045 rn
= extract32(insn
, 5, 5);
13047 a
= extract32(insn
, 23, 1);
13048 u
= extract32(insn
, 29, 1);
13049 is_scalar
= extract32(insn
, 28, 1);
13050 is_q
= extract32(insn
, 30, 1);
13052 opcode
= extract32(insn
, 12, 5);
13053 fpop
= deposit32(opcode
, 5, 1, a
);
13054 fpop
= deposit32(fpop
, 6, 1, u
);
13057 case 0x1d: /* SCVTF */
13058 case 0x5d: /* UCVTF */
13065 elements
= (is_q
? 8 : 4);
13068 if (!fp_access_check(s
)) {
13071 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13075 case 0x2c: /* FCMGT (zero) */
13076 case 0x2d: /* FCMEQ (zero) */
13077 case 0x2e: /* FCMLT (zero) */
13078 case 0x6c: /* FCMGE (zero) */
13079 case 0x6d: /* FCMLE (zero) */
13080 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13082 case 0x3d: /* FRECPE */
13083 case 0x3f: /* FRECPX */
13085 case 0x18: /* FRINTN */
13087 only_in_vector
= true;
13088 rmode
= FPROUNDING_TIEEVEN
;
13090 case 0x19: /* FRINTM */
13092 only_in_vector
= true;
13093 rmode
= FPROUNDING_NEGINF
;
13095 case 0x38: /* FRINTP */
13097 only_in_vector
= true;
13098 rmode
= FPROUNDING_POSINF
;
13100 case 0x39: /* FRINTZ */
13102 only_in_vector
= true;
13103 rmode
= FPROUNDING_ZERO
;
13105 case 0x58: /* FRINTA */
13107 only_in_vector
= true;
13108 rmode
= FPROUNDING_TIEAWAY
;
13110 case 0x59: /* FRINTX */
13111 case 0x79: /* FRINTI */
13112 only_in_vector
= true;
13113 /* current rounding mode */
13115 case 0x1a: /* FCVTNS */
13117 rmode
= FPROUNDING_TIEEVEN
;
13119 case 0x1b: /* FCVTMS */
13121 rmode
= FPROUNDING_NEGINF
;
13123 case 0x1c: /* FCVTAS */
13125 rmode
= FPROUNDING_TIEAWAY
;
13127 case 0x3a: /* FCVTPS */
13129 rmode
= FPROUNDING_POSINF
;
13131 case 0x3b: /* FCVTZS */
13133 rmode
= FPROUNDING_ZERO
;
13135 case 0x5a: /* FCVTNU */
13137 rmode
= FPROUNDING_TIEEVEN
;
13139 case 0x5b: /* FCVTMU */
13141 rmode
= FPROUNDING_NEGINF
;
13143 case 0x5c: /* FCVTAU */
13145 rmode
= FPROUNDING_TIEAWAY
;
13147 case 0x7a: /* FCVTPU */
13149 rmode
= FPROUNDING_POSINF
;
13151 case 0x7b: /* FCVTZU */
13153 rmode
= FPROUNDING_ZERO
;
13155 case 0x2f: /* FABS */
13156 case 0x6f: /* FNEG */
13159 case 0x7d: /* FRSQRTE */
13160 case 0x7f: /* FSQRT (vector) */
13163 unallocated_encoding(s
);
13168 /* Check additional constraints for the scalar encoding */
13171 unallocated_encoding(s
);
13174 /* FRINTxx is only in the vector form */
13175 if (only_in_vector
) {
13176 unallocated_encoding(s
);
13181 if (!fp_access_check(s
)) {
13185 if (need_rmode
|| need_fpst
) {
13186 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13190 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13191 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13195 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13196 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13199 case 0x1a: /* FCVTNS */
13200 case 0x1b: /* FCVTMS */
13201 case 0x1c: /* FCVTAS */
13202 case 0x3a: /* FCVTPS */
13203 case 0x3b: /* FCVTZS */
13204 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13206 case 0x3d: /* FRECPE */
13207 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13209 case 0x3f: /* FRECPX */
13210 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13212 case 0x5a: /* FCVTNU */
13213 case 0x5b: /* FCVTMU */
13214 case 0x5c: /* FCVTAU */
13215 case 0x7a: /* FCVTPU */
13216 case 0x7b: /* FCVTZU */
13217 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13219 case 0x6f: /* FNEG */
13220 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13222 case 0x7d: /* FRSQRTE */
13223 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13226 g_assert_not_reached();
13229 /* limit any sign extension going on */
13230 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13231 write_fp_sreg(s
, rd
, tcg_res
);
13233 tcg_temp_free_i32(tcg_res
);
13234 tcg_temp_free_i32(tcg_op
);
13236 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13237 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13238 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13240 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13243 case 0x1a: /* FCVTNS */
13244 case 0x1b: /* FCVTMS */
13245 case 0x1c: /* FCVTAS */
13246 case 0x3a: /* FCVTPS */
13247 case 0x3b: /* FCVTZS */
13248 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13250 case 0x3d: /* FRECPE */
13251 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13253 case 0x5a: /* FCVTNU */
13254 case 0x5b: /* FCVTMU */
13255 case 0x5c: /* FCVTAU */
13256 case 0x7a: /* FCVTPU */
13257 case 0x7b: /* FCVTZU */
13258 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13260 case 0x18: /* FRINTN */
13261 case 0x19: /* FRINTM */
13262 case 0x38: /* FRINTP */
13263 case 0x39: /* FRINTZ */
13264 case 0x58: /* FRINTA */
13265 case 0x79: /* FRINTI */
13266 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13268 case 0x59: /* FRINTX */
13269 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13271 case 0x2f: /* FABS */
13272 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13274 case 0x6f: /* FNEG */
13275 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13277 case 0x7d: /* FRSQRTE */
13278 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13280 case 0x7f: /* FSQRT */
13281 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13284 g_assert_not_reached();
13287 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13289 tcg_temp_free_i32(tcg_res
);
13290 tcg_temp_free_i32(tcg_op
);
13293 clear_vec_high(s
, is_q
, rd
);
13297 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13298 tcg_temp_free_i32(tcg_rmode
);
13301 if (tcg_fpstatus
) {
13302 tcg_temp_free_ptr(tcg_fpstatus
);
13306 /* AdvSIMD scalar x indexed element
13307 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13308 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13309 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13310 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13311 * AdvSIMD vector x indexed element
13312 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13313 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13314 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13315 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13317 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13319 /* This encoding has two kinds of instruction:
13320 * normal, where we perform elt x idxelt => elt for each
13321 * element in the vector
13322 * long, where we perform elt x idxelt and generate a result of
13323 * double the width of the input element
13324 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13326 bool is_scalar
= extract32(insn
, 28, 1);
13327 bool is_q
= extract32(insn
, 30, 1);
13328 bool u
= extract32(insn
, 29, 1);
13329 int size
= extract32(insn
, 22, 2);
13330 int l
= extract32(insn
, 21, 1);
13331 int m
= extract32(insn
, 20, 1);
13332 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13333 int rm
= extract32(insn
, 16, 4);
13334 int opcode
= extract32(insn
, 12, 4);
13335 int h
= extract32(insn
, 11, 1);
13336 int rn
= extract32(insn
, 5, 5);
13337 int rd
= extract32(insn
, 0, 5);
13338 bool is_long
= false;
13340 bool is_fp16
= false;
13344 switch (16 * u
+ opcode
) {
13345 case 0x08: /* MUL */
13346 case 0x10: /* MLA */
13347 case 0x14: /* MLS */
13349 unallocated_encoding(s
);
13353 case 0x02: /* SMLAL, SMLAL2 */
13354 case 0x12: /* UMLAL, UMLAL2 */
13355 case 0x06: /* SMLSL, SMLSL2 */
13356 case 0x16: /* UMLSL, UMLSL2 */
13357 case 0x0a: /* SMULL, SMULL2 */
13358 case 0x1a: /* UMULL, UMULL2 */
13360 unallocated_encoding(s
);
13365 case 0x03: /* SQDMLAL, SQDMLAL2 */
13366 case 0x07: /* SQDMLSL, SQDMLSL2 */
13367 case 0x0b: /* SQDMULL, SQDMULL2 */
13370 case 0x0c: /* SQDMULH */
13371 case 0x0d: /* SQRDMULH */
13373 case 0x01: /* FMLA */
13374 case 0x05: /* FMLS */
13375 case 0x09: /* FMUL */
13376 case 0x19: /* FMULX */
13379 case 0x1d: /* SQRDMLAH */
13380 case 0x1f: /* SQRDMLSH */
13381 if (!dc_isar_feature(aa64_rdm
, s
)) {
13382 unallocated_encoding(s
);
13386 case 0x0e: /* SDOT */
13387 case 0x1e: /* UDOT */
13388 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13389 unallocated_encoding(s
);
13395 case 0: /* SUDOT */
13396 case 2: /* USDOT */
13397 if (is_scalar
|| !dc_isar_feature(aa64_i8mm
, s
)) {
13398 unallocated_encoding(s
);
13403 case 1: /* BFDOT */
13404 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13405 unallocated_encoding(s
);
13410 case 3: /* BFMLAL{B,T} */
13411 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13412 unallocated_encoding(s
);
13415 /* can't set is_fp without other incorrect size checks */
13419 unallocated_encoding(s
);
13423 case 0x11: /* FCMLA #0 */
13424 case 0x13: /* FCMLA #90 */
13425 case 0x15: /* FCMLA #180 */
13426 case 0x17: /* FCMLA #270 */
13427 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13428 unallocated_encoding(s
);
13433 case 0x00: /* FMLAL */
13434 case 0x04: /* FMLSL */
13435 case 0x18: /* FMLAL2 */
13436 case 0x1c: /* FMLSL2 */
13437 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13438 unallocated_encoding(s
);
13442 /* is_fp, but we pass cpu_env not fp_status. */
13445 unallocated_encoding(s
);
13450 case 1: /* normal fp */
13451 /* convert insn encoded size to MemOp size */
13453 case 0: /* half-precision */
13457 case MO_32
: /* single precision */
13458 case MO_64
: /* double precision */
13461 unallocated_encoding(s
);
13466 case 2: /* complex fp */
13467 /* Each indexable element is a complex pair. */
13472 unallocated_encoding(s
);
13480 unallocated_encoding(s
);
13485 default: /* integer */
13489 unallocated_encoding(s
);
13494 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13495 unallocated_encoding(s
);
13499 /* Given MemOp size, adjust register and indexing. */
13502 index
= h
<< 2 | l
<< 1 | m
;
13505 index
= h
<< 1 | l
;
13510 unallocated_encoding(s
);
13517 g_assert_not_reached();
13520 if (!fp_access_check(s
)) {
13525 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13530 switch (16 * u
+ opcode
) {
13531 case 0x0e: /* SDOT */
13532 case 0x1e: /* UDOT */
13533 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13534 u
? gen_helper_gvec_udot_idx_b
13535 : gen_helper_gvec_sdot_idx_b
);
13538 switch (extract32(insn
, 22, 2)) {
13539 case 0: /* SUDOT */
13540 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13541 gen_helper_gvec_sudot_idx_b
);
13543 case 1: /* BFDOT */
13544 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13545 gen_helper_gvec_bfdot_idx
);
13547 case 2: /* USDOT */
13548 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13549 gen_helper_gvec_usdot_idx_b
);
13551 case 3: /* BFMLAL{B,T} */
13552 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, 0, (index
<< 1) | is_q
,
13553 gen_helper_gvec_bfmlal_idx
);
13556 g_assert_not_reached();
13557 case 0x11: /* FCMLA #0 */
13558 case 0x13: /* FCMLA #90 */
13559 case 0x15: /* FCMLA #180 */
13560 case 0x17: /* FCMLA #270 */
13562 int rot
= extract32(insn
, 13, 2);
13563 int data
= (index
<< 2) | rot
;
13564 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13565 vec_full_reg_offset(s
, rn
),
13566 vec_full_reg_offset(s
, rm
),
13567 vec_full_reg_offset(s
, rd
), fpst
,
13568 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13570 ? gen_helper_gvec_fcmlas_idx
13571 : gen_helper_gvec_fcmlah_idx
);
13572 tcg_temp_free_ptr(fpst
);
13576 case 0x00: /* FMLAL */
13577 case 0x04: /* FMLSL */
13578 case 0x18: /* FMLAL2 */
13579 case 0x1c: /* FMLSL2 */
13581 int is_s
= extract32(opcode
, 2, 1);
13583 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13584 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13585 vec_full_reg_offset(s
, rn
),
13586 vec_full_reg_offset(s
, rm
), cpu_env
,
13587 is_q
? 16 : 8, vec_full_reg_size(s
),
13588 data
, gen_helper_gvec_fmlal_idx_a64
);
13592 case 0x08: /* MUL */
13593 if (!is_long
&& !is_scalar
) {
13594 static gen_helper_gvec_3
* const fns
[3] = {
13595 gen_helper_gvec_mul_idx_h
,
13596 gen_helper_gvec_mul_idx_s
,
13597 gen_helper_gvec_mul_idx_d
,
13599 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13600 vec_full_reg_offset(s
, rn
),
13601 vec_full_reg_offset(s
, rm
),
13602 is_q
? 16 : 8, vec_full_reg_size(s
),
13603 index
, fns
[size
- 1]);
13608 case 0x10: /* MLA */
13609 if (!is_long
&& !is_scalar
) {
13610 static gen_helper_gvec_4
* const fns
[3] = {
13611 gen_helper_gvec_mla_idx_h
,
13612 gen_helper_gvec_mla_idx_s
,
13613 gen_helper_gvec_mla_idx_d
,
13615 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13616 vec_full_reg_offset(s
, rn
),
13617 vec_full_reg_offset(s
, rm
),
13618 vec_full_reg_offset(s
, rd
),
13619 is_q
? 16 : 8, vec_full_reg_size(s
),
13620 index
, fns
[size
- 1]);
13625 case 0x14: /* MLS */
13626 if (!is_long
&& !is_scalar
) {
13627 static gen_helper_gvec_4
* const fns
[3] = {
13628 gen_helper_gvec_mls_idx_h
,
13629 gen_helper_gvec_mls_idx_s
,
13630 gen_helper_gvec_mls_idx_d
,
13632 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13633 vec_full_reg_offset(s
, rn
),
13634 vec_full_reg_offset(s
, rm
),
13635 vec_full_reg_offset(s
, rd
),
13636 is_q
? 16 : 8, vec_full_reg_size(s
),
13637 index
, fns
[size
- 1]);
13644 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13647 assert(is_fp
&& is_q
&& !is_long
);
13649 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13651 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13652 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13653 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13655 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13657 switch (16 * u
+ opcode
) {
13658 case 0x05: /* FMLS */
13659 /* As usual for ARM, separate negation for fused multiply-add */
13660 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13662 case 0x01: /* FMLA */
13663 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13664 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13666 case 0x09: /* FMUL */
13667 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13669 case 0x19: /* FMULX */
13670 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13673 g_assert_not_reached();
13676 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13677 tcg_temp_free_i64(tcg_op
);
13678 tcg_temp_free_i64(tcg_res
);
13681 tcg_temp_free_i64(tcg_idx
);
13682 clear_vec_high(s
, !is_scalar
, rd
);
13683 } else if (!is_long
) {
13684 /* 32 bit floating point, or 16 or 32 bit integer.
13685 * For the 16 bit scalar case we use the usual Neon helpers and
13686 * rely on the fact that 0 op 0 == 0 with no side effects.
13688 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13689 int pass
, maxpasses
;
13694 maxpasses
= is_q
? 4 : 2;
13697 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13699 if (size
== 1 && !is_scalar
) {
13700 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13701 * the index into both halves of the 32 bit tcg_idx and then use
13702 * the usual Neon helpers.
13704 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13707 for (pass
= 0; pass
< maxpasses
; pass
++) {
13708 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13709 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13711 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13713 switch (16 * u
+ opcode
) {
13714 case 0x08: /* MUL */
13715 case 0x10: /* MLA */
13716 case 0x14: /* MLS */
13718 static NeonGenTwoOpFn
* const fns
[2][2] = {
13719 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13720 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13722 NeonGenTwoOpFn
*genfn
;
13723 bool is_sub
= opcode
== 0x4;
13726 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13728 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13730 if (opcode
== 0x8) {
13733 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13734 genfn
= fns
[size
- 1][is_sub
];
13735 genfn(tcg_res
, tcg_op
, tcg_res
);
13738 case 0x05: /* FMLS */
13739 case 0x01: /* FMLA */
13740 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13741 is_scalar
? size
: MO_32
);
13744 if (opcode
== 0x5) {
13745 /* As usual for ARM, separate negation for fused
13747 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13750 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13753 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13758 if (opcode
== 0x5) {
13759 /* As usual for ARM, separate negation for
13760 * fused multiply-add */
13761 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13763 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13767 g_assert_not_reached();
13770 case 0x09: /* FMUL */
13774 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13777 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13782 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13785 g_assert_not_reached();
13788 case 0x19: /* FMULX */
13792 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13795 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13800 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13803 g_assert_not_reached();
13806 case 0x0c: /* SQDMULH */
13808 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13811 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13815 case 0x0d: /* SQRDMULH */
13817 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13820 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13824 case 0x1d: /* SQRDMLAH */
13825 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13826 is_scalar
? size
: MO_32
);
13828 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13829 tcg_op
, tcg_idx
, tcg_res
);
13831 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13832 tcg_op
, tcg_idx
, tcg_res
);
13835 case 0x1f: /* SQRDMLSH */
13836 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13837 is_scalar
? size
: MO_32
);
13839 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13840 tcg_op
, tcg_idx
, tcg_res
);
13842 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13843 tcg_op
, tcg_idx
, tcg_res
);
13847 g_assert_not_reached();
13851 write_fp_sreg(s
, rd
, tcg_res
);
13853 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13856 tcg_temp_free_i32(tcg_op
);
13857 tcg_temp_free_i32(tcg_res
);
13860 tcg_temp_free_i32(tcg_idx
);
13861 clear_vec_high(s
, is_q
, rd
);
13863 /* long ops: 16x16->32 or 32x32->64 */
13864 TCGv_i64 tcg_res
[2];
13866 bool satop
= extract32(opcode
, 0, 1);
13867 MemOp memop
= MO_32
;
13874 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13876 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13878 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13879 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13880 TCGv_i64 tcg_passres
;
13886 passelt
= pass
+ (is_q
* 2);
13889 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13891 tcg_res
[pass
] = tcg_temp_new_i64();
13893 if (opcode
== 0xa || opcode
== 0xb) {
13894 /* Non-accumulating ops */
13895 tcg_passres
= tcg_res
[pass
];
13897 tcg_passres
= tcg_temp_new_i64();
13900 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13901 tcg_temp_free_i64(tcg_op
);
13904 /* saturating, doubling */
13905 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13906 tcg_passres
, tcg_passres
);
13909 if (opcode
== 0xa || opcode
== 0xb) {
13913 /* Accumulating op: handle accumulate step */
13914 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13917 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13918 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13920 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13921 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13923 case 0x7: /* SQDMLSL, SQDMLSL2 */
13924 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13926 case 0x3: /* SQDMLAL, SQDMLAL2 */
13927 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13932 g_assert_not_reached();
13934 tcg_temp_free_i64(tcg_passres
);
13936 tcg_temp_free_i64(tcg_idx
);
13938 clear_vec_high(s
, !is_scalar
, rd
);
13940 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13943 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13946 /* The simplest way to handle the 16x16 indexed ops is to
13947 * duplicate the index into both halves of the 32 bit tcg_idx
13948 * and then use the usual Neon helpers.
13950 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13953 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13954 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13955 TCGv_i64 tcg_passres
;
13958 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13960 read_vec_element_i32(s
, tcg_op
, rn
,
13961 pass
+ (is_q
* 2), MO_32
);
13964 tcg_res
[pass
] = tcg_temp_new_i64();
13966 if (opcode
== 0xa || opcode
== 0xb) {
13967 /* Non-accumulating ops */
13968 tcg_passres
= tcg_res
[pass
];
13970 tcg_passres
= tcg_temp_new_i64();
13973 if (memop
& MO_SIGN
) {
13974 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13976 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13979 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13980 tcg_passres
, tcg_passres
);
13982 tcg_temp_free_i32(tcg_op
);
13984 if (opcode
== 0xa || opcode
== 0xb) {
13988 /* Accumulating op: handle accumulate step */
13989 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13992 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13993 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13996 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13997 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
14000 case 0x7: /* SQDMLSL, SQDMLSL2 */
14001 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
14003 case 0x3: /* SQDMLAL, SQDMLAL2 */
14004 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
14009 g_assert_not_reached();
14011 tcg_temp_free_i64(tcg_passres
);
14013 tcg_temp_free_i32(tcg_idx
);
14016 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
14021 tcg_res
[1] = tcg_constant_i64(0);
14024 for (pass
= 0; pass
< 2; pass
++) {
14025 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
14026 tcg_temp_free_i64(tcg_res
[pass
]);
14031 tcg_temp_free_ptr(fpst
);
14036 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14037 * +-----------------+------+-----------+--------+-----+------+------+
14038 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14039 * +-----------------+------+-----------+--------+-----+------+------+
14041 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
14043 int size
= extract32(insn
, 22, 2);
14044 int opcode
= extract32(insn
, 12, 5);
14045 int rn
= extract32(insn
, 5, 5);
14046 int rd
= extract32(insn
, 0, 5);
14048 gen_helper_gvec_2
*genfn2
= NULL
;
14049 gen_helper_gvec_3
*genfn3
= NULL
;
14051 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
14052 unallocated_encoding(s
);
14057 case 0x4: /* AESE */
14059 genfn3
= gen_helper_crypto_aese
;
14061 case 0x6: /* AESMC */
14063 genfn2
= gen_helper_crypto_aesmc
;
14065 case 0x5: /* AESD */
14067 genfn3
= gen_helper_crypto_aese
;
14069 case 0x7: /* AESIMC */
14071 genfn2
= gen_helper_crypto_aesmc
;
14074 unallocated_encoding(s
);
14078 if (!fp_access_check(s
)) {
14082 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
14084 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14088 /* Crypto three-reg SHA
14089 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14090 * +-----------------+------+---+------+---+--------+-----+------+------+
14091 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14092 * +-----------------+------+---+------+---+--------+-----+------+------+
14094 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14096 int size
= extract32(insn
, 22, 2);
14097 int opcode
= extract32(insn
, 12, 3);
14098 int rm
= extract32(insn
, 16, 5);
14099 int rn
= extract32(insn
, 5, 5);
14100 int rd
= extract32(insn
, 0, 5);
14101 gen_helper_gvec_3
*genfn
;
14105 unallocated_encoding(s
);
14110 case 0: /* SHA1C */
14111 genfn
= gen_helper_crypto_sha1c
;
14112 feature
= dc_isar_feature(aa64_sha1
, s
);
14114 case 1: /* SHA1P */
14115 genfn
= gen_helper_crypto_sha1p
;
14116 feature
= dc_isar_feature(aa64_sha1
, s
);
14118 case 2: /* SHA1M */
14119 genfn
= gen_helper_crypto_sha1m
;
14120 feature
= dc_isar_feature(aa64_sha1
, s
);
14122 case 3: /* SHA1SU0 */
14123 genfn
= gen_helper_crypto_sha1su0
;
14124 feature
= dc_isar_feature(aa64_sha1
, s
);
14126 case 4: /* SHA256H */
14127 genfn
= gen_helper_crypto_sha256h
;
14128 feature
= dc_isar_feature(aa64_sha256
, s
);
14130 case 5: /* SHA256H2 */
14131 genfn
= gen_helper_crypto_sha256h2
;
14132 feature
= dc_isar_feature(aa64_sha256
, s
);
14134 case 6: /* SHA256SU1 */
14135 genfn
= gen_helper_crypto_sha256su1
;
14136 feature
= dc_isar_feature(aa64_sha256
, s
);
14139 unallocated_encoding(s
);
14144 unallocated_encoding(s
);
14148 if (!fp_access_check(s
)) {
14151 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14154 /* Crypto two-reg SHA
14155 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14156 * +-----------------+------+-----------+--------+-----+------+------+
14157 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14158 * +-----------------+------+-----------+--------+-----+------+------+
14160 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14162 int size
= extract32(insn
, 22, 2);
14163 int opcode
= extract32(insn
, 12, 5);
14164 int rn
= extract32(insn
, 5, 5);
14165 int rd
= extract32(insn
, 0, 5);
14166 gen_helper_gvec_2
*genfn
;
14170 unallocated_encoding(s
);
14175 case 0: /* SHA1H */
14176 feature
= dc_isar_feature(aa64_sha1
, s
);
14177 genfn
= gen_helper_crypto_sha1h
;
14179 case 1: /* SHA1SU1 */
14180 feature
= dc_isar_feature(aa64_sha1
, s
);
14181 genfn
= gen_helper_crypto_sha1su1
;
14183 case 2: /* SHA256SU0 */
14184 feature
= dc_isar_feature(aa64_sha256
, s
);
14185 genfn
= gen_helper_crypto_sha256su0
;
14188 unallocated_encoding(s
);
14193 unallocated_encoding(s
);
14197 if (!fp_access_check(s
)) {
14200 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14203 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14205 tcg_gen_rotli_i64(d
, m
, 1);
14206 tcg_gen_xor_i64(d
, d
, n
);
14209 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14211 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14212 tcg_gen_xor_vec(vece
, d
, d
, n
);
14215 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14216 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14218 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14219 static const GVecGen3 op
= {
14220 .fni8
= gen_rax1_i64
,
14221 .fniv
= gen_rax1_vec
,
14222 .opt_opc
= vecop_list
,
14223 .fno
= gen_helper_crypto_rax1
,
14226 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14229 /* Crypto three-reg SHA512
14230 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14231 * +-----------------------+------+---+---+-----+--------+------+------+
14232 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14233 * +-----------------------+------+---+---+-----+--------+------+------+
14235 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14237 int opcode
= extract32(insn
, 10, 2);
14238 int o
= extract32(insn
, 14, 1);
14239 int rm
= extract32(insn
, 16, 5);
14240 int rn
= extract32(insn
, 5, 5);
14241 int rd
= extract32(insn
, 0, 5);
14243 gen_helper_gvec_3
*oolfn
= NULL
;
14244 GVecGen3Fn
*gvecfn
= NULL
;
14248 case 0: /* SHA512H */
14249 feature
= dc_isar_feature(aa64_sha512
, s
);
14250 oolfn
= gen_helper_crypto_sha512h
;
14252 case 1: /* SHA512H2 */
14253 feature
= dc_isar_feature(aa64_sha512
, s
);
14254 oolfn
= gen_helper_crypto_sha512h2
;
14256 case 2: /* SHA512SU1 */
14257 feature
= dc_isar_feature(aa64_sha512
, s
);
14258 oolfn
= gen_helper_crypto_sha512su1
;
14261 feature
= dc_isar_feature(aa64_sha3
, s
);
14262 gvecfn
= gen_gvec_rax1
;
14265 g_assert_not_reached();
14269 case 0: /* SM3PARTW1 */
14270 feature
= dc_isar_feature(aa64_sm3
, s
);
14271 oolfn
= gen_helper_crypto_sm3partw1
;
14273 case 1: /* SM3PARTW2 */
14274 feature
= dc_isar_feature(aa64_sm3
, s
);
14275 oolfn
= gen_helper_crypto_sm3partw2
;
14277 case 2: /* SM4EKEY */
14278 feature
= dc_isar_feature(aa64_sm4
, s
);
14279 oolfn
= gen_helper_crypto_sm4ekey
;
14282 unallocated_encoding(s
);
14288 unallocated_encoding(s
);
14292 if (!fp_access_check(s
)) {
14297 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14299 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14303 /* Crypto two-reg SHA512
14304 * 31 12 11 10 9 5 4 0
14305 * +-----------------------------------------+--------+------+------+
14306 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14307 * +-----------------------------------------+--------+------+------+
14309 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14311 int opcode
= extract32(insn
, 10, 2);
14312 int rn
= extract32(insn
, 5, 5);
14313 int rd
= extract32(insn
, 0, 5);
14317 case 0: /* SHA512SU0 */
14318 feature
= dc_isar_feature(aa64_sha512
, s
);
14321 feature
= dc_isar_feature(aa64_sm4
, s
);
14324 unallocated_encoding(s
);
14329 unallocated_encoding(s
);
14333 if (!fp_access_check(s
)) {
14338 case 0: /* SHA512SU0 */
14339 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14342 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14345 g_assert_not_reached();
14349 /* Crypto four-register
14350 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14351 * +-------------------+-----+------+---+------+------+------+
14352 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14353 * +-------------------+-----+------+---+------+------+------+
14355 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14357 int op0
= extract32(insn
, 21, 2);
14358 int rm
= extract32(insn
, 16, 5);
14359 int ra
= extract32(insn
, 10, 5);
14360 int rn
= extract32(insn
, 5, 5);
14361 int rd
= extract32(insn
, 0, 5);
14367 feature
= dc_isar_feature(aa64_sha3
, s
);
14369 case 2: /* SM3SS1 */
14370 feature
= dc_isar_feature(aa64_sm3
, s
);
14373 unallocated_encoding(s
);
14378 unallocated_encoding(s
);
14382 if (!fp_access_check(s
)) {
14387 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14390 tcg_op1
= tcg_temp_new_i64();
14391 tcg_op2
= tcg_temp_new_i64();
14392 tcg_op3
= tcg_temp_new_i64();
14393 tcg_res
[0] = tcg_temp_new_i64();
14394 tcg_res
[1] = tcg_temp_new_i64();
14396 for (pass
= 0; pass
< 2; pass
++) {
14397 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14398 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14399 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14403 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14406 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14408 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14410 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14411 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14413 tcg_temp_free_i64(tcg_op1
);
14414 tcg_temp_free_i64(tcg_op2
);
14415 tcg_temp_free_i64(tcg_op3
);
14416 tcg_temp_free_i64(tcg_res
[0]);
14417 tcg_temp_free_i64(tcg_res
[1]);
14419 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14421 tcg_op1
= tcg_temp_new_i32();
14422 tcg_op2
= tcg_temp_new_i32();
14423 tcg_op3
= tcg_temp_new_i32();
14424 tcg_res
= tcg_temp_new_i32();
14425 tcg_zero
= tcg_constant_i32(0);
14427 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14428 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14429 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14431 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14432 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14433 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14434 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14436 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14437 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14438 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14439 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14441 tcg_temp_free_i32(tcg_op1
);
14442 tcg_temp_free_i32(tcg_op2
);
14443 tcg_temp_free_i32(tcg_op3
);
14444 tcg_temp_free_i32(tcg_res
);
14449 * 31 21 20 16 15 10 9 5 4 0
14450 * +-----------------------+------+--------+------+------+
14451 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14452 * +-----------------------+------+--------+------+------+
14454 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14456 int rm
= extract32(insn
, 16, 5);
14457 int imm6
= extract32(insn
, 10, 6);
14458 int rn
= extract32(insn
, 5, 5);
14459 int rd
= extract32(insn
, 0, 5);
14461 if (!dc_isar_feature(aa64_sha3
, s
)) {
14462 unallocated_encoding(s
);
14466 if (!fp_access_check(s
)) {
14470 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14471 vec_full_reg_offset(s
, rn
),
14472 vec_full_reg_offset(s
, rm
), imm6
, 16,
14473 vec_full_reg_size(s
));
14476 /* Crypto three-reg imm2
14477 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14478 * +-----------------------+------+-----+------+--------+------+------+
14479 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14480 * +-----------------------+------+-----+------+--------+------+------+
14482 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14484 static gen_helper_gvec_3
* const fns
[4] = {
14485 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14486 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14488 int opcode
= extract32(insn
, 10, 2);
14489 int imm2
= extract32(insn
, 12, 2);
14490 int rm
= extract32(insn
, 16, 5);
14491 int rn
= extract32(insn
, 5, 5);
14492 int rd
= extract32(insn
, 0, 5);
14494 if (!dc_isar_feature(aa64_sm3
, s
)) {
14495 unallocated_encoding(s
);
14499 if (!fp_access_check(s
)) {
14503 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14506 /* C3.6 Data processing - SIMD, inc Crypto
14508 * As the decode gets a little complex we are using a table based
14509 * approach for this part of the decode.
14511 static const AArch64DecodeTable data_proc_simd
[] = {
14512 /* pattern , mask , fn */
14513 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14514 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14515 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14516 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14517 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14518 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14519 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14520 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14521 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14522 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14523 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14524 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14525 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14526 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14527 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14528 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14529 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14530 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14531 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14532 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14533 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14534 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14535 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14536 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14537 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14538 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14539 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14540 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14541 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14542 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14543 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14544 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14545 { 0x00000000, 0x00000000, NULL
}
14548 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14550 /* Note that this is called with all non-FP cases from
14551 * table C3-6 so it must UNDEF for entries not specifically
14552 * allocated to instructions in that table.
14554 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14558 unallocated_encoding(s
);
14562 /* C3.6 Data processing - SIMD and floating point */
14563 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14565 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14566 disas_data_proc_fp(s
, insn
);
14568 /* SIMD, including crypto */
14569 disas_data_proc_simd(s
, insn
);
14574 * Include the generated SME FA64 decoder.
14577 #include "decode-sme-fa64.c.inc"
14579 static bool trans_OK(DisasContext
*s
, arg_OK
*a
)
14584 static bool trans_FAIL(DisasContext
*s
, arg_OK
*a
)
14586 s
->is_nonstreaming
= true;
14592 * @env: The cpu environment
14593 * @s: The DisasContext
14595 * Return true if the page is guarded.
14597 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14599 uint64_t addr
= s
->base
.pc_first
;
14600 #ifdef CONFIG_USER_ONLY
14601 return page_get_flags(addr
) & PAGE_BTI
;
14603 CPUTLBEntryFull
*full
;
14605 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14609 * We test this immediately after reading an insn, which means
14610 * that the TLB entry must be present and valid, and thus this
14611 * access will never raise an exception.
14613 flags
= probe_access_full(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
14614 false, &host
, &full
, 0);
14615 assert(!(flags
& TLB_INVALID_MASK
));
14617 return full
->guarded
;
14622 * btype_destination_ok:
14623 * @insn: The instruction at the branch destination
14624 * @bt: SCTLR_ELx.BT
14625 * @btype: PSTATE.BTYPE, and is non-zero
14627 * On a guarded page, there are a limited number of insns
14628 * that may be present at the branch target:
14629 * - branch target identifiers,
14630 * - paciasp, pacibsp,
14633 * Anything else causes a Branch Target Exception.
14635 * Return true if the branch is compatible, false to raise BTITRAP.
14637 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14639 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14641 switch (extract32(insn
, 5, 7)) {
14642 case 0b011001: /* PACIASP */
14643 case 0b011011: /* PACIBSP */
14645 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14646 * with btype == 3. Otherwise all btype are ok.
14648 return !bt
|| btype
!= 3;
14649 case 0b100000: /* BTI */
14650 /* Not compatible with any btype. */
14652 case 0b100010: /* BTI c */
14653 /* Not compatible with btype == 3 */
14655 case 0b100100: /* BTI j */
14656 /* Not compatible with btype == 2 */
14658 case 0b100110: /* BTI jc */
14659 /* Compatible with any btype. */
14663 switch (insn
& 0xffe0001fu
) {
14664 case 0xd4200000u
: /* BRK */
14665 case 0xd4400000u
: /* HLT */
14666 /* Give priority to the breakpoint exception. */
14673 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14676 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14677 CPUARMState
*env
= cpu
->env_ptr
;
14678 ARMCPU
*arm_cpu
= env_archcpu(env
);
14679 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14680 int bound
, core_mmu_idx
;
14682 dc
->isar
= &arm_cpu
->isar
;
14685 dc
->aarch64
= true;
14688 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14689 dc
->condexec_mask
= 0;
14690 dc
->condexec_cond
= 0;
14691 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14692 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14693 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14694 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14695 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14696 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14697 #if !defined(CONFIG_USER_ONLY)
14698 dc
->user
= (dc
->current_el
== 0);
14700 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14701 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14702 dc
->pstate_il
= EX_TBFLAG_ANY(tb_flags
, PSTATE__IL
);
14703 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14704 dc
->sme_excp_el
= EX_TBFLAG_A64(tb_flags
, SMEEXC_EL
);
14705 dc
->vl
= (EX_TBFLAG_A64(tb_flags
, VL
) + 1) * 16;
14706 dc
->svl
= (EX_TBFLAG_A64(tb_flags
, SVL
) + 1) * 16;
14707 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14708 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14709 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14710 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14711 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14712 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14713 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14714 dc
->pstate_sm
= EX_TBFLAG_A64(tb_flags
, PSTATE_SM
);
14715 dc
->pstate_za
= EX_TBFLAG_A64(tb_flags
, PSTATE_ZA
);
14716 dc
->sme_trap_nonstreaming
= EX_TBFLAG_A64(tb_flags
, SME_TRAP_NONSTREAMING
);
14718 dc
->vec_stride
= 0;
14719 dc
->cp_regs
= arm_cpu
->cp_regs
;
14720 dc
->features
= env
->features
;
14721 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14723 #ifdef CONFIG_USER_ONLY
14724 /* In sve_probe_page, we assume TBI is enabled. */
14725 tcg_debug_assert(dc
->tbid
& 1);
14728 /* Single step state. The code-generation logic here is:
14730 * generate code with no special handling for single-stepping (except
14731 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14732 * this happens anyway because those changes are all system register or
14734 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14735 * emit code for one insn
14736 * emit code to clear PSTATE.SS
14737 * emit code to generate software step exception for completed step
14738 * end TB (as usual for having generated an exception)
14739 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14740 * emit code to generate a software step exception
14743 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14744 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14745 dc
->is_ldex
= false;
14747 /* Bound the number of insns to execute to those left on the page. */
14748 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14750 /* If architectural single step active, limit to 1. */
14751 if (dc
->ss_active
) {
14754 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14756 init_tmp_a64_array(dc
);
14759 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14763 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14765 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14767 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14768 dc
->insn_start
= tcg_last_op();
14771 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14773 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
14774 CPUARMState
*env
= cpu
->env_ptr
;
14775 uint64_t pc
= s
->base
.pc_next
;
14778 /* Singlestep exceptions have the highest priority. */
14779 if (s
->ss_active
&& !s
->pstate_ss
) {
14780 /* Singlestep state is Active-pending.
14781 * If we're in this state at the start of a TB then either
14782 * a) we just took an exception to an EL which is being debugged
14783 * and this is the first insn in the exception handler
14784 * b) debug exceptions were masked and we just unmasked them
14785 * without changing EL (eg by clearing PSTATE.D)
14786 * In either case we're going to take a swstep exception in the
14787 * "did not step an insn" case, and so the syndrome ISV and EX
14788 * bits should be zero.
14790 assert(s
->base
.num_insns
== 1);
14791 gen_swstep_exception(s
, 0, 0);
14792 s
->base
.is_jmp
= DISAS_NORETURN
;
14793 s
->base
.pc_next
= pc
+ 4;
14799 * PC alignment fault. This has priority over the instruction abort
14800 * that we would receive from a translation fault via arm_ldl_code.
14801 * This should only be possible after an indirect branch, at the
14804 assert(s
->base
.num_insns
== 1);
14805 gen_helper_exception_pc_alignment(cpu_env
, tcg_constant_tl(pc
));
14806 s
->base
.is_jmp
= DISAS_NORETURN
;
14807 s
->base
.pc_next
= QEMU_ALIGN_UP(pc
, 4);
14812 insn
= arm_ldl_code(env
, &s
->base
, pc
, s
->sctlr_b
);
14814 s
->base
.pc_next
= pc
+ 4;
14816 s
->fp_access_checked
= false;
14817 s
->sve_access_checked
= false;
14819 if (s
->pstate_il
) {
14821 * Illegal execution state. This has priority over BTI
14822 * exceptions, but comes after instruction abort exceptions.
14824 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_illegalstate());
14828 if (dc_isar_feature(aa64_bti
, s
)) {
14829 if (s
->base
.num_insns
== 1) {
14831 * At the first insn of the TB, compute s->guarded_page.
14832 * We delayed computing this until successfully reading
14833 * the first insn of the TB, above. This (mostly) ensures
14834 * that the softmmu tlb entry has been populated, and the
14835 * page table GP bit is available.
14837 * Note that we need to compute this even if btype == 0,
14838 * because this value is used for BR instructions later
14839 * where ENV is not available.
14841 s
->guarded_page
= is_guarded_page(env
, s
);
14843 /* First insn can have btype set to non-zero. */
14844 tcg_debug_assert(s
->btype
>= 0);
14847 * Note that the Branch Target Exception has fairly high
14848 * priority -- below debugging exceptions but above most
14849 * everything else. This allows us to handle this now
14850 * instead of waiting until the insn is otherwise decoded.
14854 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14855 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_btitrap(s
->btype
));
14859 /* Not the first insn: btype must be 0. */
14860 tcg_debug_assert(s
->btype
== 0);
14864 s
->is_nonstreaming
= false;
14865 if (s
->sme_trap_nonstreaming
) {
14866 disas_sme_fa64(s
, insn
);
14869 switch (extract32(insn
, 25, 4)) {
14871 if (!extract32(insn
, 31, 1) || !disas_sme(s
, insn
)) {
14872 unallocated_encoding(s
);
14875 case 0x1: case 0x3: /* UNALLOCATED */
14876 unallocated_encoding(s
);
14879 if (!disas_sve(s
, insn
)) {
14880 unallocated_encoding(s
);
14883 case 0x8: case 0x9: /* Data processing - immediate */
14884 disas_data_proc_imm(s
, insn
);
14886 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14887 disas_b_exc_sys(s
, insn
);
14892 case 0xe: /* Loads and stores */
14893 disas_ldst(s
, insn
);
14896 case 0xd: /* Data processing - register */
14897 disas_data_proc_reg(s
, insn
);
14900 case 0xf: /* Data processing - SIMD and floating point */
14901 disas_data_proc_simd_fp(s
, insn
);
14904 assert(FALSE
); /* all 15 cases should be handled above */
14908 /* if we allocated any temporaries, free them here */
14912 * After execution of most insns, btype is reset to 0.
14913 * Note that we set btype == -1 when the insn sets btype.
14915 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14919 translator_loop_temp_check(&s
->base
);
14922 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14924 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14926 if (unlikely(dc
->ss_active
)) {
14927 /* Note that this means single stepping WFI doesn't halt the CPU.
14928 * For conditional branch insns this is harmless unreachable code as
14929 * gen_goto_tb() has already handled emitting the debug exception
14930 * (and thus a tb-jump is not possible when singlestepping).
14932 switch (dc
->base
.is_jmp
) {
14934 gen_a64_update_pc(dc
, 4);
14938 gen_step_complete_exception(dc
);
14940 case DISAS_NORETURN
:
14944 switch (dc
->base
.is_jmp
) {
14946 case DISAS_TOO_MANY
:
14947 gen_goto_tb(dc
, 1, 4);
14950 case DISAS_UPDATE_EXIT
:
14951 gen_a64_update_pc(dc
, 4);
14954 tcg_gen_exit_tb(NULL
, 0);
14956 case DISAS_UPDATE_NOCHAIN
:
14957 gen_a64_update_pc(dc
, 4);
14960 tcg_gen_lookup_and_goto_ptr();
14962 case DISAS_NORETURN
:
14966 gen_a64_update_pc(dc
, 4);
14967 gen_helper_wfe(cpu_env
);
14970 gen_a64_update_pc(dc
, 4);
14971 gen_helper_yield(cpu_env
);
14975 * This is a special case because we don't want to just halt
14976 * the CPU if trying to debug across a WFI.
14978 gen_a64_update_pc(dc
, 4);
14979 gen_helper_wfi(cpu_env
, tcg_constant_i32(4));
14981 * The helper doesn't necessarily throw an exception, but we
14982 * must go back to the main loop to check for interrupts anyway.
14984 tcg_gen_exit_tb(NULL
, 0);
14990 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14991 CPUState
*cpu
, FILE *logfile
)
14993 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14995 fprintf(logfile
, "IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14996 target_disas(logfile
, cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14999 const TranslatorOps aarch64_translator_ops
= {
15000 .init_disas_context
= aarch64_tr_init_disas_context
,
15001 .tb_start
= aarch64_tr_tb_start
,
15002 .insn_start
= aarch64_tr_insn_start
,
15003 .translate_insn
= aarch64_tr_translate_insn
,
15004 .tb_stop
= aarch64_tr_tb_stop
,
15005 .disas_log
= aarch64_tr_disas_log
,