hw/pci-host/raven.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/datadir.h"
  28 #include "qemu/units.h"
  29 #include "qemu/log.h"
  30 #include "qapi/error.h"
  31 #include "hw/pci/pci_device.h"
  32 #include "hw/pci/pci_bus.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/qdev-properties.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/intc/i8259.h"
  37 #include "hw/irq.h"
  38 #include "hw/loader.h"
  39 #include "hw/or-irq.h"
  40 #include "elf.h"
  41 #include "qom/object.h"
  42
  43 #define TYPE_RAVEN_PCI_DEVICE "raven"
  44 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  45
  46 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
  47
  48 struct RavenPCIState {
  49     PCIDevice dev;
  50
  51     uint32_t elf_machine;
  52     char *bios_name;
  53     MemoryRegion bios;
  54 };
  55
  56 typedef struct PRePPCIState PREPPCIState;
  57 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
  58                          TYPE_RAVEN_PCI_HOST_BRIDGE)
  59
  60 struct PRePPCIState {
  61     PCIHostState parent_obj;
  62
  63     OrIRQState *or_irq;
  64     qemu_irq pci_irqs[PCI_NUM_PINS];
  65     PCIBus pci_bus;
  66     AddressSpace pci_io_as;
  67     MemoryRegion pci_io;
  68     MemoryRegion pci_io_non_contiguous;
  69     MemoryRegion pci_memory;
  70     MemoryRegion pci_intack;
  71     MemoryRegion bm;
  72     MemoryRegion bm_ram_alias;
  73     MemoryRegion bm_pci_memory_alias;
  74     AddressSpace bm_as;
  75     RavenPCIState pci_dev;
  76
  77     int contiguous_map;
  78     bool is_legacy_prep;
  79 };
  80
  81 #define BIOS_SIZE (1 * MiB)
  82
  83 #define PCI_IO_BASE_ADDR    0x80000000  /* Physical address on main bus */
  84
  85 static inline uint32_t raven_pci_io_config(hwaddr addr)
  86 {
  87     int i;
  88
  89     for (i = 0; i < 11; i++) {
  90         if ((addr & (1 << (11 + i))) != 0) {
  91             break;
  92         }
  93     }
  94     return (addr & 0x7ff) |  (i << 11);
  95 }
  96
  97 static void raven_pci_io_write(void *opaque, hwaddr addr,
  98                                uint64_t val, unsigned int size)
  99 {
 100     PREPPCIState *s = opaque;
 101     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 102     pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
 103 }
 104
 105 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
 106                                   unsigned int size)
 107 {
 108     PREPPCIState *s = opaque;
 109     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 110     return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
 111 }
 112
 113 static const MemoryRegionOps raven_pci_io_ops = {
 114     .read = raven_pci_io_read,
 115     .write = raven_pci_io_write,
 116     .endianness = DEVICE_LITTLE_ENDIAN,
 117 };
 118
 119 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
 120                                   unsigned int size)
 121 {
 122     return pic_read_irq(isa_pic);
 123 }
 124
 125 static void raven_intack_write(void *opaque, hwaddr addr,
 126                                         uint64_t data, unsigned size)
 127 {
 128     qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
 129 }
 130
 131 static const MemoryRegionOps raven_intack_ops = {
 132     .read = raven_intack_read,
 133     .write = raven_intack_write,
 134     .valid = {
 135         .max_access_size = 1,
 136     },
 137 };
 138
 139 static inline hwaddr raven_io_address(PREPPCIState *s,
 140                                       hwaddr addr)
 141 {
 142     if (s->contiguous_map == 0) {
 143         /* 64 KB contiguous space for IOs */
 144         addr &= 0xFFFF;
 145     } else {
 146         /* 8 MB non-contiguous space for IOs */
 147         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 148     }
 149
 150     /* FIXME: handle endianness switch */
 151
 152     return addr;
 153 }
 154
 155 static uint64_t raven_io_read(void *opaque, hwaddr addr,
 156                               unsigned int size)
 157 {
 158     PREPPCIState *s = opaque;
 159     uint8_t buf[4];
 160
 161     addr = raven_io_address(s, addr);
 162     address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
 163                        MEMTXATTRS_UNSPECIFIED, buf, size);
 164
 165     if (size == 1) {
 166         return buf[0];
 167     } else if (size == 2) {
 168         return lduw_le_p(buf);
 169     } else if (size == 4) {
 170         return ldl_le_p(buf);
 171     } else {
 172         g_assert_not_reached();
 173     }
 174 }
 175
 176 static void raven_io_write(void *opaque, hwaddr addr,
 177                            uint64_t val, unsigned int size)
 178 {
 179     PREPPCIState *s = opaque;
 180     uint8_t buf[4];
 181
 182     addr = raven_io_address(s, addr);
 183
 184     if (size == 1) {
 185         buf[0] = val;
 186     } else if (size == 2) {
 187         stw_le_p(buf, val);
 188     } else if (size == 4) {
 189         stl_le_p(buf, val);
 190     } else {
 191         g_assert_not_reached();
 192     }
 193
 194     address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
 195                         MEMTXATTRS_UNSPECIFIED, buf, size);
 196 }
 197
 198 static const MemoryRegionOps raven_io_ops = {
 199     .read = raven_io_read,
 200     .write = raven_io_write,
 201     .endianness = DEVICE_LITTLE_ENDIAN,
 202     .impl.max_access_size = 4,
 203     .valid.unaligned = true,
 204 };
 205
 206 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 207 {
 208     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 209 }
 210
 211 static void raven_set_irq(void *opaque, int irq_num, int level)
 212 {
 213     PREPPCIState *s = opaque;
 214
 215     qemu_set_irq(s->pci_irqs[irq_num], level);
 216 }
 217
 218 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
 219                                              int devfn)
 220 {
 221     PREPPCIState *s = opaque;
 222
 223     return &s->bm_as;
 224 }
 225
 226 static const PCIIOMMUOps raven_iommu_ops = {
 227     .get_address_space = raven_pcihost_set_iommu,
 228 };
 229
 230 static void raven_change_gpio(void *opaque, int n, int level)
 231 {
 232     PREPPCIState *s = opaque;
 233
 234     s->contiguous_map = level;
 235 }
 236
 237 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 238 {
 239     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 240     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 241     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 242     MemoryRegion *address_space_mem = get_system_memory();
 243     int i;
 244
 245     if (s->is_legacy_prep) {
 246         for (i = 0; i < PCI_NUM_PINS; i++) {
 247             sysbus_init_irq(dev, &s->pci_irqs[i]);
 248         }
 249     } else {
 250         /* According to PReP specification section 6.1.6 "System Interrupt
 251          * Assignments", all PCI interrupts are routed via IRQ 15 */
 252         s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
 253         object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
 254                                 &error_fatal);
 255         qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
 256         sysbus_init_irq(dev, &s->or_irq->out_irq);
 257
 258         for (i = 0; i < PCI_NUM_PINS; i++) {
 259             s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
 260         }
 261     }
 262
 263     qdev_init_gpio_in(d, raven_change_gpio, 1);
 264
 265     pci_bus_irqs(&s->pci_bus, raven_set_irq, s, PCI_NUM_PINS);
 266     pci_bus_map_irqs(&s->pci_bus, raven_map_irq);
 267
 268     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
 269                           "pci-conf-idx", 4);
 270     memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
 271
 272     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
 273                           "pci-conf-data", 4);
 274     memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
 275
 276     memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
 277                           "pciio", 0x00400000);
 278     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 279
 280     memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
 281                           "pci-intack", 1);
 282     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
 283
 284     /* TODO Remove once realize propagates to child devices. */
 285     qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
 286 }
 287
 288 static void raven_pcihost_initfn(Object *obj)
 289 {
 290     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 291     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 292     MemoryRegion *address_space_mem = get_system_memory();
 293     DeviceState *pci_dev;
 294
 295     memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
 296     memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
 297                           "pci-io-non-contiguous", 0x00800000);
 298     memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
 299     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 300
 301     /*
 302      * Raven's raven_io_ops use the address-space API to access pci-conf-idx
 303      * (which is also owned by the raven device). As such, mark the
 304      * pci_io_non_contiguous as re-entrancy safe.
 305      */
 306     s->pci_io_non_contiguous.disable_reentrancy_guard = true;
 307
 308     /* CPU address space */
 309     memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
 310                                 &s->pci_io);
 311     memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
 312                                         &s->pci_io_non_contiguous, 1);
 313     memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
 314     pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 315                       &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
 316
 317     /* Bus master address space */
 318     memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
 319     memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
 320                              &s->pci_memory, 0,
 321                              memory_region_size(&s->pci_memory));
 322     memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
 323                              get_system_memory(), 0, 0x80000000);
 324     memory_region_add_subregion(&s->bm, 0         , &s->bm_pci_memory_alias);
 325     memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
 326     address_space_init(&s->bm_as, &s->bm, "raven-bm");
 327     pci_setup_iommu(&s->pci_bus, &raven_iommu_ops, s);
 328
 329     h->bus = &s->pci_bus;
 330
 331     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 332     pci_dev = DEVICE(&s->pci_dev);
 333     object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
 334                             NULL);
 335     qdev_prop_set_bit(pci_dev, "multifunction", false);
 336 }
 337
 338 static void raven_realize(PCIDevice *d, Error **errp)
 339 {
 340     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 341     char *filename;
 342     int bios_size = -1;
 343
 344     d->config[PCI_CACHE_LINE_SIZE] = 0x08;
 345     d->config[PCI_LATENCY_TIMER] = 0x10;
 346     d->config[PCI_CAPABILITY_LIST] = 0x00;
 347
 348     if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios",
 349                                           BIOS_SIZE, errp)) {
 350         return;
 351     }
 352     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 353                                 &s->bios);
 354     if (s->bios_name) {
 355         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 356         if (filename) {
 357             if (s->elf_machine != EM_NONE) {
 358                 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
 359                                      NULL, NULL, NULL, 1, s->elf_machine,
 360                                      0, 0);
 361             }
 362             if (bios_size < 0) {
 363                 bios_size = get_image_size(filename);
 364                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 365                     hwaddr bios_addr;
 366                     bios_size = (bios_size + 0xfff) & ~0xfff;
 367                     bios_addr = (uint32_t)(-BIOS_SIZE);
 368                     bios_size = load_image_targphys(filename, bios_addr,
 369                                                     bios_size);
 370                 }
 371             }
 372         }
 373         g_free(filename);
 374         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 375             memory_region_del_subregion(get_system_memory(), &s->bios);
 376             error_setg(errp, "Could not load bios image '%s'", s->bios_name);
 377             return;
 378         }
 379     }
 380
 381     vmstate_register_ram_global(&s->bios);
 382 }
 383
 384 static const VMStateDescription vmstate_raven = {
 385     .name = "raven",
 386     .version_id = 0,
 387     .minimum_version_id = 0,
 388     .fields = (const VMStateField[]) {
 389         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 390         VMSTATE_END_OF_LIST()
 391     },
 392 };
 393
 394 static void raven_class_init(ObjectClass *klass, void *data)
 395 {
 396     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 397     DeviceClass *dc = DEVICE_CLASS(klass);
 398
 399     k->realize = raven_realize;
 400     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 401     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 402     k->revision = 0x00;
 403     k->class_id = PCI_CLASS_BRIDGE_HOST;
 404     dc->desc = "PReP Host Bridge - Motorola Raven";
 405     dc->vmsd = &vmstate_raven;
 406     /*
 407      * Reason: PCI-facing part of the host bridge, not usable without
 408      * the host-facing part, which can't be device_add'ed, yet.
 409      */
 410     dc->user_creatable = false;
 411 }
 412
 413 static const TypeInfo raven_info = {
 414     .name = TYPE_RAVEN_PCI_DEVICE,
 415     .parent = TYPE_PCI_DEVICE,
 416     .instance_size = sizeof(RavenPCIState),
 417     .class_init = raven_class_init,
 418     .interfaces = (InterfaceInfo[]) {
 419         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 420         { },
 421     },
 422 };
 423
 424 static Property raven_pcihost_properties[] = {
 425     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 426                        EM_NONE),
 427     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 428     /* Temporary workaround until legacy prep machine is removed */
 429     DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
 430                      false),
 431     DEFINE_PROP_END_OF_LIST()
 432 };
 433
 434 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 435 {
 436     DeviceClass *dc = DEVICE_CLASS(klass);
 437
 438     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 439     dc->realize = raven_pcihost_realizefn;
 440     device_class_set_props(dc, raven_pcihost_properties);
 441     dc->fw_name = "pci";
 442 }
 443
 444 static const TypeInfo raven_pcihost_info = {
 445     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 446     .parent = TYPE_PCI_HOST_BRIDGE,
 447     .instance_size = sizeof(PREPPCIState),
 448     .instance_init = raven_pcihost_initfn,
 449     .class_init = raven_pcihost_class_init,
 450 };
 451
 452 static void raven_register_types(void)
 453 {
 454     type_register_static(&raven_pcihost_info);
 455     type_register_static(&raven_info);
 456 }
 457
 458 type_init(raven_register_types)