hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index;
  48
  49     /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
  50      * are hot plugged or unplugged.
  51      */
  52     if (!icp) {
  53         return;
  54     }
  55
  56     cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  57
  58     if (!icp->output) {
  59         return;
  60     }
  61
  62     if (kvm_irqchip_in_kernel()) {
  63         icp_synchronize_state(icp);
  64     }
  65
  66     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  67                    cpu_index, icp->xirr, icp->xirr_owner,
  68                    icp->pending_priority, icp->mfrr);
  69 }
  70
  71 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  72 {
  73     uint32_t i;
  74
  75     monitor_printf(mon, "ICS %4x..%4x %p\n",
  76                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  77
  78     if (!ics->irqs) {
  79         return;
  80     }
  81
  82     if (kvm_irqchip_in_kernel()) {
  83         ics_synchronize_state(ics);
  84     }
  85
  86     for (i = 0; i < ics->nr_irqs; i++) {
  87         ICSIRQState *irq = ics->irqs + i;
  88
  89         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  90             continue;
  91         }
  92         monitor_printf(mon, "  %4x %s %02x %02x\n",
  93                        ics->offset + i,
  94                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  95                        "LSI" : "MSI",
  96                        irq->priority, irq->status);
  97     }
  98 }
  99
 100 /*
 101  * ICP: Presentation layer
 102  */
 103
 104 #define XISR_MASK  0x00ffffff
 105 #define CPPR_MASK  0xff000000
 106
 107 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 108 #define CPPR(icp)   (((icp)->xirr) >> 24)
 109
 110 static void ics_reject(ICSState *ics, uint32_t nr);
 111 static void ics_eoi(ICSState *ics, uint32_t nr);
 112
 113 static void icp_check_ipi(ICPState *icp)
 114 {
 115     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 116         return;
 117     }
 118
 119     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 120
 121     if (XISR(icp) && icp->xirr_owner) {
 122         ics_reject(icp->xirr_owner, XISR(icp));
 123     }
 124
 125     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 126     icp->pending_priority = icp->mfrr;
 127     icp->xirr_owner = NULL;
 128     qemu_irq_raise(icp->output);
 129 }
 130
 131 void icp_resend(ICPState *icp)
 132 {
 133     XICSFabric *xi = icp->xics;
 134     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 135
 136     if (icp->mfrr < CPPR(icp)) {
 137         icp_check_ipi(icp);
 138     }
 139
 140     xic->ics_resend(xi);
 141 }
 142
 143 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 144 {
 145     uint8_t old_cppr;
 146     uint32_t old_xisr;
 147
 148     old_cppr = CPPR(icp);
 149     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 150
 151     if (cppr < old_cppr) {
 152         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 153             old_xisr = XISR(icp);
 154             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 155             icp->pending_priority = 0xff;
 156             qemu_irq_lower(icp->output);
 157             if (icp->xirr_owner) {
 158                 ics_reject(icp->xirr_owner, old_xisr);
 159                 icp->xirr_owner = NULL;
 160             }
 161         }
 162     } else {
 163         if (!XISR(icp)) {
 164             icp_resend(icp);
 165         }
 166     }
 167 }
 168
 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 170 {
 171     icp->mfrr = mfrr;
 172     if (mfrr < CPPR(icp)) {
 173         icp_check_ipi(icp);
 174     }
 175 }
 176
 177 uint32_t icp_accept(ICPState *icp)
 178 {
 179     uint32_t xirr = icp->xirr;
 180
 181     qemu_irq_lower(icp->output);
 182     icp->xirr = icp->pending_priority << 24;
 183     icp->pending_priority = 0xff;
 184     icp->xirr_owner = NULL;
 185
 186     trace_xics_icp_accept(xirr, icp->xirr);
 187
 188     return xirr;
 189 }
 190
 191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 192 {
 193     if (mfrr) {
 194         *mfrr = icp->mfrr;
 195     }
 196     return icp->xirr;
 197 }
 198
 199 void icp_eoi(ICPState *icp, uint32_t xirr)
 200 {
 201     XICSFabric *xi = icp->xics;
 202     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 203     ICSState *ics;
 204     uint32_t irq;
 205
 206     /* Send EOI -> ICS */
 207     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 208     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 209     irq = xirr & XISR_MASK;
 210
 211     ics = xic->ics_get(xi, irq);
 212     if (ics) {
 213         ics_eoi(ics, irq);
 214     }
 215     if (!XISR(icp)) {
 216         icp_resend(icp);
 217     }
 218 }
 219
 220 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 221 {
 222     ICPState *icp = xics_icp_get(ics->xics, server);
 223
 224     trace_xics_icp_irq(server, nr, priority);
 225
 226     if ((priority >= CPPR(icp))
 227         || (XISR(icp) && (icp->pending_priority <= priority))) {
 228         ics_reject(ics, nr);
 229     } else {
 230         if (XISR(icp) && icp->xirr_owner) {
 231             ics_reject(icp->xirr_owner, XISR(icp));
 232             icp->xirr_owner = NULL;
 233         }
 234         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 235         icp->xirr_owner = ics;
 236         icp->pending_priority = priority;
 237         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 238         qemu_irq_raise(icp->output);
 239     }
 240 }
 241
 242 static int icp_pre_save(void *opaque)
 243 {
 244     ICPState *icp = opaque;
 245
 246     if (kvm_irqchip_in_kernel()) {
 247         icp_get_kvm_state(icp);
 248     }
 249
 250     return 0;
 251 }
 252
 253 static int icp_post_load(void *opaque, int version_id)
 254 {
 255     ICPState *icp = opaque;
 256
 257     if (kvm_irqchip_in_kernel()) {
 258         Error *local_err = NULL;
 259         int ret;
 260
 261         ret = icp_set_kvm_state(icp, &local_err);
 262         if (ret < 0) {
 263             error_report_err(local_err);
 264             return ret;
 265         }
 266     }
 267
 268     return 0;
 269 }
 270
 271 static const VMStateDescription vmstate_icp_server = {
 272     .name = "icp/server",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .pre_save = icp_pre_save,
 276     .post_load = icp_post_load,
 277     .fields = (VMStateField[]) {
 278         /* Sanity check */
 279         VMSTATE_UINT32(xirr, ICPState),
 280         VMSTATE_UINT8(pending_priority, ICPState),
 281         VMSTATE_UINT8(mfrr, ICPState),
 282         VMSTATE_END_OF_LIST()
 283     },
 284 };
 285
 286 void icp_reset(ICPState *icp)
 287 {
 288     icp->xirr = 0;
 289     icp->pending_priority = 0xff;
 290     icp->mfrr = 0xff;
 291
 292     /* Make all outputs are deasserted */
 293     qemu_set_irq(icp->output, 0);
 294
 295     if (kvm_irqchip_in_kernel()) {
 296         Error *local_err = NULL;
 297
 298         icp_set_kvm_state(icp, &local_err);
 299         if (local_err) {
 300             error_report_err(local_err);
 301         }
 302     }
 303 }
 304
 305 static void icp_realize(DeviceState *dev, Error **errp)
 306 {
 307     ICPState *icp = ICP(dev);
 308     PowerPCCPU *cpu;
 309     CPUPPCState *env;
 310     Object *obj;
 311     Error *err = NULL;
 312
 313     assert(icp->xics);
 314
 315     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 316     if (!obj) {
 317         error_propagate_prepend(errp, err,
 318                                 "required link '" ICP_PROP_CPU
 319                                 "' not found: ");
 320         return;
 321     }
 322
 323     cpu = POWERPC_CPU(obj);
 324     icp->cs = CPU(obj);
 325
 326     env = &cpu->env;
 327     switch (PPC_INPUT(env)) {
 328     case PPC_FLAGS_INPUT_POWER7:
 329         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 330         break;
 331     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 332         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 333         break;
 334
 335     case PPC_FLAGS_INPUT_970:
 336         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 337         break;
 338
 339     default:
 340         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 341         return;
 342     }
 343
 344     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 345     if (kvm_irqchip_in_kernel()) {
 346         icp_kvm_realize(dev, &err);
 347         if (err) {
 348             error_propagate(errp, err);
 349             return;
 350         }
 351     }
 352
 353     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 354 }
 355
 356 static void icp_unrealize(DeviceState *dev, Error **errp)
 357 {
 358     ICPState *icp = ICP(dev);
 359
 360     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 361 }
 362
 363 static Property icp_properties[] = {
 364     DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
 365                      XICSFabric *),
 366     DEFINE_PROP_END_OF_LIST(),
 367 };
 368
 369 static void icp_class_init(ObjectClass *klass, void *data)
 370 {
 371     DeviceClass *dc = DEVICE_CLASS(klass);
 372
 373     dc->realize = icp_realize;
 374     dc->unrealize = icp_unrealize;
 375     dc->props = icp_properties;
 376     /*
 377      * Reason: part of XICS interrupt controller, needs to be wired up
 378      * by icp_create().
 379      */
 380     dc->user_creatable = false;
 381 }
 382
 383 static const TypeInfo icp_info = {
 384     .name = TYPE_ICP,
 385     .parent = TYPE_DEVICE,
 386     .instance_size = sizeof(ICPState),
 387     .class_init = icp_class_init,
 388     .class_size = sizeof(ICPStateClass),
 389 };
 390
 391 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 392 {
 393     Error *local_err = NULL;
 394     Object *obj;
 395
 396     obj = object_new(type);
 397     object_property_add_child(cpu, type, obj, &error_abort);
 398     object_unref(obj);
 399     object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
 400     object_ref(cpu);
 401     object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 402     object_property_set_bool(obj, true, "realized", &local_err);
 403     if (local_err) {
 404         object_unparent(obj);
 405         error_propagate(errp, local_err);
 406         obj = NULL;
 407     }
 408
 409     return obj;
 410 }
 411
 412 void icp_destroy(ICPState *icp)
 413 {
 414     Object *obj = OBJECT(icp);
 415
 416     object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort));
 417     object_unparent(obj);
 418 }
 419
 420 /*
 421  * ICS: Source layer
 422  */
 423 static void ics_resend_msi(ICSState *ics, int srcno)
 424 {
 425     ICSIRQState *irq = ics->irqs + srcno;
 426
 427     /* FIXME: filter by server#? */
 428     if (irq->status & XICS_STATUS_REJECTED) {
 429         irq->status &= ~XICS_STATUS_REJECTED;
 430         if (irq->priority != 0xff) {
 431             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 432         }
 433     }
 434 }
 435
 436 static void ics_resend_lsi(ICSState *ics, int srcno)
 437 {
 438     ICSIRQState *irq = ics->irqs + srcno;
 439
 440     if ((irq->priority != 0xff)
 441         && (irq->status & XICS_STATUS_ASSERTED)
 442         && !(irq->status & XICS_STATUS_SENT)) {
 443         irq->status |= XICS_STATUS_SENT;
 444         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 445     }
 446 }
 447
 448 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 449 {
 450     ICSIRQState *irq = ics->irqs + srcno;
 451
 452     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 453
 454     if (val) {
 455         if (irq->priority == 0xff) {
 456             irq->status |= XICS_STATUS_MASKED_PENDING;
 457             trace_xics_masked_pending();
 458         } else  {
 459             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 460         }
 461     }
 462 }
 463
 464 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 465 {
 466     ICSIRQState *irq = ics->irqs + srcno;
 467
 468     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 469     if (val) {
 470         irq->status |= XICS_STATUS_ASSERTED;
 471     } else {
 472         irq->status &= ~XICS_STATUS_ASSERTED;
 473     }
 474     ics_resend_lsi(ics, srcno);
 475 }
 476
 477 void ics_set_irq(void *opaque, int srcno, int val)
 478 {
 479     ICSState *ics = (ICSState *)opaque;
 480
 481     if (kvm_irqchip_in_kernel()) {
 482         ics_kvm_set_irq(ics, srcno, val);
 483         return;
 484     }
 485
 486     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 487         ics_set_irq_lsi(ics, srcno, val);
 488     } else {
 489         ics_set_irq_msi(ics, srcno, val);
 490     }
 491 }
 492
 493 static void ics_write_xive_msi(ICSState *ics, int srcno)
 494 {
 495     ICSIRQState *irq = ics->irqs + srcno;
 496
 497     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 498         || (irq->priority == 0xff)) {
 499         return;
 500     }
 501
 502     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 503     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 504 }
 505
 506 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 507 {
 508     ics_resend_lsi(ics, srcno);
 509 }
 510
 511 void ics_write_xive(ICSState *ics, int srcno, int server,
 512                     uint8_t priority, uint8_t saved_priority)
 513 {
 514     ICSIRQState *irq = ics->irqs + srcno;
 515
 516     irq->server = server;
 517     irq->priority = priority;
 518     irq->saved_priority = saved_priority;
 519
 520     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 521
 522     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 523         ics_write_xive_lsi(ics, srcno);
 524     } else {
 525         ics_write_xive_msi(ics, srcno);
 526     }
 527 }
 528
 529 static void ics_reject(ICSState *ics, uint32_t nr)
 530 {
 531     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 532
 533     trace_xics_ics_reject(nr, nr - ics->offset);
 534     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 535         irq->status |= XICS_STATUS_REJECTED;
 536     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 537         irq->status &= ~XICS_STATUS_SENT;
 538     }
 539 }
 540
 541 void ics_resend(ICSState *ics)
 542 {
 543     int i;
 544
 545     for (i = 0; i < ics->nr_irqs; i++) {
 546         /* FIXME: filter by server#? */
 547         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 548             ics_resend_lsi(ics, i);
 549         } else {
 550             ics_resend_msi(ics, i);
 551         }
 552     }
 553 }
 554
 555 static void ics_eoi(ICSState *ics, uint32_t nr)
 556 {
 557     int srcno = nr - ics->offset;
 558     ICSIRQState *irq = ics->irqs + srcno;
 559
 560     trace_xics_ics_eoi(nr);
 561
 562     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 563         irq->status &= ~XICS_STATUS_SENT;
 564     }
 565 }
 566
 567 static void ics_reset_irq(ICSIRQState *irq)
 568 {
 569     irq->priority = 0xff;
 570     irq->saved_priority = 0xff;
 571 }
 572
 573 static void ics_reset(DeviceState *dev)
 574 {
 575     ICSState *ics = ICS(dev);
 576     int i;
 577     uint8_t flags[ics->nr_irqs];
 578
 579     for (i = 0; i < ics->nr_irqs; i++) {
 580         flags[i] = ics->irqs[i].flags;
 581     }
 582
 583     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 584
 585     for (i = 0; i < ics->nr_irqs; i++) {
 586         ics_reset_irq(ics->irqs + i);
 587         ics->irqs[i].flags = flags[i];
 588     }
 589
 590     if (kvm_irqchip_in_kernel()) {
 591         Error *local_err = NULL;
 592
 593         ics_set_kvm_state(ICS(dev), &local_err);
 594         if (local_err) {
 595             error_report_err(local_err);
 596         }
 597     }
 598 }
 599
 600 static void ics_reset_handler(void *dev)
 601 {
 602     ics_reset(dev);
 603 }
 604
 605 static void ics_realize(DeviceState *dev, Error **errp)
 606 {
 607     ICSState *ics = ICS(dev);
 608
 609     assert(ics->xics);
 610
 611     if (!ics->nr_irqs) {
 612         error_setg(errp, "Number of interrupts needs to be greater 0");
 613         return;
 614     }
 615     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 616
 617     qemu_register_reset(ics_reset_handler, ics);
 618 }
 619
 620 static void ics_instance_init(Object *obj)
 621 {
 622     ICSState *ics = ICS(obj);
 623
 624     ics->offset = XICS_IRQ_BASE;
 625 }
 626
 627 static int ics_pre_save(void *opaque)
 628 {
 629     ICSState *ics = opaque;
 630
 631     if (kvm_irqchip_in_kernel()) {
 632         ics_get_kvm_state(ics);
 633     }
 634
 635     return 0;
 636 }
 637
 638 static int ics_post_load(void *opaque, int version_id)
 639 {
 640     ICSState *ics = opaque;
 641
 642     if (kvm_irqchip_in_kernel()) {
 643         Error *local_err = NULL;
 644         int ret;
 645
 646         ret = ics_set_kvm_state(ics, &local_err);
 647         if (ret < 0) {
 648             error_report_err(local_err);
 649             return ret;
 650         }
 651     }
 652
 653     return 0;
 654 }
 655
 656 static const VMStateDescription vmstate_ics_irq = {
 657     .name = "ics/irq",
 658     .version_id = 2,
 659     .minimum_version_id = 1,
 660     .fields = (VMStateField[]) {
 661         VMSTATE_UINT32(server, ICSIRQState),
 662         VMSTATE_UINT8(priority, ICSIRQState),
 663         VMSTATE_UINT8(saved_priority, ICSIRQState),
 664         VMSTATE_UINT8(status, ICSIRQState),
 665         VMSTATE_UINT8(flags, ICSIRQState),
 666         VMSTATE_END_OF_LIST()
 667     },
 668 };
 669
 670 static const VMStateDescription vmstate_ics = {
 671     .name = "ics",
 672     .version_id = 1,
 673     .minimum_version_id = 1,
 674     .pre_save = ics_pre_save,
 675     .post_load = ics_post_load,
 676     .fields = (VMStateField[]) {
 677         /* Sanity check */
 678         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 679
 680         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 681                                              vmstate_ics_irq,
 682                                              ICSIRQState),
 683         VMSTATE_END_OF_LIST()
 684     },
 685 };
 686
 687 static Property ics_properties[] = {
 688     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 689     DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
 690                      XICSFabric *),
 691     DEFINE_PROP_END_OF_LIST(),
 692 };
 693
 694 static void ics_class_init(ObjectClass *klass, void *data)
 695 {
 696     DeviceClass *dc = DEVICE_CLASS(klass);
 697
 698     dc->realize = ics_realize;
 699     dc->props = ics_properties;
 700     dc->reset = ics_reset;
 701     dc->vmsd = &vmstate_ics;
 702     /*
 703      * Reason: part of XICS interrupt controller, needs to be wired up,
 704      * e.g. by spapr_irq_init().
 705      */
 706     dc->user_creatable = false;
 707 }
 708
 709 static const TypeInfo ics_info = {
 710     .name = TYPE_ICS,
 711     .parent = TYPE_DEVICE,
 712     .instance_size = sizeof(ICSState),
 713     .instance_init = ics_instance_init,
 714     .class_init = ics_class_init,
 715     .class_size = sizeof(ICSStateClass),
 716 };
 717
 718 static const TypeInfo xics_fabric_info = {
 719     .name = TYPE_XICS_FABRIC,
 720     .parent = TYPE_INTERFACE,
 721     .class_size = sizeof(XICSFabricClass),
 722 };
 723
 724 /*
 725  * Exported functions
 726  */
 727 ICPState *xics_icp_get(XICSFabric *xi, int server)
 728 {
 729     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 730
 731     return xic->icp_get(xi, server);
 732 }
 733
 734 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 735 {
 736     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 737
 738     ics->irqs[srcno].flags |=
 739         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 740
 741     if (kvm_irqchip_in_kernel()) {
 742         Error *local_err = NULL;
 743
 744         ics_reset_irq(ics->irqs + srcno);
 745         ics_set_kvm_state_one(ics, srcno, &local_err);
 746         if (local_err) {
 747             error_report_err(local_err);
 748         }
 749     }
 750 }
 751
 752 static void xics_register_types(void)
 753 {
 754     type_register_static(&ics_info);
 755     type_register_static(&icp_info);
 756     type_register_static(&xics_fabric_info);
 757 }
 758
 759 type_init(xics_register_types)