2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qapi/error.h"
28 #include "ui/console.h"
29 #include "ui/pixel_ops.h"
30 #include "hw/loader.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/sysbus.h"
33 #include "migration/vmstate.h"
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qom/object.h"
38 #define TCX_ROM_FILE "QEMU,tcx.bin"
39 #define FCODE_MAX_ROM_SIZE 0x10000
43 #define TCX_DAC_NREGS 16
44 #define TCX_THC_NREGS 0x1000
45 #define TCX_DHC_NREGS 0x4000
46 #define TCX_TEC_NREGS 0x1000
47 #define TCX_ALT_NREGS 0x8000
48 #define TCX_STIP_NREGS 0x800000
49 #define TCX_BLIT_NREGS 0x800000
50 #define TCX_RSTIP_NREGS 0x800000
51 #define TCX_RBLIT_NREGS 0x800000
53 #define TCX_THC_MISC 0x818
54 #define TCX_THC_CURSXY 0x8fc
55 #define TCX_THC_CURSMASK 0x900
56 #define TCX_THC_CURSBITS 0x980
58 #define TYPE_TCX "SUNW,tcx"
59 OBJECT_DECLARE_SIMPLE_TYPE(TCXState
, TCX
)
62 SysBusDevice parent_obj
;
67 uint32_t *vram24
, *cplane
;
70 MemoryRegion vram_mem
;
71 MemoryRegion vram_8bit
;
72 MemoryRegion vram_24bit
;
75 MemoryRegion vram_cplane
;
85 ram_addr_t vram24_offset
, cplane_offset
;
88 uint32_t palette
[260];
89 uint8_t r
[260], g
[260], b
[260];
90 uint16_t width
, height
, depth
;
91 uint8_t dac_index
, dac_state
;
93 uint32_t cursmask
[32];
94 uint32_t cursbits
[32];
99 static void tcx_set_dirty(TCXState
*s
, ram_addr_t addr
, int len
)
101 memory_region_set_dirty(&s
->vram_mem
, addr
, len
);
103 if (s
->depth
== 24) {
104 memory_region_set_dirty(&s
->vram_mem
, s
->vram24_offset
+ addr
* 4,
106 memory_region_set_dirty(&s
->vram_mem
, s
->cplane_offset
+ addr
* 4,
111 static int tcx_check_dirty(TCXState
*s
, DirtyBitmapSnapshot
*snap
,
112 ram_addr_t addr
, int len
)
116 ret
= memory_region_snapshot_get_dirty(&s
->vram_mem
, snap
, addr
, len
);
118 if (s
->depth
== 24) {
119 ret
|= memory_region_snapshot_get_dirty(&s
->vram_mem
, snap
,
120 s
->vram24_offset
+ addr
* 4, len
* 4);
121 ret
|= memory_region_snapshot_get_dirty(&s
->vram_mem
, snap
,
122 s
->cplane_offset
+ addr
* 4, len
* 4);
128 static void update_palette_entries(TCXState
*s
, int start
, int end
)
130 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
133 for (i
= start
; i
< end
; i
++) {
134 if (is_surface_bgr(surface
)) {
135 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
137 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
140 tcx_set_dirty(s
, 0, memory_region_size(&s
->vram_mem
));
143 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
144 const uint8_t *s
, int width
)
148 uint32_t *p
= (uint32_t *)d
;
150 for (x
= 0; x
< width
; x
++) {
152 *p
++ = s1
->palette
[val
];
156 static void tcx_draw_cursor32(TCXState
*s1
, uint8_t *d
,
161 uint32_t *p
= (uint32_t *)d
;
164 mask
= s1
->cursmask
[y
];
165 bits
= s1
->cursbits
[y
];
166 len
= MIN(width
- s1
->cursx
, 32);
168 for (x
= 0; x
< len
; x
++) {
169 if (mask
& 0x80000000) {
170 if (bits
& 0x80000000) {
171 *p
= s1
->palette
[259];
173 *p
= s1
->palette
[258];
183 XXX Could be much more optimal:
184 * detect if line/page/whole screen is in 24 bit mode
185 * if destination is also BGR, use memcpy
187 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
188 const uint8_t *s
, int width
,
189 const uint32_t *cplane
,
192 DisplaySurface
*surface
= qemu_console_surface(s1
->con
);
195 uint32_t *p
= (uint32_t *)d
;
197 bgr
= is_surface_bgr(surface
);
198 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
199 if (be32_to_cpu(*cplane
) & 0x03000000) {
200 /* 24-bit direct, BGR order */
207 dval
= rgb_to_pixel32bgr(r
, g
, b
);
209 dval
= rgb_to_pixel32(r
, g
, b
);
211 /* 8-bit pseudocolor */
213 dval
= s1
->palette
[val
];
220 /* Fixed line length 1024 allows us to do nice tricks not possible on
223 static void tcx_update_display(void *opaque
)
225 TCXState
*ts
= opaque
;
226 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
228 DirtyBitmapSnapshot
*snap
= NULL
;
229 int y
, y_start
, dd
, ds
;
232 if (surface_bits_per_pixel(surface
) != 32) {
238 d
= surface_data(surface
);
240 dd
= surface_stride(surface
);
243 snap
= memory_region_snapshot_and_clear_dirty(&ts
->vram_mem
, 0x0,
244 memory_region_size(&ts
->vram_mem
),
247 for (y
= 0; y
< ts
->height
; y
++, page
+= ds
) {
248 if (tcx_check_dirty(ts
, snap
, page
, ds
)) {
252 tcx_draw_line32(ts
, d
, s
, ts
->width
);
253 if (y
>= ts
->cursy
&& y
< ts
->cursy
+ 32 && ts
->cursx
< ts
->width
) {
254 tcx_draw_cursor32(ts
, d
, y
, ts
->width
);
258 /* flush to display */
259 dpy_gfx_update(ts
->con
, 0, y_start
,
260 ts
->width
, y
- y_start
);
268 /* flush to display */
269 dpy_gfx_update(ts
->con
, 0, y_start
,
270 ts
->width
, y
- y_start
);
275 static void tcx24_update_display(void *opaque
)
277 TCXState
*ts
= opaque
;
278 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
280 DirtyBitmapSnapshot
*snap
= NULL
;
281 int y
, y_start
, dd
, ds
;
283 uint32_t *cptr
, *s24
;
285 if (surface_bits_per_pixel(surface
) != 32) {
291 d
= surface_data(surface
);
295 dd
= surface_stride(surface
);
298 snap
= memory_region_snapshot_and_clear_dirty(&ts
->vram_mem
, 0x0,
299 memory_region_size(&ts
->vram_mem
),
302 for (y
= 0; y
< ts
->height
; y
++, page
+= ds
) {
303 if (tcx_check_dirty(ts
, snap
, page
, ds
)) {
307 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
308 if (y
>= ts
->cursy
&& y
< ts
->cursy
+32 && ts
->cursx
< ts
->width
) {
309 tcx_draw_cursor32(ts
, d
, y
, ts
->width
);
313 /* flush to display */
314 dpy_gfx_update(ts
->con
, 0, y_start
,
315 ts
->width
, y
- y_start
);
325 /* flush to display */
326 dpy_gfx_update(ts
->con
, 0, y_start
,
327 ts
->width
, y
- y_start
);
332 static void tcx_invalidate_display(void *opaque
)
334 TCXState
*s
= opaque
;
336 tcx_set_dirty(s
, 0, memory_region_size(&s
->vram_mem
));
337 qemu_console_resize(s
->con
, s
->width
, s
->height
);
340 static void tcx24_invalidate_display(void *opaque
)
342 TCXState
*s
= opaque
;
344 tcx_set_dirty(s
, 0, memory_region_size(&s
->vram_mem
));
345 qemu_console_resize(s
->con
, s
->width
, s
->height
);
348 static int vmstate_tcx_post_load(void *opaque
, int version_id
)
350 TCXState
*s
= opaque
;
352 update_palette_entries(s
, 0, 256);
353 tcx_set_dirty(s
, 0, memory_region_size(&s
->vram_mem
));
357 static const VMStateDescription vmstate_tcx
= {
360 .minimum_version_id
= 4,
361 .post_load
= vmstate_tcx_post_load
,
362 .fields
= (VMStateField
[]) {
363 VMSTATE_UINT16(height
, TCXState
),
364 VMSTATE_UINT16(width
, TCXState
),
365 VMSTATE_UINT16(depth
, TCXState
),
366 VMSTATE_BUFFER(r
, TCXState
),
367 VMSTATE_BUFFER(g
, TCXState
),
368 VMSTATE_BUFFER(b
, TCXState
),
369 VMSTATE_UINT8(dac_index
, TCXState
),
370 VMSTATE_UINT8(dac_state
, TCXState
),
371 VMSTATE_END_OF_LIST()
375 static void tcx_reset(DeviceState
*d
)
377 TCXState
*s
= TCX(d
);
379 /* Initialize palette */
380 memset(s
->r
, 0, 260);
381 memset(s
->g
, 0, 260);
382 memset(s
->b
, 0, 260);
383 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
384 s
->r
[256] = s
->g
[256] = s
->b
[256] = 255;
385 s
->r
[258] = s
->g
[258] = s
->b
[258] = 255;
386 update_palette_entries(s
, 0, 260);
387 memset(s
->vram
, 0, MAXX
*MAXY
);
388 memory_region_reset_dirty(&s
->vram_mem
, 0, MAXX
* MAXY
* (1 + 4 + 4),
392 s
->cursx
= 0xf000; /* Put cursor off screen */
396 static uint64_t tcx_dac_readl(void *opaque
, hwaddr addr
,
399 TCXState
*s
= opaque
;
402 switch (s
->dac_state
) {
404 val
= s
->r
[s
->dac_index
] << 24;
408 val
= s
->g
[s
->dac_index
] << 24;
412 val
= s
->b
[s
->dac_index
] << 24;
413 s
->dac_index
= (s
->dac_index
+ 1) & 0xff; /* Index autoincrement */
423 static void tcx_dac_writel(void *opaque
, hwaddr addr
, uint64_t val
,
426 TCXState
*s
= opaque
;
430 case 0: /* Address */
431 s
->dac_index
= val
>> 24;
434 case 4: /* Pixel colours */
435 case 12: /* Overlay (cursor) colours */
437 index
= (s
->dac_index
& 3) + 256;
439 index
= s
->dac_index
;
441 switch (s
->dac_state
) {
443 s
->r
[index
] = val
>> 24;
444 update_palette_entries(s
, index
, index
+ 1);
448 s
->g
[index
] = val
>> 24;
449 update_palette_entries(s
, index
, index
+ 1);
453 s
->b
[index
] = val
>> 24;
454 update_palette_entries(s
, index
, index
+ 1);
455 s
->dac_index
= (s
->dac_index
+ 1) & 0xff; /* Index autoincrement */
462 default: /* Control registers */
467 static const MemoryRegionOps tcx_dac_ops
= {
468 .read
= tcx_dac_readl
,
469 .write
= tcx_dac_writel
,
470 .endianness
= DEVICE_NATIVE_ENDIAN
,
472 .min_access_size
= 4,
473 .max_access_size
= 4,
477 static uint64_t tcx_stip_readl(void *opaque
, hwaddr addr
,
483 static void tcx_stip_writel(void *opaque
, hwaddr addr
,
484 uint64_t val
, unsigned size
)
486 TCXState
*s
= opaque
;
493 addr
= (addr
>> 3) & 0xfffff;
494 col
= cpu_to_be32(s
->tmpblit
);
495 if (s
->depth
== 24) {
496 for (i
= 0; i
< 32; i
++) {
497 if (val
& 0x80000000) {
498 s
->vram
[addr
+ i
] = s
->tmpblit
;
499 s
->vram24
[addr
+ i
] = col
;
504 for (i
= 0; i
< 32; i
++) {
505 if (val
& 0x80000000) {
506 s
->vram
[addr
+ i
] = s
->tmpblit
;
511 tcx_set_dirty(s
, addr
, 32);
515 static void tcx_rstip_writel(void *opaque
, hwaddr addr
,
516 uint64_t val
, unsigned size
)
518 TCXState
*s
= opaque
;
525 addr
= (addr
>> 3) & 0xfffff;
526 col
= cpu_to_be32(s
->tmpblit
);
527 if (s
->depth
== 24) {
528 for (i
= 0; i
< 32; i
++) {
529 if (val
& 0x80000000) {
530 s
->vram
[addr
+ i
] = s
->tmpblit
;
531 s
->vram24
[addr
+ i
] = col
;
532 s
->cplane
[addr
+ i
] = col
;
537 for (i
= 0; i
< 32; i
++) {
538 if (val
& 0x80000000) {
539 s
->vram
[addr
+ i
] = s
->tmpblit
;
544 tcx_set_dirty(s
, addr
, 32);
548 static const MemoryRegionOps tcx_stip_ops
= {
549 .read
= tcx_stip_readl
,
550 .write
= tcx_stip_writel
,
551 .endianness
= DEVICE_NATIVE_ENDIAN
,
553 .min_access_size
= 4,
554 .max_access_size
= 4,
557 .min_access_size
= 4,
558 .max_access_size
= 8,
562 static const MemoryRegionOps tcx_rstip_ops
= {
563 .read
= tcx_stip_readl
,
564 .write
= tcx_rstip_writel
,
565 .endianness
= DEVICE_NATIVE_ENDIAN
,
567 .min_access_size
= 4,
568 .max_access_size
= 4,
571 .min_access_size
= 4,
572 .max_access_size
= 8,
576 static uint64_t tcx_blit_readl(void *opaque
, hwaddr addr
,
582 static void tcx_blit_writel(void *opaque
, hwaddr addr
,
583 uint64_t val
, unsigned size
)
585 TCXState
*s
= opaque
;
592 addr
= (addr
>> 3) & 0xfffff;
593 adsr
= val
& 0xffffff;
594 len
= ((val
>> 24) & 0x1f) + 1;
595 if (adsr
== 0xffffff) {
596 memset(&s
->vram
[addr
], s
->tmpblit
, len
);
597 if (s
->depth
== 24) {
598 val
= s
->tmpblit
& 0xffffff;
599 val
= cpu_to_be32(val
);
600 for (i
= 0; i
< len
; i
++) {
601 s
->vram24
[addr
+ i
] = val
;
605 memcpy(&s
->vram
[addr
], &s
->vram
[adsr
], len
);
606 if (s
->depth
== 24) {
607 memcpy(&s
->vram24
[addr
], &s
->vram24
[adsr
], len
* 4);
610 tcx_set_dirty(s
, addr
, len
);
614 static void tcx_rblit_writel(void *opaque
, hwaddr addr
,
615 uint64_t val
, unsigned size
)
617 TCXState
*s
= opaque
;
624 addr
= (addr
>> 3) & 0xfffff;
625 adsr
= val
& 0xffffff;
626 len
= ((val
>> 24) & 0x1f) + 1;
627 if (adsr
== 0xffffff) {
628 memset(&s
->vram
[addr
], s
->tmpblit
, len
);
629 if (s
->depth
== 24) {
630 val
= s
->tmpblit
& 0xffffff;
631 val
= cpu_to_be32(val
);
632 for (i
= 0; i
< len
; i
++) {
633 s
->vram24
[addr
+ i
] = val
;
634 s
->cplane
[addr
+ i
] = val
;
638 memcpy(&s
->vram
[addr
], &s
->vram
[adsr
], len
);
639 if (s
->depth
== 24) {
640 memcpy(&s
->vram24
[addr
], &s
->vram24
[adsr
], len
* 4);
641 memcpy(&s
->cplane
[addr
], &s
->cplane
[adsr
], len
* 4);
644 tcx_set_dirty(s
, addr
, len
);
648 static const MemoryRegionOps tcx_blit_ops
= {
649 .read
= tcx_blit_readl
,
650 .write
= tcx_blit_writel
,
651 .endianness
= DEVICE_NATIVE_ENDIAN
,
653 .min_access_size
= 4,
654 .max_access_size
= 4,
658 static const MemoryRegionOps tcx_rblit_ops
= {
659 .read
= tcx_blit_readl
,
660 .write
= tcx_rblit_writel
,
661 .endianness
= DEVICE_NATIVE_ENDIAN
,
663 .min_access_size
= 4,
664 .max_access_size
= 4,
667 .min_access_size
= 4,
668 .max_access_size
= 8,
672 static void tcx_invalidate_cursor_position(TCXState
*s
)
674 int ymin
, ymax
, start
, end
;
676 /* invalidate only near the cursor */
678 if (ymin
>= s
->height
) {
681 ymax
= MIN(s
->height
, ymin
+ 32);
685 tcx_set_dirty(s
, start
, end
- start
);
688 static uint64_t tcx_thc_readl(void *opaque
, hwaddr addr
,
691 TCXState
*s
= opaque
;
694 if (addr
== TCX_THC_MISC
) {
695 val
= s
->thcmisc
| 0x02000000;
702 static void tcx_thc_writel(void *opaque
, hwaddr addr
,
703 uint64_t val
, unsigned size
)
705 TCXState
*s
= opaque
;
707 if (addr
== TCX_THC_CURSXY
) {
708 tcx_invalidate_cursor_position(s
);
709 s
->cursx
= val
>> 16;
711 tcx_invalidate_cursor_position(s
);
712 } else if (addr
>= TCX_THC_CURSMASK
&& addr
< TCX_THC_CURSMASK
+ 128) {
713 s
->cursmask
[(addr
- TCX_THC_CURSMASK
) >> 2] = val
;
714 tcx_invalidate_cursor_position(s
);
715 } else if (addr
>= TCX_THC_CURSBITS
&& addr
< TCX_THC_CURSBITS
+ 128) {
716 s
->cursbits
[(addr
- TCX_THC_CURSBITS
) >> 2] = val
;
717 tcx_invalidate_cursor_position(s
);
718 } else if (addr
== TCX_THC_MISC
) {
724 static const MemoryRegionOps tcx_thc_ops
= {
725 .read
= tcx_thc_readl
,
726 .write
= tcx_thc_writel
,
727 .endianness
= DEVICE_NATIVE_ENDIAN
,
729 .min_access_size
= 4,
730 .max_access_size
= 4,
734 static uint64_t tcx_dummy_readl(void *opaque
, hwaddr addr
,
740 static void tcx_dummy_writel(void *opaque
, hwaddr addr
,
741 uint64_t val
, unsigned size
)
746 static const MemoryRegionOps tcx_dummy_ops
= {
747 .read
= tcx_dummy_readl
,
748 .write
= tcx_dummy_writel
,
749 .endianness
= DEVICE_NATIVE_ENDIAN
,
751 .min_access_size
= 4,
752 .max_access_size
= 4,
756 static const GraphicHwOps tcx_ops
= {
757 .invalidate
= tcx_invalidate_display
,
758 .gfx_update
= tcx_update_display
,
761 static const GraphicHwOps tcx24_ops
= {
762 .invalidate
= tcx24_invalidate_display
,
763 .gfx_update
= tcx24_update_display
,
766 static void tcx_initfn(Object
*obj
)
768 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
769 TCXState
*s
= TCX(obj
);
771 memory_region_init_rom_nomigrate(&s
->rom
, obj
, "tcx.prom",
772 FCODE_MAX_ROM_SIZE
, &error_fatal
);
773 sysbus_init_mmio(sbd
, &s
->rom
);
775 /* 2/STIP : Stippler */
776 memory_region_init_io(&s
->stip
, obj
, &tcx_stip_ops
, s
, "tcx.stip",
778 sysbus_init_mmio(sbd
, &s
->stip
);
780 /* 3/BLIT : Blitter */
781 memory_region_init_io(&s
->blit
, obj
, &tcx_blit_ops
, s
, "tcx.blit",
783 sysbus_init_mmio(sbd
, &s
->blit
);
785 /* 5/RSTIP : Raw Stippler */
786 memory_region_init_io(&s
->rstip
, obj
, &tcx_rstip_ops
, s
, "tcx.rstip",
788 sysbus_init_mmio(sbd
, &s
->rstip
);
790 /* 6/RBLIT : Raw Blitter */
791 memory_region_init_io(&s
->rblit
, obj
, &tcx_rblit_ops
, s
, "tcx.rblit",
793 sysbus_init_mmio(sbd
, &s
->rblit
);
796 memory_region_init_io(&s
->tec
, obj
, &tcx_dummy_ops
, s
, "tcx.tec",
798 sysbus_init_mmio(sbd
, &s
->tec
);
801 memory_region_init_io(&s
->dac
, obj
, &tcx_dac_ops
, s
, "tcx.dac",
803 sysbus_init_mmio(sbd
, &s
->dac
);
806 memory_region_init_io(&s
->thc
, obj
, &tcx_thc_ops
, s
, "tcx.thc",
808 sysbus_init_mmio(sbd
, &s
->thc
);
811 memory_region_init_io(&s
->dhc
, obj
, &tcx_dummy_ops
, s
, "tcx.dhc",
813 sysbus_init_mmio(sbd
, &s
->dhc
);
816 memory_region_init_io(&s
->alt
, obj
, &tcx_dummy_ops
, s
, "tcx.alt",
818 sysbus_init_mmio(sbd
, &s
->alt
);
821 static void tcx_realizefn(DeviceState
*dev
, Error
**errp
)
823 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
824 TCXState
*s
= TCX(dev
);
825 ram_addr_t vram_offset
= 0;
828 char *fcode_filename
;
830 memory_region_init_ram_nomigrate(&s
->vram_mem
, OBJECT(s
), "tcx.vram",
831 s
->vram_size
* (1 + 4 + 4), &error_fatal
);
832 vmstate_register_ram_global(&s
->vram_mem
);
833 memory_region_set_log(&s
->vram_mem
, true, DIRTY_MEMORY_VGA
);
834 vram_base
= memory_region_get_ram_ptr(&s
->vram_mem
);
836 /* 10/ROM : FCode ROM */
837 vmstate_register_ram_global(&s
->rom
);
838 fcode_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, TCX_ROM_FILE
);
839 if (fcode_filename
) {
840 ret
= load_image_mr(fcode_filename
, &s
->rom
);
841 g_free(fcode_filename
);
842 if (ret
< 0 || ret
> FCODE_MAX_ROM_SIZE
) {
843 warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE
);
847 /* 0/DFB8 : 8-bit plane */
850 memory_region_init_alias(&s
->vram_8bit
, OBJECT(s
), "tcx.vram.8bit",
851 &s
->vram_mem
, vram_offset
, size
);
852 sysbus_init_mmio(sbd
, &s
->vram_8bit
);
856 /* 1/DFB24 : 24bit plane */
857 size
= s
->vram_size
* 4;
858 s
->vram24
= (uint32_t *)vram_base
;
859 s
->vram24_offset
= vram_offset
;
860 memory_region_init_alias(&s
->vram_24bit
, OBJECT(s
), "tcx.vram.24bit",
861 &s
->vram_mem
, vram_offset
, size
);
862 sysbus_init_mmio(sbd
, &s
->vram_24bit
);
866 /* 4/RDFB32 : Raw Framebuffer */
867 size
= s
->vram_size
* 4;
868 s
->cplane
= (uint32_t *)vram_base
;
869 s
->cplane_offset
= vram_offset
;
870 memory_region_init_alias(&s
->vram_cplane
, OBJECT(s
), "tcx.vram.cplane",
871 &s
->vram_mem
, vram_offset
, size
);
872 sysbus_init_mmio(sbd
, &s
->vram_cplane
);
874 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
876 memory_region_init_io(&s
->thc24
, OBJECT(s
), &tcx_dummy_ops
, s
,
877 "tcx.thc24", TCX_THC_NREGS
);
878 sysbus_init_mmio(sbd
, &s
->thc24
);
881 sysbus_init_irq(sbd
, &s
->irq
);
884 s
->con
= graphic_console_init(dev
, 0, &tcx_ops
, s
);
886 s
->con
= graphic_console_init(dev
, 0, &tcx24_ops
, s
);
890 qemu_console_resize(s
->con
, s
->width
, s
->height
);
893 static Property tcx_properties
[] = {
894 DEFINE_PROP_UINT32("vram_size", TCXState
, vram_size
, -1),
895 DEFINE_PROP_UINT16("width", TCXState
, width
, -1),
896 DEFINE_PROP_UINT16("height", TCXState
, height
, -1),
897 DEFINE_PROP_UINT16("depth", TCXState
, depth
, -1),
898 DEFINE_PROP_END_OF_LIST(),
901 static void tcx_class_init(ObjectClass
*klass
, void *data
)
903 DeviceClass
*dc
= DEVICE_CLASS(klass
);
905 dc
->realize
= tcx_realizefn
;
906 dc
->reset
= tcx_reset
;
907 dc
->vmsd
= &vmstate_tcx
;
908 device_class_set_props(dc
, tcx_properties
);
911 static const TypeInfo tcx_info
= {
913 .parent
= TYPE_SYS_BUS_DEVICE
,
914 .instance_size
= sizeof(TCXState
),
915 .instance_init
= tcx_initfn
,
916 .class_init
= tcx_class_init
,
919 static void tcx_register_types(void)
921 type_register_static(&tcx_info
);
924 type_init(tcx_register_types
)