target-i386/smm_helper.c

   1 /*
   2  *  x86 SMM helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22
  23 /* SMM support */
  24
  25 #if defined(CONFIG_USER_ONLY)
  26
  27 void do_smm_enter(X86CPU *cpu)
  28 {
  29 }
  30
  31 void helper_rsm(CPUX86State *env)
  32 {
  33 }
  34
  35 #else
  36
  37 #ifdef TARGET_X86_64
  38 #define SMM_REVISION_ID 0x00020064
  39 #else
  40 #define SMM_REVISION_ID 0x00020000
  41 #endif
  42
  43 void do_smm_enter(X86CPU *cpu)
  44 {
  45     CPUX86State *env = &cpu->env;
  46     CPUState *cs = CPU(cpu);
  47     target_ulong sm_state;
  48     SegmentCache *dt;
  49     int i, offset;
  50
  51     qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
  52     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
  53
  54     env->hflags |= HF_SMM_MASK;
  55     if (env->hflags2 & HF2_NMI_MASK) {
  56         env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
  57     } else {
  58         env->hflags2 |= HF2_NMI_MASK;
  59     }
  60     cpu_smm_update(env);
  61
  62     sm_state = env->smbase + 0x8000;
  63
  64 #ifdef TARGET_X86_64
  65     for (i = 0; i < 6; i++) {
  66         dt = &env->segs[i];
  67         offset = 0x7e00 + i * 16;
  68         x86_stw_phys(cs, sm_state + offset, dt->selector);
  69         x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
  70         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
  71         x86_stq_phys(cs, sm_state + offset + 8, dt->base);
  72     }
  73
  74     x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
  75     x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
  76
  77     x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
  78     x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
  79     x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
  80     x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
  81
  82     x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
  83     x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
  84
  85     x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
  86     x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
  87     x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
  88     x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
  89
  90     x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
  91
  92     x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
  93     x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
  94     x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
  95     x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
  96     x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
  97     x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
  98     x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
  99     x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
 100     for (i = 8; i < 16; i++) {
 101         x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
 102     }
 103     x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
 104     x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
 105     x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
 106     x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
 107
 108     x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
 109     x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
 110     x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
 111
 112     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 113     x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
 114 #else
 115     x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
 116     x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
 117     x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
 118     x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
 119     x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
 120     x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
 121     x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
 122     x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
 123     x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
 124     x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
 125     x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
 126     x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
 127     x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
 128     x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
 129
 130     x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
 131     x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
 132     x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
 133     x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
 134
 135     x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
 136     x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
 137     x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
 138     x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
 139
 140     x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
 141     x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
 142
 143     x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
 144     x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
 145
 146     for (i = 0; i < 6; i++) {
 147         dt = &env->segs[i];
 148         if (i < 3) {
 149             offset = 0x7f84 + i * 12;
 150         } else {
 151             offset = 0x7f2c + (i - 3) * 12;
 152         }
 153         x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
 154         x86_stl_phys(cs, sm_state + offset + 8, dt->base);
 155         x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
 156         x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
 157     }
 158     x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
 159
 160     x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
 161     x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
 162 #endif
 163     /* init SMM cpu state */
 164
 165 #ifdef TARGET_X86_64
 166     cpu_load_efer(env, 0);
 167 #endif
 168     cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
 169                               DF_MASK));
 170     env->eip = 0x00008000;
 171     cpu_x86_update_cr0(env,
 172                        env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
 173                                       CR0_PG_MASK));
 174     cpu_x86_update_cr4(env, 0);
 175     env->dr[7] = 0x00000400;
 176
 177     cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
 178                            0xffffffff,
 179                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 180                            DESC_G_MASK | DESC_A_MASK);
 181     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
 182                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 183                            DESC_G_MASK | DESC_A_MASK);
 184     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
 185                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 186                            DESC_G_MASK | DESC_A_MASK);
 187     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
 188                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 189                            DESC_G_MASK | DESC_A_MASK);
 190     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
 191                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 192                            DESC_G_MASK | DESC_A_MASK);
 193     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
 194                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 195                            DESC_G_MASK | DESC_A_MASK);
 196 }
 197
 198 void helper_rsm(CPUX86State *env)
 199 {
 200     X86CPU *cpu = x86_env_get_cpu(env);
 201     CPUState *cs = CPU(cpu);
 202     target_ulong sm_state;
 203     int i, offset;
 204     uint32_t val;
 205
 206     sm_state = env->smbase + 0x8000;
 207 #ifdef TARGET_X86_64
 208     cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
 209
 210     env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
 211     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
 212
 213     env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
 214     env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
 215     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
 216     env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
 217
 218     env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
 219     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
 220
 221     env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
 222     env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
 223     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
 224     env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
 225
 226     env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
 227     env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
 228     env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
 229     env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
 230     env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
 231     env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
 232     env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
 233     env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
 234     for (i = 8; i < 16; i++) {
 235         env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
 236     }
 237     env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
 238     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
 239                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 240     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
 241     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
 242
 243     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
 244     cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
 245     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
 246
 247     for (i = 0; i < 6; i++) {
 248         offset = 0x7e00 + i * 16;
 249         cpu_x86_load_seg_cache(env, i,
 250                                x86_lduw_phys(cs, sm_state + offset),
 251                                x86_ldq_phys(cs, sm_state + offset + 8),
 252                                x86_ldl_phys(cs, sm_state + offset + 4),
 253                                (x86_lduw_phys(cs, sm_state + offset + 2) &
 254                                 0xf0ff) << 8);
 255     }
 256
 257     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 258     if (val & 0x20000) {
 259         env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff;
 260     }
 261 #else
 262     cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
 263     cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
 264     cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
 265                     ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
 266     env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
 267     env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
 268     env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
 269     env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
 270     env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
 271     env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
 272     env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
 273     env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
 274     env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
 275     env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
 276     env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
 277
 278     env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
 279     env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
 280     env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
 281     env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
 282
 283     env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
 284     env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
 285     env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
 286     env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
 287
 288     env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
 289     env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
 290
 291     env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
 292     env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
 293
 294     for (i = 0; i < 6; i++) {
 295         if (i < 3) {
 296             offset = 0x7f84 + i * 12;
 297         } else {
 298             offset = 0x7f2c + (i - 3) * 12;
 299         }
 300         cpu_x86_load_seg_cache(env, i,
 301                                x86_ldl_phys(cs,
 302                                         sm_state + 0x7fa8 + i * 4) & 0xffff,
 303                                x86_ldl_phys(cs, sm_state + offset + 8),
 304                                x86_ldl_phys(cs, sm_state + offset + 4),
 305                                (x86_ldl_phys(cs,
 306                                          sm_state + offset) & 0xf0ff) << 8);
 307     }
 308     cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
 309
 310     val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
 311     if (val & 0x20000) {
 312         env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff;
 313     }
 314 #endif
 315     if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
 316         env->hflags2 &= ~HF2_NMI_MASK;
 317     }
 318     env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
 319     env->hflags &= ~HF_SMM_MASK;
 320     cpu_smm_update(env);
 321
 322     qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
 323     log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
 324 }
 325
 326 #endif /* !CONFIG_USER_ONLY */