hw/i386/kvmvapic.c

   1 /*
   2  * TPR optimization for 32-bit Windows guests (XP and Server 2003)
   3  *
   4  * Copyright (C) 2007-2008 Qumranet Technologies
   5  * Copyright (C) 2012      Jan Kiszka, Siemens AG
   6  *
   7  * This work is licensed under the terms of the GNU GPL version 2, or
   8  * (at your option) any later version. See the COPYING file in the
   9  * top-level directory.
  10  */
  11 #include "qemu/osdep.h"
  12 #include "qemu-common.h"
  13 #include "cpu.h"
  14 #include "exec/exec-all.h"
  15 #include "sysemu/sysemu.h"
  16 #include "sysemu/cpus.h"
  17 #include "sysemu/kvm.h"
  18 #include "hw/i386/apic_internal.h"
  19 #include "hw/sysbus.h"
  20 #include "tcg/tcg.h"
  21
  22 #define VAPIC_IO_PORT           0x7e
  23
  24 #define VAPIC_CPU_SHIFT         7
  25
  26 #define ROM_BLOCK_SIZE          512
  27 #define ROM_BLOCK_MASK          (~(ROM_BLOCK_SIZE - 1))
  28
  29 typedef enum VAPICMode {
  30     VAPIC_INACTIVE = 0,
  31     VAPIC_ACTIVE   = 1,
  32     VAPIC_STANDBY  = 2,
  33 } VAPICMode;
  34
  35 typedef struct VAPICHandlers {
  36     uint32_t set_tpr;
  37     uint32_t set_tpr_eax;
  38     uint32_t get_tpr[8];
  39     uint32_t get_tpr_stack;
  40 } QEMU_PACKED VAPICHandlers;
  41
  42 typedef struct GuestROMState {
  43     char signature[8];
  44     uint32_t vaddr;
  45     uint32_t fixup_start;
  46     uint32_t fixup_end;
  47     uint32_t vapic_vaddr;
  48     uint32_t vapic_size;
  49     uint32_t vcpu_shift;
  50     uint32_t real_tpr_addr;
  51     VAPICHandlers up;
  52     VAPICHandlers mp;
  53 } QEMU_PACKED GuestROMState;
  54
  55 typedef struct VAPICROMState {
  56     SysBusDevice busdev;
  57     MemoryRegion io;
  58     MemoryRegion rom;
  59     uint32_t state;
  60     uint32_t rom_state_paddr;
  61     uint32_t rom_state_vaddr;
  62     uint32_t vapic_paddr;
  63     uint32_t real_tpr_addr;
  64     GuestROMState rom_state;
  65     size_t rom_size;
  66     bool rom_mapped_writable;
  67     VMChangeStateEntry *vmsentry;
  68 } VAPICROMState;
  69
  70 #define TYPE_VAPIC "kvmvapic"
  71 #define VAPIC(obj) OBJECT_CHECK(VAPICROMState, (obj), TYPE_VAPIC)
  72
  73 #define TPR_INSTR_ABS_MODRM             0x1
  74 #define TPR_INSTR_MATCH_MODRM_REG       0x2
  75
  76 typedef struct TPRInstruction {
  77     uint8_t opcode;
  78     uint8_t modrm_reg;
  79     unsigned int flags;
  80     TPRAccess access;
  81     size_t length;
  82     off_t addr_offset;
  83 } TPRInstruction;
  84
  85 /* must be sorted by length, shortest first */
  86 static const TPRInstruction tpr_instr[] = {
  87     { /* mov abs to eax */
  88         .opcode = 0xa1,
  89         .access = TPR_ACCESS_READ,
  90         .length = 5,
  91         .addr_offset = 1,
  92     },
  93     { /* mov eax to abs */
  94         .opcode = 0xa3,
  95         .access = TPR_ACCESS_WRITE,
  96         .length = 5,
  97         .addr_offset = 1,
  98     },
  99     { /* mov r32 to r/m32 */
 100         .opcode = 0x89,
 101         .flags = TPR_INSTR_ABS_MODRM,
 102         .access = TPR_ACCESS_WRITE,
 103         .length = 6,
 104         .addr_offset = 2,
 105     },
 106     { /* mov r/m32 to r32 */
 107         .opcode = 0x8b,
 108         .flags = TPR_INSTR_ABS_MODRM,
 109         .access = TPR_ACCESS_READ,
 110         .length = 6,
 111         .addr_offset = 2,
 112     },
 113     { /* push r/m32 */
 114         .opcode = 0xff,
 115         .modrm_reg = 6,
 116         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 117         .access = TPR_ACCESS_READ,
 118         .length = 6,
 119         .addr_offset = 2,
 120     },
 121     { /* mov imm32, r/m32 (c7/0) */
 122         .opcode = 0xc7,
 123         .modrm_reg = 0,
 124         .flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
 125         .access = TPR_ACCESS_WRITE,
 126         .length = 10,
 127         .addr_offset = 2,
 128     },
 129 };
 130
 131 static void read_guest_rom_state(VAPICROMState *s)
 132 {
 133     cpu_physical_memory_read(s->rom_state_paddr, &s->rom_state,
 134                              sizeof(GuestROMState));
 135 }
 136
 137 static void write_guest_rom_state(VAPICROMState *s)
 138 {
 139     cpu_physical_memory_write(s->rom_state_paddr, &s->rom_state,
 140                               sizeof(GuestROMState));
 141 }
 142
 143 static void update_guest_rom_state(VAPICROMState *s)
 144 {
 145     read_guest_rom_state(s);
 146
 147     s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
 148     s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
 149
 150     write_guest_rom_state(s);
 151 }
 152
 153 static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
 154 {
 155     CPUState *cs = CPU(x86_env_get_cpu(env));
 156     hwaddr paddr;
 157     target_ulong addr;
 158
 159     if (s->state == VAPIC_ACTIVE) {
 160         return 0;
 161     }
 162     /*
 163      * If there is no prior TPR access instruction we could analyze (which is
 164      * the case after resume from hibernation), we need to scan the possible
 165      * virtual address space for the APIC mapping.
 166      */
 167     for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
 168         paddr = cpu_get_phys_page_debug(cs, addr);
 169         if (paddr != APIC_DEFAULT_ADDRESS) {
 170             continue;
 171         }
 172         s->real_tpr_addr = addr + 0x80;
 173         update_guest_rom_state(s);
 174         return 0;
 175     }
 176     return -1;
 177 }
 178
 179 static uint8_t modrm_reg(uint8_t modrm)
 180 {
 181     return (modrm >> 3) & 7;
 182 }
 183
 184 static bool is_abs_modrm(uint8_t modrm)
 185 {
 186     return (modrm & 0xc7) == 0x05;
 187 }
 188
 189 static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
 190 {
 191     return opcode[0] == instr->opcode &&
 192         (!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
 193         (!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
 194          modrm_reg(opcode[1]) == instr->modrm_reg);
 195 }
 196
 197 static int evaluate_tpr_instruction(VAPICROMState *s, X86CPU *cpu,
 198                                     target_ulong *pip, TPRAccess access)
 199 {
 200     CPUState *cs = CPU(cpu);
 201     const TPRInstruction *instr;
 202     target_ulong ip = *pip;
 203     uint8_t opcode[2];
 204     uint32_t real_tpr_addr;
 205     int i;
 206
 207     if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
 208         (ip & 0xf0000000ULL) != 0xe0000000ULL) {
 209         return -1;
 210     }
 211
 212     /*
 213      * Early Windows 2003 SMP initialization contains a
 214      *
 215      *   mov imm32, r/m32
 216      *
 217      * instruction that is patched by TPR optimization. The problem is that
 218      * RSP, used by the patched instruction, is zero, so the guest gets a
 219      * double fault and dies.
 220      */
 221     if (cpu->env.regs[R_ESP] == 0) {
 222         return -1;
 223     }
 224
 225     if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
 226         /*
 227          * KVM without kernel-based TPR access reporting will pass an IP that
 228          * points after the accessing instruction. So we need to look backward
 229          * to find the reason.
 230          */
 231         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 232             instr = &tpr_instr[i];
 233             if (instr->access != access) {
 234                 continue;
 235             }
 236             if (cpu_memory_rw_debug(cs, ip - instr->length, opcode,
 237                                     sizeof(opcode), 0) < 0) {
 238                 return -1;
 239             }
 240             if (opcode_matches(opcode, instr)) {
 241                 ip -= instr->length;
 242                 goto instruction_ok;
 243             }
 244         }
 245         return -1;
 246     } else {
 247         if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) {
 248             return -1;
 249         }
 250         for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
 251             instr = &tpr_instr[i];
 252             if (opcode_matches(opcode, instr)) {
 253                 goto instruction_ok;
 254             }
 255         }
 256         return -1;
 257     }
 258
 259 instruction_ok:
 260     /*
 261      * Grab the virtual TPR address from the instruction
 262      * and update the cached values.
 263      */
 264     if (cpu_memory_rw_debug(cs, ip + instr->addr_offset,
 265                             (void *)&real_tpr_addr,
 266                             sizeof(real_tpr_addr), 0) < 0) {
 267         return -1;
 268     }
 269     real_tpr_addr = le32_to_cpu(real_tpr_addr);
 270     if ((real_tpr_addr & 0xfff) != 0x80) {
 271         return -1;
 272     }
 273     s->real_tpr_addr = real_tpr_addr;
 274     update_guest_rom_state(s);
 275
 276     *pip = ip;
 277     return 0;
 278 }
 279
 280 static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
 281 {
 282     CPUState *cs = CPU(x86_env_get_cpu(env));
 283     hwaddr paddr;
 284     uint32_t rom_state_vaddr;
 285     uint32_t pos, patch, offset;
 286
 287     /* nothing to do if already activated */
 288     if (s->state == VAPIC_ACTIVE) {
 289         return 0;
 290     }
 291
 292     /* bail out if ROM init code was not executed (missing ROM?) */
 293     if (s->state == VAPIC_INACTIVE) {
 294         return -1;
 295     }
 296
 297     /* find out virtual address of the ROM */
 298     rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
 299     paddr = cpu_get_phys_page_debug(cs, rom_state_vaddr);
 300     if (paddr == -1) {
 301         return -1;
 302     }
 303     paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
 304     if (paddr != s->rom_state_paddr) {
 305         return -1;
 306     }
 307     read_guest_rom_state(s);
 308     if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
 309         return -1;
 310     }
 311     s->rom_state_vaddr = rom_state_vaddr;
 312
 313     /* fixup addresses in ROM if needed */
 314     if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
 315         return 0;
 316     }
 317     for (pos = le32_to_cpu(s->rom_state.fixup_start);
 318          pos < le32_to_cpu(s->rom_state.fixup_end);
 319          pos += 4) {
 320         cpu_physical_memory_read(paddr + pos - s->rom_state.vaddr,
 321                                  &offset, sizeof(offset));
 322         offset = le32_to_cpu(offset);
 323         cpu_physical_memory_read(paddr + offset, &patch, sizeof(patch));
 324         patch = le32_to_cpu(patch);
 325         patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
 326         patch = cpu_to_le32(patch);
 327         cpu_physical_memory_write(paddr + offset, &patch, sizeof(patch));
 328     }
 329     read_guest_rom_state(s);
 330     s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
 331         le32_to_cpu(s->rom_state.vaddr);
 332
 333     return 0;
 334 }
 335
 336 /*
 337  * Tries to read the unique processor number from the Kernel Processor Control
 338  * Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
 339  * cannot be accessed or is considered invalid. This also ensures that we are
 340  * not patching the wrong guest.
 341  */
 342 static int get_kpcr_number(X86CPU *cpu)
 343 {
 344     CPUX86State *env = &cpu->env;
 345     struct kpcr {
 346         uint8_t  fill1[0x1c];
 347         uint32_t self;
 348         uint8_t  fill2[0x31];
 349         uint8_t  number;
 350     } QEMU_PACKED kpcr;
 351
 352     if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base,
 353                             (void *)&kpcr, sizeof(kpcr), 0) < 0 ||
 354         kpcr.self != env->segs[R_FS].base) {
 355         return -1;
 356     }
 357     return kpcr.number;
 358 }
 359
 360 static int vapic_enable(VAPICROMState *s, X86CPU *cpu)
 361 {
 362     int cpu_number = get_kpcr_number(cpu);
 363     hwaddr vapic_paddr;
 364     static const uint8_t enabled = 1;
 365
 366     if (cpu_number < 0) {
 367         return -1;
 368     }
 369     vapic_paddr = s->vapic_paddr +
 370         (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
 371     cpu_physical_memory_write(vapic_paddr + offsetof(VAPICState, enabled),
 372                               &enabled, sizeof(enabled));
 373     apic_enable_vapic(cpu->apic_state, vapic_paddr);
 374
 375     s->state = VAPIC_ACTIVE;
 376
 377     return 0;
 378 }
 379
 380 static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte)
 381 {
 382     cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1);
 383 }
 384
 385 static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
 386                        uint32_t target)
 387 {
 388     uint32_t offset;
 389
 390     offset = cpu_to_le32(target - ip - 5);
 391     patch_byte(cpu, ip, 0xe8); /* call near */
 392     cpu_memory_rw_debug(CPU(cpu), ip + 1, (void *)&offset, sizeof(offset), 1);
 393 }
 394
 395 static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
 396 {
 397     CPUState *cs = CPU(cpu);
 398     CPUX86State *env = &cpu->env;
 399     VAPICHandlers *handlers;
 400     uint8_t opcode[2];
 401     uint32_t imm32 = 0;
 402     target_ulong current_pc = 0;
 403     target_ulong current_cs_base = 0;
 404     uint32_t current_flags = 0;
 405
 406     if (smp_cpus == 1) {
 407         handlers = &s->rom_state.up;
 408     } else {
 409         handlers = &s->rom_state.mp;
 410     }
 411
 412     if (!kvm_enabled()) {
 413         cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
 414                              &current_flags);
 415     }
 416
 417     pause_all_vcpus();
 418
 419     cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0);
 420
 421     switch (opcode[0]) {
 422     case 0x89: /* mov r32 to r/m32 */
 423         patch_byte(cpu, ip, 0x50 + modrm_reg(opcode[1]));  /* push reg */
 424         patch_call(s, cpu, ip + 1, handlers->set_tpr);
 425         break;
 426     case 0x8b: /* mov r/m32 to r32 */
 427         patch_byte(cpu, ip, 0x90);
 428         patch_call(s, cpu, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
 429         break;
 430     case 0xa1: /* mov abs to eax */
 431         patch_call(s, cpu, ip, handlers->get_tpr[0]);
 432         break;
 433     case 0xa3: /* mov eax to abs */
 434         patch_call(s, cpu, ip, handlers->set_tpr_eax);
 435         break;
 436     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 437         patch_byte(cpu, ip, 0x68);  /* push imm32 */
 438         cpu_memory_rw_debug(cs, ip + 6, (void *)&imm32, sizeof(imm32), 0);
 439         cpu_memory_rw_debug(cs, ip + 1, (void *)&imm32, sizeof(imm32), 1);
 440         patch_call(s, cpu, ip + 5, handlers->set_tpr);
 441         break;
 442     case 0xff: /* push r/m32 */
 443         patch_byte(cpu, ip, 0x50); /* push eax */
 444         patch_call(s, cpu, ip + 1, handlers->get_tpr_stack);
 445         break;
 446     default:
 447         abort();
 448     }
 449
 450     resume_all_vcpus();
 451
 452     if (!kvm_enabled()) {
 453         /* tb_lock will be reset when cpu_loop_exit_noexc longjmps
 454          * back into the cpu_exec loop. */
 455         tb_lock();
 456         tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
 457         cpu_loop_exit_noexc(cs);
 458     }
 459 }
 460
 461 void vapic_report_tpr_access(DeviceState *dev, CPUState *cs, target_ulong ip,
 462                              TPRAccess access)
 463 {
 464     VAPICROMState *s = VAPIC(dev);
 465     X86CPU *cpu = X86_CPU(cs);
 466     CPUX86State *env = &cpu->env;
 467
 468     cpu_synchronize_state(cs);
 469
 470     if (evaluate_tpr_instruction(s, cpu, &ip, access) < 0) {
 471         if (s->state == VAPIC_ACTIVE) {
 472             vapic_enable(s, cpu);
 473         }
 474         return;
 475     }
 476     if (update_rom_mapping(s, env, ip) < 0) {
 477         return;
 478     }
 479     if (vapic_enable(s, cpu) < 0) {
 480         return;
 481     }
 482     patch_instruction(s, cpu, ip);
 483 }
 484
 485 typedef struct VAPICEnableTPRReporting {
 486     DeviceState *apic;
 487     bool enable;
 488 } VAPICEnableTPRReporting;
 489
 490 static void vapic_do_enable_tpr_reporting(CPUState *cpu, run_on_cpu_data data)
 491 {
 492     VAPICEnableTPRReporting *info = data.host_ptr;
 493     apic_enable_tpr_access_reporting(info->apic, info->enable);
 494 }
 495
 496 static void vapic_enable_tpr_reporting(bool enable)
 497 {
 498     VAPICEnableTPRReporting info = {
 499         .enable = enable,
 500     };
 501     CPUState *cs;
 502     X86CPU *cpu;
 503
 504     CPU_FOREACH(cs) {
 505         cpu = X86_CPU(cs);
 506         info.apic = cpu->apic_state;
 507         run_on_cpu(cs, vapic_do_enable_tpr_reporting, RUN_ON_CPU_HOST_PTR(&info));
 508     }
 509 }
 510
 511 static void vapic_reset(DeviceState *dev)
 512 {
 513     VAPICROMState *s = VAPIC(dev);
 514
 515     s->state = VAPIC_INACTIVE;
 516     s->rom_state_paddr = 0;
 517     vapic_enable_tpr_reporting(false);
 518 }
 519
 520 /*
 521  * Set the IRQ polling hypercalls to the supported variant:
 522  *  - vmcall if using KVM in-kernel irqchip
 523  *  - 32-bit VAPIC port write otherwise
 524  */
 525 static int patch_hypercalls(VAPICROMState *s)
 526 {
 527     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 528     static const uint8_t vmcall_pattern[] = { /* vmcall */
 529         0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
 530     };
 531     static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
 532         0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
 533     };
 534     uint8_t alternates[2];
 535     const uint8_t *pattern;
 536     const uint8_t *patch;
 537     int patches = 0;
 538     off_t pos;
 539     uint8_t *rom;
 540
 541     rom = g_malloc(s->rom_size);
 542     cpu_physical_memory_read(rom_paddr, rom, s->rom_size);
 543
 544     for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
 545         if (kvm_irqchip_in_kernel()) {
 546             pattern = outl_pattern;
 547             alternates[0] = outl_pattern[7];
 548             alternates[1] = outl_pattern[7];
 549             patch = &vmcall_pattern[5];
 550         } else {
 551             pattern = vmcall_pattern;
 552             alternates[0] = vmcall_pattern[7];
 553             alternates[1] = 0xd9; /* AMD's VMMCALL */
 554             patch = &outl_pattern[5];
 555         }
 556         if (memcmp(rom + pos, pattern, 7) == 0 &&
 557             (rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
 558             cpu_physical_memory_write(rom_paddr + pos + 5, patch, 3);
 559             /*
 560              * Don't flush the tb here. Under ordinary conditions, the patched
 561              * calls are miles away from the current IP. Under malicious
 562              * conditions, the guest could trick us to crash.
 563              */
 564         }
 565     }
 566
 567     g_free(rom);
 568
 569     if (patches != 0 && patches != 2) {
 570         return -1;
 571     }
 572
 573     return 0;
 574 }
 575
 576 /*
 577  * For TCG mode or the time KVM honors read-only memory regions, we need to
 578  * enable write access to the option ROM so that variables can be updated by
 579  * the guest.
 580  */
 581 static int vapic_map_rom_writable(VAPICROMState *s)
 582 {
 583     hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
 584     MemoryRegionSection section;
 585     MemoryRegion *as;
 586     size_t rom_size;
 587     uint8_t *ram;
 588
 589     as = sysbus_address_space(&s->busdev);
 590
 591     if (s->rom_mapped_writable) {
 592         memory_region_del_subregion(as, &s->rom);
 593         object_unparent(OBJECT(&s->rom));
 594     }
 595
 596     /* grab RAM memory region (region @rom_paddr may still be pc.rom) */
 597     section = memory_region_find(as, 0, 1);
 598
 599     /* read ROM size from RAM region */
 600     if (rom_paddr + 2 >= memory_region_size(section.mr)) {
 601         return -1;
 602     }
 603     ram = memory_region_get_ram_ptr(section.mr);
 604     rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
 605     if (rom_size == 0) {
 606         return -1;
 607     }
 608     s->rom_size = rom_size;
 609
 610     /* We need to round to avoid creating subpages
 611      * from which we cannot run code. */
 612     rom_size += rom_paddr & ~TARGET_PAGE_MASK;
 613     rom_paddr &= TARGET_PAGE_MASK;
 614     rom_size = TARGET_PAGE_ALIGN(rom_size);
 615
 616     memory_region_init_alias(&s->rom, OBJECT(s), "kvmvapic-rom", section.mr,
 617                              rom_paddr, rom_size);
 618     memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
 619     s->rom_mapped_writable = true;
 620     memory_region_unref(section.mr);
 621
 622     return 0;
 623 }
 624
 625 static int vapic_prepare(VAPICROMState *s)
 626 {
 627     if (vapic_map_rom_writable(s) < 0) {
 628         return -1;
 629     }
 630
 631     if (patch_hypercalls(s) < 0) {
 632         return -1;
 633     }
 634
 635     vapic_enable_tpr_reporting(true);
 636
 637     return 0;
 638 }
 639
 640 static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
 641                         unsigned int size)
 642 {
 643     VAPICROMState *s = opaque;
 644     X86CPU *cpu;
 645     CPUX86State *env;
 646     hwaddr rom_paddr;
 647
 648     if (!current_cpu) {
 649         return;
 650     }
 651
 652     cpu_synchronize_state(current_cpu);
 653     cpu = X86_CPU(current_cpu);
 654     env = &cpu->env;
 655
 656     /*
 657      * The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
 658      *  o 16-bit write access:
 659      *    Reports the option ROM initialization to the hypervisor. Written
 660      *    value is the offset of the state structure in the ROM.
 661      *  o 8-bit write access:
 662      *    Reactivates the VAPIC after a guest hibernation, i.e. after the
 663      *    option ROM content has been re-initialized by a guest power cycle.
 664      *  o 32-bit write access:
 665      *    Poll for pending IRQs, considering the current VAPIC state.
 666      */
 667     switch (size) {
 668     case 2:
 669         if (s->state == VAPIC_INACTIVE) {
 670             rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
 671             s->rom_state_paddr = rom_paddr + data;
 672
 673             s->state = VAPIC_STANDBY;
 674         }
 675         if (vapic_prepare(s) < 0) {
 676             s->state = VAPIC_INACTIVE;
 677             s->rom_state_paddr = 0;
 678             break;
 679         }
 680         break;
 681     case 1:
 682         if (kvm_enabled()) {
 683             /*
 684              * Disable triggering instruction in ROM by writing a NOP.
 685              *
 686              * We cannot do this in TCG mode as the reported IP is not
 687              * accurate.
 688              */
 689             pause_all_vcpus();
 690             patch_byte(cpu, env->eip - 2, 0x66);
 691             patch_byte(cpu, env->eip - 1, 0x90);
 692             resume_all_vcpus();
 693         }
 694
 695         if (s->state == VAPIC_ACTIVE) {
 696             break;
 697         }
 698         if (update_rom_mapping(s, env, env->eip) < 0) {
 699             break;
 700         }
 701         if (find_real_tpr_addr(s, env) < 0) {
 702             break;
 703         }
 704         vapic_enable(s, cpu);
 705         break;
 706     default:
 707     case 4:
 708         if (!kvm_irqchip_in_kernel()) {
 709             apic_poll_irq(cpu->apic_state);
 710         }
 711         break;
 712     }
 713 }
 714
 715 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
 716 {
 717     return 0xffffffff;
 718 }
 719
 720 static const MemoryRegionOps vapic_ops = {
 721     .write = vapic_write,
 722     .read = vapic_read,
 723     .endianness = DEVICE_NATIVE_ENDIAN,
 724 };
 725
 726 static void vapic_realize(DeviceState *dev, Error **errp)
 727 {
 728     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 729     VAPICROMState *s = VAPIC(dev);
 730
 731     memory_region_init_io(&s->io, OBJECT(s), &vapic_ops, s, "kvmvapic", 2);
 732     sysbus_add_io(sbd, VAPIC_IO_PORT, &s->io);
 733     sysbus_init_ioports(sbd, VAPIC_IO_PORT, 2);
 734
 735     option_rom[nb_option_roms].name = "kvmvapic.bin";
 736     option_rom[nb_option_roms].bootindex = -1;
 737     nb_option_roms++;
 738 }
 739
 740 static void do_vapic_enable(CPUState *cs, run_on_cpu_data data)
 741 {
 742     VAPICROMState *s = data.host_ptr;
 743     X86CPU *cpu = X86_CPU(cs);
 744
 745     static const uint8_t enabled = 1;
 746     cpu_physical_memory_write(s->vapic_paddr + offsetof(VAPICState, enabled),
 747                               &enabled, sizeof(enabled));
 748     apic_enable_vapic(cpu->apic_state, s->vapic_paddr);
 749     s->state = VAPIC_ACTIVE;
 750 }
 751
 752 static void kvmvapic_vm_state_change(void *opaque, int running,
 753                                      RunState state)
 754 {
 755     VAPICROMState *s = opaque;
 756     uint8_t *zero;
 757
 758     if (!running) {
 759         return;
 760     }
 761
 762     if (s->state == VAPIC_ACTIVE) {
 763         if (smp_cpus == 1) {
 764             run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s));
 765         } else {
 766             zero = g_malloc0(s->rom_state.vapic_size);
 767             cpu_physical_memory_write(s->vapic_paddr, zero,
 768                                       s->rom_state.vapic_size);
 769             g_free(zero);
 770         }
 771     }
 772
 773     qemu_del_vm_change_state_handler(s->vmsentry);
 774     s->vmsentry = NULL;
 775 }
 776
 777 static int vapic_post_load(void *opaque, int version_id)
 778 {
 779     VAPICROMState *s = opaque;
 780
 781     /*
 782      * The old implementation of qemu-kvm did not provide the state
 783      * VAPIC_STANDBY. Reconstruct it.
 784      */
 785     if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
 786         s->state = VAPIC_STANDBY;
 787     }
 788
 789     if (s->state != VAPIC_INACTIVE) {
 790         if (vapic_prepare(s) < 0) {
 791             return -1;
 792         }
 793     }
 794
 795     if (!s->vmsentry) {
 796         s->vmsentry =
 797             qemu_add_vm_change_state_handler(kvmvapic_vm_state_change, s);
 798     }
 799     return 0;
 800 }
 801
 802 static const VMStateDescription vmstate_handlers = {
 803     .name = "kvmvapic-handlers",
 804     .version_id = 1,
 805     .minimum_version_id = 1,
 806     .fields = (VMStateField[]) {
 807         VMSTATE_UINT32(set_tpr, VAPICHandlers),
 808         VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
 809         VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
 810         VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
 811         VMSTATE_END_OF_LIST()
 812     }
 813 };
 814
 815 static const VMStateDescription vmstate_guest_rom = {
 816     .name = "kvmvapic-guest-rom",
 817     .version_id = 1,
 818     .minimum_version_id = 1,
 819     .fields = (VMStateField[]) {
 820         VMSTATE_UNUSED(8),     /* signature */
 821         VMSTATE_UINT32(vaddr, GuestROMState),
 822         VMSTATE_UINT32(fixup_start, GuestROMState),
 823         VMSTATE_UINT32(fixup_end, GuestROMState),
 824         VMSTATE_UINT32(vapic_vaddr, GuestROMState),
 825         VMSTATE_UINT32(vapic_size, GuestROMState),
 826         VMSTATE_UINT32(vcpu_shift, GuestROMState),
 827         VMSTATE_UINT32(real_tpr_addr, GuestROMState),
 828         VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 829         VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
 830         VMSTATE_END_OF_LIST()
 831     }
 832 };
 833
 834 static const VMStateDescription vmstate_vapic = {
 835     .name = "kvm-tpr-opt",      /* compatible with qemu-kvm VAPIC */
 836     .version_id = 1,
 837     .minimum_version_id = 1,
 838     .post_load = vapic_post_load,
 839     .fields = (VMStateField[]) {
 840         VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
 841                        GuestROMState),
 842         VMSTATE_UINT32(state, VAPICROMState),
 843         VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
 844         VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
 845         VMSTATE_UINT32(vapic_paddr, VAPICROMState),
 846         VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
 847         VMSTATE_END_OF_LIST()
 848     }
 849 };
 850
 851 static void vapic_class_init(ObjectClass *klass, void *data)
 852 {
 853     DeviceClass *dc = DEVICE_CLASS(klass);
 854
 855     dc->reset   = vapic_reset;
 856     dc->vmsd    = &vmstate_vapic;
 857     dc->realize = vapic_realize;
 858 }
 859
 860 static const TypeInfo vapic_type = {
 861     .name          = TYPE_VAPIC,
 862     .parent        = TYPE_SYS_BUS_DEVICE,
 863     .instance_size = sizeof(VAPICROMState),
 864     .class_init    = vapic_class_init,
 865 };
 866
 867 static void vapic_register(void)
 868 {
 869     type_register_static(&vapic_type);
 870 }
 871
 872 type_init(vapic_register);