?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210330' into...
[qemu/ar7.git] / hw / sh4 / sh7750_regs.h
blobab073dadc74c0d644fc3d2686c4d1652483b1341
1 /*
2 * SH-7750 memory-mapped registers
3 * This file based on information provided in the following document:
4 * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S)
5 * Hardware Manual"
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
7 *
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
9 * Author: Alexandra Kossovsky <sasha@oktet.ru>
10 * Victor V. Vengerov <vvv@oktet.ru>
11 *
12 * The license and distribution terms for this file may be
13 * found in this file hereafter or at http://www.rtems.com/license/LICENSE.
14 *
15 * LICENSE INFORMATION
16 *
17 * RTEMS is free software; you can redistribute it and/or modify it under
18 * terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
20 * later version. RTEMS is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details. You should have received
24 * a copy of the GNU General Public License along with RTEMS; see
25 * file COPYING. If not, write to the Free Software Foundation, 675
26 * Mass Ave, Cambridge, MA 02139, USA.
27 *
28 * As a special exception, including RTEMS header files in a file,
29 * instantiating RTEMS generics or templates, or linking other files
30 * with RTEMS objects to produce an executable application, does not
31 * by itself cause the resulting executable application to be covered
32 * by the GNU General Public License. This exception does not
33 * however invalidate any other reasons why the executable file might be
34 * covered by the GNU Public License.
35 *
36 * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
37 */
38
39 #ifndef SH7750_REGS_H
40 #define SH7750_REGS_H
41
42 /*
43 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
44 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 */
46 #define SH7750_P4_BASE 0xff000000 /* Accessible only in
47 privileged mode */
48 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
49
50 #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
51 #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
52
53 /*
54 * MMU Registers
55 */
56
57 /* Page Table Entry High register - PTEH */
58 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS)
60 #define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS)
61 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
62 #define SH7750_PTEH_VPN_S 10
63 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
64 #define SH7750_PTEH_ASID_S 0
65
66 /* Page Table Entry Low register - PTEL */
67 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS)
69 #define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS)
70 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
71 #define SH7750_PTEL_PPN_S 10
72 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */
74 #define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */
75 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
76 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
77 #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */
78 #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */
79 #define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */
80 #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */
81 #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
82 #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode */
83 #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode */
84 #define SH7750_PTEL_C 0x00000008 /* Cacheability
85 (0 - page not cacheable) */
86 #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
87 performed to a page) */
88 #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are
89 shared by processes) */
90 #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the
91 cache write mode:
92 0 - Copy-back mode
93 1 - Write-through mode */
94
95 /* Page Table Entry Assistance register - PTEA */
96 #define SH7750_PTEA_REGOFS 0x000034 /* offset */
97 #define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS)
98 #define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS)
99 #define SH7750_PTEA_TC 0x00000008 /* Timing Control bit
100 0 - use area 5 wait states
101 1 - use area 6 wait states */
102 #define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */
103 #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */
104 #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */
105 #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */
106 #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */
107 #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space */
108 #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space */
109 #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */
110 #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */
111
112
113 /* Translation table base register */
114 #define SH7750_TTB_REGOFS 0x000008 /* offset */
115 #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS)
116 #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS)
117
118 /* TLB exeption address register - TEA */
119 #define SH7750_TEA_REGOFS 0x00000c /* offset */
120 #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS)
121 #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS)
122
123 /* MMU control register - MMUCR */
124 #define SH7750_MMUCR_REGOFS 0x000010 /* offset */
125 #define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
126 #define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
127 #define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */
128 #define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */
129 #define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */
130 #define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */
131 #define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */
132 #define SH7750_MMUCR_URC_S 10
133 #define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */
134 #define SH7750_MMUCR_URB_S 18
135 #define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */
136 #define SH7750_MMUCR_LRUI_S 26
137
138
139
140
141 /*
142 * Cache registers
143 * IC -- instructions cache
144 * OC -- operand cache
145 */
146
147 /* Cache Control Register - CCR */
148 #define SH7750_CCR_REGOFS 0x00001c /* offset */
149 #define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS)
150 #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS)
151
152 #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */
153 #define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
154 set it to clear IC */
155 #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */
156 #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */
157 #define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
158 if you set OCE = 0,
159 you should set ORA = 0 */
160 #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */
161 #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
162 #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */
163 #define SH7750_CCR_OCE 0x00000001 /* OC enable bit */
164
165 /* Queue address control register 0 - QACR0 */
166 #define SH7750_QACR0_REGOFS 0x000038 /* offset */
167 #define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS)
168 #define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS)
169
170 /* Queue address control register 1 - QACR1 */
171 #define SH7750_QACR1_REGOFS 0x00003c /* offset */
172 #define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS)
173 #define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS)
174
175
176 /*
177 * Exeption-related registers
178 */
179
180 /* Immediate data for TRAPA instruction - TRA */
181 #define SH7750_TRA_REGOFS 0x000020 /* offset */
182 #define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS)
183 #define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS)
184
185 #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */
186 #define SH7750_TRA_IMM_S 2
187
188 /* Exeption event register - EXPEVT */
189 #define SH7750_EXPEVT_REGOFS 0x000024
190 #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
191 #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
192
193 #define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */
194 #define SH7750_EXPEVT_EX_S 0
195
196 /* Interrupt event register */
197 #define SH7750_INTEVT_REGOFS 0x000028
198 #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
199 #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
200 #define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
201 #define SH7750_INTEVT_EX_S 0
202
203 /*
204 * Exception/interrupt codes
205 */
206 #define SH7750_EVT_TO_NUM(evt) ((evt) >> 5)
207
208 /* Reset exception category */
209 #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */
210 #define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */
211 #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */
212
213 /* General exception category */
214 #define SH7750_EVT_USER_BREAK 0x1E0 /* User break */
215 #define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */
216 #define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception /
217 DTLB miss exception (read) */
218 #define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation /
219 DTLB protection violation (read) */
220 #define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction
221 exception */
222 #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction
223 exception */
224 #define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception */
225 #define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */
226 #define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */
227 #define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */
228 #define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */
229 #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation
230 exception (write) */
231 #define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */
232 #define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */
233 #define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */
234
235 /* Interrupt exception category */
236 #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */
237 #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */
238 #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */
239 #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */
240 #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */
241 #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */
242 #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */
243 #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */
244 #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */
245 #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */
246 #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */
247 #define SH7750_EVT_IRQA 0x340 /* External Interrupt A */
248 #define SH7750_EVT_IRQB 0x360 /* External Interrupt B */
249 #define SH7750_EVT_IRQC 0x380 /* External Interrupt C */
250 #define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */
251 #define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */
252
253 /* Peripheral Module Interrupts - Timer Unit (TMU) */
254 #define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */
255 #define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */
256 #define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */
257 #define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2 */
258
259 /* Peripheral Module Interrupts - Real-Time Clock (RTC) */
260 #define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */
261 #define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */
262 #define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */
263
264 /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
265 #define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */
266 #define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */
267 #define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */
268 #define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */
269
270 /* Peripheral Module Interrupts - Watchdog Timer (WDT) */
271 #define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt
272 (used when WDT operates in
273 interval timer mode) */
274
275 /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
276 #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
277 #define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
278 interrupt */
279
280 /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
281 #define SH7750_EVT_HUDI 0x600 /* UDI interrupt */
282
283 /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
284 #define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */
285
286 /* Peripheral Module Interrupts - DMA Controller (DMAC) */
287 #define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt */
288 #define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt */
289 #define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt */
290 #define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt */
291 #define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */
292
293 /* Peripheral Module Interrupts - Serial Communication Interface with FIFO */
294 /* (SCIF) */
295 #define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */
296 #define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or
297 Receive Data ready interrupt */
298 #define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */
299 #define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */
300
301 /*
302 * Power Management
303 */
304 #define SH7750_STBCR_REGOFS 0xC00004 /* offset */
305 #define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS)
306 #define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS)
307
308 #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode:
309 0 - Transition to SLEEP mode on SLEEP
310 1 - Transition to STANDBY mode on SLEEP */
311 #define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in
312 standby mode:
313 0 - normal state
314 1 - high-impendance state */
315
316 #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls */
317 #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */
318 #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
319 #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */
320 #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
321 #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */
322 #define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2
323 #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */
324 #define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1
325 #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */
326 #define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0
327
328 #define SH7750_STBCR_STBY 0x80
329
330
331 #define SH7750_STBCR2_REGOFS 0xC00010 /* offset */
332 #define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
333 #define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
334
335 #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode:
336 0 - transition to sleep or standby mode
337 as it is specified in STBY bit
338 1 - transition to deep sleep mode on
339 execution of SLEEP instruction */
340 #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue
341 in the cache controller */
342 #define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6
343 #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User
344 Break Controller (UBC) */
345 #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
346
347 /*
348 * Clock Pulse Generator (CPG)
349 */
350 #define SH7750_FRQCR_REGOFS 0xC00000 /* offset */
351 #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
352 #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
353
354 #define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
355 0 - CKIO pin goes to HiZ/pullup
356 1 - Clock is output from CKIO */
357 #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
358 #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */
359
360 #define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */
361 #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */
362 #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */
363 #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */
364 #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */
365 #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */
366 #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */
367
368 #define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */
369 #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */
370 #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */
371 #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */
372 #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */
373 #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */
374 #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */
375
376 #define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency
377 division ratio: */
378 #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */
379 #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */
380 #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */
381 #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */
382 #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */
383
384 /*
385 * Watchdog Timer (WDT)
386 */
387
388 /* Watchdog Timer Counter register - WTCNT */
389 #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */
390 #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
391 #define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
392 #define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written,
393 you have to set the upper byte to
394 0x5A */
395
396 /* Watchdog Timer Control/Status register - WTCSR */
397 #define SH7750_WTCSR_REGOFS 0xC0000C /* offset */
398 #define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
399 #define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
400 #define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written,
401 you have to set the upper byte to
402 0xA5 */
403 #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */
404 #define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */
405 #define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */
406 #define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */
407 #define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */
408 #define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */
409 #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */
410 #define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */
411 #define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */
412 #define SH7750_WTCSR_CKS 0x07 /* Clock Select: */
413 #define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */
414 #define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */
415 #define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */
416 #define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */
417 #define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */
418 #define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */
419 #define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */
420 #define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */
421
422 /*
423 * Real-Time Clock (RTC)
424 */
425 /* 64-Hz Counter Register (byte, read-only) - R64CNT */
426 #define SH7750_R64CNT_REGOFS 0xC80000 /* offset */
427 #define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
428 #define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
429
430 /* Second Counter Register (byte, BCD-coded) - RSECCNT */
431 #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */
432 #define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
433 #define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
434
435 /* Minute Counter Register (byte, BCD-coded) - RMINCNT */
436 #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */
437 #define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
438 #define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
439
440 /* Hour Counter Register (byte, BCD-coded) - RHRCNT */
441 #define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */
442 #define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
443 #define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
444
445 /* Day-of-Week Counter Register (byte) - RWKCNT */
446 #define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */
447 #define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
448 #define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
449
450 #define SH7750_RWKCNT_SUN 0 /* Sunday */
451 #define SH7750_RWKCNT_MON 1 /* Monday */
452 #define SH7750_RWKCNT_TUE 2 /* Tuesday */
453 #define SH7750_RWKCNT_WED 3 /* Wednesday */
454 #define SH7750_RWKCNT_THU 4 /* Thursday */
455 #define SH7750_RWKCNT_FRI 5 /* Friday */
456 #define SH7750_RWKCNT_SAT 6 /* Saturday */
457
458 /* Day Counter Register (byte, BCD-coded) - RDAYCNT */
459 #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */
460 #define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
461 #define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
462
463 /* Month Counter Register (byte, BCD-coded) - RMONCNT */
464 #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */
465 #define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
466 #define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
467
468 /* Year Counter Register (half, BCD-coded) - RYRCNT */
469 #define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */
470 #define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
471 #define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
472
473 /* Second Alarm Register (byte, BCD-coded) - RSECAR */
474 #define SH7750_RSECAR_REGOFS 0xC80020 /* offset */
475 #define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
476 #define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
477 #define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */
478
479 /* Minute Alarm Register (byte, BCD-coded) - RMINAR */
480 #define SH7750_RMINAR_REGOFS 0xC80024 /* offset */
481 #define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
482 #define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
483 #define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */
484
485 /* Hour Alarm Register (byte, BCD-coded) - RHRAR */
486 #define SH7750_RHRAR_REGOFS 0xC80028 /* offset */
487 #define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
488 #define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
489 #define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */
490
491 /* Day-of-Week Alarm Register (byte) - RWKAR */
492 #define SH7750_RWKAR_REGOFS 0xC8002C /* offset */
493 #define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
494 #define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
495 #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */
496
497 #define SH7750_RWKAR_SUN 0 /* Sunday */
498 #define SH7750_RWKAR_MON 1 /* Monday */
499 #define SH7750_RWKAR_TUE 2 /* Tuesday */
500 #define SH7750_RWKAR_WED 3 /* Wednesday */
501 #define SH7750_RWKAR_THU 4 /* Thursday */
502 #define SH7750_RWKAR_FRI 5 /* Friday */
503 #define SH7750_RWKAR_SAT 6 /* Saturday */
504
505 /* Day Alarm Register (byte, BCD-coded) - RDAYAR */
506 #define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */
507 #define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
508 #define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
509 #define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */
510
511 /* Month Counter Register (byte, BCD-coded) - RMONAR */
512 #define SH7750_RMONAR_REGOFS 0xC80034 /* offset */
513 #define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
514 #define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
515 #define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */
516
517 /* RTC Control Register 1 (byte) - RCR1 */
518 #define SH7750_RCR1_REGOFS 0xC80038 /* offset */
519 #define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS)
520 #define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS)
521 #define SH7750_RCR1_CF 0x80 /* Carry Flag */
522 #define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */
523 #define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */
524 #define SH7750_RCR1_AF 0x01 /* Alarm Flag */
525
526 /* RTC Control Register 2 (byte) - RCR2 */
527 #define SH7750_RCR2_REGOFS 0xC8003C /* offset */
528 #define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS)
529 #define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS)
530 #define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */
531 #define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */
532 #define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */
533 #define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */
534 #define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */
535 #define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */
536 #define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */
537 #define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */
538 #define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */
539 #define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */
540 #define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */
541 #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */
542 #define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset */
543 #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month,
544 year counters are stopped
545 1 - sec, min, hr, day-of-week, month,
546 year counters operate normally */
547 /*
548 * Bus State Controller - BSC
549 */
550 /* Bus Control Register 1 - BCR1 */
551 #define SH7750_BCR1_REGOFS 0x800000 /* offset */
552 #define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS)
553 #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS)
554 #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */
555 #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */
556 #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
557 #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control:
558 0 - pull-up resistor is on for
559 control input pins
560 1 - pull-up resistor is off */
561 #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control:
562 0 - pull-up resistor is on for
563 control output pins
564 1 - pull-up resistor is off */
565 #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode:
566 0 - Area 1 SRAM is set to
567 normal mode
568 1 - Area 1 SRAM is set to byte
569 control mode */
570 #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode:
571 0 - Area 4 SRAM is set to
572 normal mode
573 1 - Area 4 SRAM is set to byte
574 control mode */
575 #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable:
576 0 - External requests are not
577 accepted
578 1 - External requests are
579 accepted */
580 #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit:
581 0 - Master Mode
582 1 - Partial-sharing Mode */
583 #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface:
584 0 - SRAM/burst ROM interface
585 1 - MPX interface */
586 #define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies
587 the state of A[25:0], BS\, CSn\,
588 RD/WR\, CE2A\, CE2B\ in standby
589 mode and when bus is released:
590 0 - signals go to High-Z mode
591 1 - signals driven */
592 #define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies
593 the state of the RAS\, RAS2\, WEn\,
594 CASn\, DQMn, RD\, CASS\, FRAME\,
595 RD2\ signals in standby mode and
596 when bus is released:
597 0 - signals go to High-Z mode
598 1 - signals driven */
599 #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */
600 #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */
601 #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM
602 interface, 4 cosequtive access */
603 #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM
604 interface, 8 cosequtive access */
605 #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM
606 interface, 16 cosequtive access */
607 #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM
608 interface, 32 cosequtive access */
609
610 #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */
611 #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */
612 #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM
613 interface, 4 cosequtive access */
614 #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM
615 interface, 8 cosequtive access */
616 #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM
617 interface, 16 cosequtive access */
618 #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM
619 interface, 32 cosequtive access */
620
621 #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */
622 #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */
623 #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM
624 interface, 4 cosequtive access */
625 #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM
626 interface, 8 cosequtive access */
627 #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM
628 interface, 16 cosequtive access */
629 #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM
630 interface, 32 cosequtive access */
631
632 #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */
633 #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX
634 interface. */
635 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 -
636 synchronous DRAM */
637 #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous
638 DRAM interface */
639 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 -
640 DRAM interface */
641 #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM
642 interface */
643
644 #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type:
645 0 - SRAM interface
646 1 - PCMCIA interface */
647
648 /* Bus Control Register 2 (half) - BCR2 */
649 #define SH7750_BCR2_REGOFS 0x800004 /* offset */
650 #define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS)
651 #define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS)
652
653 #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */
654 #define SH7750_BCR2_A0SZ_S 14
655 #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */
656 #define SH7750_BCR2_A6SZ_S 12
657 #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */
658 #define SH7750_BCR2_A5SZ_S 10
659 #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */
660 #define SH7750_BCR2_A4SZ_S 8
661 #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */
662 #define SH7750_BCR2_A3SZ_S 6
663 #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */
664 #define SH7750_BCR2_A2SZ_S 4
665 #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */
666 #define SH7750_BCR2_A1SZ_S 2
667 #define SH7750_BCR2_SZ_64 0 /* 64 bits */
668 #define SH7750_BCR2_SZ_8 1 /* 8 bits */
669 #define SH7750_BCR2_SZ_16 2 /* 16 bits */
670 #define SH7750_BCR2_SZ_32 3 /* 32 bits */
671 #define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable :
672 0 - D51-D32 are not used as a port
673 1 - D51-D32 are used as a port */
674
675 /* Wait Control Register 1 - WCR1 */
676 #define SH7750_WCR1_REGOFS 0x800008 /* offset */
677 #define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS)
678 #define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS)
679 #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle
680 specification */
681 #define SH7750_WCR1_DMAIW_S 28
682 #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
683 #define SH7750_WCR1_A6IW_S 24
684 #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
685 #define SH7750_WCR1_A5IW_S 20
686 #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
687 #define SH7750_WCR1_A4IW_S 16
688 #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
689 #define SH7750_WCR1_A3IW_S 12
690 #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
691 #define SH7750_WCR1_A2IW_S 8
692 #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
693 #define SH7750_WCR1_A1IW_S 4
694 #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
695 #define SH7750_WCR1_A0IW_S 0
696
697 /* Wait Control Register 2 - WCR2 */
698 #define SH7750_WCR2_REGOFS 0x80000C /* offset */
699 #define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS)
700 #define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS)
701
702 #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */
703 #define SH7750_WCR2_A6W_S 29
704 #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */
705 #define SH7750_WCR2_A6B_S 26
706 #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */
707 #define SH7750_WCR2_A5W_S 23
708 #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */
709 #define SH7750_WCR2_A5B_S 20
710 #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */
711 #define SH7750_WCR2_A4W_S 17
712 #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */
713 #define SH7750_WCR2_A3W_S 13
714 #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */
715 #define SH7750_WCR2_A2W_S 9
716 #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */
717 #define SH7750_WCR2_A1W_S 6
718 #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */
719 #define SH7750_WCR2_A0W_S 3
720 #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */
721 #define SH7750_WCR2_A0B_S 0
722
723 #define SH7750_WCR2_WS0 0 /* 0 wait states inserted */
724 #define SH7750_WCR2_WS1 1 /* 1 wait states inserted */
725 #define SH7750_WCR2_WS2 2 /* 2 wait states inserted */
726 #define SH7750_WCR2_WS3 3 /* 3 wait states inserted */
727 #define SH7750_WCR2_WS6 4 /* 6 wait states inserted */
728 #define SH7750_WCR2_WS9 5 /* 9 wait states inserted */
729 #define SH7750_WCR2_WS12 6 /* 12 wait states inserted */
730 #define SH7750_WCR2_WS15 7 /* 15 wait states inserted */
731
732 #define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */
733 #define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */
734 #define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */
735 #define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */
736 #define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */
737 #define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */
738 #define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */
739 #define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */
740
741 /* DRAM CAS\ Assertion Delay (area 3,2) */
742 #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */
743 #define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */
744 #define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */
745 #define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */
746 #define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */
747 #define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */
748 #define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */
749 #define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */
750
751 /* SDRAM CAS\ Latency Cycles */
752 #define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */
753 #define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */
754 #define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */
755 #define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */
756 #define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */
757
758 /* Wait Control Register 3 - WCR3 */
759 #define SH7750_WCR3_REGOFS 0x800010 /* offset */
760 #define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS)
761 #define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS)
762
763 #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */
764 #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */
765 #define SH7750_WCR3_A6H_S 24
766 #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */
767 #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */
768 #define SH7750_WCR3_A5H_S 20
769 #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */
770 #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */
771 #define SH7750_WCR3_A4H_S 16
772 #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */
773 #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */
774 #define SH7750_WCR3_A3H_S 12
775 #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */
776 #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */
777 #define SH7750_WCR3_A2H_S 8
778 #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */
779 #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */
780 #define SH7750_WCR3_A1H_S 4
781 #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */
782 #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */
783 #define SH7750_WCR3_A0H_S 0
784
785 #define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */
786 #define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */
787 #define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */
788 #define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */
789
790 #define SH7750_MCR_REGOFS 0x800014 /* offset */
791 #define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS)
792 #define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS)
793
794 #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */
795 #define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */
796 #define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */
797 #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of
798 Refresh: */
799 #define SH7750_MCR_TRC_0 0x00000000 /* 0 */
800 #define SH7750_MCR_TRC_3 0x08000000 /* 3 */
801 #define SH7750_MCR_TRC_6 0x10000000 /* 6 */
802 #define SH7750_MCR_TRC_9 0x18000000 /* 9 */
803 #define SH7750_MCR_TRC_12 0x20000000 /* 12 */
804 #define SH7750_MCR_TRC_15 0x28000000 /* 15 */
805 #define SH7750_MCR_TRC_18 0x30000000 /* 18 */
806 #define SH7750_MCR_TRC_21 0x38000000 /* 21 */
807
808 #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */
809 #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */
810 #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */
811
812 #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
813 SDRAM: minimum number of cycles
814 until the next bank active cmd
815 is output after precharging */
816 #define SH7750_MCR_TPC_S 19
817 #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
818 #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
819 #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
820 #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
821 #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
822 #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
823 #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */
824 #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */
825
826 #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time
827 SDRAM: bank active-read/write cmd
828 delay time */
829 #define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */
830 #define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */
831 #define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */
832 #define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */
833 #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */
834 #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */
835 #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */
836
837 #define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */
838 #define SH7750_MCR_TRWL_1 0x00000000 /* 1 */
839 #define SH7750_MCR_TRWL_2 0x00002000 /* 2 */
840 #define SH7750_MCR_TRWL_3 0x00004000 /* 3 */
841 #define SH7750_MCR_TRWL_4 0x00006000 /* 4 */
842 #define SH7750_MCR_TRWL_5 0x00008000 /* 5 */
843
844 #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS
845 asserting period
846 SDRAM: Command interval after
847 synchronous DRAM refresh */
848 #define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */
849 #define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */
850 #define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */
851 #define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */
852 #define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */
853 #define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */
854 #define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */
855 #define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */
856
857 #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */
858 #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */
859 #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */
860 #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */
861 #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */
862 #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */
863 #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */
864 #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */
865
866 #define SH7750_MCR_BE 0x00000200 /* Burst Enable */
867 #define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */
868 #define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */
869 #define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */
870 #define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */
871
872 #define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */
873 #define SH7750_MCR_AMX_S 3
874 #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */
875 #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */
876 #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */
877 #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */
878 #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */
879 /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */
880
881 #define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */
882 #define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */
883 #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */
884 #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */
885 #define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */
886
887 /* SDRAM Mode Set address */
888 #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000
889 #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000
890 #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
891 #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
892 #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
893 #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
894
895
896 /* PCMCIA Control Register (half) - PCR */
897 #define SH7750_PCR_REGOFS 0x800018 /* offset */
898 #define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS)
899 #define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS)
900
901 #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait
902 states to be added to the number of
903 waits specified by WCR2 in a low-speed
904 PCMCIA wait cycle */
905 #define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */
906 #define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */
907 #define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */
908 #define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */
909
910 #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait
911 states to be added to the number of
912 waits specified by WCR2 in a low-speed
913 PCMCIA wait cycle */
914 #define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */
915 #define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */
916 #define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */
917 #define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */
918
919 #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay,
920 delay time from address output to
921 OE\/WE\ assertion on the connected
922 PCMCIA interface */
923 #define SH7750_PCR_A5TED_S 9
924 #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay */
925 #define SH7750_PCR_A6TED_S 6
926
927 #define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */
928 #define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */
929 #define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */
930 #define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */
931 #define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */
932 #define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */
933 #define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */
934 #define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */
935
936 #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay,
937 address hold delay time from OE\/WE\
938 negation in a write on the connected
939 PCMCIA interface */
940 #define SH7750_PCR_A5TEH_S 3
941
942 #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay */
943 #define SH7750_PCR_A6TEH_S 0
944
945 #define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */
946 #define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */
947 #define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */
948 #define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */
949 #define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */
950 #define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */
951 #define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */
952 #define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */
953
954 /* Refresh Timer Control/Status Register (half) - RTSCR */
955 #define SH7750_RTCSR_REGOFS 0x80001C /* offset */
956 #define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
957 #define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
958
959 #define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */
960 #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a
961 match between the refresh timer
962 counter and refresh time constant) */
963 #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */
964 #define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */
965 #define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */
966 #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */
967 #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */
968 #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */
969 #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */
970 #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */
971 #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */
972 #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */
973
974 #define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */
975 #define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt
976 Enable */
977 #define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */
978 #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */
979 #define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */
980
981 /* Refresh Timer Counter (half) - RTCNT */
982 #define SH7750_RTCNT_REGOFS 0x800020 /* offset */
983 #define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
984 #define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
985
986 #define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */
987
988 /* Refresh Time Constant Register (half) - RTCOR */
989 #define SH7750_RTCOR_REGOFS 0x800024 /* offset */
990 #define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
991 #define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
992
993 #define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */
994
995 /* Refresh Count Register (half) - RFCR */
996 #define SH7750_RFCR_REGOFS 0x800028 /* offset */
997 #define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS)
998 #define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS)
999
1000 #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
1001
1002 /* Synchronous DRAM mode registers - SDMR */
1003 #define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
1004 #define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
1005 #define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
1006 #define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
1007
1008 #define SH7750_SDMR3_REGOFS 0x940000 /* offset */
1009 #define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
1010 #define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
1011 #define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
1012
1013 /*
1014 * Direct Memory Access Controller (DMAC)
1015 */
1016
1017 /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
1018 #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */
1019 #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
1020 #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
1021 #define SH7750_SAR0 SH7750_SAR(0)
1022 #define SH7750_SAR1 SH7750_SAR(1)
1023 #define SH7750_SAR2 SH7750_SAR(2)
1024 #define SH7750_SAR3 SH7750_SAR(3)
1025 #define SH7750_SAR0_A7 SH7750_SAR_A7(0)
1026 #define SH7750_SAR1_A7 SH7750_SAR_A7(1)
1027 #define SH7750_SAR2_A7 SH7750_SAR_A7(2)
1028 #define SH7750_SAR3_A7 SH7750_SAR_A7(3)
1029
1030 /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
1031 #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */
1032 #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
1033 #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
1034 #define SH7750_DAR0 SH7750_DAR(0)
1035 #define SH7750_DAR1 SH7750_DAR(1)
1036 #define SH7750_DAR2 SH7750_DAR(2)
1037 #define SH7750_DAR3 SH7750_DAR(3)
1038 #define SH7750_DAR0_A7 SH7750_DAR_A7(0)
1039 #define SH7750_DAR1_A7 SH7750_DAR_A7(1)
1040 #define SH7750_DAR2_A7 SH7750_DAR_A7(2)
1041 #define SH7750_DAR3_A7 SH7750_DAR_A7(3)
1042
1043 /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
1044 #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */
1045 #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
1046 #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
1047 #define SH7750_DMATCR0_P4 SH7750_DMATCR(0)
1048 #define SH7750_DMATCR1_P4 SH7750_DMATCR(1)
1049 #define SH7750_DMATCR2_P4 SH7750_DMATCR(2)
1050 #define SH7750_DMATCR3_P4 SH7750_DMATCR(3)
1051 #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0)
1052 #define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1)
1053 #define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2)
1054 #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3)
1055
1056 /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
1057 #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */
1058 #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
1059 #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
1060 #define SH7750_CHCR0 SH7750_CHCR(0)
1061 #define SH7750_CHCR1 SH7750_CHCR(1)
1062 #define SH7750_CHCR2 SH7750_CHCR(2)
1063 #define SH7750_CHCR3 SH7750_CHCR(3)
1064 #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0)
1065 #define SH7750_CHCR1_A7 SH7750_CHCR_A7(1)
1066 #define SH7750_CHCR2_A7 SH7750_CHCR_A7(2)
1067 #define SH7750_CHCR3_A7 SH7750_CHCR_A7(3)
1068
1069 #define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */
1070 #define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
1071 #define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */
1072 #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */
1073 #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */
1074 #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */
1075 #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */
1076 #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */
1077 #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */
1078
1079 #define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select,
1080 specifies CS5 or CS6 space wait
1081 control for PCMCIA access */
1082
1083 #define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */
1084 #define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */
1085 #define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */
1086 #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */
1087 #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */
1088 #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */
1089 #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */
1090 #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */
1091 #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
1092
1093 #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control
1094 Select, specifies CS5 or CS6
1095 space wait control for PCMCIA
1096 access */
1097
1098 #define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */
1099 #define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */
1100 #define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */
1101
1102 #define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */
1103 #define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */
1104 #define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */
1105
1106 #define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */
1107 #define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */
1108 #define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle */
1109
1110 #define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */
1111 #define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */
1112 #define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */
1113
1114 #define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */
1115 #define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */
1116 #define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */
1117 #define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */
1118
1119 #define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */
1120 #define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */
1121 #define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */
1122 #define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */
1123
1124 #define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */
1125 #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address
1126 Mode (External Addr Space->
1127 External Addr Space) */
1128 #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single
1129 Address Mode (External Addr
1130 Space -> External Device) */
1131 #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single
1132 Address Mode, (External
1133 Device -> External Addr
1134 Space) */
1135 #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr
1136 Space -> External Addr Space) */
1137
1138 #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr
1139 Space -> On-chip Peripheral
1140 Module) */
1141 #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
1142 Peripheral Module ->
1143 External Addr Space */
1144 #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr
1145 transfer request (external
1146 address space -> SCTDR1) */
1147 #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr
1148 transfer request (SCRDR1 ->
1149 External Addr Space) */
1150 #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr
1151 transfer request (external
1152 address space -> SCFTDR1) */
1153 #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr
1154 transfer request (SCFRDR2 ->
1155 External Addr Space) */
1156 #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture
1157 interrupt), (external address
1158 space -> external address
1159 space) */
1160 #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture
1161 interrupt), (external address
1162 space -> on-chip peripheral
1163 module) */
1164 #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture
1165 interrupt), (on-chip
1166 peripheral module -> external
1167 address space) */
1168
1169 #define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */
1170 #define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */
1171 #define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */
1172
1173 #define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */
1174 #define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */
1175 #define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */
1176 #define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */
1177 #define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */
1178 #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */
1179
1180 #define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */
1181 #define SH7750_CHCR_TE 0x00000002 /* Transfer End */
1182 #define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */
1183
1184 /* DMA Operation Register - DMAOR */
1185 #define SH7750_DMAOR_REGOFS 0xA00040 /* offset */
1186 #define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
1187 #define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
1188
1189 #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */
1190
1191 #define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */
1192 #define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */
1193 #define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */
1194 #define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */
1195 #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */
1196
1197 #define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */
1198 #define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */
1199 #define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */
1200 #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */
1201
1202 /*
1203 * I/O Ports
1204 */
1205 /* Port Control Register A - PCTRA */
1206 #define SH7750_PCTRA_REGOFS 0x80002C /* offset */
1207 #define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
1208 #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
1209
1210 #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */
1211 #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */
1212 #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */
1213 #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */
1214
1215 /* Port Data Register A - PDTRA(half) */
1216 #define SH7750_PDTRA_REGOFS 0x800030 /* offset */
1217 #define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
1218 #define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
1219
1220 #define SH7750_PDTRA_BIT(n) (1 << (n))
1221
1222 /* Port Control Register B - PCTRB */
1223 #define SH7750_PCTRB_REGOFS 0x800040 /* offset */
1224 #define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
1225 #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
1226
1227 #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */
1228 #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */
1229 #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */
1230 #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */
1231
1232 /* Port Data Register B - PDTRB(half) */
1233 #define SH7750_PDTRB_REGOFS 0x800044 /* offset */
1234 #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
1235 #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
1236
1237 #define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
1238
1239 /* GPIO Interrupt Control Register - GPIOIC(half) */
1240 #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */
1241 #define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
1242 #define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
1243
1244 #define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */
1245
1246 /*
1247 * Interrupt Controller - INTC
1248 */
1249 /* Interrupt Control Register - ICR (half) */
1250 #define SH7750_ICR_REGOFS 0xD00000 /* offset */
1251 #define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS)
1252 #define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS)
1253
1254 #define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */
1255 #define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */
1256
1257 #define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */
1258 #define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while
1259 SR.BL bit is set to 1 */
1260 #define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit
1261 set to 1 */
1262
1263 #define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */
1264 #define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling
1265 edge of NMI input */
1266 #define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising
1267 edge of NMI input */
1268
1269 #define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */
1270 #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded
1271 interrupt requests */
1272 #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent
1273 interrupt requests */
1274
1275 /*
1276 * User Break Controller registers
1277 */
1278 #define SH7750_BARA 0x200000 /* Break address regiser A */
1279 #define SH7750_BAMRA 0x200004 /* Break address mask regiser A */
1280 #define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */
1281 #define SH7750_BARB 0x20000c /* Break address regiser B */
1282 #define SH7750_BAMRB 0x200010 /* Break address mask regiser B */
1283 #define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */
1284 #define SH7750_BASRB 0x000018 /* Break ASID regiser B */
1285 #define SH7750_BDRB 0x200018 /* Break data regiser B */
1286 #define SH7750_BDMRB 0x20001c /* Break data mask regiser B */
1287 #define SH7750_BRCR 0x200020 /* Break control register */
1288
1289 #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */
1290
1291 /*
1292 * Missing in RTEMS, added for QEMU
1293 */
1294 #define SH7750_BCR3_A7 0x1f800050
1295 #define SH7750_BCR4_A7 0x1e0a00f0
1296
1297 #endif
AR7 emulation for QEMU