hw/gpio/puv3_gpio.c

   1 /*
   2  * GPIO device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "qom/object.h"
  15
  16 #undef DEBUG_PUV3
  17 #include "hw/unicore32/puv3.h"
  18 #include "qemu/module.h"
  19 #include "qemu/log.h"
  20
  21 #define TYPE_PUV3_GPIO "puv3_gpio"
  22 OBJECT_DECLARE_SIMPLE_TYPE(PUV3GPIOState, PUV3_GPIO)
  23
  24 struct PUV3GPIOState {
  25     SysBusDevice parent_obj;
  26
  27     MemoryRegion iomem;
  28     qemu_irq irq[9];
  29
  30     uint32_t reg_GPLR;
  31     uint32_t reg_GPDR;
  32     uint32_t reg_GPIR;
  33 };
  34
  35 static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
  36         unsigned size)
  37 {
  38     PUV3GPIOState *s = opaque;
  39     uint32_t ret = 0;
  40
  41     switch (offset) {
  42     case 0x00:
  43         ret = s->reg_GPLR;
  44         break;
  45     case 0x04:
  46         ret = s->reg_GPDR;
  47         break;
  48     case 0x20:
  49         ret = s->reg_GPIR;
  50         break;
  51     default:
  52         qemu_log_mask(LOG_GUEST_ERROR,
  53                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  54                       __func__, offset);
  55     }
  56     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  57
  58     return ret;
  59 }
  60
  61 static void puv3_gpio_write(void *opaque, hwaddr offset,
  62         uint64_t value, unsigned size)
  63 {
  64     PUV3GPIOState *s = opaque;
  65
  66     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  67     switch (offset) {
  68     case 0x04:
  69         s->reg_GPDR = value;
  70         break;
  71     case 0x08:
  72         if (s->reg_GPDR & value) {
  73             s->reg_GPLR |= value;
  74         } else {
  75             qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
  76                           __func__);
  77         }
  78         break;
  79     case 0x0c:
  80         if (s->reg_GPDR & value) {
  81             s->reg_GPLR &= ~value;
  82         } else {
  83             qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
  84                           __func__);
  85         }
  86         break;
  87     case 0x10: /* GRER */
  88     case 0x14: /* GFER */
  89     case 0x18: /* GEDR */
  90         break;
  91     case 0x20: /* GPIR */
  92         s->reg_GPIR = value;
  93         break;
  94     default:
  95         qemu_log_mask(LOG_GUEST_ERROR,
  96                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  97                       __func__, offset);
  98     }
  99 }
 100
 101 static const MemoryRegionOps puv3_gpio_ops = {
 102     .read = puv3_gpio_read,
 103     .write = puv3_gpio_write,
 104     .impl = {
 105         .min_access_size = 4,
 106         .max_access_size = 4,
 107     },
 108     .endianness = DEVICE_NATIVE_ENDIAN,
 109 };
 110
 111 static void puv3_gpio_realize(DeviceState *dev, Error **errp)
 112 {
 113     PUV3GPIOState *s = PUV3_GPIO(dev);
 114     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 115
 116     s->reg_GPLR = 0;
 117     s->reg_GPDR = 0;
 118
 119     /* FIXME: these irqs not handled yet */
 120     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
 121     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
 122     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
 123     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
 124     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
 125     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
 126     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
 127     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
 128     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
 129
 130     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
 131             PUV3_REGS_OFFSET);
 132     sysbus_init_mmio(sbd, &s->iomem);
 133 }
 134
 135 static void puv3_gpio_class_init(ObjectClass *klass, void *data)
 136 {
 137     DeviceClass *dc = DEVICE_CLASS(klass);
 138
 139     dc->realize = puv3_gpio_realize;
 140 }
 141
 142 static const TypeInfo puv3_gpio_info = {
 143     .name = TYPE_PUV3_GPIO,
 144     .parent = TYPE_SYS_BUS_DEVICE,
 145     .instance_size = sizeof(PUV3GPIOState),
 146     .class_init = puv3_gpio_class_init,
 147 };
 148
 149 static void puv3_gpio_register_type(void)
 150 {
 151     type_register_static(&puv3_gpio_info);
 152 }
 153
 154 type_init(puv3_gpio_register_type)