hw/gpio/pl061.c

   1 /*
   2  * Arm PrimeCell PL061 General Purpose IO with additional
   3  * Luminary Micro Stellaris bits.
   4  *
   5  * Copyright (c) 2007 CodeSourcery.
   6  * Written by Paul Brook
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "hw/irq.h"
  13 #include "hw/sysbus.h"
  14 #include "migration/vmstate.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17 #include "qom/object.h"
  18
  19 //#define DEBUG_PL061 1
  20
  21 #ifdef DEBUG_PL061
  22 #define DPRINTF(fmt, ...) \
  23 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
  24 #define BADF(fmt, ...) \
  25 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  26 #else
  27 #define DPRINTF(fmt, ...) do {} while(0)
  28 #define BADF(fmt, ...) \
  29 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
  30 #endif
  31
  32 static const uint8_t pl061_id[12] =
  33   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  34 static const uint8_t pl061_id_luminary[12] =
  35   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  36
  37 #define TYPE_PL061 "pl061"
  38 OBJECT_DECLARE_SIMPLE_TYPE(PL061State, PL061)
  39
  40 #define N_GPIOS 8
  41
  42 struct PL061State {
  43     SysBusDevice parent_obj;
  44
  45     MemoryRegion iomem;
  46     uint32_t locked;
  47     uint32_t data;
  48     uint32_t old_out_data;
  49     uint32_t old_in_data;
  50     uint32_t dir;
  51     uint32_t isense;
  52     uint32_t ibe;
  53     uint32_t iev;
  54     uint32_t im;
  55     uint32_t istate;
  56     uint32_t afsel;
  57     uint32_t dr2r;
  58     uint32_t dr4r;
  59     uint32_t dr8r;
  60     uint32_t odr;
  61     uint32_t pur;
  62     uint32_t pdr;
  63     uint32_t slr;
  64     uint32_t den;
  65     uint32_t cr;
  66     uint32_t amsel;
  67     qemu_irq irq;
  68     qemu_irq out[N_GPIOS];
  69     const unsigned char *id;
  70     uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
  71 };
  72
  73 static const VMStateDescription vmstate_pl061 = {
  74     .name = "pl061",
  75     .version_id = 4,
  76     .minimum_version_id = 4,
  77     .fields = (VMStateField[]) {
  78         VMSTATE_UINT32(locked, PL061State),
  79         VMSTATE_UINT32(data, PL061State),
  80         VMSTATE_UINT32(old_out_data, PL061State),
  81         VMSTATE_UINT32(old_in_data, PL061State),
  82         VMSTATE_UINT32(dir, PL061State),
  83         VMSTATE_UINT32(isense, PL061State),
  84         VMSTATE_UINT32(ibe, PL061State),
  85         VMSTATE_UINT32(iev, PL061State),
  86         VMSTATE_UINT32(im, PL061State),
  87         VMSTATE_UINT32(istate, PL061State),
  88         VMSTATE_UINT32(afsel, PL061State),
  89         VMSTATE_UINT32(dr2r, PL061State),
  90         VMSTATE_UINT32(dr4r, PL061State),
  91         VMSTATE_UINT32(dr8r, PL061State),
  92         VMSTATE_UINT32(odr, PL061State),
  93         VMSTATE_UINT32(pur, PL061State),
  94         VMSTATE_UINT32(pdr, PL061State),
  95         VMSTATE_UINT32(slr, PL061State),
  96         VMSTATE_UINT32(den, PL061State),
  97         VMSTATE_UINT32(cr, PL061State),
  98         VMSTATE_UINT32_V(amsel, PL061State, 2),
  99         VMSTATE_END_OF_LIST()
 100     }
 101 };
 102
 103 static void pl061_update(PL061State *s)
 104 {
 105     uint8_t changed;
 106     uint8_t mask;
 107     uint8_t out;
 108     int i;
 109
 110     DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
 111
 112     /* Outputs float high.  */
 113     /* FIXME: This is board dependent.  */
 114     out = (s->data & s->dir) | ~s->dir;
 115     changed = s->old_out_data ^ out;
 116     if (changed) {
 117         s->old_out_data = out;
 118         for (i = 0; i < N_GPIOS; i++) {
 119             mask = 1 << i;
 120             if (changed & mask) {
 121                 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 122                 qemu_set_irq(s->out[i], (out & mask) != 0);
 123             }
 124         }
 125     }
 126
 127     /* Inputs */
 128     changed = (s->old_in_data ^ s->data) & ~s->dir;
 129     if (changed) {
 130         s->old_in_data = s->data;
 131         for (i = 0; i < N_GPIOS; i++) {
 132             mask = 1 << i;
 133             if (changed & mask) {
 134                 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
 135
 136                 if (!(s->isense & mask)) {
 137                     /* Edge interrupt */
 138                     if (s->ibe & mask) {
 139                         /* Any edge triggers the interrupt */
 140                         s->istate |= mask;
 141                     } else {
 142                         /* Edge is selected by IEV */
 143                         s->istate |= ~(s->data ^ s->iev) & mask;
 144                     }
 145                 }
 146             }
 147         }
 148     }
 149
 150     /* Level interrupt */
 151     s->istate |= ~(s->data ^ s->iev) & s->isense;
 152
 153     DPRINTF("istate = %02X\n", s->istate);
 154
 155     qemu_set_irq(s->irq, (s->istate & s->im) != 0);
 156 }
 157
 158 static uint64_t pl061_read(void *opaque, hwaddr offset,
 159                            unsigned size)
 160 {
 161     PL061State *s = (PL061State *)opaque;
 162
 163     if (offset < 0x400) {
 164         return s->data & (offset >> 2);
 165     }
 166     if (offset >= s->rsvd_start && offset <= 0xfcc) {
 167         goto err_out;
 168     }
 169     if (offset >= 0xfd0 && offset < 0x1000) {
 170         return s->id[(offset - 0xfd0) >> 2];
 171     }
 172     switch (offset) {
 173     case 0x400: /* Direction */
 174         return s->dir;
 175     case 0x404: /* Interrupt sense */
 176         return s->isense;
 177     case 0x408: /* Interrupt both edges */
 178         return s->ibe;
 179     case 0x40c: /* Interrupt event */
 180         return s->iev;
 181     case 0x410: /* Interrupt mask */
 182         return s->im;
 183     case 0x414: /* Raw interrupt status */
 184         return s->istate;
 185     case 0x418: /* Masked interrupt status */
 186         return s->istate & s->im;
 187     case 0x420: /* Alternate function select */
 188         return s->afsel;
 189     case 0x500: /* 2mA drive */
 190         return s->dr2r;
 191     case 0x504: /* 4mA drive */
 192         return s->dr4r;
 193     case 0x508: /* 8mA drive */
 194         return s->dr8r;
 195     case 0x50c: /* Open drain */
 196         return s->odr;
 197     case 0x510: /* Pull-up */
 198         return s->pur;
 199     case 0x514: /* Pull-down */
 200         return s->pdr;
 201     case 0x518: /* Slew rate control */
 202         return s->slr;
 203     case 0x51c: /* Digital enable */
 204         return s->den;
 205     case 0x520: /* Lock */
 206         return s->locked;
 207     case 0x524: /* Commit */
 208         return s->cr;
 209     case 0x528: /* Analog mode select */
 210         return s->amsel;
 211     default:
 212         break;
 213     }
 214 err_out:
 215     qemu_log_mask(LOG_GUEST_ERROR,
 216                   "pl061_read: Bad offset %x\n", (int)offset);
 217     return 0;
 218 }
 219
 220 static void pl061_write(void *opaque, hwaddr offset,
 221                         uint64_t value, unsigned size)
 222 {
 223     PL061State *s = (PL061State *)opaque;
 224     uint8_t mask;
 225
 226     if (offset < 0x400) {
 227         mask = (offset >> 2) & s->dir;
 228         s->data = (s->data & ~mask) | (value & mask);
 229         pl061_update(s);
 230         return;
 231     }
 232     if (offset >= s->rsvd_start) {
 233         goto err_out;
 234     }
 235     switch (offset) {
 236     case 0x400: /* Direction */
 237         s->dir = value & 0xff;
 238         break;
 239     case 0x404: /* Interrupt sense */
 240         s->isense = value & 0xff;
 241         break;
 242     case 0x408: /* Interrupt both edges */
 243         s->ibe = value & 0xff;
 244         break;
 245     case 0x40c: /* Interrupt event */
 246         s->iev = value & 0xff;
 247         break;
 248     case 0x410: /* Interrupt mask */
 249         s->im = value & 0xff;
 250         break;
 251     case 0x41c: /* Interrupt clear */
 252         s->istate &= ~value;
 253         break;
 254     case 0x420: /* Alternate function select */
 255         mask = s->cr;
 256         s->afsel = (s->afsel & ~mask) | (value & mask);
 257         break;
 258     case 0x500: /* 2mA drive */
 259         s->dr2r = value & 0xff;
 260         break;
 261     case 0x504: /* 4mA drive */
 262         s->dr4r = value & 0xff;
 263         break;
 264     case 0x508: /* 8mA drive */
 265         s->dr8r = value & 0xff;
 266         break;
 267     case 0x50c: /* Open drain */
 268         s->odr = value & 0xff;
 269         break;
 270     case 0x510: /* Pull-up */
 271         s->pur = value & 0xff;
 272         break;
 273     case 0x514: /* Pull-down */
 274         s->pdr = value & 0xff;
 275         break;
 276     case 0x518: /* Slew rate control */
 277         s->slr = value & 0xff;
 278         break;
 279     case 0x51c: /* Digital enable */
 280         s->den = value & 0xff;
 281         break;
 282     case 0x520: /* Lock */
 283         s->locked = (value != 0xacce551);
 284         break;
 285     case 0x524: /* Commit */
 286         if (!s->locked)
 287             s->cr = value & 0xff;
 288         break;
 289     case 0x528:
 290         s->amsel = value & 0xff;
 291         break;
 292     default:
 293         goto err_out;
 294     }
 295     pl061_update(s);
 296     return;
 297 err_out:
 298     qemu_log_mask(LOG_GUEST_ERROR,
 299                   "pl061_write: Bad offset %x\n", (int)offset);
 300 }
 301
 302 static void pl061_reset(DeviceState *dev)
 303 {
 304     PL061State *s = PL061(dev);
 305
 306     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
 307     s->data = 0;
 308     s->old_out_data = 0;
 309     s->old_in_data = 0;
 310     s->dir = 0;
 311     s->isense = 0;
 312     s->ibe = 0;
 313     s->iev = 0;
 314     s->im = 0;
 315     s->istate = 0;
 316     s->afsel = 0;
 317     s->dr2r = 0xff;
 318     s->dr4r = 0;
 319     s->dr8r = 0;
 320     s->odr = 0;
 321     s->pur = 0;
 322     s->pdr = 0;
 323     s->slr = 0;
 324     s->den = 0;
 325     s->locked = 1;
 326     s->cr = 0xff;
 327     s->amsel = 0;
 328 }
 329
 330 static void pl061_set_irq(void * opaque, int irq, int level)
 331 {
 332     PL061State *s = (PL061State *)opaque;
 333     uint8_t mask;
 334
 335     mask = 1 << irq;
 336     if ((s->dir & mask) == 0) {
 337         s->data &= ~mask;
 338         if (level)
 339             s->data |= mask;
 340         pl061_update(s);
 341     }
 342 }
 343
 344 static const MemoryRegionOps pl061_ops = {
 345     .read = pl061_read,
 346     .write = pl061_write,
 347     .endianness = DEVICE_NATIVE_ENDIAN,
 348 };
 349
 350 static void pl061_luminary_init(Object *obj)
 351 {
 352     PL061State *s = PL061(obj);
 353
 354     s->id = pl061_id_luminary;
 355     s->rsvd_start = 0x52c;
 356 }
 357
 358 static void pl061_init(Object *obj)
 359 {
 360     PL061State *s = PL061(obj);
 361     DeviceState *dev = DEVICE(obj);
 362     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 363
 364     s->id = pl061_id;
 365     s->rsvd_start = 0x424;
 366
 367     memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
 368     sysbus_init_mmio(sbd, &s->iomem);
 369     sysbus_init_irq(sbd, &s->irq);
 370     qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS);
 371     qdev_init_gpio_out(dev, s->out, N_GPIOS);
 372 }
 373
 374 static void pl061_class_init(ObjectClass *klass, void *data)
 375 {
 376     DeviceClass *dc = DEVICE_CLASS(klass);
 377
 378     dc->vmsd = &vmstate_pl061;
 379     dc->reset = &pl061_reset;
 380 }
 381
 382 static const TypeInfo pl061_info = {
 383     .name          = TYPE_PL061,
 384     .parent        = TYPE_SYS_BUS_DEVICE,
 385     .instance_size = sizeof(PL061State),
 386     .instance_init = pl061_init,
 387     .class_init    = pl061_class_init,
 388 };
 389
 390 static const TypeInfo pl061_luminary_info = {
 391     .name          = "pl061_luminary",
 392     .parent        = TYPE_PL061,
 393     .instance_init = pl061_luminary_init,
 394 };
 395
 396 static void pl061_register_types(void)
 397 {
 398     type_register_static(&pl061_info);
 399     type_register_static(&pl061_luminary_info);
 400 }
 401
 402 type_init(pl061_register_types)