4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
51 static TCGv_i32 cpu_halted
;
52 static TCGv_i32 cpu_exception_index
;
54 static TCGv_env cpu_env
;
56 static char cpu_reg_names
[3*8*3 + 5*4];
57 static TCGv cpu_dregs
[8];
58 static TCGv cpu_aregs
[8];
59 static TCGv_i64 cpu_fregs
[8];
60 static TCGv_i64 cpu_macc
[4];
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
69 static TCGv NULL_QREG
;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy
;
74 #include "exec/gen-icount.h"
76 void m68k_tcg_init(void)
81 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
82 tcg_ctx
.tcg_env
= cpu_env
;
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
96 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
97 -offsetof(M68kCPU
, env
) +
98 offsetof(CPUState
, halted
), "HALTED");
99 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
100 -offsetof(M68kCPU
, env
) +
101 offsetof(CPUState
, exception_index
),
105 for (i
= 0; i
< 8; i
++) {
106 sprintf(p
, "D%d", i
);
107 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
108 offsetof(CPUM68KState
, dregs
[i
]), p
);
110 sprintf(p
, "A%d", i
);
111 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUM68KState
, aregs
[i
]), p
);
114 sprintf(p
, "F%d", i
);
115 cpu_fregs
[i
] = tcg_global_mem_new_i64(cpu_env
,
116 offsetof(CPUM68KState
, fregs
[i
]), p
);
119 for (i
= 0; i
< 4; i
++) {
120 sprintf(p
, "ACC%d", i
);
121 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
122 offsetof(CPUM68KState
, macc
[i
]), p
);
126 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
127 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
130 /* internal defines */
131 typedef struct DisasContext
{
133 target_ulong insn_pc
; /* Start of the current instruction. */
136 CCOp cc_op
; /* Current CC operation */
140 struct TranslationBlock
*tb
;
141 int singlestep_enabled
;
146 #define DISAS_JUMP_NEXT 4
148 #if defined(CONFIG_USER_ONLY)
151 #define IS_USER(s) s->user
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception
;
157 #define gen_last_qop NULL
159 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
179 static const uint8_t cc_op_live
[CC_OP_NB
] = {
180 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
181 [CC_OP_ADD
] = CCF_X
| CCF_N
| CCF_V
,
182 [CC_OP_SUB
] = CCF_X
| CCF_N
| CCF_V
,
183 [CC_OP_CMP
] = CCF_X
| CCF_N
| CCF_V
,
184 [CC_OP_LOGIC
] = CCF_X
| CCF_N
187 static void set_cc_op(DisasContext
*s
, CCOp op
)
189 CCOp old_op
= s
->cc_op
;
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
202 tcg_gen_discard_i32(QREG_CC_C
);
205 tcg_gen_discard_i32(QREG_CC_Z
);
208 tcg_gen_discard_i32(QREG_CC_V
);
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext
*s
)
215 if (!s
->cc_op_synced
) {
217 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
226 int index
= IS_USER(s
);
227 tmp
= tcg_temp_new_i32();
231 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
233 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
237 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
239 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
243 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
246 g_assert_not_reached();
248 gen_throws_exception
= gen_last_qop
;
252 static inline TCGv_i64
gen_load64(DisasContext
* s
, TCGv addr
)
255 int index
= IS_USER(s
);
256 tmp
= tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp
, addr
, index
);
258 gen_throws_exception
= gen_last_qop
;
262 /* Generate a store. */
263 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
265 int index
= IS_USER(s
);
268 tcg_gen_qemu_st8(val
, addr
, index
);
271 tcg_gen_qemu_st16(val
, addr
, index
);
275 tcg_gen_qemu_st32(val
, addr
, index
);
278 g_assert_not_reached();
280 gen_throws_exception
= gen_last_qop
;
283 static inline void gen_store64(DisasContext
*s
, TCGv addr
, TCGv_i64 val
)
285 int index
= IS_USER(s
);
286 tcg_gen_qemu_stf64(val
, addr
, index
);
287 gen_throws_exception
= gen_last_qop
;
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
301 if (what
== EA_STORE
) {
302 gen_store(s
, opsize
, addr
, val
);
305 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
313 im
= cpu_lduw_code(env
, s
->pc
);
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
321 return read_im16(env
, s
);
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
328 im
= read_im16(env
, s
) << 16;
329 im
|= 0xffff & read_im16(env
, s
);
333 /* Calculate and address index. */
334 static TCGv
gen_addr_index(uint16_t ext
, TCGv tmp
)
339 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
340 if ((ext
& 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp
, add
);
344 scale
= (ext
>> 9) & 3;
346 tcg_gen_shli_i32(tmp
, add
, scale
);
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
363 ext
= read_im16(env
, s
);
365 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
368 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
369 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
374 /* full extension word format */
375 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
378 if ((ext
& 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext
& 0x30) == 0x20) {
381 bd
= (int16_t)read_im16(env
, s
);
383 bd
= read_im32(env
, s
);
388 tmp
= tcg_temp_new();
389 if ((ext
& 0x44) == 0) {
391 add
= gen_addr_index(ext
, tmp
);
395 if ((ext
& 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base
)) {
398 base
= tcg_const_i32(offset
+ bd
);
401 if (!IS_NULL_QREG(add
)) {
402 tcg_gen_add_i32(tmp
, add
, base
);
408 if (!IS_NULL_QREG(add
)) {
410 tcg_gen_addi_i32(tmp
, add
, bd
);
414 add
= tcg_const_i32(bd
);
416 if ((ext
& 3) != 0) {
417 /* memory indirect */
418 base
= gen_load(s
, OS_LONG
, add
, 0);
419 if ((ext
& 0x44) == 4) {
420 add
= gen_addr_index(ext
, tmp
);
421 tcg_gen_add_i32(tmp
, add
, base
);
427 /* outer displacement */
428 if ((ext
& 3) == 2) {
429 od
= (int16_t)read_im16(env
, s
);
431 od
= read_im32(env
, s
);
437 tcg_gen_addi_i32(tmp
, add
, od
);
442 /* brief extension word format */
443 tmp
= tcg_temp_new();
444 add
= gen_addr_index(ext
, tmp
);
445 if (!IS_NULL_QREG(base
)) {
446 tcg_gen_add_i32(tmp
, add
, base
);
448 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
450 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
457 /* Evaluate all the CC flags. */
459 static void gen_flush_flags(DisasContext
*s
)
467 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
470 tmp
= tcg_const_i32(s
->cc_op
);
471 gen_helper_flush_flags(cpu_env
, tmp
);
476 /* Note that flush_flags also assigned to env->cc_op. */
477 s
->cc_op
= CC_OP_FLAGS
;
481 /* Sign or zero extend a value. */
483 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
488 tcg_gen_ext8s_i32(res
, val
);
490 tcg_gen_ext8u_i32(res
, val
);
495 tcg_gen_ext16s_i32(res
, val
);
497 tcg_gen_ext16u_i32(res
, val
);
501 tcg_gen_mov_i32(res
, val
);
504 g_assert_not_reached();
508 static TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
512 if (opsize
== OS_LONG
) {
515 tmp
= tcg_temp_new();
516 gen_ext(tmp
, val
, opsize
, sign
);
522 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
524 gen_ext(QREG_CC_N
, val
, opsize
, 1);
525 set_cc_op(s
, CC_OP_LOGIC
);
528 static void gen_update_cc_add(TCGv dest
, TCGv src
)
530 tcg_gen_mov_i32(QREG_CC_N
, dest
);
531 tcg_gen_mov_i32(QREG_CC_V
, src
);
534 static inline int opsize_bytes(int opsize
)
537 case OS_BYTE
: return 1;
538 case OS_WORD
: return 2;
539 case OS_LONG
: return 4;
540 case OS_SINGLE
: return 4;
541 case OS_DOUBLE
: return 8;
542 case OS_EXTENDED
: return 12;
543 case OS_PACKED
: return 12;
545 g_assert_not_reached();
549 static inline int insn_opsize(int insn
)
551 switch ((insn
>> 6) & 3) {
552 case 0: return OS_BYTE
;
553 case 1: return OS_WORD
;
554 case 2: return OS_LONG
;
556 g_assert_not_reached();
560 /* Assign value to a register. If the width is less than the register width
561 only the low part of the register is set. */
562 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
567 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
568 tmp
= tcg_temp_new();
569 tcg_gen_ext8u_i32(tmp
, val
);
570 tcg_gen_or_i32(reg
, reg
, tmp
);
573 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
574 tmp
= tcg_temp_new();
575 tcg_gen_ext16u_i32(tmp
, val
);
576 tcg_gen_or_i32(reg
, reg
, tmp
);
580 tcg_gen_mov_i32(reg
, val
);
583 g_assert_not_reached();
587 /* Generate code for an "effective address". Does not adjust the base
588 register for autoincrement addressing modes. */
589 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
597 switch ((insn
>> 3) & 7) {
598 case 0: /* Data register direct. */
599 case 1: /* Address register direct. */
601 case 2: /* Indirect register */
602 case 3: /* Indirect postincrement. */
603 return AREG(insn
, 0);
604 case 4: /* Indirect predecrememnt. */
606 tmp
= tcg_temp_new();
607 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
609 case 5: /* Indirect displacement. */
611 tmp
= tcg_temp_new();
612 ext
= read_im16(env
, s
);
613 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
615 case 6: /* Indirect index + displacement. */
617 return gen_lea_indexed(env
, s
, reg
);
620 case 0: /* Absolute short. */
621 offset
= (int16_t)read_im16(env
, s
);
622 return tcg_const_i32(offset
);
623 case 1: /* Absolute long. */
624 offset
= read_im32(env
, s
);
625 return tcg_const_i32(offset
);
626 case 2: /* pc displacement */
628 offset
+= (int16_t)read_im16(env
, s
);
629 return tcg_const_i32(offset
);
630 case 3: /* pc index+displacement. */
631 return gen_lea_indexed(env
, s
, NULL_QREG
);
632 case 4: /* Immediate. */
637 /* Should never happen. */
641 /* Helper function for gen_ea. Reuse the computed address between the
642 for read/write operands. */
643 static inline TCGv
gen_ea_once(CPUM68KState
*env
, DisasContext
*s
,
644 uint16_t insn
, int opsize
, TCGv val
,
645 TCGv
*addrp
, ea_what what
)
649 if (addrp
&& what
== EA_STORE
) {
652 tmp
= gen_lea(env
, s
, insn
, opsize
);
653 if (IS_NULL_QREG(tmp
))
658 return gen_ldst(s
, opsize
, tmp
, val
, what
);
661 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
662 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
663 ADDRP is non-null for readwrite operands. */
664 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
665 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
671 switch ((insn
>> 3) & 7) {
672 case 0: /* Data register direct. */
674 if (what
== EA_STORE
) {
675 gen_partset_reg(opsize
, reg
, val
);
678 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
680 case 1: /* Address register direct. */
682 if (what
== EA_STORE
) {
683 tcg_gen_mov_i32(reg
, val
);
686 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
688 case 2: /* Indirect register */
690 return gen_ldst(s
, opsize
, reg
, val
, what
);
691 case 3: /* Indirect postincrement. */
693 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
694 /* ??? This is not exception safe. The instruction may still
695 fault after this point. */
696 if (what
== EA_STORE
|| !addrp
)
697 tcg_gen_addi_i32(reg
, reg
, opsize_bytes(opsize
));
699 case 4: /* Indirect predecrememnt. */
702 if (addrp
&& what
== EA_STORE
) {
705 tmp
= gen_lea(env
, s
, insn
, opsize
);
706 if (IS_NULL_QREG(tmp
))
711 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
712 /* ??? This is not exception safe. The instruction may still
713 fault after this point. */
714 if (what
== EA_STORE
|| !addrp
) {
716 tcg_gen_mov_i32(reg
, tmp
);
720 case 5: /* Indirect displacement. */
721 case 6: /* Indirect index + displacement. */
722 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
725 case 0: /* Absolute short. */
726 case 1: /* Absolute long. */
727 case 2: /* pc displacement */
728 case 3: /* pc index+displacement. */
729 return gen_ea_once(env
, s
, insn
, opsize
, val
, addrp
, what
);
730 case 4: /* Immediate. */
731 /* Sign extend values for consistency. */
734 if (what
== EA_LOADS
) {
735 offset
= (int8_t)read_im8(env
, s
);
737 offset
= read_im8(env
, s
);
741 if (what
== EA_LOADS
) {
742 offset
= (int16_t)read_im16(env
, s
);
744 offset
= read_im16(env
, s
);
748 offset
= read_im32(env
, s
);
751 g_assert_not_reached();
753 return tcg_const_i32(offset
);
758 /* Should never happen. */
770 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
775 /* TODO: Optimize compare/branch pairs rather than always flushing
776 flag state to CC_OP_FLAGS. */
781 c
->v2
= tcg_const_i32(0);
787 tcond
= TCG_COND_NEVER
;
789 case 2: /* HI (!C && !Z) -> !(C || Z)*/
790 case 3: /* LS (C || Z) */
791 c
->v1
= tmp
= tcg_temp_new();
793 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
794 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
797 case 4: /* CC (!C) */
802 case 6: /* NE (!Z) */
807 case 8: /* VC (!V) */
812 case 10: /* PL (!N) */
813 case 11: /* MI (N) */
817 case 12: /* GE (!(N ^ V)) */
818 case 13: /* LT (N ^ V) */
819 c
->v1
= tmp
= tcg_temp_new();
821 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
824 case 14: /* GT (!(Z || (N ^ V))) */
825 case 15: /* LE (Z || (N ^ V)) */
826 c
->v1
= tmp
= tcg_temp_new();
828 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
829 tcg_gen_neg_i32(tmp
, tmp
);
830 tmp2
= tcg_temp_new();
831 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
832 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
837 /* Should ever happen. */
840 if ((cond
& 1) == 0) {
841 tcond
= tcg_invert_cond(tcond
);
846 static void free_cond(DisasCompare
*c
)
849 tcg_temp_free(c
->v1
);
852 tcg_temp_free(c
->v2
);
856 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
860 gen_cc_cond(&c
, s
, cond
);
862 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
872 cond
= (insn
>> 8) & 0xf;
873 gen_cc_cond(&c
, s
, cond
);
875 tmp
= tcg_temp_new();
876 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
880 tcg_gen_neg_i32(tmp
, tmp
);
881 tcg_gen_deposit_i32(reg
, reg
, tmp
, 0, 8);
885 /* Force a TB lookup after an instruction that changes the CPU state. */
886 static void gen_lookup_tb(DisasContext
*s
)
889 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
890 s
->is_jmp
= DISAS_UPDATE
;
893 /* Generate a jump to an immediate address. */
894 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
897 tcg_gen_movi_i32(QREG_PC
, dest
);
898 s
->is_jmp
= DISAS_JUMP
;
901 /* Generate a jump to the address in qreg DEST. */
902 static void gen_jmp(DisasContext
*s
, TCGv dest
)
905 tcg_gen_mov_i32(QREG_PC
, dest
);
906 s
->is_jmp
= DISAS_JUMP
;
909 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
912 gen_jmp_im(s
, where
);
913 gen_helper_raise_exception(cpu_env
, tcg_const_i32(nr
));
916 static inline void gen_addr_fault(DisasContext
*s
)
918 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
921 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
922 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
923 op_sign ? EA_LOADS : EA_LOADU); \
924 if (IS_NULL_QREG(result)) { \
930 #define DEST_EA(env, insn, opsize, val, addrp) do { \
931 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
932 if (IS_NULL_QREG(ea_result)) { \
938 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
940 #ifndef CONFIG_USER_ONLY
941 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
942 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
948 /* Generate a jump to an immediate address. */
949 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
951 if (unlikely(s
->singlestep_enabled
)) {
952 gen_exception(s
, dest
, EXCP_DEBUG
);
953 } else if (use_goto_tb(s
, dest
)) {
955 tcg_gen_movi_i32(QREG_PC
, dest
);
956 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
961 s
->is_jmp
= DISAS_TB_JUMP
;
964 DISAS_INSN(undef_mac
)
966 gen_exception(s
, s
->pc
- 2, EXCP_LINEA
);
969 DISAS_INSN(undef_fpu
)
971 gen_exception(s
, s
->pc
- 2, EXCP_LINEF
);
976 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
978 gen_exception(s
, s
->pc
- 2, EXCP_UNSUPPORTED
);
979 cpu_abort(CPU(cpu
), "Illegal instruction: %04x @ %08x", insn
, s
->pc
- 2);
989 sign
= (insn
& 0x100) != 0;
991 tmp
= tcg_temp_new();
993 tcg_gen_ext16s_i32(tmp
, reg
);
995 tcg_gen_ext16u_i32(tmp
, reg
);
996 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
997 tcg_gen_mul_i32(tmp
, tmp
, src
);
998 tcg_gen_mov_i32(reg
, tmp
);
999 gen_logic_cc(s
, tmp
, OS_WORD
);
1009 sign
= (insn
& 0x100) != 0;
1010 reg
= DREG(insn
, 9);
1012 tcg_gen_ext16s_i32(QREG_DIV1
, reg
);
1014 tcg_gen_ext16u_i32(QREG_DIV1
, reg
);
1016 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1017 tcg_gen_mov_i32(QREG_DIV2
, src
);
1019 gen_helper_divs(cpu_env
, tcg_const_i32(1));
1021 gen_helper_divu(cpu_env
, tcg_const_i32(1));
1024 tmp
= tcg_temp_new();
1025 src
= tcg_temp_new();
1026 tcg_gen_ext16u_i32(tmp
, QREG_DIV1
);
1027 tcg_gen_shli_i32(src
, QREG_DIV2
, 16);
1028 tcg_gen_or_i32(reg
, tmp
, src
);
1030 set_cc_op(s
, CC_OP_FLAGS
);
1040 ext
= read_im16(env
, s
);
1042 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1045 num
= DREG(ext
, 12);
1047 tcg_gen_mov_i32(QREG_DIV1
, num
);
1048 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1049 tcg_gen_mov_i32(QREG_DIV2
, den
);
1051 gen_helper_divs(cpu_env
, tcg_const_i32(0));
1053 gen_helper_divu(cpu_env
, tcg_const_i32(0));
1055 if ((ext
& 7) == ((ext
>> 12) & 7)) {
1057 tcg_gen_mov_i32 (reg
, QREG_DIV1
);
1060 tcg_gen_mov_i32 (reg
, QREG_DIV2
);
1062 set_cc_op(s
, CC_OP_FLAGS
);
1074 add
= (insn
& 0x4000) != 0;
1075 reg
= DREG(insn
, 9);
1076 dest
= tcg_temp_new();
1078 SRC_EA(env
, tmp
, OS_LONG
, 0, &addr
);
1082 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1085 tcg_gen_add_i32(dest
, tmp
, src
);
1086 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1087 set_cc_op(s
, CC_OP_ADD
);
1089 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1090 tcg_gen_sub_i32(dest
, tmp
, src
);
1091 set_cc_op(s
, CC_OP_SUB
);
1093 gen_update_cc_add(dest
, src
);
1095 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1097 tcg_gen_mov_i32(reg
, dest
);
1102 /* Reverse the order of the bits in REG. */
1106 reg
= DREG(insn
, 0);
1107 gen_helper_bitrev(reg
, reg
);
1110 DISAS_INSN(bitop_reg
)
1120 if ((insn
& 0x38) != 0)
1124 op
= (insn
>> 6) & 3;
1128 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1129 src2
= DREG(insn
, 9);
1130 dest
= tcg_temp_new();
1132 tmp
= tcg_temp_new();
1133 if (opsize
== OS_BYTE
)
1134 tcg_gen_andi_i32(tmp
, src2
, 7);
1136 tcg_gen_andi_i32(tmp
, src2
, 31);
1138 src2
= tcg_const_i32(1);
1139 tcg_gen_shl_i32(src2
, src2
, tmp
);
1142 tcg_gen_and_i32(QREG_CC_Z
, src1
, src2
);
1146 tcg_gen_xor_i32(dest
, src1
, src2
);
1149 tcg_gen_andc_i32(dest
, src1
, src2
);
1152 tcg_gen_or_i32(dest
, src1
, src2
);
1157 tcg_temp_free(src2
);
1159 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1161 tcg_temp_free(dest
);
1167 reg
= DREG(insn
, 0);
1169 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1170 gen_logic_cc(s
, reg
, OS_LONG
);
1173 static void gen_push(DisasContext
*s
, TCGv val
)
1177 tmp
= tcg_temp_new();
1178 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1179 gen_store(s
, OS_LONG
, tmp
, val
);
1180 tcg_gen_mov_i32(QREG_SP
, tmp
);
1192 mask
= read_im16(env
, s
);
1193 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1194 if (IS_NULL_QREG(tmp
)) {
1198 addr
= tcg_temp_new();
1199 tcg_gen_mov_i32(addr
, tmp
);
1200 is_load
= ((insn
& 0x0400) != 0);
1201 for (i
= 0; i
< 16; i
++, mask
>>= 1) {
1208 tmp
= gen_load(s
, OS_LONG
, addr
, 0);
1209 tcg_gen_mov_i32(reg
, tmp
);
1211 gen_store(s
, OS_LONG
, addr
, reg
);
1214 tcg_gen_addi_i32(addr
, addr
, 4);
1219 DISAS_INSN(bitop_im
)
1229 if ((insn
& 0x38) != 0)
1233 op
= (insn
>> 6) & 3;
1235 bitnum
= read_im16(env
, s
);
1236 if (bitnum
& 0xff00) {
1237 disas_undef(env
, s
, insn
);
1243 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1245 if (opsize
== OS_BYTE
)
1251 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
1254 tmp
= tcg_temp_new();
1257 tcg_gen_xori_i32(tmp
, src1
, mask
);
1260 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
1263 tcg_gen_ori_i32(tmp
, src1
, mask
);
1268 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
1273 DISAS_INSN(arith_im
)
1281 op
= (insn
>> 9) & 7;
1282 SRC_EA(env
, src1
, OS_LONG
, 0, (op
== 6) ? NULL
: &addr
);
1283 im
= read_im32(env
, s
);
1284 dest
= tcg_temp_new();
1287 tcg_gen_ori_i32(dest
, src1
, im
);
1288 gen_logic_cc(s
, dest
, OS_LONG
);
1291 tcg_gen_andi_i32(dest
, src1
, im
);
1292 gen_logic_cc(s
, dest
, OS_LONG
);
1295 tcg_gen_mov_i32(dest
, src1
);
1296 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1297 tcg_gen_subi_i32(dest
, dest
, im
);
1298 gen_update_cc_add(dest
, tcg_const_i32(im
));
1299 set_cc_op(s
, CC_OP_SUB
);
1302 tcg_gen_mov_i32(dest
, src1
);
1303 tcg_gen_addi_i32(dest
, dest
, im
);
1304 gen_update_cc_add(dest
, tcg_const_i32(im
));
1305 tcg_gen_setcondi_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
1306 set_cc_op(s
, CC_OP_ADD
);
1309 tcg_gen_xori_i32(dest
, src1
, im
);
1310 gen_logic_cc(s
, dest
, OS_LONG
);
1313 gen_update_cc_add(src1
, tcg_const_i32(im
));
1314 set_cc_op(s
, CC_OP_CMP
);
1320 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1328 reg
= DREG(insn
, 0);
1329 tcg_gen_bswap32_i32(reg
, reg
);
1339 switch (insn
>> 12) {
1340 case 1: /* move.b */
1343 case 2: /* move.l */
1346 case 3: /* move.w */
1352 SRC_EA(env
, src
, opsize
, 1, NULL
);
1353 op
= (insn
>> 6) & 7;
1356 /* The value will already have been sign extended. */
1357 dest
= AREG(insn
, 9);
1358 tcg_gen_mov_i32(dest
, src
);
1362 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
1363 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
1364 /* This will be correct because loads sign extend. */
1365 gen_logic_cc(s
, src
, opsize
);
1374 reg
= DREG(insn
, 0);
1375 gen_helper_subx_cc(reg
, cpu_env
, tcg_const_i32(0), reg
);
1383 reg
= AREG(insn
, 9);
1384 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1385 if (IS_NULL_QREG(tmp
)) {
1389 tcg_gen_mov_i32(reg
, tmp
);
1396 opsize
= insn_opsize(insn
);
1397 DEST_EA(env
, insn
, opsize
, tcg_const_i32(0), NULL
);
1398 gen_logic_cc(s
, tcg_const_i32(0), opsize
);
1401 static TCGv
gen_get_ccr(DisasContext
*s
)
1407 dest
= tcg_temp_new();
1408 gen_helper_get_ccr(dest
, cpu_env
);
1412 DISAS_INSN(move_from_ccr
)
1416 ccr
= gen_get_ccr(s
);
1417 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
1425 reg
= DREG(insn
, 0);
1426 src1
= tcg_temp_new();
1427 tcg_gen_mov_i32(src1
, reg
);
1428 tcg_gen_neg_i32(reg
, src1
);
1429 gen_update_cc_add(reg
, src1
);
1430 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, src1
, 0);
1431 set_cc_op(s
, CC_OP_SUB
);
1434 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
1437 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
1438 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
1439 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
1440 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
1441 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
1443 gen_helper_set_sr(cpu_env
, tcg_const_i32(val
));
1445 set_cc_op(s
, CC_OP_FLAGS
);
1448 static void gen_set_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1451 if ((insn
& 0x38) == 0) {
1453 gen_helper_set_ccr(cpu_env
, DREG(insn
, 0));
1455 gen_helper_set_sr(cpu_env
, DREG(insn
, 0));
1457 set_cc_op(s
, CC_OP_FLAGS
);
1458 } else if ((insn
& 0x3f) == 0x3c) {
1460 val
= read_im16(env
, s
);
1461 gen_set_sr_im(s
, val
, ccr_only
);
1463 disas_undef(env
, s
, insn
);
1468 DISAS_INSN(move_to_ccr
)
1470 gen_set_sr(env
, s
, insn
, 1);
1477 reg
= DREG(insn
, 0);
1478 tcg_gen_not_i32(reg
, reg
);
1479 gen_logic_cc(s
, reg
, OS_LONG
);
1488 src1
= tcg_temp_new();
1489 src2
= tcg_temp_new();
1490 reg
= DREG(insn
, 0);
1491 tcg_gen_shli_i32(src1
, reg
, 16);
1492 tcg_gen_shri_i32(src2
, reg
, 16);
1493 tcg_gen_or_i32(reg
, src1
, src2
);
1494 gen_logic_cc(s
, reg
, OS_LONG
);
1501 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1502 if (IS_NULL_QREG(tmp
)) {
1515 reg
= DREG(insn
, 0);
1516 op
= (insn
>> 6) & 7;
1517 tmp
= tcg_temp_new();
1519 tcg_gen_ext16s_i32(tmp
, reg
);
1521 tcg_gen_ext8s_i32(tmp
, reg
);
1523 gen_partset_reg(OS_WORD
, reg
, tmp
);
1525 tcg_gen_mov_i32(reg
, tmp
);
1526 gen_logic_cc(s
, tmp
, OS_LONG
);
1534 opsize
= insn_opsize(insn
);
1535 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
1536 gen_logic_cc(s
, tmp
, opsize
);
1541 /* Implemented as a NOP. */
1546 gen_exception(s
, s
->pc
- 2, EXCP_ILLEGAL
);
1549 /* ??? This should be atomic. */
1556 dest
= tcg_temp_new();
1557 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
1558 gen_logic_cc(s
, src1
, OS_BYTE
);
1559 tcg_gen_ori_i32(dest
, src1
, 0x80);
1560 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1570 /* The upper 32 bits of the product are discarded, so
1571 muls.l and mulu.l are functionally equivalent. */
1572 ext
= read_im16(env
, s
);
1574 gen_exception(s
, s
->pc
- 4, EXCP_UNSUPPORTED
);
1577 reg
= DREG(ext
, 12);
1578 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
1579 dest
= tcg_temp_new();
1580 tcg_gen_mul_i32(dest
, src1
, reg
);
1581 tcg_gen_mov_i32(reg
, dest
);
1582 /* Unlike m68k, coldfire always clears the overflow bit. */
1583 gen_logic_cc(s
, dest
, OS_LONG
);
1592 offset
= cpu_ldsw_code(env
, s
->pc
);
1594 reg
= AREG(insn
, 0);
1595 tmp
= tcg_temp_new();
1596 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1597 gen_store(s
, OS_LONG
, tmp
, reg
);
1598 if ((insn
& 7) != 7)
1599 tcg_gen_mov_i32(reg
, tmp
);
1600 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
1609 src
= tcg_temp_new();
1610 reg
= AREG(insn
, 0);
1611 tcg_gen_mov_i32(src
, reg
);
1612 tmp
= gen_load(s
, OS_LONG
, src
, 0);
1613 tcg_gen_mov_i32(reg
, tmp
);
1614 tcg_gen_addi_i32(QREG_SP
, src
, 4);
1625 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
1626 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
1634 /* Load the target address first to ensure correct exception
1636 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
1637 if (IS_NULL_QREG(tmp
)) {
1641 if ((insn
& 0x40) == 0) {
1643 gen_push(s
, tcg_const_i32(s
->pc
));
1656 SRC_EA(env
, src1
, OS_LONG
, 0, &addr
);
1657 val
= (insn
>> 9) & 7;
1660 dest
= tcg_temp_new();
1661 tcg_gen_mov_i32(dest
, src1
);
1662 if ((insn
& 0x38) == 0x08) {
1663 /* Don't update condition codes if the destination is an
1664 address register. */
1665 if (insn
& 0x0100) {
1666 tcg_gen_subi_i32(dest
, dest
, val
);
1668 tcg_gen_addi_i32(dest
, dest
, val
);
1671 src2
= tcg_const_i32(val
);
1672 if (insn
& 0x0100) {
1673 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1674 tcg_gen_sub_i32(dest
, dest
, src2
);
1675 set_cc_op(s
, CC_OP_SUB
);
1677 tcg_gen_add_i32(dest
, dest
, src2
);
1678 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src2
);
1679 set_cc_op(s
, CC_OP_ADD
);
1681 gen_update_cc_add(dest
, src2
);
1683 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1689 case 2: /* One extension word. */
1692 case 3: /* Two extension words. */
1695 case 4: /* No extension words. */
1698 disas_undef(env
, s
, insn
);
1710 op
= (insn
>> 8) & 0xf;
1711 offset
= (int8_t)insn
;
1713 offset
= (int16_t)read_im16(env
, s
);
1714 } else if (offset
== -1) {
1715 offset
= read_im32(env
, s
);
1719 gen_push(s
, tcg_const_i32(s
->pc
));
1723 l1
= gen_new_label();
1724 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
1725 gen_jmp_tb(s
, 1, base
+ offset
);
1727 gen_jmp_tb(s
, 0, s
->pc
);
1729 /* Unconditional branch. */
1730 gen_jmp_tb(s
, 0, base
+ offset
);
1739 tcg_gen_movi_i32(DREG(insn
, 9), val
);
1740 gen_logic_cc(s
, tcg_const_i32(val
), OS_LONG
);
1753 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
1754 reg
= DREG(insn
, 9);
1755 tcg_gen_mov_i32(reg
, src
);
1756 gen_logic_cc(s
, src
, opsize
);
1766 reg
= DREG(insn
, 9);
1767 dest
= tcg_temp_new();
1769 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1770 tcg_gen_or_i32(dest
, src
, reg
);
1771 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1773 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1774 tcg_gen_or_i32(dest
, src
, reg
);
1775 tcg_gen_mov_i32(reg
, dest
);
1777 gen_logic_cc(s
, dest
, OS_LONG
);
1785 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1786 reg
= AREG(insn
, 9);
1787 tcg_gen_sub_i32(reg
, reg
, src
);
1796 reg
= DREG(insn
, 9);
1797 src
= DREG(insn
, 0);
1798 gen_helper_subx_cc(reg
, cpu_env
, reg
, src
);
1806 val
= (insn
>> 9) & 7;
1809 src
= tcg_const_i32(val
);
1810 gen_logic_cc(s
, src
, OS_LONG
);
1811 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
1820 opsize
= insn_opsize(insn
);
1821 SRC_EA(env
, src
, opsize
, -1, NULL
);
1822 reg
= DREG(insn
, 9);
1823 gen_update_cc_add(reg
, src
);
1824 set_cc_op(s
, CC_OP_CMP
);
1838 SRC_EA(env
, src
, opsize
, 1, NULL
);
1839 reg
= AREG(insn
, 9);
1840 gen_update_cc_add(reg
, src
);
1841 set_cc_op(s
, CC_OP_CMP
);
1851 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1852 reg
= DREG(insn
, 9);
1853 dest
= tcg_temp_new();
1854 tcg_gen_xor_i32(dest
, src
, reg
);
1855 gen_logic_cc(s
, dest
, OS_LONG
);
1856 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1866 reg
= DREG(insn
, 9);
1867 dest
= tcg_temp_new();
1869 SRC_EA(env
, src
, OS_LONG
, 0, &addr
);
1870 tcg_gen_and_i32(dest
, src
, reg
);
1871 DEST_EA(env
, insn
, OS_LONG
, dest
, &addr
);
1873 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1874 tcg_gen_and_i32(dest
, src
, reg
);
1875 tcg_gen_mov_i32(reg
, dest
);
1877 gen_logic_cc(s
, dest
, OS_LONG
);
1885 SRC_EA(env
, src
, OS_LONG
, 0, NULL
);
1886 reg
= AREG(insn
, 9);
1887 tcg_gen_add_i32(reg
, reg
, src
);
1896 reg
= DREG(insn
, 9);
1897 src
= DREG(insn
, 0);
1898 gen_helper_addx_cc(reg
, cpu_env
, reg
, src
);
1901 /* TODO: This could be implemented without helper functions. */
1902 DISAS_INSN(shift_im
)
1908 set_cc_op(s
, CC_OP_FLAGS
);
1910 reg
= DREG(insn
, 0);
1911 tmp
= (insn
>> 9) & 7;
1914 shift
= tcg_const_i32(tmp
);
1915 /* No need to flush flags becuse we know we will set C flag. */
1917 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1920 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1922 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1927 DISAS_INSN(shift_reg
)
1932 reg
= DREG(insn
, 0);
1933 shift
= DREG(insn
, 9);
1935 gen_helper_shl_cc(reg
, cpu_env
, reg
, shift
);
1938 gen_helper_shr_cc(reg
, cpu_env
, reg
, shift
);
1940 gen_helper_sar_cc(reg
, cpu_env
, reg
, shift
);
1943 set_cc_op(s
, CC_OP_FLAGS
);
1949 reg
= DREG(insn
, 0);
1950 gen_logic_cc(s
, reg
, OS_LONG
);
1951 gen_helper_ff1(reg
, reg
);
1954 static TCGv
gen_get_sr(DisasContext
*s
)
1959 ccr
= gen_get_ccr(s
);
1960 sr
= tcg_temp_new();
1961 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
1962 tcg_gen_or_i32(sr
, sr
, ccr
);
1972 ext
= read_im16(env
, s
);
1973 if (ext
!= 0x46FC) {
1974 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
1977 ext
= read_im16(env
, s
);
1978 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
1979 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
1982 gen_push(s
, gen_get_sr(s
));
1983 gen_set_sr_im(s
, ext
, 0);
1986 DISAS_INSN(move_from_sr
)
1990 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
1991 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
1995 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
1998 DISAS_INSN(move_to_sr
)
2001 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2004 gen_set_sr(env
, s
, insn
, 0);
2008 DISAS_INSN(move_from_usp
)
2011 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2014 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
2015 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2018 DISAS_INSN(move_to_usp
)
2021 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2024 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
2025 offsetof(CPUM68KState
, sp
[M68K_USP
]));
2030 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
2038 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2042 ext
= read_im16(env
, s
);
2044 gen_set_sr_im(s
, ext
, 0);
2045 tcg_gen_movi_i32(cpu_halted
, 1);
2046 gen_exception(s
, s
->pc
, EXCP_HLT
);
2052 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2055 gen_exception(s
, s
->pc
- 2, EXCP_RTE
);
2064 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2068 ext
= read_im16(env
, s
);
2071 reg
= AREG(ext
, 12);
2073 reg
= DREG(ext
, 12);
2075 gen_helper_movec(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
2082 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2085 /* ICache fetch. Implement as no-op. */
2091 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2094 /* Cache push/invalidate. Implement as no-op. */
2099 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2104 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2107 gen_exception(s
, s
->pc
- 2, EXCP_PRIVILEGE
);
2110 /* TODO: Implement wdebug. */
2111 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
2116 gen_exception(s
, s
->pc
- 2, EXCP_TRAP0
+ (insn
& 0xf));
2119 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2120 immediately before the next FP instruction is executed. */
2134 ext
= read_im16(env
, s
);
2135 opmode
= ext
& 0x7f;
2136 switch ((ext
>> 13) & 7) {
2141 case 3: /* fmove out */
2143 tmp32
= tcg_temp_new_i32();
2145 /* ??? TODO: Proper behavior on overflow. */
2146 switch ((ext
>> 10) & 7) {
2149 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2153 gen_helper_f64_to_f32(tmp32
, cpu_env
, src
);
2157 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2159 case 5: /* OS_DOUBLE */
2160 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2161 switch ((insn
>> 3) & 7) {
2166 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2169 offset
= cpu_ldsw_code(env
, s
->pc
);
2171 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2176 gen_store64(s
, tmp32
, src
);
2177 switch ((insn
>> 3) & 7) {
2179 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2180 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2183 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2186 tcg_temp_free_i32(tmp32
);
2190 gen_helper_f64_to_i32(tmp32
, cpu_env
, src
);
2195 DEST_EA(env
, insn
, opsize
, tmp32
, NULL
);
2196 tcg_temp_free_i32(tmp32
);
2198 case 4: /* fmove to control register. */
2199 switch ((ext
>> 10) & 7) {
2201 /* Not implemented. Ignore writes. */
2206 cpu_abort(NULL
, "Unimplemented: fmove to control %d",
2210 case 5: /* fmove from control register. */
2211 switch ((ext
>> 10) & 7) {
2213 /* Not implemented. Always return zero. */
2214 tmp32
= tcg_const_i32(0);
2219 cpu_abort(NULL
, "Unimplemented: fmove from control %d",
2223 DEST_EA(env
, insn
, OS_LONG
, tmp32
, NULL
);
2225 case 6: /* fmovem */
2231 if ((ext
& 0x1f00) != 0x1000 || (ext
& 0xff) == 0)
2233 tmp32
= gen_lea(env
, s
, insn
, OS_LONG
);
2234 if (IS_NULL_QREG(tmp32
)) {
2238 addr
= tcg_temp_new_i32();
2239 tcg_gen_mov_i32(addr
, tmp32
);
2241 for (i
= 0; i
< 8; i
++) {
2244 if (ext
& (1 << 13)) {
2246 tcg_gen_qemu_stf64(dest
, addr
, IS_USER(s
));
2249 tcg_gen_qemu_ldf64(dest
, addr
, IS_USER(s
));
2251 if (ext
& (mask
- 1))
2252 tcg_gen_addi_i32(addr
, addr
, 8);
2256 tcg_temp_free_i32(addr
);
2260 if (ext
& (1 << 14)) {
2261 /* Source effective address. */
2262 switch ((ext
>> 10) & 7) {
2263 case 0: opsize
= OS_LONG
; break;
2264 case 1: opsize
= OS_SINGLE
; break;
2265 case 4: opsize
= OS_WORD
; break;
2266 case 5: opsize
= OS_DOUBLE
; break;
2267 case 6: opsize
= OS_BYTE
; break;
2271 if (opsize
== OS_DOUBLE
) {
2272 tmp32
= tcg_temp_new_i32();
2273 tcg_gen_mov_i32(tmp32
, AREG(insn
, 0));
2274 switch ((insn
>> 3) & 7) {
2279 tcg_gen_addi_i32(tmp32
, tmp32
, -8);
2282 offset
= cpu_ldsw_code(env
, s
->pc
);
2284 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2287 offset
= cpu_ldsw_code(env
, s
->pc
);
2288 offset
+= s
->pc
- 2;
2290 tcg_gen_addi_i32(tmp32
, tmp32
, offset
);
2295 src
= gen_load64(s
, tmp32
);
2296 switch ((insn
>> 3) & 7) {
2298 tcg_gen_addi_i32(tmp32
, tmp32
, 8);
2299 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2302 tcg_gen_mov_i32(AREG(insn
, 0), tmp32
);
2305 tcg_temp_free_i32(tmp32
);
2307 SRC_EA(env
, tmp32
, opsize
, 1, NULL
);
2308 src
= tcg_temp_new_i64();
2313 gen_helper_i32_to_f64(src
, cpu_env
, tmp32
);
2316 gen_helper_f32_to_f64(src
, cpu_env
, tmp32
);
2321 /* Source register. */
2322 src
= FREG(ext
, 10);
2324 dest
= FREG(ext
, 7);
2325 res
= tcg_temp_new_i64();
2327 tcg_gen_mov_f64(res
, dest
);
2331 case 0: case 0x40: case 0x44: /* fmove */
2332 tcg_gen_mov_f64(res
, src
);
2335 gen_helper_iround_f64(res
, cpu_env
, src
);
2338 case 3: /* fintrz */
2339 gen_helper_itrunc_f64(res
, cpu_env
, src
);
2342 case 4: case 0x41: case 0x45: /* fsqrt */
2343 gen_helper_sqrt_f64(res
, cpu_env
, src
);
2345 case 0x18: case 0x58: case 0x5c: /* fabs */
2346 gen_helper_abs_f64(res
, src
);
2348 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2349 gen_helper_chs_f64(res
, src
);
2351 case 0x20: case 0x60: case 0x64: /* fdiv */
2352 gen_helper_div_f64(res
, cpu_env
, res
, src
);
2354 case 0x22: case 0x62: case 0x66: /* fadd */
2355 gen_helper_add_f64(res
, cpu_env
, res
, src
);
2357 case 0x23: case 0x63: case 0x67: /* fmul */
2358 gen_helper_mul_f64(res
, cpu_env
, res
, src
);
2360 case 0x28: case 0x68: case 0x6c: /* fsub */
2361 gen_helper_sub_f64(res
, cpu_env
, res
, src
);
2363 case 0x38: /* fcmp */
2364 gen_helper_sub_cmp_f64(res
, cpu_env
, res
, src
);
2368 case 0x3a: /* ftst */
2369 tcg_gen_mov_f64(res
, src
);
2376 if (ext
& (1 << 14)) {
2377 tcg_temp_free_i64(src
);
2380 if (opmode
& 0x40) {
2381 if ((opmode
& 0x4) != 0)
2383 } else if ((s
->fpcr
& M68K_FPCR_PREC
) == 0) {
2388 TCGv tmp
= tcg_temp_new_i32();
2389 gen_helper_f64_to_f32(tmp
, cpu_env
, res
);
2390 gen_helper_f32_to_f64(res
, cpu_env
, tmp
);
2391 tcg_temp_free_i32(tmp
);
2393 tcg_gen_mov_f64(QREG_FP_RESULT
, res
);
2395 tcg_gen_mov_f64(dest
, res
);
2397 tcg_temp_free_i64(res
);
2400 /* FIXME: Is this right for offset addressing modes? */
2402 disas_undef_fpu(env
, s
, insn
);
2413 offset
= cpu_ldsw_code(env
, s
->pc
);
2415 if (insn
& (1 << 6)) {
2416 offset
= (offset
<< 16) | read_im16(env
, s
);
2419 l1
= gen_new_label();
2420 /* TODO: Raise BSUN exception. */
2421 flag
= tcg_temp_new();
2422 gen_helper_compare_f64(flag
, cpu_env
, QREG_FP_RESULT
);
2423 /* Jump to l1 if condition is true. */
2424 switch (insn
& 0xf) {
2427 case 1: /* eq (=0) */
2428 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2430 case 2: /* ogt (=1) */
2431 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(1), l1
);
2433 case 3: /* oge (=0 or =1) */
2434 tcg_gen_brcond_i32(TCG_COND_LEU
, flag
, tcg_const_i32(1), l1
);
2436 case 4: /* olt (=-1) */
2437 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(0), l1
);
2439 case 5: /* ole (=-1 or =0) */
2440 tcg_gen_brcond_i32(TCG_COND_LE
, flag
, tcg_const_i32(0), l1
);
2442 case 6: /* ogl (=-1 or =1) */
2443 tcg_gen_andi_i32(flag
, flag
, 1);
2444 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2446 case 7: /* or (=2) */
2447 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(2), l1
);
2449 case 8: /* un (<2) */
2450 tcg_gen_brcond_i32(TCG_COND_LT
, flag
, tcg_const_i32(2), l1
);
2452 case 9: /* ueq (=0 or =2) */
2453 tcg_gen_andi_i32(flag
, flag
, 1);
2454 tcg_gen_brcond_i32(TCG_COND_EQ
, flag
, tcg_const_i32(0), l1
);
2456 case 10: /* ugt (>0) */
2457 tcg_gen_brcond_i32(TCG_COND_GT
, flag
, tcg_const_i32(0), l1
);
2459 case 11: /* uge (>=0) */
2460 tcg_gen_brcond_i32(TCG_COND_GE
, flag
, tcg_const_i32(0), l1
);
2462 case 12: /* ult (=-1 or =2) */
2463 tcg_gen_brcond_i32(TCG_COND_GEU
, flag
, tcg_const_i32(2), l1
);
2465 case 13: /* ule (!=1) */
2466 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(1), l1
);
2468 case 14: /* ne (!=0) */
2469 tcg_gen_brcond_i32(TCG_COND_NE
, flag
, tcg_const_i32(0), l1
);
2475 gen_jmp_tb(s
, 0, s
->pc
);
2477 gen_jmp_tb(s
, 1, addr
+ offset
);
2480 DISAS_INSN(frestore
)
2482 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2484 /* TODO: Implement frestore. */
2485 cpu_abort(CPU(cpu
), "FRESTORE not implemented");
2490 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
2492 /* TODO: Implement fsave. */
2493 cpu_abort(CPU(cpu
), "FSAVE not implemented");
2496 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
2498 TCGv tmp
= tcg_temp_new();
2499 if (s
->env
->macsr
& MACSR_FI
) {
2501 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
2503 tcg_gen_shli_i32(tmp
, val
, 16);
2504 } else if (s
->env
->macsr
& MACSR_SU
) {
2506 tcg_gen_sari_i32(tmp
, val
, 16);
2508 tcg_gen_ext16s_i32(tmp
, val
);
2511 tcg_gen_shri_i32(tmp
, val
, 16);
2513 tcg_gen_ext16u_i32(tmp
, val
);
2518 static void gen_mac_clear_flags(void)
2520 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
2521 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
2537 s
->mactmp
= tcg_temp_new_i64();
2541 ext
= read_im16(env
, s
);
2543 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
2544 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
2545 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
2546 disas_undef(env
, s
, insn
);
2550 /* MAC with load. */
2551 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2552 addr
= tcg_temp_new();
2553 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
2554 /* Load the value now to ensure correct exception behavior.
2555 Perform writeback after reading the MAC inputs. */
2556 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
2559 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
2560 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
2562 loadval
= addr
= NULL_QREG
;
2563 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2564 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2567 gen_mac_clear_flags();
2570 /* Disabled because conditional branches clobber temporary vars. */
2571 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
2572 /* Skip the multiply if we know we will ignore it. */
2573 l1
= gen_new_label();
2574 tmp
= tcg_temp_new();
2575 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
2576 gen_op_jmp_nz32(tmp
, l1
);
2580 if ((ext
& 0x0800) == 0) {
2582 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
2583 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
2585 if (s
->env
->macsr
& MACSR_FI
) {
2586 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
2588 if (s
->env
->macsr
& MACSR_SU
)
2589 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
2591 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
2592 switch ((ext
>> 9) & 3) {
2594 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
2597 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
2603 /* Save the overflow flag from the multiply. */
2604 saved_flags
= tcg_temp_new();
2605 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
2607 saved_flags
= NULL_QREG
;
2611 /* Disabled because conditional branches clobber temporary vars. */
2612 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
2613 /* Skip the accumulate if the value is already saturated. */
2614 l1
= gen_new_label();
2615 tmp
= tcg_temp_new();
2616 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2617 gen_op_jmp_nz32(tmp
, l1
);
2622 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2624 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2626 if (s
->env
->macsr
& MACSR_FI
)
2627 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2628 else if (s
->env
->macsr
& MACSR_SU
)
2629 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2631 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2634 /* Disabled because conditional branches clobber temporary vars. */
2640 /* Dual accumulate variant. */
2641 acc
= (ext
>> 2) & 3;
2642 /* Restore the overflow flag from the multiplier. */
2643 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
2645 /* Disabled because conditional branches clobber temporary vars. */
2646 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
2647 /* Skip the accumulate if the value is already saturated. */
2648 l1
= gen_new_label();
2649 tmp
= tcg_temp_new();
2650 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
2651 gen_op_jmp_nz32(tmp
, l1
);
2655 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2657 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
2658 if (s
->env
->macsr
& MACSR_FI
)
2659 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
2660 else if (s
->env
->macsr
& MACSR_SU
)
2661 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
2663 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
2665 /* Disabled because conditional branches clobber temporary vars. */
2670 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
2674 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
2675 tcg_gen_mov_i32(rw
, loadval
);
2676 /* FIXME: Should address writeback happen with the masked or
2678 switch ((insn
>> 3) & 7) {
2679 case 3: /* Post-increment. */
2680 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
2682 case 4: /* Pre-decrement. */
2683 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2688 DISAS_INSN(from_mac
)
2694 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2695 accnum
= (insn
>> 9) & 3;
2696 acc
= MACREG(accnum
);
2697 if (s
->env
->macsr
& MACSR_FI
) {
2698 gen_helper_get_macf(rx
, cpu_env
, acc
);
2699 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
2700 tcg_gen_extrl_i64_i32(rx
, acc
);
2701 } else if (s
->env
->macsr
& MACSR_SU
) {
2702 gen_helper_get_macs(rx
, acc
);
2704 gen_helper_get_macu(rx
, acc
);
2707 tcg_gen_movi_i64(acc
, 0);
2708 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2712 DISAS_INSN(move_mac
)
2714 /* FIXME: This can be done without a helper. */
2718 dest
= tcg_const_i32((insn
>> 9) & 3);
2719 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
2720 gen_mac_clear_flags();
2721 gen_helper_mac_set_flags(cpu_env
, dest
);
2724 DISAS_INSN(from_macsr
)
2728 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2729 tcg_gen_mov_i32(reg
, QREG_MACSR
);
2732 DISAS_INSN(from_mask
)
2735 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2736 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
2739 DISAS_INSN(from_mext
)
2743 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
2744 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2745 if (s
->env
->macsr
& MACSR_FI
)
2746 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
2748 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
2751 DISAS_INSN(macsr_to_ccr
)
2753 TCGv tmp
= tcg_temp_new();
2754 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
2755 gen_helper_set_sr(cpu_env
, tmp
);
2757 set_cc_op(s
, CC_OP_FLAGS
);
2765 accnum
= (insn
>> 9) & 3;
2766 acc
= MACREG(accnum
);
2767 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2768 if (s
->env
->macsr
& MACSR_FI
) {
2769 tcg_gen_ext_i32_i64(acc
, val
);
2770 tcg_gen_shli_i64(acc
, acc
, 8);
2771 } else if (s
->env
->macsr
& MACSR_SU
) {
2772 tcg_gen_ext_i32_i64(acc
, val
);
2774 tcg_gen_extu_i32_i64(acc
, val
);
2776 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
2777 gen_mac_clear_flags();
2778 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
2781 DISAS_INSN(to_macsr
)
2784 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2785 gen_helper_set_macsr(cpu_env
, val
);
2792 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2793 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
2800 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
2801 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
2802 if (s
->env
->macsr
& MACSR_FI
)
2803 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
2804 else if (s
->env
->macsr
& MACSR_SU
)
2805 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
2807 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
2810 static disas_proc opcode_table
[65536];
2813 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
2819 /* Sanity check. All set bits must be included in the mask. */
2820 if (opcode
& ~mask
) {
2822 "qemu internal error: bogus opcode definition %04x/%04x\n",
2826 /* This could probably be cleverer. For now just optimize the case where
2827 the top bits are known. */
2828 /* Find the first zero bit in the mask. */
2830 while ((i
& mask
) != 0)
2832 /* Iterate over all combinations of this and lower bits. */
2837 from
= opcode
& ~(i
- 1);
2839 for (i
= from
; i
< to
; i
++) {
2840 if ((i
& mask
) == opcode
)
2841 opcode_table
[i
] = proc
;
2845 /* Register m68k opcode handlers. Order is important.
2846 Later insn override earlier ones. */
2847 void register_m68k_insns (CPUM68KState
*env
)
2849 /* Build the opcode table only once to avoid
2850 multithreading issues. */
2851 if (opcode_table
[0] != NULL
) {
2855 /* use BASE() for instruction available
2856 * for CF_ISA_A and M68000.
2858 #define BASE(name, opcode, mask) \
2859 register_opcode(disas_##name, 0x##opcode, 0x##mask)
2860 #define INSN(name, opcode, mask, feature) do { \
2861 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2862 BASE(name, opcode, mask); \
2864 BASE(undef
, 0000, 0000);
2865 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
2866 INSN(arith_im
, 0000, ff00
, M68000
);
2867 INSN(undef
, 00c0
, ffc0
, M68000
);
2868 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
2869 BASE(bitop_reg
, 0100, f1c0
);
2870 BASE(bitop_reg
, 0140, f1c0
);
2871 BASE(bitop_reg
, 0180, f1c0
);
2872 BASE(bitop_reg
, 01c0
, f1c0
);
2873 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
2874 INSN(arith_im
, 0200, ff00
, M68000
);
2875 INSN(undef
, 02c0
, ffc0
, M68000
);
2876 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
2877 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
2878 INSN(arith_im
, 0400, ff00
, M68000
);
2879 INSN(undef
, 04c0
, ffc0
, M68000
);
2880 INSN(arith_im
, 0600, ff00
, M68000
);
2881 INSN(undef
, 06c0
, ffc0
, M68000
);
2882 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
2883 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
2884 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
2885 INSN(arith_im
, 0c00
, ff00
, M68000
);
2886 BASE(bitop_im
, 0800, ffc0
);
2887 BASE(bitop_im
, 0840, ffc0
);
2888 BASE(bitop_im
, 0880, ffc0
);
2889 BASE(bitop_im
, 08c0
, ffc0
);
2890 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
2891 INSN(arith_im
, 0a00
, ff00
, M68000
);
2892 BASE(move
, 1000, f000
);
2893 BASE(move
, 2000, f000
);
2894 BASE(move
, 3000, f000
);
2895 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
2896 INSN(negx
, 4080, fff8
, CF_ISA_A
);
2897 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
2898 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
2899 BASE(lea
, 41c0
, f1c0
);
2900 BASE(clr
, 4200, ff00
);
2901 BASE(undef
, 42c0
, ffc0
);
2902 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
2903 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
2904 INSN(neg
, 4480, fff8
, CF_ISA_A
);
2905 INSN(neg
, 4400, ff00
, M68000
);
2906 INSN(undef
, 44c0
, ffc0
, M68000
);
2907 BASE(move_to_ccr
, 44c0
, ffc0
);
2908 INSN(not, 4680, fff8
, CF_ISA_A
);
2909 INSN(not, 4600, ff00
, M68000
);
2910 INSN(undef
, 46c0
, ffc0
, M68000
);
2911 INSN(move_to_sr
, 46c0
, ffc0
, CF_ISA_A
);
2912 BASE(pea
, 4840, ffc0
);
2913 BASE(swap
, 4840, fff8
);
2914 BASE(movem
, 48c0
, fbc0
);
2915 BASE(ext
, 4880, fff8
);
2916 BASE(ext
, 48c0
, fff8
);
2917 BASE(ext
, 49c0
, fff8
);
2918 BASE(tst
, 4a00
, ff00
);
2919 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
2920 INSN(tas
, 4ac0
, ffc0
, M68000
);
2921 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
2922 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
2923 BASE(illegal
, 4afc
, ffff
);
2924 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
2925 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
2926 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
2927 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
2928 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
2929 BASE(trap
, 4e40
, fff0
);
2930 BASE(link
, 4e50
, fff8
);
2931 BASE(unlk
, 4e58
, fff8
);
2932 INSN(move_to_usp
, 4e60
, fff8
, USP
);
2933 INSN(move_from_usp
, 4e68
, fff8
, USP
);
2934 BASE(nop
, 4e71
, ffff
);
2935 BASE(stop
, 4e72
, ffff
);
2936 BASE(rte
, 4e73
, ffff
);
2937 BASE(rts
, 4e75
, ffff
);
2938 INSN(movec
, 4e7b
, ffff
, CF_ISA_A
);
2939 BASE(jump
, 4e80
, ffc0
);
2940 INSN(jump
, 4ec0
, ffc0
, CF_ISA_A
);
2941 INSN(addsubq
, 5180, f1c0
, CF_ISA_A
);
2942 INSN(jump
, 4ec0
, ffc0
, M68000
);
2943 INSN(addsubq
, 5000, f080
, M68000
);
2944 INSN(addsubq
, 5080, f0c0
, M68000
);
2945 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
);
2946 INSN(addsubq
, 5080, f1c0
, CF_ISA_A
);
2947 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
2949 /* Branch instructions. */
2950 BASE(branch
, 6000, f000
);
2951 /* Disable long branch instructions, then add back the ones we want. */
2952 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
2953 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
2954 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
2955 INSN(branch
, 60ff
, ffff
, BRAL
);
2956 INSN(branch
, 60ff
, f0ff
, BCCL
);
2958 BASE(moveq
, 7000, f100
);
2959 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
2960 BASE(or, 8000, f000
);
2961 BASE(divw
, 80c0
, f0c0
);
2962 BASE(addsub
, 9000, f000
);
2963 INSN(subx
, 9180, f1f8
, CF_ISA_A
);
2964 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
2966 BASE(undef_mac
, a000
, f000
);
2967 INSN(mac
, a000
, f100
, CF_EMAC
);
2968 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
2969 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
2970 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
2971 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
2972 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
2973 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
2974 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
2975 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
2976 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
2977 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
2979 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
2980 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
2981 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
2982 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
2983 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
2984 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
2985 INSN(cmp
, b000
, f100
, M68000
);
2986 INSN(eor
, b100
, f100
, M68000
);
2987 INSN(cmpa
, b0c0
, f0c0
, M68000
);
2988 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
2989 BASE(and, c000
, f000
);
2990 BASE(mulw
, c0c0
, f0c0
);
2991 BASE(addsub
, d000
, f000
);
2992 INSN(addx
, d180
, f1f8
, CF_ISA_A
);
2993 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
2994 INSN(adda
, d0c0
, f0c0
, M68000
);
2995 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
2996 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
2997 INSN(undef_fpu
, f000
, f000
, CF_ISA_A
);
2998 INSN(fpu
, f200
, ffc0
, CF_FPU
);
2999 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
3000 INSN(frestore
, f340
, ffc0
, CF_FPU
);
3001 INSN(fsave
, f340
, ffc0
, CF_FPU
);
3002 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
3003 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
3004 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
3005 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
3009 /* ??? Some of this implementation is not exception safe. We should always
3010 write back the result to memory before setting the condition codes. */
3011 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
3015 insn
= read_im16(env
, s
);
3017 opcode_table
[insn
](env
, s
, insn
);
3020 /* generate intermediate code for basic block 'tb'. */
3021 void gen_intermediate_code(CPUM68KState
*env
, TranslationBlock
*tb
)
3023 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
3024 CPUState
*cs
= CPU(cpu
);
3025 DisasContext dc1
, *dc
= &dc1
;
3026 target_ulong pc_start
;
3031 /* generate intermediate code */
3037 dc
->is_jmp
= DISAS_NEXT
;
3039 dc
->cc_op
= CC_OP_DYNAMIC
;
3040 dc
->cc_op_synced
= 1;
3041 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3042 dc
->fpcr
= env
->fpcr
;
3043 dc
->user
= (env
->sr
& SR_S
) == 0;
3046 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3047 if (max_insns
== 0) {
3048 max_insns
= CF_COUNT_MASK
;
3050 if (max_insns
> TCG_MAX_INSNS
) {
3051 max_insns
= TCG_MAX_INSNS
;
3056 pc_offset
= dc
->pc
- pc_start
;
3057 gen_throws_exception
= NULL
;
3058 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
3061 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
3062 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
3063 dc
->is_jmp
= DISAS_JUMP
;
3064 /* The address covered by the breakpoint must be included in
3065 [tb->pc, tb->pc + tb->size) in order to for it to be
3066 properly cleared -- thus we increment the PC here so that
3067 the logic setting tb->size below does the right thing. */
3072 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3076 dc
->insn_pc
= dc
->pc
;
3077 disas_m68k_insn(env
, dc
);
3078 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
3079 !cs
->singlestep_enabled
&&
3081 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
3082 num_insns
< max_insns
);
3084 if (tb
->cflags
& CF_LAST_IO
)
3086 if (unlikely(cs
->singlestep_enabled
)) {
3087 /* Make sure the pc is updated, and raise a debug exception. */
3090 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
3092 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
3094 switch(dc
->is_jmp
) {
3097 gen_jmp_tb(dc
, 0, dc
->pc
);
3103 /* indicate that the hash table must be used to find the next TB */
3107 /* nothing more to generate */
3111 gen_tb_end(tb
, num_insns
);
3114 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3115 && qemu_log_in_addr_range(pc_start
)) {
3116 qemu_log("----------------\n");
3117 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3118 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
3122 tb
->size
= dc
->pc
- pc_start
;
3123 tb
->icount
= num_insns
;
3126 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3129 M68kCPU
*cpu
= M68K_CPU(cs
);
3130 CPUM68KState
*env
= &cpu
->env
;
3134 for (i
= 0; i
< 8; i
++)
3136 u
.d
= env
->fregs
[i
];
3137 cpu_fprintf(f
, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3138 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
3139 i
, u
.l
.upper
, u
.l
.lower
, *(double *)&u
.d
);
3141 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
3142 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
3143 cpu_fprintf(f
, "SR = %04x %c%c%c%c%c ", sr
, (sr
& CCF_X
) ? 'X' : '-',
3144 (sr
& CCF_N
) ? 'N' : '-', (sr
& CCF_Z
) ? 'Z' : '-',
3145 (sr
& CCF_V
) ? 'V' : '-', (sr
& CCF_C
) ? 'C' : '-');
3146 cpu_fprintf (f
, "FPRESULT = %12g\n", *(double *)&env
->fp_result
);
3149 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
3152 int cc_op
= data
[1];
3154 if (cc_op
!= CC_OP_DYNAMIC
) {