2 * libqos virtio PCI driver
4 * Copyright (c) 2014 Marc MarĂ
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "libqos/virtio.h"
13 #include "libqos/virtio-pci.h"
14 #include "libqos/pci.h"
15 #include "libqos/pci-pc.h"
16 #include "libqos/malloc.h"
17 #include "libqos/malloc-pc.h"
18 #include "standard-headers/linux/virtio_ring.h"
19 #include "standard-headers/linux/virtio_pci.h"
21 #include "hw/pci/pci.h"
22 #include "hw/pci/pci_regs.h"
24 typedef struct QVirtioPCIForeachData
{
25 void (*func
)(QVirtioDevice
*d
, void *data
);
28 } QVirtioPCIForeachData
;
30 static QVirtioPCIDevice
*qpcidevice_to_qvirtiodevice(QPCIDevice
*pdev
)
32 QVirtioPCIDevice
*vpcidev
;
33 vpcidev
= g_malloc0(sizeof(*vpcidev
));
37 vpcidev
->vdev
.device_type
=
38 qpci_config_readw(vpcidev
->pdev
, PCI_SUBSYSTEM_ID
);
41 vpcidev
->config_msix_entry
= -1;
46 static void qvirtio_pci_foreach_callback(
47 QPCIDevice
*dev
, int devfn
, void *data
)
49 QVirtioPCIForeachData
*d
= data
;
50 QVirtioPCIDevice
*vpcidev
= qpcidevice_to_qvirtiodevice(dev
);
52 if (vpcidev
->vdev
.device_type
== d
->device_type
) {
53 d
->func(&vpcidev
->vdev
, d
->user_data
);
59 static void qvirtio_pci_assign_device(QVirtioDevice
*d
, void *data
)
61 QVirtioPCIDevice
**vpcidev
= data
;
62 *vpcidev
= (QVirtioPCIDevice
*)d
;
65 #define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
67 static uint8_t qvirtio_pci_config_readb(QVirtioDevice
*d
, uint64_t off
)
69 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
70 return qpci_io_readb(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
73 /* PCI is always read in little-endian order
74 * but virtio ( < 1.0) is in guest order
75 * so with a big-endian guest the order has been reversed,
77 * virtio-1.0 is always little-endian, like PCI, but this
78 * case will be managed inside qvirtio_is_big_endian()
81 static uint16_t qvirtio_pci_config_readw(QVirtioDevice
*d
, uint64_t off
)
83 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
86 value
= qpci_io_readw(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
87 if (qvirtio_is_big_endian(d
)) {
88 value
= bswap16(value
);
93 static uint32_t qvirtio_pci_config_readl(QVirtioDevice
*d
, uint64_t off
)
95 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
98 value
= qpci_io_readl(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
99 if (qvirtio_is_big_endian(d
)) {
100 value
= bswap32(value
);
105 static uint64_t qvirtio_pci_config_readq(QVirtioDevice
*d
, uint64_t off
)
107 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
110 val
= qpci_io_readq(dev
->pdev
, dev
->bar
, CONFIG_BASE(dev
) + off
);
111 if (qvirtio_is_big_endian(d
)) {
118 static uint32_t qvirtio_pci_get_features(QVirtioDevice
*d
)
120 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
121 return qpci_io_readl(dev
->pdev
, dev
->bar
, VIRTIO_PCI_HOST_FEATURES
);
124 static void qvirtio_pci_set_features(QVirtioDevice
*d
, uint32_t features
)
126 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
127 qpci_io_writel(dev
->pdev
, dev
->bar
, VIRTIO_PCI_GUEST_FEATURES
, features
);
130 static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice
*d
)
132 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
133 return qpci_io_readl(dev
->pdev
, dev
->bar
, VIRTIO_PCI_GUEST_FEATURES
);
136 static uint8_t qvirtio_pci_get_status(QVirtioDevice
*d
)
138 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
139 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_STATUS
);
142 static void qvirtio_pci_set_status(QVirtioDevice
*d
, uint8_t status
)
144 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
145 qpci_io_writeb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_STATUS
, status
);
148 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice
*d
, QVirtQueue
*vq
)
150 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
151 QVirtQueuePCI
*vqpci
= (QVirtQueuePCI
*)vq
;
154 if (dev
->pdev
->msix_enabled
) {
155 g_assert_cmpint(vqpci
->msix_entry
, !=, -1);
156 if (qpci_msix_masked(dev
->pdev
, vqpci
->msix_entry
)) {
157 /* No ISR checking should be done if masked, but read anyway */
158 return qpci_msix_pending(dev
->pdev
, vqpci
->msix_entry
);
160 data
= readl(vqpci
->msix_addr
);
161 if (data
== vqpci
->msix_data
) {
162 writel(vqpci
->msix_addr
, 0);
169 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_ISR
) & 1;
173 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice
*d
)
175 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
178 if (dev
->pdev
->msix_enabled
) {
179 g_assert_cmpint(dev
->config_msix_entry
, !=, -1);
180 if (qpci_msix_masked(dev
->pdev
, dev
->config_msix_entry
)) {
181 /* No ISR checking should be done if masked, but read anyway */
182 return qpci_msix_pending(dev
->pdev
, dev
->config_msix_entry
);
184 data
= readl(dev
->config_msix_addr
);
185 if (data
== dev
->config_msix_data
) {
186 writel(dev
->config_msix_addr
, 0);
193 return qpci_io_readb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_ISR
) & 2;
197 static void qvirtio_pci_queue_select(QVirtioDevice
*d
, uint16_t index
)
199 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
200 qpci_io_writeb(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_SEL
, index
);
203 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice
*d
)
205 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
206 return qpci_io_readw(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_NUM
);
209 static void qvirtio_pci_set_queue_address(QVirtioDevice
*d
, uint32_t pfn
)
211 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
212 qpci_io_writel(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_PFN
, pfn
);
215 static QVirtQueue
*qvirtio_pci_virtqueue_setup(QVirtioDevice
*d
,
216 QGuestAllocator
*alloc
, uint16_t index
)
220 QVirtQueuePCI
*vqpci
;
222 vqpci
= g_malloc0(sizeof(*vqpci
));
223 feat
= qvirtio_pci_get_guest_features(d
);
225 qvirtio_pci_queue_select(d
, index
);
226 vqpci
->vq
.index
= index
;
227 vqpci
->vq
.size
= qvirtio_pci_get_queue_size(d
);
228 vqpci
->vq
.free_head
= 0;
229 vqpci
->vq
.num_free
= vqpci
->vq
.size
;
230 vqpci
->vq
.align
= VIRTIO_PCI_VRING_ALIGN
;
231 vqpci
->vq
.indirect
= (feat
& (1u << VIRTIO_RING_F_INDIRECT_DESC
)) != 0;
232 vqpci
->vq
.event
= (feat
& (1u << VIRTIO_RING_F_EVENT_IDX
)) != 0;
234 vqpci
->msix_entry
= -1;
235 vqpci
->msix_addr
= 0;
236 vqpci
->msix_data
= 0x12345678;
238 /* Check different than 0 */
239 g_assert_cmpint(vqpci
->vq
.size
, !=, 0);
241 /* Check power of 2 */
242 g_assert_cmpint(vqpci
->vq
.size
& (vqpci
->vq
.size
- 1), ==, 0);
244 addr
= guest_alloc(alloc
, qvring_size(vqpci
->vq
.size
,
245 VIRTIO_PCI_VRING_ALIGN
));
246 qvring_init(alloc
, &vqpci
->vq
, addr
);
247 qvirtio_pci_set_queue_address(d
, vqpci
->vq
.desc
/ VIRTIO_PCI_VRING_ALIGN
);
252 static void qvirtio_pci_virtqueue_cleanup(QVirtQueue
*vq
,
253 QGuestAllocator
*alloc
)
255 QVirtQueuePCI
*vqpci
= container_of(vq
, QVirtQueuePCI
, vq
);
257 guest_free(alloc
, vq
->desc
);
261 static void qvirtio_pci_virtqueue_kick(QVirtioDevice
*d
, QVirtQueue
*vq
)
263 QVirtioPCIDevice
*dev
= (QVirtioPCIDevice
*)d
;
264 qpci_io_writew(dev
->pdev
, dev
->bar
, VIRTIO_PCI_QUEUE_NOTIFY
, vq
->index
);
267 const QVirtioBus qvirtio_pci
= {
268 .config_readb
= qvirtio_pci_config_readb
,
269 .config_readw
= qvirtio_pci_config_readw
,
270 .config_readl
= qvirtio_pci_config_readl
,
271 .config_readq
= qvirtio_pci_config_readq
,
272 .get_features
= qvirtio_pci_get_features
,
273 .set_features
= qvirtio_pci_set_features
,
274 .get_guest_features
= qvirtio_pci_get_guest_features
,
275 .get_status
= qvirtio_pci_get_status
,
276 .set_status
= qvirtio_pci_set_status
,
277 .get_queue_isr_status
= qvirtio_pci_get_queue_isr_status
,
278 .get_config_isr_status
= qvirtio_pci_get_config_isr_status
,
279 .queue_select
= qvirtio_pci_queue_select
,
280 .get_queue_size
= qvirtio_pci_get_queue_size
,
281 .set_queue_address
= qvirtio_pci_set_queue_address
,
282 .virtqueue_setup
= qvirtio_pci_virtqueue_setup
,
283 .virtqueue_cleanup
= qvirtio_pci_virtqueue_cleanup
,
284 .virtqueue_kick
= qvirtio_pci_virtqueue_kick
,
287 void qvirtio_pci_foreach(QPCIBus
*bus
, uint16_t device_type
,
288 void (*func
)(QVirtioDevice
*d
, void *data
), void *data
)
290 QVirtioPCIForeachData d
= { .func
= func
,
291 .device_type
= device_type
,
294 qpci_device_foreach(bus
, PCI_VENDOR_ID_REDHAT_QUMRANET
, -1,
295 qvirtio_pci_foreach_callback
, &d
);
298 QVirtioPCIDevice
*qvirtio_pci_device_find(QPCIBus
*bus
, uint16_t device_type
)
300 QVirtioPCIDevice
*dev
= NULL
;
301 qvirtio_pci_foreach(bus
, device_type
, qvirtio_pci_assign_device
, &dev
);
303 dev
->vdev
.bus
= &qvirtio_pci
;
308 void qvirtio_pci_device_enable(QVirtioPCIDevice
*d
)
310 qpci_device_enable(d
->pdev
);
311 d
->bar
= qpci_iomap(d
->pdev
, 0, NULL
);
314 void qvirtio_pci_device_disable(QVirtioPCIDevice
*d
)
316 qpci_iounmap(d
->pdev
, d
->bar
);
319 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice
*d
, QVirtQueuePCI
*vqpci
,
320 QGuestAllocator
*alloc
, uint16_t entry
)
326 g_assert(d
->pdev
->msix_enabled
);
327 off
= d
->pdev
->msix_table_off
+ (entry
* 16);
329 g_assert_cmpint(entry
, >=, 0);
330 g_assert_cmpint(entry
, <, qpci_msix_table_size(d
->pdev
));
331 vqpci
->msix_entry
= entry
;
333 vqpci
->msix_addr
= guest_alloc(alloc
, 4);
334 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
335 off
+ PCI_MSIX_ENTRY_LOWER_ADDR
, vqpci
->msix_addr
& ~0UL);
336 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
337 off
+ PCI_MSIX_ENTRY_UPPER_ADDR
,
338 (vqpci
->msix_addr
>> 32) & ~0UL);
339 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
340 off
+ PCI_MSIX_ENTRY_DATA
, vqpci
->msix_data
);
342 control
= qpci_io_readl(d
->pdev
, d
->pdev
->msix_table_bar
,
343 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
344 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
345 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
,
346 control
& ~PCI_MSIX_ENTRY_CTRL_MASKBIT
);
348 qvirtio_pci_queue_select(&d
->vdev
, vqpci
->vq
.index
);
349 qpci_io_writew(d
->pdev
, d
->bar
, VIRTIO_MSI_QUEUE_VECTOR
, entry
);
350 vector
= qpci_io_readw(d
->pdev
, d
->bar
, VIRTIO_MSI_QUEUE_VECTOR
);
351 g_assert_cmphex(vector
, !=, VIRTIO_MSI_NO_VECTOR
);
354 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice
*d
,
355 QGuestAllocator
*alloc
, uint16_t entry
)
361 g_assert(d
->pdev
->msix_enabled
);
362 off
= d
->pdev
->msix_table_off
+ (entry
* 16);
364 g_assert_cmpint(entry
, >=, 0);
365 g_assert_cmpint(entry
, <, qpci_msix_table_size(d
->pdev
));
366 d
->config_msix_entry
= entry
;
368 d
->config_msix_data
= 0x12345678;
369 d
->config_msix_addr
= guest_alloc(alloc
, 4);
371 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
372 off
+ PCI_MSIX_ENTRY_LOWER_ADDR
, d
->config_msix_addr
& ~0UL);
373 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
374 off
+ PCI_MSIX_ENTRY_UPPER_ADDR
,
375 (d
->config_msix_addr
>> 32) & ~0UL);
376 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
377 off
+ PCI_MSIX_ENTRY_DATA
, d
->config_msix_data
);
379 control
= qpci_io_readl(d
->pdev
, d
->pdev
->msix_table_bar
,
380 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
381 qpci_io_writel(d
->pdev
, d
->pdev
->msix_table_bar
,
382 off
+ PCI_MSIX_ENTRY_VECTOR_CTRL
,
383 control
& ~PCI_MSIX_ENTRY_CTRL_MASKBIT
);
385 qpci_io_writew(d
->pdev
, d
->bar
, VIRTIO_MSI_CONFIG_VECTOR
, entry
);
386 vector
= qpci_io_readw(d
->pdev
, d
->bar
, VIRTIO_MSI_CONFIG_VECTOR
);
387 g_assert_cmphex(vector
, !=, VIRTIO_MSI_NO_VECTOR
);