target/s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "internal.h"
  24 #include "exec/gdbstub.h"
  25 #include "qemu/timer.h"
  26 #include "exec/exec-all.h"
  27 #include "hw/s390x/ioinst.h"
  28 #include "sysemu/hw_accel.h"
  29 #ifndef CONFIG_USER_ONLY
  30 #include "sysemu/sysemu.h"
  31 #endif
  32
  33 #ifndef CONFIG_USER_ONLY
  34 void s390x_tod_timer(void *opaque)
  35 {
  36     cpu_inject_clock_comparator((S390CPU *) opaque);
  37 }
  38
  39 void s390x_cpu_timer(void *opaque)
  40 {
  41     cpu_inject_cpu_timer((S390CPU *) opaque);
  42 }
  43 #endif
  44
  45 #ifndef CONFIG_USER_ONLY
  46
  47 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
  48 {
  49     S390CPU *cpu = S390_CPU(cs);
  50     CPUS390XState *env = &cpu->env;
  51     target_ulong raddr;
  52     int prot;
  53     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
  54
  55     /* 31-Bit mode */
  56     if (!(env->psw.mask & PSW_MASK_64)) {
  57         vaddr &= 0x7fffffff;
  58     }
  59
  60     if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
  61         return -1;
  62     }
  63     return raddr;
  64 }
  65
  66 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
  67 {
  68     hwaddr phys_addr;
  69     target_ulong page;
  70
  71     page = vaddr & TARGET_PAGE_MASK;
  72     phys_addr = cpu_get_phys_page_debug(cs, page);
  73     phys_addr += (vaddr & ~TARGET_PAGE_MASK);
  74
  75     return phys_addr;
  76 }
  77
  78 static inline bool is_special_wait_psw(uint64_t psw_addr)
  79 {
  80     /* signal quiesce */
  81     return psw_addr == 0xfffUL;
  82 }
  83
  84 void s390_handle_wait(S390CPU *cpu)
  85 {
  86     if (s390_cpu_halt(cpu) == 0) {
  87 #ifndef CONFIG_USER_ONLY
  88         if (is_special_wait_psw(cpu->env.psw.addr)) {
  89             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  90         } else {
  91             qemu_system_guest_panicked(NULL);
  92         }
  93 #endif
  94     }
  95 }
  96
  97 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
  98 {
  99     uint64_t old_mask = env->psw.mask;
 100
 101     env->psw.addr = addr;
 102     env->psw.mask = mask;
 103     if (tcg_enabled()) {
 104         env->cc_op = (mask >> 44) & 3;
 105     }
 106
 107     if ((old_mask ^ mask) & PSW_MASK_PER) {
 108         s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
 109     }
 110
 111     /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */
 112     if (tcg_enabled() && (mask & PSW_MASK_WAIT)) {
 113         s390_handle_wait(s390_env_get_cpu(env));
 114     }
 115 }
 116
 117 uint64_t get_psw_mask(CPUS390XState *env)
 118 {
 119     uint64_t r = env->psw.mask;
 120
 121     if (tcg_enabled()) {
 122         env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
 123                              env->cc_vr);
 124
 125         r &= ~PSW_MASK_CC;
 126         assert(!(env->cc_op & ~3));
 127         r |= (uint64_t)env->cc_op << 44;
 128     }
 129
 130     return r;
 131 }
 132
 133 LowCore *cpu_map_lowcore(CPUS390XState *env)
 134 {
 135     S390CPU *cpu = s390_env_get_cpu(env);
 136     LowCore *lowcore;
 137     hwaddr len = sizeof(LowCore);
 138
 139     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 140
 141     if (len < sizeof(LowCore)) {
 142         cpu_abort(CPU(cpu), "Could not map lowcore\n");
 143     }
 144
 145     return lowcore;
 146 }
 147
 148 void cpu_unmap_lowcore(LowCore *lowcore)
 149 {
 150     cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
 151 }
 152
 153 void do_restart_interrupt(CPUS390XState *env)
 154 {
 155     uint64_t mask, addr;
 156     LowCore *lowcore;
 157
 158     lowcore = cpu_map_lowcore(env);
 159
 160     lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 161     lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
 162     mask = be64_to_cpu(lowcore->restart_new_psw.mask);
 163     addr = be64_to_cpu(lowcore->restart_new_psw.addr);
 164
 165     cpu_unmap_lowcore(lowcore);
 166     env->pending_int &= ~INTERRUPT_RESTART;
 167
 168     load_psw(env, mask, addr);
 169 }
 170
 171 void s390_cpu_recompute_watchpoints(CPUState *cs)
 172 {
 173     const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
 174     S390CPU *cpu = S390_CPU(cs);
 175     CPUS390XState *env = &cpu->env;
 176
 177     /* We are called when the watchpoints have changed. First
 178        remove them all.  */
 179     cpu_watchpoint_remove_all(cs, BP_CPU);
 180
 181     /* Return if PER is not enabled */
 182     if (!(env->psw.mask & PSW_MASK_PER)) {
 183         return;
 184     }
 185
 186     /* Return if storage-alteration event is not enabled.  */
 187     if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
 188         return;
 189     }
 190
 191     if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
 192         /* We can't create a watchoint spanning the whole memory range, so
 193            split it in two parts.   */
 194         cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
 195         cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
 196     } else if (env->cregs[10] > env->cregs[11]) {
 197         /* The address range loops, create two watchpoints.  */
 198         cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
 199                               wp_flags, NULL);
 200         cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
 201
 202     } else {
 203         /* Default case, create a single watchpoint.  */
 204         cpu_watchpoint_insert(cs, env->cregs[10],
 205                               env->cregs[11] - env->cregs[10] + 1,
 206                               wp_flags, NULL);
 207     }
 208 }
 209
 210 struct sigp_save_area {
 211     uint64_t    fprs[16];                       /* 0x0000 */
 212     uint64_t    grs[16];                        /* 0x0080 */
 213     PSW         psw;                            /* 0x0100 */
 214     uint8_t     pad_0x0110[0x0118 - 0x0110];    /* 0x0110 */
 215     uint32_t    prefix;                         /* 0x0118 */
 216     uint32_t    fpc;                            /* 0x011c */
 217     uint8_t     pad_0x0120[0x0124 - 0x0120];    /* 0x0120 */
 218     uint32_t    todpr;                          /* 0x0124 */
 219     uint64_t    cputm;                          /* 0x0128 */
 220     uint64_t    ckc;                            /* 0x0130 */
 221     uint8_t     pad_0x0138[0x0140 - 0x0138];    /* 0x0138 */
 222     uint32_t    ars[16];                        /* 0x0140 */
 223     uint64_t    crs[16];                        /* 0x0384 */
 224 };
 225 QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512);
 226
 227 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
 228 {
 229     static const uint8_t ar_id = 1;
 230     struct sigp_save_area *sa;
 231     hwaddr len = sizeof(*sa);
 232     int i;
 233
 234     sa = cpu_physical_memory_map(addr, &len, 1);
 235     if (!sa) {
 236         return -EFAULT;
 237     }
 238     if (len != sizeof(*sa)) {
 239         cpu_physical_memory_unmap(sa, len, 1, 0);
 240         return -EFAULT;
 241     }
 242
 243     if (store_arch) {
 244         cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
 245     }
 246     for (i = 0; i < 16; ++i) {
 247         sa->fprs[i] = cpu_to_be64(get_freg(&cpu->env, i)->ll);
 248     }
 249     for (i = 0; i < 16; ++i) {
 250         sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
 251     }
 252     sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
 253     sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env));
 254     sa->prefix = cpu_to_be32(cpu->env.psa);
 255     sa->fpc = cpu_to_be32(cpu->env.fpc);
 256     sa->todpr = cpu_to_be32(cpu->env.todpr);
 257     sa->cputm = cpu_to_be64(cpu->env.cputm);
 258     sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
 259     for (i = 0; i < 16; ++i) {
 260         sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
 261     }
 262     for (i = 0; i < 16; ++i) {
 263         sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
 264     }
 265
 266     cpu_physical_memory_unmap(sa, len, 1, len);
 267
 268     return 0;
 269 }
 270
 271 #define ADTL_GS_OFFSET   1024 /* offset of GS data in adtl save area */
 272 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
 273 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
 274 {
 275     hwaddr save = len;
 276     void *mem;
 277
 278     mem = cpu_physical_memory_map(addr, &save, 1);
 279     if (!mem) {
 280         return -EFAULT;
 281     }
 282     if (save != len) {
 283         cpu_physical_memory_unmap(mem, len, 1, 0);
 284         return -EFAULT;
 285     }
 286
 287     /* FIXME: as soon as TCG supports these features, convert cpu->be */
 288     if (s390_has_feat(S390_FEAT_VECTOR)) {
 289         memcpy(mem, &cpu->env.vregs, 512);
 290     }
 291     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
 292         memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32);
 293     }
 294
 295     cpu_physical_memory_unmap(mem, len, 1, len);
 296
 297     return 0;
 298 }
 299 #endif /* CONFIG_USER_ONLY */
 300
 301 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 302                          int flags)
 303 {
 304     S390CPU *cpu = S390_CPU(cs);
 305     CPUS390XState *env = &cpu->env;
 306     int i;
 307
 308     if (env->cc_op > 3) {
 309         cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
 310                     env->psw.mask, env->psw.addr, cc_name(env->cc_op));
 311     } else {
 312         cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
 313                     env->psw.mask, env->psw.addr, env->cc_op);
 314     }
 315
 316     for (i = 0; i < 16; i++) {
 317         cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
 318         if ((i % 4) == 3) {
 319             cpu_fprintf(f, "\n");
 320         } else {
 321             cpu_fprintf(f, " ");
 322         }
 323     }
 324
 325     for (i = 0; i < 16; i++) {
 326         cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
 327         if ((i % 4) == 3) {
 328             cpu_fprintf(f, "\n");
 329         } else {
 330             cpu_fprintf(f, " ");
 331         }
 332     }
 333
 334     for (i = 0; i < 32; i++) {
 335         cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
 336                     env->vregs[i][0].ll, env->vregs[i][1].ll);
 337         cpu_fprintf(f, (i % 2) ? "\n" : " ");
 338     }
 339
 340 #ifndef CONFIG_USER_ONLY
 341     for (i = 0; i < 16; i++) {
 342         cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
 343         if ((i % 4) == 3) {
 344             cpu_fprintf(f, "\n");
 345         } else {
 346             cpu_fprintf(f, " ");
 347         }
 348     }
 349 #endif
 350
 351 #ifdef DEBUG_INLINE_BRANCHES
 352     for (i = 0; i < CC_OP_MAX; i++) {
 353         cpu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
 354                     inline_branch_miss[i], inline_branch_hit[i]);
 355     }
 356 #endif
 357
 358     cpu_fprintf(f, "\n");
 359 }
 360
 361 const char *cc_name(enum cc_op cc_op)
 362 {
 363     static const char * const cc_names[] = {
 364         [CC_OP_CONST0]    = "CC_OP_CONST0",
 365         [CC_OP_CONST1]    = "CC_OP_CONST1",
 366         [CC_OP_CONST2]    = "CC_OP_CONST2",
 367         [CC_OP_CONST3]    = "CC_OP_CONST3",
 368         [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 369         [CC_OP_STATIC]    = "CC_OP_STATIC",
 370         [CC_OP_NZ]        = "CC_OP_NZ",
 371         [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 372         [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 373         [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 374         [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 375         [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 376         [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 377         [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 378         [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 379         [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 380         [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 381         [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 382         [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 383         [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 384         [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 385         [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 386         [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 387         [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 388         [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 389         [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 390         [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 391         [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 392         [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 393         [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 394         [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 395         [CC_OP_TM_32]     = "CC_OP_TM_32",
 396         [CC_OP_TM_64]     = "CC_OP_TM_64",
 397         [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 398         [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 399         [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 400         [CC_OP_ICM]       = "CC_OP_ICM",
 401         [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 402         [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 403         [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 404     };
 405
 406     return cc_names[cc_op];
 407 }