4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
25 #include "qemu-common.h"
26 #include "exec/exec-all.h"
29 static void alpha_cpu_set_pc(CPUState
*cs
, vaddr value
)
31 AlphaCPU
*cpu
= ALPHA_CPU(cs
);
36 static bool alpha_cpu_has_work(CPUState
*cs
)
38 /* Here we are checking to see if the CPU should wake up from HALT.
39 We will have gotten into this state only for WTINT from PALmode. */
40 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
41 asleep even if (some) interrupts have been asserted. For now,
42 assume that if a CPU really wants to stay asleep, it will mask
43 interrupts at the chipset level, which will prevent these bits
44 from being set in the first place. */
45 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_MCHK
);
51 static void alpha_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
53 info
->mach
= bfd_mach_alpha_ev6
;
54 info
->print_insn
= print_insn_alpha
;
57 static void alpha_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
59 CPUState
*cs
= CPU(dev
);
60 AlphaCPUClass
*acc
= ALPHA_CPU_GET_CLASS(dev
);
61 Error
*local_err
= NULL
;
63 cpu_exec_realizefn(cs
, &local_err
);
64 if (local_err
!= NULL
) {
65 error_propagate(errp
, local_err
);
71 acc
->parent_realize(dev
, errp
);
74 /* Sort alphabetically by type name. */
75 static gint
alpha_cpu_list_compare(gconstpointer a
, gconstpointer b
)
77 ObjectClass
*class_a
= (ObjectClass
*)a
;
78 ObjectClass
*class_b
= (ObjectClass
*)b
;
79 const char *name_a
, *name_b
;
81 name_a
= object_class_get_name(class_a
);
82 name_b
= object_class_get_name(class_b
);
83 return strcmp(name_a
, name_b
);
86 static void alpha_cpu_list_entry(gpointer data
, gpointer user_data
)
88 ObjectClass
*oc
= data
;
89 CPUListState
*s
= user_data
;
91 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
92 object_class_get_name(oc
));
95 void alpha_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
99 .cpu_fprintf
= cpu_fprintf
,
103 list
= object_class_get_list(TYPE_ALPHA_CPU
, false);
104 list
= g_slist_sort(list
, alpha_cpu_list_compare
);
105 (*cpu_fprintf
)(f
, "Available CPUs:\n");
106 g_slist_foreach(list
, alpha_cpu_list_entry
, &s
);
111 typedef struct AlphaCPUAlias
{
113 const char *typename
;
116 static const AlphaCPUAlias alpha_cpu_aliases
[] = {
117 { "21064", ALPHA_CPU_TYPE_NAME("ev4") },
118 { "21164", ALPHA_CPU_TYPE_NAME("ev5") },
119 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") },
120 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
121 { "21264", ALPHA_CPU_TYPE_NAME("ev6") },
122 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") },
125 static ObjectClass
*alpha_cpu_class_by_name(const char *cpu_model
)
131 oc
= object_class_by_name(cpu_model
);
132 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_ALPHA_CPU
) != NULL
&&
133 !object_class_is_abstract(oc
)) {
137 for (i
= 0; i
< ARRAY_SIZE(alpha_cpu_aliases
); i
++) {
138 if (strcmp(cpu_model
, alpha_cpu_aliases
[i
].alias
) == 0) {
139 oc
= object_class_by_name(alpha_cpu_aliases
[i
].typename
);
140 assert(oc
!= NULL
&& !object_class_is_abstract(oc
));
145 typename
= g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model
);
146 oc
= object_class_by_name(typename
);
148 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
152 /* TODO: remove match everything nonsense */
153 /* Default to ev67; no reason not to emulate insns by default. */
155 oc
= object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
161 static void ev4_cpu_initfn(Object
*obj
)
163 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
164 CPUAlphaState
*env
= &cpu
->env
;
166 env
->implver
= IMPLVER_2106x
;
169 static void ev5_cpu_initfn(Object
*obj
)
171 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
172 CPUAlphaState
*env
= &cpu
->env
;
174 env
->implver
= IMPLVER_21164
;
177 static void ev56_cpu_initfn(Object
*obj
)
179 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
180 CPUAlphaState
*env
= &cpu
->env
;
182 env
->amask
|= AMASK_BWX
;
185 static void pca56_cpu_initfn(Object
*obj
)
187 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
188 CPUAlphaState
*env
= &cpu
->env
;
190 env
->amask
|= AMASK_MVI
;
193 static void ev6_cpu_initfn(Object
*obj
)
195 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
196 CPUAlphaState
*env
= &cpu
->env
;
198 env
->implver
= IMPLVER_21264
;
199 env
->amask
= AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
;
202 static void ev67_cpu_initfn(Object
*obj
)
204 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
205 CPUAlphaState
*env
= &cpu
->env
;
207 env
->amask
|= AMASK_CIX
| AMASK_PREFETCH
;
210 static void alpha_cpu_initfn(Object
*obj
)
212 CPUState
*cs
= CPU(obj
);
213 AlphaCPU
*cpu
= ALPHA_CPU(obj
);
214 CPUAlphaState
*env
= &cpu
->env
;
220 #if defined(CONFIG_USER_ONLY)
221 env
->flags
= ENV_FLAG_PS_USER
| ENV_FLAG_FEN
;
222 cpu_alpha_store_fpcr(env
, (FPCR_INVD
| FPCR_DZED
| FPCR_OVFD
223 | FPCR_UNFD
| FPCR_INED
| FPCR_DNOD
226 env
->flags
= ENV_FLAG_PAL_MODE
| ENV_FLAG_FEN
;
230 static void alpha_cpu_class_init(ObjectClass
*oc
, void *data
)
232 DeviceClass
*dc
= DEVICE_CLASS(oc
);
233 CPUClass
*cc
= CPU_CLASS(oc
);
234 AlphaCPUClass
*acc
= ALPHA_CPU_CLASS(oc
);
236 acc
->parent_realize
= dc
->realize
;
237 dc
->realize
= alpha_cpu_realizefn
;
239 cc
->class_by_name
= alpha_cpu_class_by_name
;
240 cc
->has_work
= alpha_cpu_has_work
;
241 cc
->do_interrupt
= alpha_cpu_do_interrupt
;
242 cc
->cpu_exec_interrupt
= alpha_cpu_exec_interrupt
;
243 cc
->dump_state
= alpha_cpu_dump_state
;
244 cc
->set_pc
= alpha_cpu_set_pc
;
245 cc
->gdb_read_register
= alpha_cpu_gdb_read_register
;
246 cc
->gdb_write_register
= alpha_cpu_gdb_write_register
;
247 #ifdef CONFIG_USER_ONLY
248 cc
->handle_mmu_fault
= alpha_cpu_handle_mmu_fault
;
250 cc
->do_transaction_failed
= alpha_cpu_do_transaction_failed
;
251 cc
->do_unaligned_access
= alpha_cpu_do_unaligned_access
;
252 cc
->get_phys_page_debug
= alpha_cpu_get_phys_page_debug
;
253 dc
->vmsd
= &vmstate_alpha_cpu
;
255 cc
->disas_set_info
= alpha_cpu_disas_set_info
;
256 cc
->tcg_initialize
= alpha_translate_init
;
258 cc
->gdb_num_core_regs
= 67;
261 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
263 .parent = base_type, \
264 .instance_init = initfn, \
265 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \
268 static const TypeInfo alpha_cpu_type_infos
[] = {
270 .name
= TYPE_ALPHA_CPU
,
272 .instance_size
= sizeof(AlphaCPU
),
273 .instance_init
= alpha_cpu_initfn
,
275 .class_size
= sizeof(AlphaCPUClass
),
276 .class_init
= alpha_cpu_class_init
,
278 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev4", ev4_cpu_initfn
),
279 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev5", ev5_cpu_initfn
),
280 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn
),
281 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
283 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU
, "ev6", ev6_cpu_initfn
),
284 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn
),
285 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL
),
288 DEFINE_TYPES(alpha_cpu_type_infos
)