user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "translate-all.h"
  26
  27 #undef EAX
  28 #undef ECX
  29 #undef EDX
  30 #undef EBX
  31 #undef ESP
  32 #undef EBP
  33 #undef ESI
  34 #undef EDI
  35 #undef EIP
  36 #include <signal.h>
  37 #ifdef __linux__
  38 #include <sys/ucontext.h>
  39 #endif
  40
  41 //#define DEBUG_SIGNAL
  42
  43 static void exception_action(CPUState *cpu)
  44 {
  45 #if defined(TARGET_I386)
  46     X86CPU *x86_cpu = X86_CPU(cpu);
  47     CPUX86State *env1 = &x86_cpu->env;
  48
  49     raise_exception_err(env1, cpu->exception_index, env1->error_code);
  50 #else
  51     cpu_loop_exit(cpu);
  52 #endif
  53 }
  54
  55 /* exit the current TB from a signal handler. The host registers are
  56    restored in a state compatible with the CPU emulator
  57  */
  58 void cpu_resume_from_signal(CPUState *cpu, void *puc)
  59 {
  60 #ifdef __linux__
  61     struct ucontext *uc = puc;
  62 #elif defined(__OpenBSD__)
  63     struct sigcontext *uc = puc;
  64 #endif
  65
  66     if (puc) {
  67         /* XXX: use siglongjmp ? */
  68 #ifdef __linux__
  69 #ifdef __ia64
  70         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  71 #else
  72         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  73 #endif
  74 #elif defined(__OpenBSD__)
  75         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  76 #endif
  77     }
  78     cpu->exception_index = -1;
  79     siglongjmp(cpu->jmp_env, 1);
  80 }
  81
  82 /* 'pc' is the host PC at which the exception was raised. 'address' is
  83    the effective address of the memory exception. 'is_write' is 1 if a
  84    write caused the exception and otherwise 0'. 'old_set' is the
  85    signal set which should be restored */
  86 static inline int handle_cpu_signal(uintptr_t pc, void *ptr,
  87                                     int is_write, sigset_t *old_set,
  88                                     void *puc)
  89 {
  90     uintptr_t address = (uintptr_t)ptr;
  91     CPUState *cpu;
  92     CPUClass *cc;
  93     int ret;
  94
  95 #if defined(DEBUG_SIGNAL)
  96     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  97                 pc, address, is_write, *(unsigned long *)old_set);
  98 #endif
  99     /* XXX: locking issue */
 100     if (is_write && h2g_valid(address)
 101         && page_unprotect(h2g(address), pc, puc)) {
 102         return 1;
 103     }
 104
 105     /* Convert forcefully to guest address space, invalid addresses
 106        are still valid segv ones */
 107     address = h2g_nocheck(address);
 108
 109     cpu = current_cpu;
 110     cc = CPU_GET_CLASS(cpu);
 111     /* see if it is an MMU fault */
 112     g_assert(cc->handle_mmu_fault);
 113     ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
 114     if (ret < 0) {
 115         return 0; /* not an MMU fault */
 116     }
 117     if (ret == 0) {
 118         return 1; /* the MMU fault was handled without causing real CPU fault */
 119     }
 120     /* now we have a real cpu fault */
 121     cpu_restore_state(cpu, pc);
 122
 123     /* we restore the process signal mask as the sigreturn should
 124        do it (XXX: use sigsetjmp) */
 125     sigprocmask(SIG_SETMASK, old_set, NULL);
 126     exception_action(cpu);
 127
 128     /* never comes here */
 129     return 1;
 130 }
 131
 132 #if defined(__i386__)
 133
 134 #if defined(__APPLE__)
 135 #include <sys/ucontext.h>
 136
 137 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 138 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 139 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 140 #define MASK_sig(context)    ((context)->uc_sigmask)
 141 #elif defined(__NetBSD__)
 142 #include <ucontext.h>
 143
 144 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 145 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 146 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 147 #define MASK_sig(context)    ((context)->uc_sigmask)
 148 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 149 #include <ucontext.h>
 150
 151 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 152 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 153 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 154 #define MASK_sig(context)    ((context)->uc_sigmask)
 155 #elif defined(__OpenBSD__)
 156 #define EIP_sig(context)     ((context)->sc_eip)
 157 #define TRAP_sig(context)    ((context)->sc_trapno)
 158 #define ERROR_sig(context)   ((context)->sc_err)
 159 #define MASK_sig(context)    ((context)->sc_mask)
 160 #else
 161 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 162 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 163 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 164 #define MASK_sig(context)    ((context)->uc_sigmask)
 165 #endif
 166
 167 int cpu_signal_handler(int host_signum, void *pinfo,
 168                        void *puc)
 169 {
 170     siginfo_t *info = pinfo;
 171 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 172     ucontext_t *uc = puc;
 173 #elif defined(__OpenBSD__)
 174     struct sigcontext *uc = puc;
 175 #else
 176     struct ucontext *uc = puc;
 177 #endif
 178     uintptr_t pc;
 179     int trapno;
 180
 181 #ifndef REG_EIP
 182 /* for glibc 2.1 */
 183 #define REG_EIP    EIP
 184 #define REG_ERR    ERR
 185 #define REG_TRAPNO TRAPNO
 186 #endif
 187     pc = EIP_sig(uc);
 188     trapno = TRAP_sig(uc);
 189     return handle_cpu_signal(pc, info->si_addr,
 190                              trapno == 0xe ?
 191                              (ERROR_sig(uc) >> 1) & 1 : 0,
 192                              &MASK_sig(uc), puc);
 193 }
 194
 195 #elif defined(__x86_64__)
 196
 197 #ifdef __NetBSD__
 198 #define PC_sig(context)       _UC_MACHINE_PC(context)
 199 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 200 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 201 #define MASK_sig(context)     ((context)->uc_sigmask)
 202 #elif defined(__OpenBSD__)
 203 #define PC_sig(context)       ((context)->sc_rip)
 204 #define TRAP_sig(context)     ((context)->sc_trapno)
 205 #define ERROR_sig(context)    ((context)->sc_err)
 206 #define MASK_sig(context)     ((context)->sc_mask)
 207 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 208 #include <ucontext.h>
 209
 210 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 211 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 212 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 213 #define MASK_sig(context)     ((context)->uc_sigmask)
 214 #else
 215 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 216 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 217 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 218 #define MASK_sig(context)     ((context)->uc_sigmask)
 219 #endif
 220
 221 int cpu_signal_handler(int host_signum, void *pinfo,
 222                        void *puc)
 223 {
 224     siginfo_t *info = pinfo;
 225     uintptr_t pc;
 226 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 227     ucontext_t *uc = puc;
 228 #elif defined(__OpenBSD__)
 229     struct sigcontext *uc = puc;
 230 #else
 231     struct ucontext *uc = puc;
 232 #endif
 233
 234     pc = PC_sig(uc);
 235     return handle_cpu_signal(pc, info->si_addr,
 236                              TRAP_sig(uc) == 0xe ?
 237                              (ERROR_sig(uc) >> 1) & 1 : 0,
 238                              &MASK_sig(uc), puc);
 239 }
 240
 241 #elif defined(_ARCH_PPC)
 242
 243 /***********************************************************************
 244  * signal context platform-specific definitions
 245  * From Wine
 246  */
 247 #ifdef linux
 248 /* All Registers access - only for local access */
 249 #define REG_sig(reg_name, context)              \
 250     ((context)->uc_mcontext.regs->reg_name)
 251 /* Gpr Registers access  */
 252 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 253 /* Program counter */
 254 #define IAR_sig(context)                       REG_sig(nip, context)
 255 /* Machine State Register (Supervisor) */
 256 #define MSR_sig(context)                       REG_sig(msr, context)
 257 /* Count register */
 258 #define CTR_sig(context)                       REG_sig(ctr, context)
 259 /* User's integer exception register */
 260 #define XER_sig(context)                       REG_sig(xer, context)
 261 /* Link register */
 262 #define LR_sig(context)                        REG_sig(link, context)
 263 /* Condition register */
 264 #define CR_sig(context)                        REG_sig(ccr, context)
 265
 266 /* Float Registers access  */
 267 #define FLOAT_sig(reg_num, context)                                     \
 268     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 269 #define FPSCR_sig(context) \
 270     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 271 /* Exception Registers access */
 272 #define DAR_sig(context)                       REG_sig(dar, context)
 273 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 274 #define TRAP_sig(context)                      REG_sig(trap, context)
 275 #endif /* linux */
 276
 277 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 278 #include <ucontext.h>
 279 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 280 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 281 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 282 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 283 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 284 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 285 /* Exception Registers access */
 286 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 287 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 288 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 289 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 290
 291 #ifdef __APPLE__
 292 #include <sys/ucontext.h>
 293 typedef struct ucontext SIGCONTEXT;
 294 /* All Registers access - only for local access */
 295 #define REG_sig(reg_name, context)              \
 296     ((context)->uc_mcontext->ss.reg_name)
 297 #define FLOATREG_sig(reg_name, context)         \
 298     ((context)->uc_mcontext->fs.reg_name)
 299 #define EXCEPREG_sig(reg_name, context)         \
 300     ((context)->uc_mcontext->es.reg_name)
 301 #define VECREG_sig(reg_name, context)           \
 302     ((context)->uc_mcontext->vs.reg_name)
 303 /* Gpr Registers access */
 304 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 305 /* Program counter */
 306 #define IAR_sig(context)                       REG_sig(srr0, context)
 307 /* Machine State Register (Supervisor) */
 308 #define MSR_sig(context)                       REG_sig(srr1, context)
 309 #define CTR_sig(context)                       REG_sig(ctr, context)
 310 /* Link register */
 311 #define XER_sig(context)                       REG_sig(xer, context)
 312 /* User's integer exception register */
 313 #define LR_sig(context)                        REG_sig(lr, context)
 314 /* Condition register */
 315 #define CR_sig(context)                        REG_sig(cr, context)
 316 /* Float Registers access */
 317 #define FLOAT_sig(reg_num, context)             \
 318     FLOATREG_sig(fpregs[reg_num], context)
 319 #define FPSCR_sig(context)                      \
 320     ((double)FLOATREG_sig(fpscr, context))
 321 /* Exception Registers access */
 322 /* Fault registers for coredump */
 323 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 324 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 325 /* number of powerpc exception taken */
 326 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 327 #endif /* __APPLE__ */
 328
 329 int cpu_signal_handler(int host_signum, void *pinfo,
 330                        void *puc)
 331 {
 332     siginfo_t *info = pinfo;
 333 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 334     ucontext_t *uc = puc;
 335 #else
 336     struct ucontext *uc = puc;
 337 #endif
 338     uintptr_t pc;
 339     int is_write;
 340
 341     pc = IAR_sig(uc);
 342     is_write = 0;
 343 #if 0
 344     /* ppc 4xx case */
 345     if (DSISR_sig(uc) & 0x00800000) {
 346         is_write = 1;
 347     }
 348 #else
 349     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 350         is_write = 1;
 351     }
 352 #endif
 353     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 354 }
 355
 356 #elif defined(__alpha__)
 357
 358 int cpu_signal_handler(int host_signum, void *pinfo,
 359                            void *puc)
 360 {
 361     siginfo_t *info = pinfo;
 362     struct ucontext *uc = puc;
 363     uint32_t *pc = uc->uc_mcontext.sc_pc;
 364     uint32_t insn = *pc;
 365     int is_write = 0;
 366
 367     /* XXX: need kernel patch to get write flag faster */
 368     switch (insn >> 26) {
 369     case 0x0d: /* stw */
 370     case 0x0e: /* stb */
 371     case 0x0f: /* stq_u */
 372     case 0x24: /* stf */
 373     case 0x25: /* stg */
 374     case 0x26: /* sts */
 375     case 0x27: /* stt */
 376     case 0x2c: /* stl */
 377     case 0x2d: /* stq */
 378     case 0x2e: /* stl_c */
 379     case 0x2f: /* stq_c */
 380         is_write = 1;
 381     }
 382
 383     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 384 }
 385 #elif defined(__sparc__)
 386
 387 int cpu_signal_handler(int host_signum, void *pinfo,
 388                        void *puc)
 389 {
 390     siginfo_t *info = pinfo;
 391     int is_write;
 392     uint32_t insn;
 393 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 394     uint32_t *regs = (uint32_t *)(info + 1);
 395     void *sigmask = (regs + 20);
 396     /* XXX: is there a standard glibc define ? */
 397     uintptr_t pc = regs[1];
 398 #else
 399 #ifdef __linux__
 400     struct sigcontext *sc = puc;
 401     uintptr_t pc = sc->sigc_regs.tpc;
 402     void *sigmask = (void *)sc->sigc_mask;
 403 #elif defined(__OpenBSD__)
 404     struct sigcontext *uc = puc;
 405     uintptr_t pc = uc->sc_pc;
 406     void *sigmask = (void *)(long)uc->sc_mask;
 407 #elif defined(__NetBSD__)
 408     ucontext_t *uc = puc;
 409     unsigned long pc = _UC_MACHINE_PC(uc);
 410     void *sigmask = (void *)&uc->uc_sigmask;
 411 #endif
 412 #endif
 413
 414     /* XXX: need kernel patch to get write flag faster */
 415     is_write = 0;
 416     insn = *(uint32_t *)pc;
 417     if ((insn >> 30) == 3) {
 418         switch ((insn >> 19) & 0x3f) {
 419         case 0x05: /* stb */
 420         case 0x15: /* stba */
 421         case 0x06: /* sth */
 422         case 0x16: /* stha */
 423         case 0x04: /* st */
 424         case 0x14: /* sta */
 425         case 0x07: /* std */
 426         case 0x17: /* stda */
 427         case 0x0e: /* stx */
 428         case 0x1e: /* stxa */
 429         case 0x24: /* stf */
 430         case 0x34: /* stfa */
 431         case 0x27: /* stdf */
 432         case 0x37: /* stdfa */
 433         case 0x26: /* stqf */
 434         case 0x36: /* stqfa */
 435         case 0x25: /* stfsr */
 436         case 0x3c: /* casa */
 437         case 0x3e: /* casxa */
 438             is_write = 1;
 439             break;
 440         }
 441     }
 442     return handle_cpu_signal(pc, info->si_addr, is_write, sigmask, NULL);
 443 }
 444
 445 #elif defined(__arm__)
 446
 447 #if defined(__NetBSD__)
 448 #include <ucontext.h>
 449 #endif
 450
 451 int cpu_signal_handler(int host_signum, void *pinfo,
 452                        void *puc)
 453 {
 454     siginfo_t *info = pinfo;
 455 #if defined(__NetBSD__)
 456     ucontext_t *uc = puc;
 457 #else
 458     struct ucontext *uc = puc;
 459 #endif
 460     uintptr_t pc;
 461     int is_write;
 462
 463 #if defined(__NetBSD__)
 464     pc = uc->uc_mcontext.__gregs[_REG_R15];
 465 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 466     pc = uc->uc_mcontext.gregs[R15];
 467 #else
 468     pc = uc->uc_mcontext.arm_pc;
 469 #endif
 470
 471     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 472      * later processor; on v5 we will always report this as a read).
 473      */
 474     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 475     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 476 }
 477
 478 #elif defined(__aarch64__)
 479
 480 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 481 {
 482     siginfo_t *info = pinfo;
 483     struct ucontext *uc = puc;
 484     uintptr_t pc = uc->uc_mcontext.pc;
 485     uint32_t insn = *(uint32_t *)pc;
 486     bool is_write;
 487
 488     /* XXX: need kernel patch to get write flag faster.  */
 489     is_write = (   (insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 490                 || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 491                 || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 492                 || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 493                 || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 494                 || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 495                 || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 496                 /* Ingore bits 10, 11 & 21, controlling indexing.  */
 497                 || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 498                 || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 499                 /* Ignore bits 23 & 24, controlling indexing.  */
 500                 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 501
 502     return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
 503                              is_write, &uc->uc_sigmask, puc);
 504 }
 505
 506 #elif defined(__mc68000)
 507
 508 int cpu_signal_handler(int host_signum, void *pinfo,
 509                        void *puc)
 510 {
 511     siginfo_t *info = pinfo;
 512     struct ucontext *uc = puc;
 513     uintptr_t pc;
 514     int is_write;
 515
 516     pc = uc->uc_mcontext.gregs[16];
 517     /* XXX: compute is_write */
 518     is_write = 0;
 519     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 520 }
 521
 522 #elif defined(__ia64)
 523
 524 #ifndef __ISR_VALID
 525   /* This ought to be in <bits/siginfo.h>... */
 526 # define __ISR_VALID    1
 527 #endif
 528
 529 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 530 {
 531     siginfo_t *info = pinfo;
 532     struct ucontext *uc = puc;
 533     unsigned long ip;
 534     int is_write = 0;
 535
 536     ip = uc->uc_mcontext.sc_ip;
 537     switch (host_signum) {
 538     case SIGILL:
 539     case SIGFPE:
 540     case SIGSEGV:
 541     case SIGBUS:
 542     case SIGTRAP:
 543         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 544             /* ISR.W (write-access) is bit 33:  */
 545             is_write = (info->si_isr >> 33) & 1;
 546         }
 547         break;
 548
 549     default:
 550         break;
 551     }
 552     return handle_cpu_signal(ip, info->si_addr, is_write,
 553                              (sigset_t *)&uc->uc_sigmask, puc);
 554 }
 555
 556 #elif defined(__s390__)
 557
 558 int cpu_signal_handler(int host_signum, void *pinfo,
 559                        void *puc)
 560 {
 561     siginfo_t *info = pinfo;
 562     struct ucontext *uc = puc;
 563     uintptr_t pc;
 564     uint16_t *pinsn;
 565     int is_write = 0;
 566
 567     pc = uc->uc_mcontext.psw.addr;
 568
 569     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 570        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 571        from the hardware which does in fact contain the is_write value.
 572        The rt signal handler, as far as I can tell, does not give this value
 573        at all.  Not that we could get to it from here even if it were.  */
 574     /* ??? This is not even close to complete, since it ignores all
 575        of the read-modify-write instructions.  */
 576     pinsn = (uint16_t *)pc;
 577     switch (pinsn[0] >> 8) {
 578     case 0x50: /* ST */
 579     case 0x42: /* STC */
 580     case 0x40: /* STH */
 581         is_write = 1;
 582         break;
 583     case 0xc4: /* RIL format insns */
 584         switch (pinsn[0] & 0xf) {
 585         case 0xf: /* STRL */
 586         case 0xb: /* STGRL */
 587         case 0x7: /* STHRL */
 588             is_write = 1;
 589         }
 590         break;
 591     case 0xe3: /* RXY format insns */
 592         switch (pinsn[2] & 0xff) {
 593         case 0x50: /* STY */
 594         case 0x24: /* STG */
 595         case 0x72: /* STCY */
 596         case 0x70: /* STHY */
 597         case 0x8e: /* STPQ */
 598         case 0x3f: /* STRVH */
 599         case 0x3e: /* STRV */
 600         case 0x2f: /* STRVG */
 601             is_write = 1;
 602         }
 603         break;
 604     }
 605     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 606 }
 607
 608 #elif defined(__mips__)
 609
 610 int cpu_signal_handler(int host_signum, void *pinfo,
 611                        void *puc)
 612 {
 613     siginfo_t *info = pinfo;
 614     struct ucontext *uc = puc;
 615     greg_t pc = uc->uc_mcontext.pc;
 616     int is_write;
 617
 618     /* XXX: compute is_write */
 619     is_write = 0;
 620     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 621 }
 622
 623 #elif defined(__hppa__)
 624
 625 int cpu_signal_handler(int host_signum, void *pinfo,
 626                        void *puc)
 627 {
 628     siginfo_t *info = pinfo;
 629     struct ucontext *uc = puc;
 630     uintptr_t pc = uc->uc_mcontext.sc_iaoq[0];
 631     uint32_t insn = *(uint32_t *)pc;
 632     int is_write = 0;
 633
 634     /* XXX: need kernel patch to get write flag faster.  */
 635     switch (insn >> 26) {
 636     case 0x1a: /* STW */
 637     case 0x19: /* STH */
 638     case 0x18: /* STB */
 639     case 0x1b: /* STWM */
 640         is_write = 1;
 641         break;
 642
 643     case 0x09: /* CSTWX, FSTWX, FSTWS */
 644     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 645         /* Distinguish from coprocessor load ... */
 646         is_write = (insn >> 9) & 1;
 647         break;
 648
 649     case 0x03:
 650         switch ((insn >> 6) & 15) {
 651         case 0xa: /* STWS */
 652         case 0x9: /* STHS */
 653         case 0x8: /* STBS */
 654         case 0xe: /* STWAS */
 655         case 0xc: /* STBYS */
 656             is_write = 1;
 657         }
 658         break;
 659     }
 660
 661     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask, puc);
 662 }
 663
 664 #else
 665
 666 #error host CPU specific signal handler needed
 667
 668 #endif