1 // Copyright 2013, ARM Limited
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #ifndef VIXL_A64_CONSTANTS_A64_H_
28 #define VIXL_A64_CONSTANTS_A64_H_
32 const unsigned kNumberOfRegisters
= 32;
33 const unsigned kNumberOfFPRegisters
= 32;
35 #define REGISTER_CODE_LIST(R) \
36 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
37 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
38 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
39 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
41 #define INSTRUCTION_FIELDS_LIST(V_) \
42 /* Register fields */ \
43 V_(Rd, 4, 0, Bits) /* Destination register. */ \
44 V_(Rn, 9, 5, Bits) /* First source register. */ \
45 V_(Rm, 20, 16, Bits) /* Second source register. */ \
46 V_(Ra, 14, 10, Bits) /* Third source register. */ \
47 V_(Rt, 4, 0, Bits) /* Load/store register. */ \
48 V_(Rt2, 14, 10, Bits) /* Load/store second register. */ \
49 V_(Rs, 20, 16, Bits) /* Exclusive access status. */ \
52 V_(SixtyFourBits, 31, 31, Bits) \
53 V_(FlagsUpdate, 29, 29, Bits) \
55 /* PC relative addressing */ \
56 V_(ImmPCRelHi, 23, 5, SignedBits) \
57 V_(ImmPCRelLo, 30, 29, Bits) \
59 /* Add/subtract/logical shift register */ \
60 V_(ShiftDP, 23, 22, Bits) \
61 V_(ImmDPShift, 15, 10, Bits) \
63 /* Add/subtract immediate */ \
64 V_(ImmAddSub, 21, 10, Bits) \
65 V_(ShiftAddSub, 23, 22, Bits) \
67 /* Add/substract extend */ \
68 V_(ImmExtendShift, 12, 10, Bits) \
69 V_(ExtendMode, 15, 13, Bits) \
72 V_(ImmMoveWide, 20, 5, Bits) \
73 V_(ShiftMoveWide, 22, 21, Bits) \
75 /* Logical immediate, bitfield and extract */ \
76 V_(BitN, 22, 22, Bits) \
77 V_(ImmRotate, 21, 16, Bits) \
78 V_(ImmSetBits, 15, 10, Bits) \
79 V_(ImmR, 21, 16, Bits) \
80 V_(ImmS, 15, 10, Bits) \
82 /* Test and branch immediate */ \
83 V_(ImmTestBranch, 18, 5, SignedBits) \
84 V_(ImmTestBranchBit40, 23, 19, Bits) \
85 V_(ImmTestBranchBit5, 31, 31, Bits) \
88 V_(Condition, 15, 12, Bits) \
89 V_(ConditionBranch, 3, 0, Bits) \
90 V_(Nzcv, 3, 0, Bits) \
91 V_(ImmCondCmp, 20, 16, Bits) \
92 V_(ImmCondBranch, 23, 5, SignedBits) \
94 /* Floating point */ \
95 V_(FPType, 23, 22, Bits) \
96 V_(ImmFP, 20, 13, Bits) \
97 V_(FPScale, 15, 10, Bits) \
100 V_(ImmLS, 20, 12, SignedBits) \
101 V_(ImmLSUnsigned, 21, 10, Bits) \
102 V_(ImmLSPair, 21, 15, SignedBits) \
103 V_(SizeLS, 31, 30, Bits) \
104 V_(ImmShiftLS, 12, 12, Bits) \
105 V_(ImmPrefetchOperation, 4, 0, Bits) \
106 V_(PrefetchHint, 4, 3, Bits) \
107 V_(PrefetchTarget, 2, 1, Bits) \
108 V_(PrefetchStream, 0, 0, Bits) \
110 /* Other immediates */ \
111 V_(ImmUncondBranch, 25, 0, SignedBits) \
112 V_(ImmCmpBranch, 23, 5, SignedBits) \
113 V_(ImmLLiteral, 23, 5, SignedBits) \
114 V_(ImmException, 20, 5, Bits) \
115 V_(ImmHint, 11, 5, Bits) \
116 V_(ImmBarrierDomain, 11, 10, Bits) \
117 V_(ImmBarrierType, 9, 8, Bits) \
119 /* System (MRS, MSR) */ \
120 V_(ImmSystemRegister, 19, 5, Bits) \
121 V_(SysO0, 19, 19, Bits) \
122 V_(SysOp1, 18, 16, Bits) \
123 V_(SysOp2, 7, 5, Bits) \
124 V_(CRn, 15, 12, Bits) \
125 V_(CRm, 11, 8, Bits) \
127 /* Load-/store-exclusive */ \
128 V_(LdStXLoad, 22, 22, Bits) \
129 V_(LdStXNotExclusive, 23, 23, Bits) \
130 V_(LdStXAcquireRelease, 15, 15, Bits) \
131 V_(LdStXSizeLog2, 31, 30, Bits) \
132 V_(LdStXPair, 21, 21, Bits) \
135 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
137 V_(Flags, 31, 28, Bits) \
138 V_(N, 31, 31, Bits) \
139 V_(Z, 30, 30, Bits) \
140 V_(C, 29, 29, Bits) \
141 V_(V, 28, 28, Bits) \
142 M_(NZCV, Flags_mask) \
145 V_(AHP, 26, 26, Bits) \
146 V_(DN, 25, 25, Bits) \
147 V_(FZ, 24, 24, Bits) \
148 V_(RMode, 23, 22, Bits) \
149 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
153 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
154 const int Name##_offset = LowBit; \
155 const int Name##_width = HighBit - LowBit + 1; \
156 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
157 #define NOTHING(A, B)
158 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS
)
159 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS
, NOTHING
)
161 #undef DECLARE_FIELDS_BITS
163 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
164 // from ImmPCRelLo and ImmPCRelHi.
165 const int ImmPCRel_mask
= ImmPCRelLo_mask
| ImmPCRelHi_mask
;
184 nv
= 15 // Behaves as always/al.
187 inline Condition
InvertCondition(Condition cond
) {
188 // Conditions al and nv behave identically, as "always true". They can't be
189 // inverted, because there is no "always false" condition.
190 VIXL_ASSERT((cond
!= al
) && (cond
!= nv
));
191 return static_cast<Condition
>(cond
^ 1);
202 // Derive the flag combinations from the system register bit descriptions.
207 NZFlag
= NFlag
| ZFlag
,
208 NCFlag
= NFlag
| CFlag
,
209 NVFlag
= NFlag
| VFlag
,
210 ZCFlag
= ZFlag
| CFlag
,
211 ZVFlag
= ZFlag
| VFlag
,
212 CVFlag
= CFlag
| VFlag
,
213 NZCFlag
= NFlag
| ZFlag
| CFlag
,
214 NZVFlag
= NFlag
| ZFlag
| VFlag
,
215 NCVFlag
= NFlag
| CFlag
| VFlag
,
216 ZCVFlag
= ZFlag
| CFlag
| VFlag
,
217 NZCVFlag
= NFlag
| ZFlag
| CFlag
| VFlag
,
219 // Floating-point comparison results.
220 FPEqualFlag
= ZCFlag
,
221 FPLessThanFlag
= NFlag
,
222 FPGreaterThanFlag
= CFlag
,
223 FPUnorderedFlag
= CVFlag
269 enum PrefetchOperation
{
292 // System/special register names.
293 // This information is not encoded as one field but as the concatenation of
294 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
295 enum SystemRegister
{
296 NZCV
= ((0x1 << SysO0_offset
) |
297 (0x3 << SysOp1_offset
) |
298 (0x4 << CRn_offset
) |
299 (0x2 << CRm_offset
) |
300 (0x0 << SysOp2_offset
)) >> ImmSystemRegister_offset
,
301 FPCR
= ((0x1 << SysO0_offset
) |
302 (0x3 << SysOp1_offset
) |
303 (0x4 << CRn_offset
) |
304 (0x4 << CRm_offset
) |
305 (0x0 << SysOp2_offset
)) >> ImmSystemRegister_offset
308 // Instruction enumerations.
310 // These are the masks that define a class of instructions, and the list of
311 // instructions within each class. Each enumeration has a Fixed, FMask and
314 // Fixed: The fixed bits in this instruction class.
315 // FMask: The mask used to extract the fixed bits in the class.
316 // Mask: The mask used to identify the instructions within a class.
318 // The enumerations can be used like this:
320 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
321 // switch(instr->Mask(PCRelAddressingMask)) {
322 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
323 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
324 // default: printf("Unknown instruction\n");
329 enum GenericInstrField
{
330 SixtyFourBits
= 0x80000000,
331 ThirtyTwoBits
= 0x00000000,
336 // PC relative addressing.
337 enum PCRelAddressingOp
{
338 PCRelAddressingFixed
= 0x10000000,
339 PCRelAddressingFMask
= 0x1F000000,
340 PCRelAddressingMask
= 0x9F000000,
341 ADR
= PCRelAddressingFixed
| 0x00000000,
342 ADRP
= PCRelAddressingFixed
| 0x80000000
345 // Add/sub (immediate, shifted and extended.)
346 const int kSFOffset
= 31;
348 AddSubOpMask
= 0x60000000,
349 AddSubSetFlagsBit
= 0x20000000,
351 ADDS
= ADD
| AddSubSetFlagsBit
,
353 SUBS
= SUB
| AddSubSetFlagsBit
356 #define ADD_SUB_OP_LIST(V) \
362 enum AddSubImmediateOp
{
363 AddSubImmediateFixed
= 0x11000000,
364 AddSubImmediateFMask
= 0x1F000000,
365 AddSubImmediateMask
= 0xFF000000,
366 #define ADD_SUB_IMMEDIATE(A) \
367 A##_w_imm = AddSubImmediateFixed | A, \
368 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
369 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE
)
370 #undef ADD_SUB_IMMEDIATE
373 enum AddSubShiftedOp
{
374 AddSubShiftedFixed
= 0x0B000000,
375 AddSubShiftedFMask
= 0x1F200000,
376 AddSubShiftedMask
= 0xFF200000,
377 #define ADD_SUB_SHIFTED(A) \
378 A##_w_shift = AddSubShiftedFixed | A, \
379 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
380 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED
)
381 #undef ADD_SUB_SHIFTED
384 enum AddSubExtendedOp
{
385 AddSubExtendedFixed
= 0x0B200000,
386 AddSubExtendedFMask
= 0x1F200000,
387 AddSubExtendedMask
= 0xFFE00000,
388 #define ADD_SUB_EXTENDED(A) \
389 A##_w_ext = AddSubExtendedFixed | A, \
390 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
391 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED
)
392 #undef ADD_SUB_EXTENDED
395 // Add/sub with carry.
396 enum AddSubWithCarryOp
{
397 AddSubWithCarryFixed
= 0x1A000000,
398 AddSubWithCarryFMask
= 0x1FE00000,
399 AddSubWithCarryMask
= 0xFFE0FC00,
400 ADC_w
= AddSubWithCarryFixed
| ADD
,
401 ADC_x
= AddSubWithCarryFixed
| ADD
| SixtyFourBits
,
403 ADCS_w
= AddSubWithCarryFixed
| ADDS
,
404 ADCS_x
= AddSubWithCarryFixed
| ADDS
| SixtyFourBits
,
405 SBC_w
= AddSubWithCarryFixed
| SUB
,
406 SBC_x
= AddSubWithCarryFixed
| SUB
| SixtyFourBits
,
408 SBCS_w
= AddSubWithCarryFixed
| SUBS
,
409 SBCS_x
= AddSubWithCarryFixed
| SUBS
| SixtyFourBits
413 // Logical (immediate and shifted register).
415 LogicalOpMask
= 0x60200000,
427 // Logical immediate.
428 enum LogicalImmediateOp
{
429 LogicalImmediateFixed
= 0x12000000,
430 LogicalImmediateFMask
= 0x1F800000,
431 LogicalImmediateMask
= 0xFF800000,
432 AND_w_imm
= LogicalImmediateFixed
| AND
,
433 AND_x_imm
= LogicalImmediateFixed
| AND
| SixtyFourBits
,
434 ORR_w_imm
= LogicalImmediateFixed
| ORR
,
435 ORR_x_imm
= LogicalImmediateFixed
| ORR
| SixtyFourBits
,
436 EOR_w_imm
= LogicalImmediateFixed
| EOR
,
437 EOR_x_imm
= LogicalImmediateFixed
| EOR
| SixtyFourBits
,
438 ANDS_w_imm
= LogicalImmediateFixed
| ANDS
,
439 ANDS_x_imm
= LogicalImmediateFixed
| ANDS
| SixtyFourBits
442 // Logical shifted register.
443 enum LogicalShiftedOp
{
444 LogicalShiftedFixed
= 0x0A000000,
445 LogicalShiftedFMask
= 0x1F000000,
446 LogicalShiftedMask
= 0xFF200000,
447 AND_w
= LogicalShiftedFixed
| AND
,
448 AND_x
= LogicalShiftedFixed
| AND
| SixtyFourBits
,
450 BIC_w
= LogicalShiftedFixed
| BIC
,
451 BIC_x
= LogicalShiftedFixed
| BIC
| SixtyFourBits
,
453 ORR_w
= LogicalShiftedFixed
| ORR
,
454 ORR_x
= LogicalShiftedFixed
| ORR
| SixtyFourBits
,
456 ORN_w
= LogicalShiftedFixed
| ORN
,
457 ORN_x
= LogicalShiftedFixed
| ORN
| SixtyFourBits
,
459 EOR_w
= LogicalShiftedFixed
| EOR
,
460 EOR_x
= LogicalShiftedFixed
| EOR
| SixtyFourBits
,
462 EON_w
= LogicalShiftedFixed
| EON
,
463 EON_x
= LogicalShiftedFixed
| EON
| SixtyFourBits
,
465 ANDS_w
= LogicalShiftedFixed
| ANDS
,
466 ANDS_x
= LogicalShiftedFixed
| ANDS
| SixtyFourBits
,
468 BICS_w
= LogicalShiftedFixed
| BICS
,
469 BICS_x
= LogicalShiftedFixed
| BICS
| SixtyFourBits
,
473 // Move wide immediate.
474 enum MoveWideImmediateOp
{
475 MoveWideImmediateFixed
= 0x12800000,
476 MoveWideImmediateFMask
= 0x1F800000,
477 MoveWideImmediateMask
= 0xFF800000,
481 MOVN_w
= MoveWideImmediateFixed
| MOVN
,
482 MOVN_x
= MoveWideImmediateFixed
| MOVN
| SixtyFourBits
,
483 MOVZ_w
= MoveWideImmediateFixed
| MOVZ
,
484 MOVZ_x
= MoveWideImmediateFixed
| MOVZ
| SixtyFourBits
,
485 MOVK_w
= MoveWideImmediateFixed
| MOVK
,
486 MOVK_x
= MoveWideImmediateFixed
| MOVK
| SixtyFourBits
490 const int kBitfieldNOffset
= 22;
492 BitfieldFixed
= 0x13000000,
493 BitfieldFMask
= 0x1F800000,
494 BitfieldMask
= 0xFF800000,
495 SBFM_w
= BitfieldFixed
| 0x00000000,
496 SBFM_x
= BitfieldFixed
| 0x80000000,
498 BFM_w
= BitfieldFixed
| 0x20000000,
499 BFM_x
= BitfieldFixed
| 0xA0000000,
501 UBFM_w
= BitfieldFixed
| 0x40000000,
502 UBFM_x
= BitfieldFixed
| 0xC0000000,
509 ExtractFixed
= 0x13800000,
510 ExtractFMask
= 0x1F800000,
511 ExtractMask
= 0xFFA00000,
512 EXTR_w
= ExtractFixed
| 0x00000000,
513 EXTR_x
= ExtractFixed
| 0x80000000,
517 // Unconditional branch.
518 enum UnconditionalBranchOp
{
519 UnconditionalBranchFixed
= 0x14000000,
520 UnconditionalBranchFMask
= 0x7C000000,
521 UnconditionalBranchMask
= 0xFC000000,
522 B
= UnconditionalBranchFixed
| 0x00000000,
523 BL
= UnconditionalBranchFixed
| 0x80000000
526 // Unconditional branch to register.
527 enum UnconditionalBranchToRegisterOp
{
528 UnconditionalBranchToRegisterFixed
= 0xD6000000,
529 UnconditionalBranchToRegisterFMask
= 0xFE000000,
530 UnconditionalBranchToRegisterMask
= 0xFFFFFC1F,
531 BR
= UnconditionalBranchToRegisterFixed
| 0x001F0000,
532 BLR
= UnconditionalBranchToRegisterFixed
| 0x003F0000,
533 RET
= UnconditionalBranchToRegisterFixed
| 0x005F0000
536 // Compare and branch.
537 enum CompareBranchOp
{
538 CompareBranchFixed
= 0x34000000,
539 CompareBranchFMask
= 0x7E000000,
540 CompareBranchMask
= 0xFF000000,
541 CBZ_w
= CompareBranchFixed
| 0x00000000,
542 CBZ_x
= CompareBranchFixed
| 0x80000000,
544 CBNZ_w
= CompareBranchFixed
| 0x01000000,
545 CBNZ_x
= CompareBranchFixed
| 0x81000000,
551 TestBranchFixed
= 0x36000000,
552 TestBranchFMask
= 0x7E000000,
553 TestBranchMask
= 0x7F000000,
554 TBZ
= TestBranchFixed
| 0x00000000,
555 TBNZ
= TestBranchFixed
| 0x01000000
558 // Conditional branch.
559 enum ConditionalBranchOp
{
560 ConditionalBranchFixed
= 0x54000000,
561 ConditionalBranchFMask
= 0xFE000000,
562 ConditionalBranchMask
= 0xFF000010,
563 B_cond
= ConditionalBranchFixed
| 0x00000000
567 // System instruction encoding is complicated because some instructions use op
568 // and CR fields to encode parameters. To handle this cleanly, the system
569 // instructions are split into more than one enum.
572 SystemFixed
= 0xD5000000,
573 SystemFMask
= 0xFFC00000
576 enum SystemSysRegOp
{
577 SystemSysRegFixed
= 0xD5100000,
578 SystemSysRegFMask
= 0xFFD00000,
579 SystemSysRegMask
= 0xFFF00000,
580 MRS
= SystemSysRegFixed
| 0x00200000,
581 MSR
= SystemSysRegFixed
| 0x00000000
585 SystemHintFixed
= 0xD503201F,
586 SystemHintFMask
= 0xFFFFF01F,
587 SystemHintMask
= 0xFFFFF01F,
588 HINT
= SystemHintFixed
| 0x00000000
593 ExceptionFixed
= 0xD4000000,
594 ExceptionFMask
= 0xFF000000,
595 ExceptionMask
= 0xFFE0001F,
596 HLT
= ExceptionFixed
| 0x00400000,
597 BRK
= ExceptionFixed
| 0x00200000,
598 SVC
= ExceptionFixed
| 0x00000001,
599 HVC
= ExceptionFixed
| 0x00000002,
600 SMC
= ExceptionFixed
| 0x00000003,
601 DCPS1
= ExceptionFixed
| 0x00A00001,
602 DCPS2
= ExceptionFixed
| 0x00A00002,
603 DCPS3
= ExceptionFixed
| 0x00A00003
607 MemBarrierFixed
= 0xD503309F,
608 MemBarrierFMask
= 0xFFFFF09F,
609 MemBarrierMask
= 0xFFFFF0FF,
610 DSB
= MemBarrierFixed
| 0x00000000,
611 DMB
= MemBarrierFixed
| 0x00000020,
612 ISB
= MemBarrierFixed
| 0x00000040
615 enum SystemExclusiveMonitorOp
{
616 SystemExclusiveMonitorFixed
= 0xD503305F,
617 SystemExclusiveMonitorFMask
= 0xFFFFF0FF,
618 SystemExclusiveMonitorMask
= 0xFFFFF0FF,
619 CLREX
= SystemExclusiveMonitorFixed
622 // Any load or store.
623 enum LoadStoreAnyOp
{
624 LoadStoreAnyFMask
= 0x0a000000,
625 LoadStoreAnyFixed
= 0x08000000
628 // Any load pair or store pair.
629 enum LoadStorePairAnyOp
{
630 LoadStorePairAnyFMask
= 0x3a000000,
631 LoadStorePairAnyFixed
= 0x28000000
634 #define LOAD_STORE_PAIR_OP_LIST(V) \
635 V(STP, w, 0x00000000), \
636 V(LDP, w, 0x00400000), \
637 V(LDPSW, x, 0x40400000), \
638 V(STP, x, 0x80000000), \
639 V(LDP, x, 0x80400000), \
640 V(STP, s, 0x04000000), \
641 V(LDP, s, 0x04400000), \
642 V(STP, d, 0x44000000), \
643 V(LDP, d, 0x44400000)
645 // Load/store pair (post, pre and offset.)
646 enum LoadStorePairOp
{
647 LoadStorePairMask
= 0xC4400000,
648 LoadStorePairLBit
= 1 << 22,
649 #define LOAD_STORE_PAIR(A, B, C) \
651 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR
)
652 #undef LOAD_STORE_PAIR
655 enum LoadStorePairPostIndexOp
{
656 LoadStorePairPostIndexFixed
= 0x28800000,
657 LoadStorePairPostIndexFMask
= 0x3B800000,
658 LoadStorePairPostIndexMask
= 0xFFC00000,
659 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
660 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
661 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX
)
662 #undef LOAD_STORE_PAIR_POST_INDEX
665 enum LoadStorePairPreIndexOp
{
666 LoadStorePairPreIndexFixed
= 0x29800000,
667 LoadStorePairPreIndexFMask
= 0x3B800000,
668 LoadStorePairPreIndexMask
= 0xFFC00000,
669 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
670 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
671 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX
)
672 #undef LOAD_STORE_PAIR_PRE_INDEX
675 enum LoadStorePairOffsetOp
{
676 LoadStorePairOffsetFixed
= 0x29000000,
677 LoadStorePairOffsetFMask
= 0x3B800000,
678 LoadStorePairOffsetMask
= 0xFFC00000,
679 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
680 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
681 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET
)
682 #undef LOAD_STORE_PAIR_OFFSET
685 enum LoadStorePairNonTemporalOp
{
686 LoadStorePairNonTemporalFixed
= 0x28000000,
687 LoadStorePairNonTemporalFMask
= 0x3B800000,
688 LoadStorePairNonTemporalMask
= 0xFFC00000,
689 STNP_w
= LoadStorePairNonTemporalFixed
| STP_w
,
690 LDNP_w
= LoadStorePairNonTemporalFixed
| LDP_w
,
691 STNP_x
= LoadStorePairNonTemporalFixed
| STP_x
,
692 LDNP_x
= LoadStorePairNonTemporalFixed
| LDP_x
,
693 STNP_s
= LoadStorePairNonTemporalFixed
| STP_s
,
694 LDNP_s
= LoadStorePairNonTemporalFixed
| LDP_s
,
695 STNP_d
= LoadStorePairNonTemporalFixed
| STP_d
,
696 LDNP_d
= LoadStorePairNonTemporalFixed
| LDP_d
701 LoadLiteralFixed
= 0x18000000,
702 LoadLiteralFMask
= 0x3B000000,
703 LoadLiteralMask
= 0xFF000000,
704 LDR_w_lit
= LoadLiteralFixed
| 0x00000000,
705 LDR_x_lit
= LoadLiteralFixed
| 0x40000000,
706 LDRSW_x_lit
= LoadLiteralFixed
| 0x80000000,
707 PRFM_lit
= LoadLiteralFixed
| 0xC0000000,
708 LDR_s_lit
= LoadLiteralFixed
| 0x04000000,
709 LDR_d_lit
= LoadLiteralFixed
| 0x44000000
712 #define LOAD_STORE_OP_LIST(V) \
713 V(ST, RB, w, 0x00000000), \
714 V(ST, RH, w, 0x40000000), \
715 V(ST, R, w, 0x80000000), \
716 V(ST, R, x, 0xC0000000), \
717 V(LD, RB, w, 0x00400000), \
718 V(LD, RH, w, 0x40400000), \
719 V(LD, R, w, 0x80400000), \
720 V(LD, R, x, 0xC0400000), \
721 V(LD, RSB, x, 0x00800000), \
722 V(LD, RSH, x, 0x40800000), \
723 V(LD, RSW, x, 0x80800000), \
724 V(LD, RSB, w, 0x00C00000), \
725 V(LD, RSH, w, 0x40C00000), \
726 V(ST, R, s, 0x84000000), \
727 V(ST, R, d, 0xC4000000), \
728 V(LD, R, s, 0x84400000), \
729 V(LD, R, d, 0xC4400000)
732 // Load/store (post, pre, offset and unsigned.)
734 LoadStoreOpMask
= 0xC4C00000,
735 #define LOAD_STORE(A, B, C, D) \
737 LOAD_STORE_OP_LIST(LOAD_STORE
),
742 // Load/store unscaled offset.
743 enum LoadStoreUnscaledOffsetOp
{
744 LoadStoreUnscaledOffsetFixed
= 0x38000000,
745 LoadStoreUnscaledOffsetFMask
= 0x3B200C00,
746 LoadStoreUnscaledOffsetMask
= 0xFFE00C00,
747 PRFUM
= LoadStoreUnscaledOffsetFixed
| PRFM
,
748 #define LOAD_STORE_UNSCALED(A, B, C, D) \
749 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
750 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED
)
751 #undef LOAD_STORE_UNSCALED
754 // Load/store post index.
755 enum LoadStorePostIndex
{
756 LoadStorePostIndexFixed
= 0x38000400,
757 LoadStorePostIndexFMask
= 0x3B200C00,
758 LoadStorePostIndexMask
= 0xFFE00C00,
759 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
760 A##B##_##C##_post = LoadStorePostIndexFixed | D
761 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX
)
762 #undef LOAD_STORE_POST_INDEX
765 // Load/store pre index.
766 enum LoadStorePreIndex
{
767 LoadStorePreIndexFixed
= 0x38000C00,
768 LoadStorePreIndexFMask
= 0x3B200C00,
769 LoadStorePreIndexMask
= 0xFFE00C00,
770 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
771 A##B##_##C##_pre = LoadStorePreIndexFixed | D
772 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX
)
773 #undef LOAD_STORE_PRE_INDEX
776 // Load/store unsigned offset.
777 enum LoadStoreUnsignedOffset
{
778 LoadStoreUnsignedOffsetFixed
= 0x39000000,
779 LoadStoreUnsignedOffsetFMask
= 0x3B000000,
780 LoadStoreUnsignedOffsetMask
= 0xFFC00000,
781 PRFM_unsigned
= LoadStoreUnsignedOffsetFixed
| PRFM
,
782 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
783 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
784 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET
)
785 #undef LOAD_STORE_UNSIGNED_OFFSET
788 // Load/store register offset.
789 enum LoadStoreRegisterOffset
{
790 LoadStoreRegisterOffsetFixed
= 0x38200800,
791 LoadStoreRegisterOffsetFMask
= 0x3B200C00,
792 LoadStoreRegisterOffsetMask
= 0xFFE00C00,
793 PRFM_reg
= LoadStoreRegisterOffsetFixed
| PRFM
,
794 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
795 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
796 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET
)
797 #undef LOAD_STORE_REGISTER_OFFSET
800 enum LoadStoreExclusive
{
801 LoadStoreExclusiveFixed
= 0x08000000,
802 LoadStoreExclusiveFMask
= 0x3F000000,
803 LoadStoreExclusiveMask
= 0xFFE08000,
804 STXRB_w
= LoadStoreExclusiveFixed
| 0x00000000,
805 STXRH_w
= LoadStoreExclusiveFixed
| 0x40000000,
806 STXR_w
= LoadStoreExclusiveFixed
| 0x80000000,
807 STXR_x
= LoadStoreExclusiveFixed
| 0xC0000000,
808 LDXRB_w
= LoadStoreExclusiveFixed
| 0x00400000,
809 LDXRH_w
= LoadStoreExclusiveFixed
| 0x40400000,
810 LDXR_w
= LoadStoreExclusiveFixed
| 0x80400000,
811 LDXR_x
= LoadStoreExclusiveFixed
| 0xC0400000,
812 STXP_w
= LoadStoreExclusiveFixed
| 0x80200000,
813 STXP_x
= LoadStoreExclusiveFixed
| 0xC0200000,
814 LDXP_w
= LoadStoreExclusiveFixed
| 0x80600000,
815 LDXP_x
= LoadStoreExclusiveFixed
| 0xC0600000,
816 STLXRB_w
= LoadStoreExclusiveFixed
| 0x00008000,
817 STLXRH_w
= LoadStoreExclusiveFixed
| 0x40008000,
818 STLXR_w
= LoadStoreExclusiveFixed
| 0x80008000,
819 STLXR_x
= LoadStoreExclusiveFixed
| 0xC0008000,
820 LDAXRB_w
= LoadStoreExclusiveFixed
| 0x00408000,
821 LDAXRH_w
= LoadStoreExclusiveFixed
| 0x40408000,
822 LDAXR_w
= LoadStoreExclusiveFixed
| 0x80408000,
823 LDAXR_x
= LoadStoreExclusiveFixed
| 0xC0408000,
824 STLXP_w
= LoadStoreExclusiveFixed
| 0x80208000,
825 STLXP_x
= LoadStoreExclusiveFixed
| 0xC0208000,
826 LDAXP_w
= LoadStoreExclusiveFixed
| 0x80608000,
827 LDAXP_x
= LoadStoreExclusiveFixed
| 0xC0608000,
828 STLRB_w
= LoadStoreExclusiveFixed
| 0x00808000,
829 STLRH_w
= LoadStoreExclusiveFixed
| 0x40808000,
830 STLR_w
= LoadStoreExclusiveFixed
| 0x80808000,
831 STLR_x
= LoadStoreExclusiveFixed
| 0xC0808000,
832 LDARB_w
= LoadStoreExclusiveFixed
| 0x00C08000,
833 LDARH_w
= LoadStoreExclusiveFixed
| 0x40C08000,
834 LDAR_w
= LoadStoreExclusiveFixed
| 0x80C08000,
835 LDAR_x
= LoadStoreExclusiveFixed
| 0xC0C08000
838 // Conditional compare.
839 enum ConditionalCompareOp
{
840 ConditionalCompareMask
= 0x60000000,
845 // Conditional compare register.
846 enum ConditionalCompareRegisterOp
{
847 ConditionalCompareRegisterFixed
= 0x1A400000,
848 ConditionalCompareRegisterFMask
= 0x1FE00800,
849 ConditionalCompareRegisterMask
= 0xFFE00C10,
850 CCMN_w
= ConditionalCompareRegisterFixed
| CCMN
,
851 CCMN_x
= ConditionalCompareRegisterFixed
| SixtyFourBits
| CCMN
,
852 CCMP_w
= ConditionalCompareRegisterFixed
| CCMP
,
853 CCMP_x
= ConditionalCompareRegisterFixed
| SixtyFourBits
| CCMP
856 // Conditional compare immediate.
857 enum ConditionalCompareImmediateOp
{
858 ConditionalCompareImmediateFixed
= 0x1A400800,
859 ConditionalCompareImmediateFMask
= 0x1FE00800,
860 ConditionalCompareImmediateMask
= 0xFFE00C10,
861 CCMN_w_imm
= ConditionalCompareImmediateFixed
| CCMN
,
862 CCMN_x_imm
= ConditionalCompareImmediateFixed
| SixtyFourBits
| CCMN
,
863 CCMP_w_imm
= ConditionalCompareImmediateFixed
| CCMP
,
864 CCMP_x_imm
= ConditionalCompareImmediateFixed
| SixtyFourBits
| CCMP
867 // Conditional select.
868 enum ConditionalSelectOp
{
869 ConditionalSelectFixed
= 0x1A800000,
870 ConditionalSelectFMask
= 0x1FE00000,
871 ConditionalSelectMask
= 0xFFE00C00,
872 CSEL_w
= ConditionalSelectFixed
| 0x00000000,
873 CSEL_x
= ConditionalSelectFixed
| 0x80000000,
875 CSINC_w
= ConditionalSelectFixed
| 0x00000400,
876 CSINC_x
= ConditionalSelectFixed
| 0x80000400,
878 CSINV_w
= ConditionalSelectFixed
| 0x40000000,
879 CSINV_x
= ConditionalSelectFixed
| 0xC0000000,
881 CSNEG_w
= ConditionalSelectFixed
| 0x40000400,
882 CSNEG_x
= ConditionalSelectFixed
| 0xC0000400,
886 // Data processing 1 source.
887 enum DataProcessing1SourceOp
{
888 DataProcessing1SourceFixed
= 0x5AC00000,
889 DataProcessing1SourceFMask
= 0x5FE00000,
890 DataProcessing1SourceMask
= 0xFFFFFC00,
891 RBIT
= DataProcessing1SourceFixed
| 0x00000000,
893 RBIT_x
= RBIT
| SixtyFourBits
,
894 REV16
= DataProcessing1SourceFixed
| 0x00000400,
896 REV16_x
= REV16
| SixtyFourBits
,
897 REV
= DataProcessing1SourceFixed
| 0x00000800,
899 REV32_x
= REV
| SixtyFourBits
,
900 REV_x
= DataProcessing1SourceFixed
| SixtyFourBits
| 0x00000C00,
901 CLZ
= DataProcessing1SourceFixed
| 0x00001000,
903 CLZ_x
= CLZ
| SixtyFourBits
,
904 CLS
= DataProcessing1SourceFixed
| 0x00001400,
906 CLS_x
= CLS
| SixtyFourBits
909 // Data processing 2 source.
910 enum DataProcessing2SourceOp
{
911 DataProcessing2SourceFixed
= 0x1AC00000,
912 DataProcessing2SourceFMask
= 0x5FE00000,
913 DataProcessing2SourceMask
= 0xFFE0FC00,
914 UDIV_w
= DataProcessing2SourceFixed
| 0x00000800,
915 UDIV_x
= DataProcessing2SourceFixed
| 0x80000800,
917 SDIV_w
= DataProcessing2SourceFixed
| 0x00000C00,
918 SDIV_x
= DataProcessing2SourceFixed
| 0x80000C00,
920 LSLV_w
= DataProcessing2SourceFixed
| 0x00002000,
921 LSLV_x
= DataProcessing2SourceFixed
| 0x80002000,
923 LSRV_w
= DataProcessing2SourceFixed
| 0x00002400,
924 LSRV_x
= DataProcessing2SourceFixed
| 0x80002400,
926 ASRV_w
= DataProcessing2SourceFixed
| 0x00002800,
927 ASRV_x
= DataProcessing2SourceFixed
| 0x80002800,
929 RORV_w
= DataProcessing2SourceFixed
| 0x00002C00,
930 RORV_x
= DataProcessing2SourceFixed
| 0x80002C00,
932 CRC32B
= DataProcessing2SourceFixed
| 0x00004000,
933 CRC32H
= DataProcessing2SourceFixed
| 0x00004400,
934 CRC32W
= DataProcessing2SourceFixed
| 0x00004800,
935 CRC32X
= DataProcessing2SourceFixed
| SixtyFourBits
| 0x00004C00,
936 CRC32CB
= DataProcessing2SourceFixed
| 0x00005000,
937 CRC32CH
= DataProcessing2SourceFixed
| 0x00005400,
938 CRC32CW
= DataProcessing2SourceFixed
| 0x00005800,
939 CRC32CX
= DataProcessing2SourceFixed
| SixtyFourBits
| 0x00005C00
942 // Data processing 3 source.
943 enum DataProcessing3SourceOp
{
944 DataProcessing3SourceFixed
= 0x1B000000,
945 DataProcessing3SourceFMask
= 0x1F000000,
946 DataProcessing3SourceMask
= 0xFFE08000,
947 MADD_w
= DataProcessing3SourceFixed
| 0x00000000,
948 MADD_x
= DataProcessing3SourceFixed
| 0x80000000,
950 MSUB_w
= DataProcessing3SourceFixed
| 0x00008000,
951 MSUB_x
= DataProcessing3SourceFixed
| 0x80008000,
953 SMADDL_x
= DataProcessing3SourceFixed
| 0x80200000,
954 SMSUBL_x
= DataProcessing3SourceFixed
| 0x80208000,
955 SMULH_x
= DataProcessing3SourceFixed
| 0x80400000,
956 UMADDL_x
= DataProcessing3SourceFixed
| 0x80A00000,
957 UMSUBL_x
= DataProcessing3SourceFixed
| 0x80A08000,
958 UMULH_x
= DataProcessing3SourceFixed
| 0x80C00000
961 // Floating point compare.
963 FPCompareFixed
= 0x1E202000,
964 FPCompareFMask
= 0x5F203C00,
965 FPCompareMask
= 0xFFE0FC1F,
966 FCMP_s
= FPCompareFixed
| 0x00000000,
967 FCMP_d
= FPCompareFixed
| FP64
| 0x00000000,
969 FCMP_s_zero
= FPCompareFixed
| 0x00000008,
970 FCMP_d_zero
= FPCompareFixed
| FP64
| 0x00000008,
971 FCMP_zero
= FCMP_s_zero
,
972 FCMPE_s
= FPCompareFixed
| 0x00000010,
973 FCMPE_d
= FPCompareFixed
| FP64
| 0x00000010,
974 FCMPE_s_zero
= FPCompareFixed
| 0x00000018,
975 FCMPE_d_zero
= FPCompareFixed
| FP64
| 0x00000018
978 // Floating point conditional compare.
979 enum FPConditionalCompareOp
{
980 FPConditionalCompareFixed
= 0x1E200400,
981 FPConditionalCompareFMask
= 0x5F200C00,
982 FPConditionalCompareMask
= 0xFFE00C10,
983 FCCMP_s
= FPConditionalCompareFixed
| 0x00000000,
984 FCCMP_d
= FPConditionalCompareFixed
| FP64
| 0x00000000,
986 FCCMPE_s
= FPConditionalCompareFixed
| 0x00000010,
987 FCCMPE_d
= FPConditionalCompareFixed
| FP64
| 0x00000010,
991 // Floating point conditional select.
992 enum FPConditionalSelectOp
{
993 FPConditionalSelectFixed
= 0x1E200C00,
994 FPConditionalSelectFMask
= 0x5F200C00,
995 FPConditionalSelectMask
= 0xFFE00C00,
996 FCSEL_s
= FPConditionalSelectFixed
| 0x00000000,
997 FCSEL_d
= FPConditionalSelectFixed
| FP64
| 0x00000000,
1001 // Floating point immediate.
1002 enum FPImmediateOp
{
1003 FPImmediateFixed
= 0x1E201000,
1004 FPImmediateFMask
= 0x5F201C00,
1005 FPImmediateMask
= 0xFFE01C00,
1006 FMOV_s_imm
= FPImmediateFixed
| 0x00000000,
1007 FMOV_d_imm
= FPImmediateFixed
| FP64
| 0x00000000
1010 // Floating point data processing 1 source.
1011 enum FPDataProcessing1SourceOp
{
1012 FPDataProcessing1SourceFixed
= 0x1E204000,
1013 FPDataProcessing1SourceFMask
= 0x5F207C00,
1014 FPDataProcessing1SourceMask
= 0xFFFFFC00,
1015 FMOV_s
= FPDataProcessing1SourceFixed
| 0x00000000,
1016 FMOV_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00000000,
1018 FABS_s
= FPDataProcessing1SourceFixed
| 0x00008000,
1019 FABS_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00008000,
1021 FNEG_s
= FPDataProcessing1SourceFixed
| 0x00010000,
1022 FNEG_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00010000,
1024 FSQRT_s
= FPDataProcessing1SourceFixed
| 0x00018000,
1025 FSQRT_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00018000,
1027 FCVT_ds
= FPDataProcessing1SourceFixed
| 0x00028000,
1028 FCVT_sd
= FPDataProcessing1SourceFixed
| FP64
| 0x00020000,
1029 FRINTN_s
= FPDataProcessing1SourceFixed
| 0x00040000,
1030 FRINTN_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00040000,
1032 FRINTP_s
= FPDataProcessing1SourceFixed
| 0x00048000,
1033 FRINTP_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00048000,
1035 FRINTM_s
= FPDataProcessing1SourceFixed
| 0x00050000,
1036 FRINTM_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00050000,
1038 FRINTZ_s
= FPDataProcessing1SourceFixed
| 0x00058000,
1039 FRINTZ_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00058000,
1041 FRINTA_s
= FPDataProcessing1SourceFixed
| 0x00060000,
1042 FRINTA_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00060000,
1044 FRINTX_s
= FPDataProcessing1SourceFixed
| 0x00070000,
1045 FRINTX_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00070000,
1047 FRINTI_s
= FPDataProcessing1SourceFixed
| 0x00078000,
1048 FRINTI_d
= FPDataProcessing1SourceFixed
| FP64
| 0x00078000,
1052 // Floating point data processing 2 source.
1053 enum FPDataProcessing2SourceOp
{
1054 FPDataProcessing2SourceFixed
= 0x1E200800,
1055 FPDataProcessing2SourceFMask
= 0x5F200C00,
1056 FPDataProcessing2SourceMask
= 0xFFE0FC00,
1057 FMUL
= FPDataProcessing2SourceFixed
| 0x00000000,
1059 FMUL_d
= FMUL
| FP64
,
1060 FDIV
= FPDataProcessing2SourceFixed
| 0x00001000,
1062 FDIV_d
= FDIV
| FP64
,
1063 FADD
= FPDataProcessing2SourceFixed
| 0x00002000,
1065 FADD_d
= FADD
| FP64
,
1066 FSUB
= FPDataProcessing2SourceFixed
| 0x00003000,
1068 FSUB_d
= FSUB
| FP64
,
1069 FMAX
= FPDataProcessing2SourceFixed
| 0x00004000,
1071 FMAX_d
= FMAX
| FP64
,
1072 FMIN
= FPDataProcessing2SourceFixed
| 0x00005000,
1074 FMIN_d
= FMIN
| FP64
,
1075 FMAXNM
= FPDataProcessing2SourceFixed
| 0x00006000,
1077 FMAXNM_d
= FMAXNM
| FP64
,
1078 FMINNM
= FPDataProcessing2SourceFixed
| 0x00007000,
1080 FMINNM_d
= FMINNM
| FP64
,
1081 FNMUL
= FPDataProcessing2SourceFixed
| 0x00008000,
1083 FNMUL_d
= FNMUL
| FP64
1086 // Floating point data processing 3 source.
1087 enum FPDataProcessing3SourceOp
{
1088 FPDataProcessing3SourceFixed
= 0x1F000000,
1089 FPDataProcessing3SourceFMask
= 0x5F000000,
1090 FPDataProcessing3SourceMask
= 0xFFE08000,
1091 FMADD_s
= FPDataProcessing3SourceFixed
| 0x00000000,
1092 FMSUB_s
= FPDataProcessing3SourceFixed
| 0x00008000,
1093 FNMADD_s
= FPDataProcessing3SourceFixed
| 0x00200000,
1094 FNMSUB_s
= FPDataProcessing3SourceFixed
| 0x00208000,
1095 FMADD_d
= FPDataProcessing3SourceFixed
| 0x00400000,
1096 FMSUB_d
= FPDataProcessing3SourceFixed
| 0x00408000,
1097 FNMADD_d
= FPDataProcessing3SourceFixed
| 0x00600000,
1098 FNMSUB_d
= FPDataProcessing3SourceFixed
| 0x00608000
1101 // Conversion between floating point and integer.
1102 enum FPIntegerConvertOp
{
1103 FPIntegerConvertFixed
= 0x1E200000,
1104 FPIntegerConvertFMask
= 0x5F20FC00,
1105 FPIntegerConvertMask
= 0xFFFFFC00,
1106 FCVTNS
= FPIntegerConvertFixed
| 0x00000000,
1108 FCVTNS_xs
= FCVTNS
| SixtyFourBits
,
1109 FCVTNS_wd
= FCVTNS
| FP64
,
1110 FCVTNS_xd
= FCVTNS
| SixtyFourBits
| FP64
,
1111 FCVTNU
= FPIntegerConvertFixed
| 0x00010000,
1113 FCVTNU_xs
= FCVTNU
| SixtyFourBits
,
1114 FCVTNU_wd
= FCVTNU
| FP64
,
1115 FCVTNU_xd
= FCVTNU
| SixtyFourBits
| FP64
,
1116 FCVTPS
= FPIntegerConvertFixed
| 0x00080000,
1118 FCVTPS_xs
= FCVTPS
| SixtyFourBits
,
1119 FCVTPS_wd
= FCVTPS
| FP64
,
1120 FCVTPS_xd
= FCVTPS
| SixtyFourBits
| FP64
,
1121 FCVTPU
= FPIntegerConvertFixed
| 0x00090000,
1123 FCVTPU_xs
= FCVTPU
| SixtyFourBits
,
1124 FCVTPU_wd
= FCVTPU
| FP64
,
1125 FCVTPU_xd
= FCVTPU
| SixtyFourBits
| FP64
,
1126 FCVTMS
= FPIntegerConvertFixed
| 0x00100000,
1128 FCVTMS_xs
= FCVTMS
| SixtyFourBits
,
1129 FCVTMS_wd
= FCVTMS
| FP64
,
1130 FCVTMS_xd
= FCVTMS
| SixtyFourBits
| FP64
,
1131 FCVTMU
= FPIntegerConvertFixed
| 0x00110000,
1133 FCVTMU_xs
= FCVTMU
| SixtyFourBits
,
1134 FCVTMU_wd
= FCVTMU
| FP64
,
1135 FCVTMU_xd
= FCVTMU
| SixtyFourBits
| FP64
,
1136 FCVTZS
= FPIntegerConvertFixed
| 0x00180000,
1138 FCVTZS_xs
= FCVTZS
| SixtyFourBits
,
1139 FCVTZS_wd
= FCVTZS
| FP64
,
1140 FCVTZS_xd
= FCVTZS
| SixtyFourBits
| FP64
,
1141 FCVTZU
= FPIntegerConvertFixed
| 0x00190000,
1143 FCVTZU_xs
= FCVTZU
| SixtyFourBits
,
1144 FCVTZU_wd
= FCVTZU
| FP64
,
1145 FCVTZU_xd
= FCVTZU
| SixtyFourBits
| FP64
,
1146 SCVTF
= FPIntegerConvertFixed
| 0x00020000,
1148 SCVTF_sx
= SCVTF
| SixtyFourBits
,
1149 SCVTF_dw
= SCVTF
| FP64
,
1150 SCVTF_dx
= SCVTF
| SixtyFourBits
| FP64
,
1151 UCVTF
= FPIntegerConvertFixed
| 0x00030000,
1153 UCVTF_sx
= UCVTF
| SixtyFourBits
,
1154 UCVTF_dw
= UCVTF
| FP64
,
1155 UCVTF_dx
= UCVTF
| SixtyFourBits
| FP64
,
1156 FCVTAS
= FPIntegerConvertFixed
| 0x00040000,
1158 FCVTAS_xs
= FCVTAS
| SixtyFourBits
,
1159 FCVTAS_wd
= FCVTAS
| FP64
,
1160 FCVTAS_xd
= FCVTAS
| SixtyFourBits
| FP64
,
1161 FCVTAU
= FPIntegerConvertFixed
| 0x00050000,
1163 FCVTAU_xs
= FCVTAU
| SixtyFourBits
,
1164 FCVTAU_wd
= FCVTAU
| FP64
,
1165 FCVTAU_xd
= FCVTAU
| SixtyFourBits
| FP64
,
1166 FMOV_ws
= FPIntegerConvertFixed
| 0x00060000,
1167 FMOV_sw
= FPIntegerConvertFixed
| 0x00070000,
1168 FMOV_xd
= FMOV_ws
| SixtyFourBits
| FP64
,
1169 FMOV_dx
= FMOV_sw
| SixtyFourBits
| FP64
1172 // Conversion between fixed point and floating point.
1173 enum FPFixedPointConvertOp
{
1174 FPFixedPointConvertFixed
= 0x1E000000,
1175 FPFixedPointConvertFMask
= 0x5F200000,
1176 FPFixedPointConvertMask
= 0xFFFF0000,
1177 FCVTZS_fixed
= FPFixedPointConvertFixed
| 0x00180000,
1178 FCVTZS_ws_fixed
= FCVTZS_fixed
,
1179 FCVTZS_xs_fixed
= FCVTZS_fixed
| SixtyFourBits
,
1180 FCVTZS_wd_fixed
= FCVTZS_fixed
| FP64
,
1181 FCVTZS_xd_fixed
= FCVTZS_fixed
| SixtyFourBits
| FP64
,
1182 FCVTZU_fixed
= FPFixedPointConvertFixed
| 0x00190000,
1183 FCVTZU_ws_fixed
= FCVTZU_fixed
,
1184 FCVTZU_xs_fixed
= FCVTZU_fixed
| SixtyFourBits
,
1185 FCVTZU_wd_fixed
= FCVTZU_fixed
| FP64
,
1186 FCVTZU_xd_fixed
= FCVTZU_fixed
| SixtyFourBits
| FP64
,
1187 SCVTF_fixed
= FPFixedPointConvertFixed
| 0x00020000,
1188 SCVTF_sw_fixed
= SCVTF_fixed
,
1189 SCVTF_sx_fixed
= SCVTF_fixed
| SixtyFourBits
,
1190 SCVTF_dw_fixed
= SCVTF_fixed
| FP64
,
1191 SCVTF_dx_fixed
= SCVTF_fixed
| SixtyFourBits
| FP64
,
1192 UCVTF_fixed
= FPFixedPointConvertFixed
| 0x00030000,
1193 UCVTF_sw_fixed
= UCVTF_fixed
,
1194 UCVTF_sx_fixed
= UCVTF_fixed
| SixtyFourBits
,
1195 UCVTF_dw_fixed
= UCVTF_fixed
| FP64
,
1196 UCVTF_dx_fixed
= UCVTF_fixed
| SixtyFourBits
| FP64
1199 // Unimplemented and unallocated instructions. These are defined to make fixed
1200 // bit assertion easier.
1201 enum UnimplementedOp
{
1202 UnimplementedFixed
= 0x00000000,
1203 UnimplementedFMask
= 0x00000000
1206 enum UnallocatedOp
{
1207 UnallocatedFixed
= 0x00000000,
1208 UnallocatedFMask
= 0x00000000
1213 #endif // VIXL_A64_CONSTANTS_A64_H_