hw/i2c/imx_i2c.c

   1 /*
   2  *  i.MX I2C Bus Serial Interface Emulation
   3  *
   4  *  Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "hw/i2c/imx_i2c.h"
  22 #include "hw/i2c/i2c.h"
  23
  24 #ifndef DEBUG_IMX_I2C
  25 #define DEBUG_IMX_I2C 0
  26 #endif
  27
  28 #define DPRINTF(fmt, args...) \
  29     do { \
  30         if (DEBUG_IMX_I2C) { \
  31             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
  32                                              __func__, ##args); \
  33         } \
  34     } while (0)
  35
  36 static const char *imx_i2c_get_regname(unsigned offset)
  37 {
  38     switch (offset) {
  39     case IADR_ADDR:
  40         return "IADR";
  41     case IFDR_ADDR:
  42         return "IFDR";
  43     case I2CR_ADDR:
  44         return "I2CR";
  45     case I2SR_ADDR:
  46         return "I2SR";
  47     case I2DR_ADDR:
  48         return "I2DR";
  49     default:
  50         return "[?]";
  51     }
  52 }
  53
  54 static inline bool imx_i2c_is_enabled(IMXI2CState *s)
  55 {
  56     return s->i2cr & I2CR_IEN;
  57 }
  58
  59 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState *s)
  60 {
  61     return s->i2cr & I2CR_IIEN;
  62 }
  63
  64 static inline bool imx_i2c_is_master(IMXI2CState *s)
  65 {
  66     return s->i2cr & I2CR_MSTA;
  67 }
  68
  69 static void imx_i2c_reset(DeviceState *dev)
  70 {
  71     IMXI2CState *s = IMX_I2C(dev);
  72
  73     if (s->address != ADDR_RESET) {
  74         i2c_end_transfer(s->bus);
  75     }
  76
  77     s->address    = ADDR_RESET;
  78     s->iadr       = IADR_RESET;
  79     s->ifdr       = IFDR_RESET;
  80     s->i2cr       = I2CR_RESET;
  81     s->i2sr       = I2SR_RESET;
  82     s->i2dr_read  = I2DR_RESET;
  83     s->i2dr_write = I2DR_RESET;
  84 }
  85
  86 static inline void imx_i2c_raise_interrupt(IMXI2CState *s)
  87 {
  88     /*
  89      * raise an interrupt if the device is enabled and it is configured
  90      * to generate some interrupts.
  91      */
  92     if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) {
  93         s->i2sr |= I2SR_IIF;
  94         qemu_irq_raise(s->irq);
  95     }
  96 }
  97
  98 static uint64_t imx_i2c_read(void *opaque, hwaddr offset,
  99                              unsigned size)
 100 {
 101     uint16_t value;
 102     IMXI2CState *s = IMX_I2C(opaque);
 103
 104     switch (offset) {
 105     case IADR_ADDR:
 106         value = s->iadr;
 107         break;
 108     case IFDR_ADDR:
 109         value = s->ifdr;
 110         break;
 111     case I2CR_ADDR:
 112         value = s->i2cr;
 113         break;
 114     case I2SR_ADDR:
 115         value = s->i2sr;
 116         break;
 117     case I2DR_ADDR:
 118         value = s->i2dr_read;
 119
 120         if (imx_i2c_is_master(s)) {
 121             int ret = 0xff;
 122
 123             if (s->address == ADDR_RESET) {
 124                 /* something is wrong as the address is not set */
 125                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
 126                               "without specifying the slave address\n",
 127                               TYPE_IMX_I2C, __func__);
 128             } else if (s->i2cr & I2CR_MTX) {
 129                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
 130                               "but MTX is set\n", TYPE_IMX_I2C, __func__);
 131             } else {
 132                 /* get the next byte */
 133                 ret = i2c_recv(s->bus);
 134
 135                 if (ret >= 0) {
 136                     imx_i2c_raise_interrupt(s);
 137                 } else {
 138                     qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
 139                                   "for device 0x%02x\n", TYPE_IMX_I2C,
 140                                   __func__, s->address);
 141                     ret = 0xff;
 142                 }
 143             }
 144
 145             s->i2dr_read = ret;
 146         } else {
 147             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 148                           TYPE_IMX_I2C, __func__);
 149         }
 150         break;
 151     default:
 152         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 153                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
 154         value = 0;
 155         break;
 156     }
 157
 158     DPRINTF("read %s [0x%" HWADDR_PRIx "] -> 0x%02x\n",
 159             imx_i2c_get_regname(offset), offset, value);
 160
 161     return (uint64_t)value;
 162 }
 163
 164 static void imx_i2c_write(void *opaque, hwaddr offset,
 165                           uint64_t value, unsigned size)
 166 {
 167     IMXI2CState *s = IMX_I2C(opaque);
 168
 169     DPRINTF("write %s [0x%" HWADDR_PRIx "] <- 0x%02x\n",
 170             imx_i2c_get_regname(offset), offset, (int)value);
 171
 172     value &= 0xff;
 173
 174     switch (offset) {
 175     case IADR_ADDR:
 176         s->iadr = value & IADR_MASK;
 177         /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
 178         break;
 179     case IFDR_ADDR:
 180         s->ifdr = value & IFDR_MASK;
 181         break;
 182     case I2CR_ADDR:
 183         if (imx_i2c_is_enabled(s) && ((value & I2CR_IEN) == 0)) {
 184             /* This is a soft reset. IADR is preserved during soft resets */
 185             uint16_t iadr = s->iadr;
 186             imx_i2c_reset(DEVICE(s));
 187             s->iadr = iadr;
 188         } else { /* normal write */
 189             s->i2cr = value & I2CR_MASK;
 190
 191             if (imx_i2c_is_master(s)) {
 192                 /* set the bus to busy */
 193                 s->i2sr |= I2SR_IBB;
 194             } else { /* slave mode */
 195                 /* bus is not busy anymore */
 196                 s->i2sr &= ~I2SR_IBB;
 197
 198                 /*
 199                  * if we unset the master mode then it ends the ongoing
 200                  * transfer if any
 201                  */
 202                 if (s->address != ADDR_RESET) {
 203                     i2c_end_transfer(s->bus);
 204                     s->address = ADDR_RESET;
 205                 }
 206             }
 207
 208             if (s->i2cr & I2CR_RSTA) { /* Restart */
 209                 /* if this is a restart then it ends the ongoing transfer */
 210                 if (s->address != ADDR_RESET) {
 211                     i2c_end_transfer(s->bus);
 212                     s->address = ADDR_RESET;
 213                     s->i2cr &= ~I2CR_RSTA;
 214                 }
 215             }
 216         }
 217         break;
 218     case I2SR_ADDR:
 219         /*
 220          * if the user writes 0 to IIF then lower the interrupt and
 221          * reset the bit
 222          */
 223         if ((s->i2sr & I2SR_IIF) && !(value & I2SR_IIF)) {
 224             s->i2sr &= ~I2SR_IIF;
 225             qemu_irq_lower(s->irq);
 226         }
 227
 228         /*
 229          * if the user writes 0 to IAL, reset the bit
 230          */
 231         if ((s->i2sr & I2SR_IAL) && !(value & I2SR_IAL)) {
 232             s->i2sr &= ~I2SR_IAL;
 233         }
 234
 235         break;
 236     case I2DR_ADDR:
 237         /* if the device is not enabled, nothing to do */
 238         if (!imx_i2c_is_enabled(s)) {
 239             break;
 240         }
 241
 242         s->i2dr_write = value & I2DR_MASK;
 243
 244         if (imx_i2c_is_master(s)) {
 245             /* If this is the first write cycle then it is the slave addr */
 246             if (s->address == ADDR_RESET) {
 247                 if (i2c_start_transfer(s->bus, extract32(s->i2dr_write, 1, 7),
 248                                        extract32(s->i2dr_write, 0, 1))) {
 249                     /* if non zero is returned, the adress is not valid */
 250                     s->i2sr |= I2SR_RXAK;
 251                 } else {
 252                     s->address = s->i2dr_write;
 253                     s->i2sr &= ~I2SR_RXAK;
 254                     imx_i2c_raise_interrupt(s);
 255                 }
 256             } else { /* This is a normal data write */
 257                 if (i2c_send(s->bus, s->i2dr_write)) {
 258                     /* if the target return non zero then end the transfer */
 259                     s->i2sr |= I2SR_RXAK;
 260                     s->address = ADDR_RESET;
 261                     i2c_end_transfer(s->bus);
 262                 } else {
 263                     s->i2sr &= ~I2SR_RXAK;
 264                     imx_i2c_raise_interrupt(s);
 265                 }
 266             }
 267         } else {
 268             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 269                           TYPE_IMX_I2C, __func__);
 270         }
 271         break;
 272     default:
 273         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 274                       HWADDR_PRIx "\n", TYPE_IMX_I2C, __func__, offset);
 275         break;
 276     }
 277 }
 278
 279 static const MemoryRegionOps imx_i2c_ops = {
 280     .read = imx_i2c_read,
 281     .write = imx_i2c_write,
 282     .valid.min_access_size = 1,
 283     .valid.max_access_size = 2,
 284     .endianness = DEVICE_NATIVE_ENDIAN,
 285 };
 286
 287 static const VMStateDescription imx_i2c_vmstate = {
 288     .name = TYPE_IMX_I2C,
 289     .version_id = 1,
 290     .minimum_version_id = 1,
 291     .fields = (VMStateField[]) {
 292         VMSTATE_UINT16(address, IMXI2CState),
 293         VMSTATE_UINT16(iadr, IMXI2CState),
 294         VMSTATE_UINT16(ifdr, IMXI2CState),
 295         VMSTATE_UINT16(i2cr, IMXI2CState),
 296         VMSTATE_UINT16(i2sr, IMXI2CState),
 297         VMSTATE_UINT16(i2dr_read, IMXI2CState),
 298         VMSTATE_UINT16(i2dr_write, IMXI2CState),
 299         VMSTATE_END_OF_LIST()
 300     }
 301 };
 302
 303 static void imx_i2c_realize(DeviceState *dev, Error **errp)
 304 {
 305     IMXI2CState *s = IMX_I2C(dev);
 306
 307     memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
 308                           IMX_I2C_MEM_SIZE);
 309     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 310     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 311     s->bus = i2c_init_bus(DEVICE(dev), "i2c");
 312 }
 313
 314 static void imx_i2c_class_init(ObjectClass *klass, void *data)
 315 {
 316     DeviceClass *dc = DEVICE_CLASS(klass);
 317
 318     dc->vmsd = &imx_i2c_vmstate;
 319     dc->reset = imx_i2c_reset;
 320     dc->realize = imx_i2c_realize;
 321 }
 322
 323 static const TypeInfo imx_i2c_type_info = {
 324     .name = TYPE_IMX_I2C,
 325     .parent = TYPE_SYS_BUS_DEVICE,
 326     .instance_size = sizeof(IMXI2CState),
 327     .class_init = imx_i2c_class_init,
 328 };
 329
 330 static void imx_i2c_register_types(void)
 331 {
 332     type_register_static(&imx_i2c_type_info);
 333 }
 334
 335 type_init(imx_i2c_register_types)