ahci: QOM'ify some more
[qemu/ar7.git] / target-i386 / arch_dump.c
blob10dc2284bf10c778d966f9673ac5d47f22320a3a
1 /*
2 * i386 memory mapping
4 * Copyright Fujitsu, Corp. 2011, 2012
6 * Authors:
7 * Wen Congyang <wency@cn.fujitsu.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "cpu.h"
15 #include "exec/cpu-all.h"
16 #include "sysemu/dump.h"
17 #include "elf.h"
19 #ifdef TARGET_X86_64
20 typedef struct {
21 target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
22 target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
23 target_ulong rip, cs, eflags;
24 target_ulong rsp, ss;
25 target_ulong fs_base, gs_base;
26 target_ulong ds, es, fs, gs;
27 } x86_64_user_regs_struct;
29 typedef struct {
30 char pad1[32];
31 uint32_t pid;
32 char pad2[76];
33 x86_64_user_regs_struct regs;
34 char pad3[8];
35 } x86_64_elf_prstatus;
37 static int x86_64_write_elf64_note(WriteCoreDumpFunction f,
38 CPUX86State *env, int id,
39 void *opaque)
41 x86_64_user_regs_struct regs;
42 Elf64_Nhdr *note;
43 char *buf;
44 int descsz, note_size, name_size = 5;
45 const char *name = "CORE";
46 int ret;
48 regs.r15 = env->regs[15];
49 regs.r14 = env->regs[14];
50 regs.r13 = env->regs[13];
51 regs.r12 = env->regs[12];
52 regs.r11 = env->regs[11];
53 regs.r10 = env->regs[10];
54 regs.r9 = env->regs[9];
55 regs.r8 = env->regs[8];
56 regs.rbp = env->regs[R_EBP];
57 regs.rsp = env->regs[R_ESP];
58 regs.rdi = env->regs[R_EDI];
59 regs.rsi = env->regs[R_ESI];
60 regs.rdx = env->regs[R_EDX];
61 regs.rcx = env->regs[R_ECX];
62 regs.rbx = env->regs[R_EBX];
63 regs.rax = env->regs[R_EAX];
64 regs.rip = env->eip;
65 regs.eflags = env->eflags;
67 regs.orig_rax = 0; /* FIXME */
68 regs.cs = env->segs[R_CS].selector;
69 regs.ss = env->segs[R_SS].selector;
70 regs.fs_base = env->segs[R_FS].base;
71 regs.gs_base = env->segs[R_GS].base;
72 regs.ds = env->segs[R_DS].selector;
73 regs.es = env->segs[R_ES].selector;
74 regs.fs = env->segs[R_FS].selector;
75 regs.gs = env->segs[R_GS].selector;
77 descsz = sizeof(x86_64_elf_prstatus);
78 note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
79 (descsz + 3) / 4) * 4;
80 note = g_malloc(note_size);
82 memset(note, 0, note_size);
83 note->n_namesz = cpu_to_le32(name_size);
84 note->n_descsz = cpu_to_le32(descsz);
85 note->n_type = cpu_to_le32(NT_PRSTATUS);
86 buf = (char *)note;
87 buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
88 memcpy(buf, name, name_size);
89 buf += ((name_size + 3) / 4) * 4;
90 memcpy(buf + 32, &id, 4); /* pr_pid */
91 buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
92 memcpy(buf, &regs, sizeof(x86_64_user_regs_struct));
94 ret = f(note, note_size, opaque);
95 g_free(note);
96 if (ret < 0) {
97 return -1;
100 return 0;
102 #endif
104 typedef struct {
105 uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
106 unsigned short ds, __ds, es, __es;
107 unsigned short fs, __fs, gs, __gs;
108 uint32_t orig_eax, eip;
109 unsigned short cs, __cs;
110 uint32_t eflags, esp;
111 unsigned short ss, __ss;
112 } x86_user_regs_struct;
114 typedef struct {
115 char pad1[24];
116 uint32_t pid;
117 char pad2[44];
118 x86_user_regs_struct regs;
119 char pad3[4];
120 } x86_elf_prstatus;
122 static void x86_fill_elf_prstatus(x86_elf_prstatus *prstatus, CPUX86State *env,
123 int id)
125 memset(prstatus, 0, sizeof(x86_elf_prstatus));
126 prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
127 prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
128 prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
129 prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
130 prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
131 prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
132 prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
133 prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
134 prstatus->regs.eip = env->eip & 0xffffffff;
135 prstatus->regs.eflags = env->eflags & 0xffffffff;
137 prstatus->regs.cs = env->segs[R_CS].selector;
138 prstatus->regs.ss = env->segs[R_SS].selector;
139 prstatus->regs.ds = env->segs[R_DS].selector;
140 prstatus->regs.es = env->segs[R_ES].selector;
141 prstatus->regs.fs = env->segs[R_FS].selector;
142 prstatus->regs.gs = env->segs[R_GS].selector;
144 prstatus->pid = id;
147 static int x86_write_elf64_note(WriteCoreDumpFunction f, CPUX86State *env,
148 int id, void *opaque)
150 x86_elf_prstatus prstatus;
151 Elf64_Nhdr *note;
152 char *buf;
153 int descsz, note_size, name_size = 5;
154 const char *name = "CORE";
155 int ret;
157 x86_fill_elf_prstatus(&prstatus, env, id);
158 descsz = sizeof(x86_elf_prstatus);
159 note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
160 (descsz + 3) / 4) * 4;
161 note = g_malloc(note_size);
163 memset(note, 0, note_size);
164 note->n_namesz = cpu_to_le32(name_size);
165 note->n_descsz = cpu_to_le32(descsz);
166 note->n_type = cpu_to_le32(NT_PRSTATUS);
167 buf = (char *)note;
168 buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
169 memcpy(buf, name, name_size);
170 buf += ((name_size + 3) / 4) * 4;
171 memcpy(buf, &prstatus, sizeof(prstatus));
173 ret = f(note, note_size, opaque);
174 g_free(note);
175 if (ret < 0) {
176 return -1;
179 return 0;
182 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
183 int cpuid, void *opaque)
185 X86CPU *cpu = X86_CPU(cs);
186 int ret;
187 #ifdef TARGET_X86_64
188 X86CPU *first_x86_cpu = X86_CPU(first_cpu);
189 bool lma = !!(first_x86_cpu->env.hflags & HF_LMA_MASK);
191 if (lma) {
192 ret = x86_64_write_elf64_note(f, &cpu->env, cpuid, opaque);
193 } else {
194 #endif
195 ret = x86_write_elf64_note(f, &cpu->env, cpuid, opaque);
196 #ifdef TARGET_X86_64
198 #endif
200 return ret;
203 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
204 int cpuid, void *opaque)
206 X86CPU *cpu = X86_CPU(cs);
207 x86_elf_prstatus prstatus;
208 Elf32_Nhdr *note;
209 char *buf;
210 int descsz, note_size, name_size = 5;
211 const char *name = "CORE";
212 int ret;
214 x86_fill_elf_prstatus(&prstatus, &cpu->env, cpuid);
215 descsz = sizeof(x86_elf_prstatus);
216 note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
217 (descsz + 3) / 4) * 4;
218 note = g_malloc(note_size);
220 memset(note, 0, note_size);
221 note->n_namesz = cpu_to_le32(name_size);
222 note->n_descsz = cpu_to_le32(descsz);
223 note->n_type = cpu_to_le32(NT_PRSTATUS);
224 buf = (char *)note;
225 buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
226 memcpy(buf, name, name_size);
227 buf += ((name_size + 3) / 4) * 4;
228 memcpy(buf, &prstatus, sizeof(prstatus));
230 ret = f(note, note_size, opaque);
231 g_free(note);
232 if (ret < 0) {
233 return -1;
236 return 0;
240 * please count up QEMUCPUSTATE_VERSION if you have changed definition of
241 * QEMUCPUState, and modify the tools using this information accordingly.
243 #define QEMUCPUSTATE_VERSION (1)
245 struct QEMUCPUSegment {
246 uint32_t selector;
247 uint32_t limit;
248 uint32_t flags;
249 uint32_t pad;
250 uint64_t base;
253 typedef struct QEMUCPUSegment QEMUCPUSegment;
255 struct QEMUCPUState {
256 uint32_t version;
257 uint32_t size;
258 uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
259 uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
260 uint64_t rip, rflags;
261 QEMUCPUSegment cs, ds, es, fs, gs, ss;
262 QEMUCPUSegment ldt, tr, gdt, idt;
263 uint64_t cr[5];
266 typedef struct QEMUCPUState QEMUCPUState;
268 static void copy_segment(QEMUCPUSegment *d, SegmentCache *s)
270 d->pad = 0;
271 d->selector = s->selector;
272 d->limit = s->limit;
273 d->flags = s->flags;
274 d->base = s->base;
277 static void qemu_get_cpustate(QEMUCPUState *s, CPUX86State *env)
279 memset(s, 0, sizeof(QEMUCPUState));
281 s->version = QEMUCPUSTATE_VERSION;
282 s->size = sizeof(QEMUCPUState);
284 s->rax = env->regs[R_EAX];
285 s->rbx = env->regs[R_EBX];
286 s->rcx = env->regs[R_ECX];
287 s->rdx = env->regs[R_EDX];
288 s->rsi = env->regs[R_ESI];
289 s->rdi = env->regs[R_EDI];
290 s->rsp = env->regs[R_ESP];
291 s->rbp = env->regs[R_EBP];
292 #ifdef TARGET_X86_64
293 s->r8 = env->regs[8];
294 s->r9 = env->regs[9];
295 s->r10 = env->regs[10];
296 s->r11 = env->regs[11];
297 s->r12 = env->regs[12];
298 s->r13 = env->regs[13];
299 s->r14 = env->regs[14];
300 s->r15 = env->regs[15];
301 #endif
302 s->rip = env->eip;
303 s->rflags = env->eflags;
305 copy_segment(&s->cs, &env->segs[R_CS]);
306 copy_segment(&s->ds, &env->segs[R_DS]);
307 copy_segment(&s->es, &env->segs[R_ES]);
308 copy_segment(&s->fs, &env->segs[R_FS]);
309 copy_segment(&s->gs, &env->segs[R_GS]);
310 copy_segment(&s->ss, &env->segs[R_SS]);
311 copy_segment(&s->ldt, &env->ldt);
312 copy_segment(&s->tr, &env->tr);
313 copy_segment(&s->gdt, &env->gdt);
314 copy_segment(&s->idt, &env->idt);
316 s->cr[0] = env->cr[0];
317 s->cr[1] = env->cr[1];
318 s->cr[2] = env->cr[2];
319 s->cr[3] = env->cr[3];
320 s->cr[4] = env->cr[4];
323 static inline int cpu_write_qemu_note(WriteCoreDumpFunction f,
324 CPUX86State *env,
325 void *opaque,
326 int type)
328 QEMUCPUState state;
329 Elf64_Nhdr *note64;
330 Elf32_Nhdr *note32;
331 void *note;
332 char *buf;
333 int descsz, note_size, name_size = 5, note_head_size;
334 const char *name = "QEMU";
335 int ret;
337 qemu_get_cpustate(&state, env);
339 descsz = sizeof(state);
340 if (type == 0) {
341 note_head_size = sizeof(Elf32_Nhdr);
342 } else {
343 note_head_size = sizeof(Elf64_Nhdr);
345 note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
346 (descsz + 3) / 4) * 4;
347 note = g_malloc(note_size);
349 memset(note, 0, note_size);
350 if (type == 0) {
351 note32 = note;
352 note32->n_namesz = cpu_to_le32(name_size);
353 note32->n_descsz = cpu_to_le32(descsz);
354 note32->n_type = 0;
355 } else {
356 note64 = note;
357 note64->n_namesz = cpu_to_le32(name_size);
358 note64->n_descsz = cpu_to_le32(descsz);
359 note64->n_type = 0;
361 buf = note;
362 buf += ((note_head_size + 3) / 4) * 4;
363 memcpy(buf, name, name_size);
364 buf += ((name_size + 3) / 4) * 4;
365 memcpy(buf, &state, sizeof(state));
367 ret = f(note, note_size, opaque);
368 g_free(note);
369 if (ret < 0) {
370 return -1;
373 return 0;
376 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cs,
377 void *opaque)
379 X86CPU *cpu = X86_CPU(cs);
381 return cpu_write_qemu_note(f, &cpu->env, opaque, 1);
384 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs,
385 void *opaque)
387 X86CPU *cpu = X86_CPU(cs);
389 return cpu_write_qemu_note(f, &cpu->env, opaque, 0);
392 int cpu_get_dump_info(ArchDumpInfo *info)
394 bool lma = false;
395 RAMBlock *block;
397 #ifdef TARGET_X86_64
398 X86CPU *first_x86_cpu = X86_CPU(first_cpu);
400 lma = !!(first_x86_cpu->env.hflags & HF_LMA_MASK);
401 #endif
403 if (lma) {
404 info->d_machine = EM_X86_64;
405 } else {
406 info->d_machine = EM_386;
408 info->d_endian = ELFDATA2LSB;
410 if (lma) {
411 info->d_class = ELFCLASS64;
412 } else {
413 info->d_class = ELFCLASS32;
415 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
416 if (block->offset + block->length > UINT_MAX) {
417 /* The memory size is greater than 4G */
418 info->d_class = ELFCLASS64;
419 break;
424 return 0;
427 ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
429 int name_size = 5; /* "CORE" or "QEMU" */
430 size_t elf_note_size = 0;
431 size_t qemu_note_size = 0;
432 int elf_desc_size = 0;
433 int qemu_desc_size = 0;
434 int note_head_size;
436 if (class == ELFCLASS32) {
437 note_head_size = sizeof(Elf32_Nhdr);
438 } else {
439 note_head_size = sizeof(Elf64_Nhdr);
442 if (machine == EM_386) {
443 elf_desc_size = sizeof(x86_elf_prstatus);
445 #ifdef TARGET_X86_64
446 else {
447 elf_desc_size = sizeof(x86_64_elf_prstatus);
449 #endif
450 qemu_desc_size = sizeof(QEMUCPUState);
452 elf_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
453 (elf_desc_size + 3) / 4) * 4;
454 qemu_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
455 (qemu_desc_size + 3) / 4) * 4;
457 return (elf_note_size + qemu_note_size) * nr_cpus;