2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #define TARGET_LONG_BITS 32
34 /* Xtensa processors have a weak memory model */
35 #define TCG_GUEST_DEFAULT_MO (0)
37 #define CPUArchState struct CPUXtensaState
39 #include "qemu-common.h"
41 #include "exec/cpu-defs.h"
42 #include "xtensa-isa.h"
44 #define NB_MMU_MODES 4
46 #define TARGET_PHYS_ADDR_SPACE_BITS 32
47 #ifdef CONFIG_USER_ONLY
48 #define TARGET_VIRT_ADDR_SPACE_BITS 30
50 #define TARGET_VIRT_ADDR_SPACE_BITS 32
52 #define TARGET_PAGE_BITS 12
55 /* Additional instructions */
56 XTENSA_OPTION_CODE_DENSITY
,
58 XTENSA_OPTION_EXTENDED_L32R
,
59 XTENSA_OPTION_16_BIT_IMUL
,
60 XTENSA_OPTION_32_BIT_IMUL
,
61 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
62 XTENSA_OPTION_32_BIT_IDIV
,
64 XTENSA_OPTION_MISC_OP_NSA
,
65 XTENSA_OPTION_MISC_OP_MINMAX
,
66 XTENSA_OPTION_MISC_OP_SEXT
,
67 XTENSA_OPTION_MISC_OP_CLAMPS
,
68 XTENSA_OPTION_COPROCESSOR
,
69 XTENSA_OPTION_BOOLEAN
,
70 XTENSA_OPTION_FP_COPROCESSOR
,
71 XTENSA_OPTION_MP_SYNCHRO
,
72 XTENSA_OPTION_CONDITIONAL_STORE
,
73 XTENSA_OPTION_ATOMCTL
,
74 XTENSA_OPTION_DEPBITS
,
76 /* Interrupts and exceptions */
77 XTENSA_OPTION_EXCEPTION
,
78 XTENSA_OPTION_RELOCATABLE_VECTOR
,
79 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
80 XTENSA_OPTION_INTERRUPT
,
81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
82 XTENSA_OPTION_TIMER_INTERRUPT
,
86 XTENSA_OPTION_ICACHE_TEST
,
87 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
89 XTENSA_OPTION_DCACHE_TEST
,
90 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
96 XTENSA_OPTION_HW_ALIGNMENT
,
97 XTENSA_OPTION_MEMORY_ECC_PARITY
,
99 /* Memory protection and translation */
100 XTENSA_OPTION_REGION_PROTECTION
,
101 XTENSA_OPTION_REGION_TRANSLATION
,
104 XTENSA_OPTION_CACHEATTR
,
107 XTENSA_OPTION_WINDOWED_REGISTER
,
108 XTENSA_OPTION_PROCESSOR_INTERFACE
,
109 XTENSA_OPTION_MISC_SR
,
110 XTENSA_OPTION_THREAD_POINTER
,
111 XTENSA_OPTION_PROCESSOR_ID
,
113 XTENSA_OPTION_TRACE_PORT
,
114 XTENSA_OPTION_EXTERN_REGS
,
184 #define PS_INTLEVEL 0xf
185 #define PS_INTLEVEL_SHIFT 0
191 #define PS_RING_SHIFT 6
194 #define PS_OWB_SHIFT 8
197 #define PS_CALLINC 0x30000
198 #define PS_CALLINC_SHIFT 16
199 #define PS_CALLINC_LEN 2
201 #define PS_WOE 0x40000
203 #define DEBUGCAUSE_IC 0x1
204 #define DEBUGCAUSE_IB 0x2
205 #define DEBUGCAUSE_DB 0x4
206 #define DEBUGCAUSE_BI 0x8
207 #define DEBUGCAUSE_BN 0x10
208 #define DEBUGCAUSE_DI 0x20
209 #define DEBUGCAUSE_DBNUM 0xf00
210 #define DEBUGCAUSE_DBNUM_SHIFT 8
212 #define DBREAKC_SB 0x80000000
213 #define DBREAKC_LB 0x40000000
214 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
215 #define DBREAKC_MASK 0x3f
217 #define MEMCTL_INIT 0x00800000
218 #define MEMCTL_IUSEWAYS_SHIFT 18
219 #define MEMCTL_IUSEWAYS_LEN 5
220 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
221 #define MEMCTL_DALLOCWAYS_SHIFT 13
222 #define MEMCTL_DALLOCWAYS_LEN 5
223 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
224 #define MEMCTL_DUSEWAYS_SHIFT 8
225 #define MEMCTL_DUSEWAYS_LEN 5
226 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
227 #define MEMCTL_ISNP 0x4
228 #define MEMCTL_DSNP 0x2
229 #define MEMCTL_IL0EN 0x1
231 #define MAX_INSN_LENGTH 64
232 #define MAX_INSN_SLOTS 32
233 #define MAX_OPCODE_ARGS 16
235 #define MAX_NINTERRUPT 32
238 #define MAX_NCCOMPARE 3
239 #define MAX_TLB_WAY_SIZE 8
240 #define MAX_NDBREAK 2
241 #define MAX_NMEMORY 4
242 #define MAX_MPU_FOREGROUND_SEGMENTS 32
244 #define REGION_PAGE_MASK 0xe0000000
246 #define PAGE_CACHE_MASK 0x700
247 #define PAGE_CACHE_SHIFT 8
248 #define PAGE_CACHE_INVALID 0x000
249 #define PAGE_CACHE_BYPASS 0x100
250 #define PAGE_CACHE_WT 0x200
251 #define PAGE_CACHE_WB 0x400
252 #define PAGE_CACHE_ISOLATE 0x600
260 /* Dynamic vectors */
261 EXC_WINDOW_OVERFLOW4
,
262 EXC_WINDOW_UNDERFLOW4
,
263 EXC_WINDOW_OVERFLOW8
,
264 EXC_WINDOW_UNDERFLOW8
,
265 EXC_WINDOW_OVERFLOW12
,
266 EXC_WINDOW_UNDERFLOW12
,
276 ILLEGAL_INSTRUCTION_CAUSE
= 0,
278 INSTRUCTION_FETCH_ERROR_CAUSE
,
279 LOAD_STORE_ERROR_CAUSE
,
280 LEVEL1_INTERRUPT_CAUSE
,
282 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
283 PC_VALUE_ERROR_CAUSE
,
285 LOAD_STORE_ALIGNMENT_CAUSE
,
286 EXTERNAL_REG_PRIVILEGE_CAUSE
,
287 EXCLUSIVE_ERROR_CAUSE
,
288 INSTR_PIF_DATA_ERROR_CAUSE
,
289 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
290 INSTR_PIF_ADDR_ERROR_CAUSE
,
291 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
293 INST_TLB_MULTI_HIT_CAUSE
,
294 INST_FETCH_PRIVILEGE_CAUSE
,
295 INST_FETCH_PROHIBITED_CAUSE
= 20,
296 LOAD_STORE_TLB_MISS_CAUSE
= 24,
297 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
298 LOAD_STORE_PRIVILEGE_CAUSE
,
299 LOAD_PROHIBITED_CAUSE
= 28,
300 STORE_PROHIBITED_CAUSE
,
302 COPROCESSOR0_DISABLED
= 32,
320 struct CPUXtensaState
;
322 typedef struct xtensa_tlb_entry
{
330 typedef struct xtensa_tlb
{
332 const unsigned way_size
[10];
334 unsigned nrefillentries
;
337 typedef struct xtensa_mpu_entry
{
342 typedef struct XtensaGdbReg
{
350 typedef struct XtensaGdbRegmap
{
353 /* PC + a + ar + sr + ur */
354 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
357 typedef struct XtensaCcompareTimer
{
358 struct CPUXtensaState
*env
;
360 } XtensaCcompareTimer
;
362 typedef struct XtensaMemory
{
364 struct XtensaMemoryRegion
{
367 } location
[MAX_NMEMORY
];
370 typedef struct opcode_arg
{
377 typedef struct DisasContext DisasContext
;
378 typedef void (*XtensaOpcodeOp
)(DisasContext
*dc
, const OpcodeArg arg
[],
379 const uint32_t par
[]);
380 typedef bool (*XtensaOpcodeBoolTest
)(DisasContext
*dc
,
381 const OpcodeArg arg
[],
382 const uint32_t par
[]);
383 typedef uint32_t (*XtensaOpcodeUintTest
)(DisasContext
*dc
,
384 const OpcodeArg arg
[],
385 const uint32_t par
[]);
389 XTENSA_OP_PRIVILEGED
= 0x2,
390 XTENSA_OP_SYSCALL
= 0x4,
391 XTENSA_OP_DEBUG_BREAK
= 0x8,
393 XTENSA_OP_OVERFLOW
= 0x10,
394 XTENSA_OP_UNDERFLOW
= 0x20,
395 XTENSA_OP_ALLOCA
= 0x40,
396 XTENSA_OP_COPROCESSOR
= 0x80,
398 XTENSA_OP_DIVIDE_BY_ZERO
= 0x100,
400 /* Postprocessing flags */
401 XTENSA_OP_CHECK_INTERRUPTS
= 0x200,
402 XTENSA_OP_EXIT_TB_M1
= 0x400,
403 XTENSA_OP_EXIT_TB_0
= 0x800,
404 XTENSA_OP_SYNC_REGISTER_WINDOW
= 0x1000,
406 XTENSA_OP_POSTPROCESS
=
407 XTENSA_OP_CHECK_INTERRUPTS
|
408 XTENSA_OP_EXIT_TB_M1
|
409 XTENSA_OP_EXIT_TB_0
|
410 XTENSA_OP_SYNC_REGISTER_WINDOW
,
412 XTENSA_OP_NAME_ARRAY
= 0x8000,
414 XTENSA_OP_CONTROL_FLOW
= 0x10000,
415 XTENSA_OP_STORE
= 0x20000,
416 XTENSA_OP_LOAD
= 0x40000,
417 XTENSA_OP_LOAD_STORE
=
418 XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
421 typedef struct XtensaOpcodeOps
{
423 XtensaOpcodeOp translate
;
424 XtensaOpcodeBoolTest test_ill
;
425 XtensaOpcodeUintTest test_overflow
;
428 uint32_t coprocessor
;
431 typedef struct XtensaOpcodeTranslators
{
432 unsigned num_opcodes
;
433 const XtensaOpcodeOps
*opcode
;
434 } XtensaOpcodeTranslators
;
436 extern const XtensaOpcodeTranslators xtensa_core_opcodes
;
437 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
;
439 struct XtensaConfig
{
442 XtensaGdbRegmap gdb_regmap
;
446 unsigned inst_fetch_width
;
447 unsigned max_insn_size
;
449 uint32_t exception_vector
[EXC_MAX
];
452 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
453 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
454 uint32_t inttype_mask
[INTTYPE_MAX
];
457 interrupt_type inttype
;
458 } interrupt
[MAX_NINTERRUPT
];
460 uint32_t timerint
[MAX_NCCOMPARE
];
462 unsigned extint
[MAX_NINTERRUPT
];
464 unsigned debug_level
;
468 unsigned icache_ways
;
469 unsigned dcache_ways
;
470 unsigned dcache_line_bytes
;
471 uint32_t memctl_mask
;
473 XtensaMemory instrom
;
474 XtensaMemory instram
;
475 XtensaMemory datarom
;
476 XtensaMemory dataram
;
480 uint32_t configid
[2];
484 XtensaOpcodeOps
**opcode_ops
;
485 const XtensaOpcodeTranslators
**opcode_translators
;
486 xtensa_regfile a_regfile
;
489 uint32_t clock_freq_khz
;
495 unsigned n_mpu_fg_segments
;
496 unsigned n_mpu_bg_segments
;
497 const xtensa_mpu_entry
*mpu_bg
;
500 typedef struct XtensaConfigList
{
501 const XtensaConfig
*config
;
502 struct XtensaConfigList
*next
;
505 #ifdef HOST_WORDS_BIGENDIAN
517 typedef struct CPUXtensaState
{
518 const XtensaConfig
*config
;
523 uint32_t phys_regs
[MAX_NAREG
];
528 float_status fp_status
;
529 uint32_t windowbase_next
;
530 uint32_t exclusive_addr
;
531 uint32_t exclusive_val
;
533 #ifndef CONFIG_USER_ONLY
534 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
535 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
536 xtensa_mpu_entry mpu_fg
[MAX_MPU_FOREGROUND_SEGMENTS
];
537 unsigned autorefill_idx
;
539 AddressSpace
*address_space_er
;
540 MemoryRegion
*system_er
;
541 int pending_irq_level
; /* level of last raised IRQ */
542 qemu_irq
*irq_inputs
;
543 qemu_irq ext_irq_inputs
[MAX_NINTERRUPT
];
544 qemu_irq runstall_irq
;
545 XtensaCcompareTimer ccompare
[MAX_NCCOMPARE
];
547 uint64_t ccount_time
;
548 uint32_t ccount_base
;
553 unsigned static_vectors
;
555 /* Watchpoints for DBREAK registers */
556 struct CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
563 * @env: #CPUXtensaState
575 static inline XtensaCPU
*xtensa_env_get_cpu(const CPUXtensaState
*env
)
577 return container_of(env
, XtensaCPU
, env
);
580 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
582 #define ENV_OFFSET offsetof(XtensaCPU, env)
585 int xtensa_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
, int size
,
587 void xtensa_cpu_do_interrupt(CPUState
*cpu
);
588 bool xtensa_cpu_exec_interrupt(CPUState
*cpu
, int interrupt_request
);
589 void xtensa_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
590 unsigned size
, MMUAccessType access_type
,
591 int mmu_idx
, MemTxAttrs attrs
,
592 MemTxResult response
, uintptr_t retaddr
);
593 void xtensa_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
594 hwaddr
xtensa_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
595 void xtensa_count_regs(const XtensaConfig
*config
,
596 unsigned *n_regs
, unsigned *n_core_regs
);
597 int xtensa_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
598 int xtensa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
599 void xtensa_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
600 MMUAccessType access_type
,
601 int mmu_idx
, uintptr_t retaddr
);
603 #define cpu_signal_handler cpu_xtensa_signal_handler
604 #define cpu_list xtensa_cpu_list
606 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
607 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
608 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
610 #ifdef TARGET_WORDS_BIGENDIAN
611 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
612 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
614 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
615 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
617 #define XTENSA_DEFAULT_CPU_TYPE \
618 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
619 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
620 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
622 void xtensa_collect_sr_names(const XtensaConfig
*config
);
623 void xtensa_translate_init(void);
624 void **xtensa_get_regfile_by_name(const char *name
);
625 void xtensa_breakpoint_handler(CPUState
*cs
);
626 void xtensa_register_core(XtensaConfigList
*node
);
627 void xtensa_sim_open_console(Chardev
*chr
);
628 void check_interrupts(CPUXtensaState
*s
);
629 void xtensa_irq_init(CPUXtensaState
*env
);
630 qemu_irq
*xtensa_get_extints(CPUXtensaState
*env
);
631 qemu_irq
xtensa_get_runstall(CPUXtensaState
*env
);
632 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
633 void xtensa_cpu_list(void);
634 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
635 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
636 void xtensa_rotate_window(CPUXtensaState
*env
, uint32_t delta
);
637 void xtensa_restore_owb(CPUXtensaState
*env
);
638 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
640 static inline void xtensa_select_static_vectors(CPUXtensaState
*env
,
644 env
->static_vectors
= n
;
646 void xtensa_runstall(CPUXtensaState
*env
, bool runstall
);
648 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
649 #define XTENSA_OPTION_ALL (~(uint64_t)0)
651 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
654 return (config
->options
& opt
) != 0;
657 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
659 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
662 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
664 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
665 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
666 level
= env
->config
->excm_level
;
671 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
673 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
674 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
680 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
682 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
683 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
684 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
690 #ifndef CONFIG_USER_ONLY
691 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
692 uint32_t vaddr
, int is_write
, int mmu_idx
,
693 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
694 void reset_mmu(CPUXtensaState
*env
);
695 void dump_mmu(CPUXtensaState
*env
);
697 static inline MemoryRegion
*xtensa_get_er_region(CPUXtensaState
*env
)
699 return env
->system_er
;
703 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState
*env
)
705 return env
->sregs
[WINDOW_START
] |
706 (env
->sregs
[WINDOW_START
] << env
->config
->nareg
/ 4);
709 /* MMU modes definitions */
710 #define MMU_MODE0_SUFFIX _ring0
711 #define MMU_MODE1_SUFFIX _ring1
712 #define MMU_MODE2_SUFFIX _ring2
713 #define MMU_MODE3_SUFFIX _ring3
714 #define MMU_USER_IDX 3
716 static inline int cpu_mmu_index(CPUXtensaState
*env
, bool ifetch
)
718 return xtensa_get_cring(env
);
721 #define XTENSA_TBFLAG_RING_MASK 0x3
722 #define XTENSA_TBFLAG_EXCM 0x4
723 #define XTENSA_TBFLAG_LITBASE 0x8
724 #define XTENSA_TBFLAG_DEBUG 0x10
725 #define XTENSA_TBFLAG_ICOUNT 0x20
726 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
727 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
728 #define XTENSA_TBFLAG_EXCEPTION 0x4000
729 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
730 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
731 #define XTENSA_TBFLAG_YIELD 0x20000
732 #define XTENSA_TBFLAG_CWOE 0x40000
733 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
734 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
736 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
737 #define XTENSA_CSBASE_LEND_SHIFT 0
738 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
739 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
741 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, target_ulong
*pc
,
742 target_ulong
*cs_base
, uint32_t *flags
)
744 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
749 *flags
|= xtensa_get_ring(env
);
750 if (env
->sregs
[PS
] & PS_EXCM
) {
751 *flags
|= XTENSA_TBFLAG_EXCM
;
752 } else if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_LOOP
)) {
753 target_ulong lend_dist
=
754 env
->sregs
[LEND
] - (env
->pc
& -(1u << TARGET_PAGE_BITS
));
757 * 0 in the csbase_lend field means that there may not be a loopback
758 * for any instruction that starts inside this page. Any other value
759 * means that an instruction that ends at this offset from the page
760 * start may loop back and will need loopback code to be generated.
762 * lend_dist is 0 when LEND points to the start of the page, but
763 * no instruction that starts inside this page may end at offset 0,
764 * so it's still correct.
766 * When an instruction ends at a page boundary it may only start in
767 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
768 * for the TB that contains this instruction.
770 if (lend_dist
< (1u << TARGET_PAGE_BITS
) + env
->config
->max_insn_size
) {
771 target_ulong lbeg_off
= env
->sregs
[LEND
] - env
->sregs
[LBEG
];
773 *cs_base
= lend_dist
;
774 if (lbeg_off
< 256) {
775 *cs_base
|= lbeg_off
<< XTENSA_CSBASE_LBEG_OFF_SHIFT
;
779 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
780 (env
->sregs
[LITBASE
] & 1)) {
781 *flags
|= XTENSA_TBFLAG_LITBASE
;
783 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
784 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
785 *flags
|= XTENSA_TBFLAG_DEBUG
;
787 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
788 *flags
|= XTENSA_TBFLAG_ICOUNT
;
791 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
792 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
794 if (cs
->singlestep_enabled
&& env
->exception_taken
) {
795 *flags
|= XTENSA_TBFLAG_EXCEPTION
;
797 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
798 (env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) == PS_WOE
) {
799 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
800 (env
->sregs
[WINDOW_BASE
] + 1);
801 uint32_t w
= ctz32(windowstart
| 0x8);
803 *flags
|= (w
<< XTENSA_TBFLAG_WINDOW_SHIFT
) | XTENSA_TBFLAG_CWOE
;
804 *flags
|= extract32(env
->sregs
[PS
], PS_CALLINC_SHIFT
,
805 PS_CALLINC_LEN
) << XTENSA_TBFLAG_CALLINC_SHIFT
;
807 *flags
|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT
;
809 if (env
->yield_needed
) {
810 *flags
|= XTENSA_TBFLAG_YIELD
;
814 #include "exec/cpu-all.h"