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target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
[qemu/ar7.git] / target-mips / translate.c
blobcd0cf8b655fd2aa5949967b7b4802fbeea3e78cb
1 /*
2 * MIPS32 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "cpu.h"
25 #include "disas/disas.h"
26 #include "tcg-op.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31 #include "sysemu/kvm.h"
32 #include "exec/semihost.h"
33
34 #include "trace-tcg.h"
35
36 #define MIPS_DEBUG_DISAS 0
37
38 /* MIPS major opcodes */
39 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
40
41 enum {
42 /* indirect opcode tables */
43 OPC_SPECIAL = (0x00 << 26),
44 OPC_REGIMM = (0x01 << 26),
45 OPC_CP0 = (0x10 << 26),
46 OPC_CP1 = (0x11 << 26),
47 OPC_CP2 = (0x12 << 26),
48 OPC_CP3 = (0x13 << 26),
49 OPC_SPECIAL2 = (0x1C << 26),
50 OPC_SPECIAL3 = (0x1F << 26),
51 /* arithmetic with immediate */
52 OPC_ADDI = (0x08 << 26),
53 OPC_ADDIU = (0x09 << 26),
54 OPC_SLTI = (0x0A << 26),
55 OPC_SLTIU = (0x0B << 26),
56 /* logic with immediate */
57 OPC_ANDI = (0x0C << 26),
58 OPC_ORI = (0x0D << 26),
59 OPC_XORI = (0x0E << 26),
60 OPC_LUI = (0x0F << 26),
61 /* arithmetic with immediate */
62 OPC_DADDI = (0x18 << 26),
63 OPC_DADDIU = (0x19 << 26),
64 /* Jump and branches */
65 OPC_J = (0x02 << 26),
66 OPC_JAL = (0x03 << 26),
67 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL = (0x14 << 26),
69 OPC_BNE = (0x05 << 26),
70 OPC_BNEL = (0x15 << 26),
71 OPC_BLEZ = (0x06 << 26),
72 OPC_BLEZL = (0x16 << 26),
73 OPC_BGTZ = (0x07 << 26),
74 OPC_BGTZL = (0x17 << 26),
75 OPC_JALX = (0x1D << 26),
76 OPC_DAUI = (0x1D << 26),
77 /* Load and stores */
78 OPC_LDL = (0x1A << 26),
79 OPC_LDR = (0x1B << 26),
80 OPC_LB = (0x20 << 26),
81 OPC_LH = (0x21 << 26),
82 OPC_LWL = (0x22 << 26),
83 OPC_LW = (0x23 << 26),
84 OPC_LWPC = OPC_LW | 0x5,
85 OPC_LBU = (0x24 << 26),
86 OPC_LHU = (0x25 << 26),
87 OPC_LWR = (0x26 << 26),
88 OPC_LWU = (0x27 << 26),
89 OPC_SB = (0x28 << 26),
90 OPC_SH = (0x29 << 26),
91 OPC_SWL = (0x2A << 26),
92 OPC_SW = (0x2B << 26),
93 OPC_SDL = (0x2C << 26),
94 OPC_SDR = (0x2D << 26),
95 OPC_SWR = (0x2E << 26),
96 OPC_LL = (0x30 << 26),
97 OPC_LLD = (0x34 << 26),
98 OPC_LD = (0x37 << 26),
99 OPC_LDPC = OPC_LD | 0x5,
100 OPC_SC = (0x38 << 26),
101 OPC_SCD = (0x3C << 26),
102 OPC_SD = (0x3F << 26),
103 /* Floating point load/store */
104 OPC_LWC1 = (0x31 << 26),
105 OPC_LWC2 = (0x32 << 26),
106 OPC_LDC1 = (0x35 << 26),
107 OPC_LDC2 = (0x36 << 26),
108 OPC_SWC1 = (0x39 << 26),
109 OPC_SWC2 = (0x3A << 26),
110 OPC_SDC1 = (0x3D << 26),
111 OPC_SDC2 = (0x3E << 26),
112 /* Compact Branches */
113 OPC_BLEZALC = (0x06 << 26),
114 OPC_BGEZALC = (0x06 << 26),
115 OPC_BGEUC = (0x06 << 26),
116 OPC_BGTZALC = (0x07 << 26),
117 OPC_BLTZALC = (0x07 << 26),
118 OPC_BLTUC = (0x07 << 26),
119 OPC_BOVC = (0x08 << 26),
120 OPC_BEQZALC = (0x08 << 26),
121 OPC_BEQC = (0x08 << 26),
122 OPC_BLEZC = (0x16 << 26),
123 OPC_BGEZC = (0x16 << 26),
124 OPC_BGEC = (0x16 << 26),
125 OPC_BGTZC = (0x17 << 26),
126 OPC_BLTZC = (0x17 << 26),
127 OPC_BLTC = (0x17 << 26),
128 OPC_BNVC = (0x18 << 26),
129 OPC_BNEZALC = (0x18 << 26),
130 OPC_BNEC = (0x18 << 26),
131 OPC_BC = (0x32 << 26),
132 OPC_BEQZC = (0x36 << 26),
133 OPC_JIC = (0x36 << 26),
134 OPC_BALC = (0x3A << 26),
135 OPC_BNEZC = (0x3E << 26),
136 OPC_JIALC = (0x3E << 26),
137 /* MDMX ASE specific */
138 OPC_MDMX = (0x1E << 26),
139 /* MSA ASE, same as MDMX */
140 OPC_MSA = OPC_MDMX,
141 /* Cache and prefetch */
142 OPC_CACHE = (0x2F << 26),
143 OPC_PREF = (0x33 << 26),
144 /* PC-relative address computation / loads */
145 OPC_PCREL = (0x3B << 26),
146 };
147
148 /* PC-relative address computation / loads */
149 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
150 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
151 enum {
152 /* Instructions determined by bits 19 and 20 */
153 OPC_ADDIUPC = OPC_PCREL | (0 << 19),
154 R6_OPC_LWPC = OPC_PCREL | (1 << 19),
155 OPC_LWUPC = OPC_PCREL | (2 << 19),
156
157 /* Instructions determined by bits 16 ... 20 */
158 OPC_AUIPC = OPC_PCREL | (0x1e << 16),
159 OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
160
161 /* Other */
162 R6_OPC_LDPC = OPC_PCREL | (6 << 18),
163 };
164
165 /* MIPS special opcodes */
166 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
167
168 enum {
169 /* Shifts */
170 OPC_SLL = 0x00 | OPC_SPECIAL,
171 /* NOP is SLL r0, r0, 0 */
172 /* SSNOP is SLL r0, r0, 1 */
173 /* EHB is SLL r0, r0, 3 */
174 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
175 OPC_ROTR = OPC_SRL | (1 << 21),
176 OPC_SRA = 0x03 | OPC_SPECIAL,
177 OPC_SLLV = 0x04 | OPC_SPECIAL,
178 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
179 OPC_ROTRV = OPC_SRLV | (1 << 6),
180 OPC_SRAV = 0x07 | OPC_SPECIAL,
181 OPC_DSLLV = 0x14 | OPC_SPECIAL,
182 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
183 OPC_DROTRV = OPC_DSRLV | (1 << 6),
184 OPC_DSRAV = 0x17 | OPC_SPECIAL,
185 OPC_DSLL = 0x38 | OPC_SPECIAL,
186 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
187 OPC_DROTR = OPC_DSRL | (1 << 21),
188 OPC_DSRA = 0x3B | OPC_SPECIAL,
189 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
190 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
191 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
192 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
193 /* Multiplication / division */
194 OPC_MULT = 0x18 | OPC_SPECIAL,
195 OPC_MULTU = 0x19 | OPC_SPECIAL,
196 OPC_DIV = 0x1A | OPC_SPECIAL,
197 OPC_DIVU = 0x1B | OPC_SPECIAL,
198 OPC_DMULT = 0x1C | OPC_SPECIAL,
199 OPC_DMULTU = 0x1D | OPC_SPECIAL,
200 OPC_DDIV = 0x1E | OPC_SPECIAL,
201 OPC_DDIVU = 0x1F | OPC_SPECIAL,
202
203 /* 2 registers arithmetic / logic */
204 OPC_ADD = 0x20 | OPC_SPECIAL,
205 OPC_ADDU = 0x21 | OPC_SPECIAL,
206 OPC_SUB = 0x22 | OPC_SPECIAL,
207 OPC_SUBU = 0x23 | OPC_SPECIAL,
208 OPC_AND = 0x24 | OPC_SPECIAL,
209 OPC_OR = 0x25 | OPC_SPECIAL,
210 OPC_XOR = 0x26 | OPC_SPECIAL,
211 OPC_NOR = 0x27 | OPC_SPECIAL,
212 OPC_SLT = 0x2A | OPC_SPECIAL,
213 OPC_SLTU = 0x2B | OPC_SPECIAL,
214 OPC_DADD = 0x2C | OPC_SPECIAL,
215 OPC_DADDU = 0x2D | OPC_SPECIAL,
216 OPC_DSUB = 0x2E | OPC_SPECIAL,
217 OPC_DSUBU = 0x2F | OPC_SPECIAL,
218 /* Jumps */
219 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
220 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
221 /* Traps */
222 OPC_TGE = 0x30 | OPC_SPECIAL,
223 OPC_TGEU = 0x31 | OPC_SPECIAL,
224 OPC_TLT = 0x32 | OPC_SPECIAL,
225 OPC_TLTU = 0x33 | OPC_SPECIAL,
226 OPC_TEQ = 0x34 | OPC_SPECIAL,
227 OPC_TNE = 0x36 | OPC_SPECIAL,
228 /* HI / LO registers load & stores */
229 OPC_MFHI = 0x10 | OPC_SPECIAL,
230 OPC_MTHI = 0x11 | OPC_SPECIAL,
231 OPC_MFLO = 0x12 | OPC_SPECIAL,
232 OPC_MTLO = 0x13 | OPC_SPECIAL,
233 /* Conditional moves */
234 OPC_MOVZ = 0x0A | OPC_SPECIAL,
235 OPC_MOVN = 0x0B | OPC_SPECIAL,
236
237 OPC_SELEQZ = 0x35 | OPC_SPECIAL,
238 OPC_SELNEZ = 0x37 | OPC_SPECIAL,
239
240 OPC_MOVCI = 0x01 | OPC_SPECIAL,
241
242 /* Special */
243 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
244 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
245 OPC_BREAK = 0x0D | OPC_SPECIAL,
246 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
247 OPC_SYNC = 0x0F | OPC_SPECIAL,
248
249 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
250 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
251 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
252 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
253 };
254
255 /* R6 Multiply and Divide instructions have the same Opcode
256 and function field as legacy OPC_MULT[U]/OPC_DIV[U] */
257 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
258
259 enum {
260 R6_OPC_MUL = OPC_MULT | (2 << 6),
261 R6_OPC_MUH = OPC_MULT | (3 << 6),
262 R6_OPC_MULU = OPC_MULTU | (2 << 6),
263 R6_OPC_MUHU = OPC_MULTU | (3 << 6),
264 R6_OPC_DIV = OPC_DIV | (2 << 6),
265 R6_OPC_MOD = OPC_DIV | (3 << 6),
266 R6_OPC_DIVU = OPC_DIVU | (2 << 6),
267 R6_OPC_MODU = OPC_DIVU | (3 << 6),
268
269 R6_OPC_DMUL = OPC_DMULT | (2 << 6),
270 R6_OPC_DMUH = OPC_DMULT | (3 << 6),
271 R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
272 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
273 R6_OPC_DDIV = OPC_DDIV | (2 << 6),
274 R6_OPC_DMOD = OPC_DDIV | (3 << 6),
275 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
276 R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
277
278 R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
279 R6_OPC_CLO = 0x11 | OPC_SPECIAL,
280 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
281 R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
282 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
283
284 OPC_LSA = 0x05 | OPC_SPECIAL,
285 OPC_DLSA = 0x15 | OPC_SPECIAL,
286 };
287
288 /* Multiplication variants of the vr54xx. */
289 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
290
291 enum {
292 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
293 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
294 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
295 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
296 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
297 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
298 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
299 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
300 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
301 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
302 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
303 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
304 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
305 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
306 };
307
308 /* REGIMM (rt field) opcodes */
309 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
310
311 enum {
312 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
313 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
314 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
315 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
316 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
317 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
318 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
319 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
320 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
321 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
322 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
323 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
324 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
325 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
326 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
327
328 OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
329 OPC_DATI = (0x1e << 16) | OPC_REGIMM,
330 };
331
332 /* Special2 opcodes */
333 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
334
335 enum {
336 /* Multiply & xxx operations */
337 OPC_MADD = 0x00 | OPC_SPECIAL2,
338 OPC_MADDU = 0x01 | OPC_SPECIAL2,
339 OPC_MUL = 0x02 | OPC_SPECIAL2,
340 OPC_MSUB = 0x04 | OPC_SPECIAL2,
341 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
342 /* Loongson 2F */
343 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
344 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
345 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
346 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
347 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
348 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
349 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
350 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
351 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
352 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
353 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
354 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
355 /* Misc */
356 OPC_CLZ = 0x20 | OPC_SPECIAL2,
357 OPC_CLO = 0x21 | OPC_SPECIAL2,
358 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
359 OPC_DCLO = 0x25 | OPC_SPECIAL2,
360 /* Special */
361 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
362 };
363
364 /* Special3 opcodes */
365 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
366
367 enum {
368 OPC_EXT = 0x00 | OPC_SPECIAL3,
369 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
370 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
371 OPC_DEXT = 0x03 | OPC_SPECIAL3,
372 OPC_INS = 0x04 | OPC_SPECIAL3,
373 OPC_DINSM = 0x05 | OPC_SPECIAL3,
374 OPC_DINSU = 0x06 | OPC_SPECIAL3,
375 OPC_DINS = 0x07 | OPC_SPECIAL3,
376 OPC_FORK = 0x08 | OPC_SPECIAL3,
377 OPC_YIELD = 0x09 | OPC_SPECIAL3,
378 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
379 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
380 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
381
382 /* Loongson 2E */
383 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
384 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
385 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
386 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
387 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
388 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
389 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
390 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
391 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
392 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
393 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
394 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
395
396 /* MIPS DSP Load */
397 OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
398 /* MIPS DSP Arithmetic */
399 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
400 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
401 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
402 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
403 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
404 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
405 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
406 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
407 /* MIPS DSP GPR-Based Shift Sub-class */
408 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
409 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
410 /* MIPS DSP Multiply Sub-class insns */
411 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
412 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
413 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
414 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
415 /* DSP Bit/Manipulation Sub-class */
416 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
417 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
418 /* MIPS DSP Append Sub-class */
419 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3,
420 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3,
421 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
422 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3,
423 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3,
424
425 /* R6 */
426 R6_OPC_PREF = 0x35 | OPC_SPECIAL3,
427 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3,
428 R6_OPC_LL = 0x36 | OPC_SPECIAL3,
429 R6_OPC_SC = 0x26 | OPC_SPECIAL3,
430 R6_OPC_LLD = 0x37 | OPC_SPECIAL3,
431 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
432 };
433
434 /* BSHFL opcodes */
435 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
436
437 enum {
438 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
439 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
440 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
441 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
442 OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
443 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
444 };
445
446 /* DBSHFL opcodes */
447 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
448
449 enum {
450 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
451 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
452 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
453 OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
454 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
455 };
456
457 /* MIPS DSP REGIMM opcodes */
458 enum {
459 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
460 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
461 };
462
463 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
464 /* MIPS DSP Load */
465 enum {
466 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
467 OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
468 OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
469 OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
470 };
471
472 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
473 enum {
474 /* MIPS DSP Arithmetic Sub-class */
475 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
476 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
477 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
478 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
479 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
480 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
481 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
482 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
483 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
484 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
485 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
486 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
487 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
488 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
489 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
490 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
491 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
492 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
493 /* MIPS DSP Multiply Sub-class insns */
494 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
495 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
496 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
497 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
498 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
499 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
500 };
501
502 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
503 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
504 enum {
505 /* MIPS DSP Arithmetic Sub-class */
506 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
507 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
508 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
509 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
510 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
511 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
512 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
513 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
514 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
515 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
516 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
517 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
518 /* MIPS DSP Multiply Sub-class insns */
519 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
520 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
521 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
522 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
523 };
524
525 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
526 enum {
527 /* MIPS DSP Arithmetic Sub-class */
528 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
529 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
530 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
531 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
532 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
533 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
534 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
535 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
536 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
537 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
538 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
539 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
540 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
541 /* DSP Bit/Manipulation Sub-class */
542 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
543 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
544 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
545 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
546 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
547 };
548
549 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
550 enum {
551 /* MIPS DSP Arithmetic Sub-class */
552 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
553 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
554 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
555 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
556 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
557 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
558 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
559 /* DSP Compare-Pick Sub-class */
560 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
561 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
562 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
563 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
564 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
565 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
566 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
567 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
568 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
569 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
570 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
571 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
572 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
573 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
574 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
575 };
576
577 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
578 enum {
579 /* MIPS DSP GPR-Based Shift Sub-class */
580 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
581 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
582 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
583 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
584 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
585 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
586 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
587 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
588 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
589 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
590 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
591 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
592 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
593 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
594 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
595 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
596 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
597 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
598 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
599 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
600 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
601 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
602 };
603
604 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
605 enum {
606 /* MIPS DSP Multiply Sub-class insns */
607 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
608 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
609 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
610 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
611 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
612 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
613 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
614 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
615 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
616 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
617 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
618 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
619 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
620 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
621 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
622 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
623 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
624 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
625 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
626 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
627 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
628 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
629 };
630
631 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
632 enum {
633 /* DSP Bit/Manipulation Sub-class */
634 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
635 };
636
637 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
638 enum {
639 /* MIPS DSP Append Sub-class */
640 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
641 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
642 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
643 };
644
645 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
646 enum {
647 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
648 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
649 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
650 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
651 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
652 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
653 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
654 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
655 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
656 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
657 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
658 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
659 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
660 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
661 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
662 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
663 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
664 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
665 };
666
667 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
668 enum {
669 /* MIPS DSP Arithmetic Sub-class */
670 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
671 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
672 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
673 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
674 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
675 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
676 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
677 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
678 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
679 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
680 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
681 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
682 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
683 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
684 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
685 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
686 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
687 /* DSP Bit/Manipulation Sub-class */
688 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
689 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
690 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
691 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
692 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
693 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
694 };
695
696 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
697 enum {
698 /* MIPS DSP Multiply Sub-class insns */
699 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
700 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
701 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
702 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
703 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP,
704 /* MIPS DSP Arithmetic Sub-class */
705 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
706 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
707 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
708 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
709 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
710 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
711 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
712 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
713 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
714 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
715 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
716 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
717 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
718 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
719 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
720 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
721 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
722 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
723 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
724 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
725 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
726 };
727
728 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
729 enum {
730 /* DSP Compare-Pick Sub-class */
731 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
732 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
733 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
734 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
735 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
736 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
737 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
738 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
739 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
740 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
741 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
742 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
743 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
744 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
745 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
746 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
747 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
748 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
749 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
750 /* MIPS DSP Arithmetic Sub-class */
751 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
752 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
753 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
754 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
755 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
756 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
757 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
758 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
759 };
760
761 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
762 enum {
763 /* DSP Append Sub-class */
764 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP,
765 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
766 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
767 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP,
768 };
769
770 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
771 enum {
772 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
773 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP,
774 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP,
775 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP,
776 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP,
777 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP,
778 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP,
779 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP,
780 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP,
781 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP,
782 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP,
783 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP,
784 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP,
785 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP,
786 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP,
787 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP,
788 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
789 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP,
790 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP,
791 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP,
792 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
793 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP,
794 };
795
796 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
797 enum {
798 /* DSP Bit/Manipulation Sub-class */
799 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
800 };
801
802 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
803 enum {
804 /* MIPS DSP Multiply Sub-class insns */
805 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
806 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
807 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
808 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
809 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
810 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
811 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
812 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
813 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
814 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
815 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
816 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
817 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
818 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
819 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
820 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
821 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
822 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
823 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
824 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
825 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
826 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
827 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
828 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
829 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
830 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
831 };
832
833 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
834 enum {
835 /* MIPS DSP GPR-Based Shift Sub-class */
836 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP,
837 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP,
838 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP,
839 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP,
840 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
841 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP,
842 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
843 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP,
844 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP,
845 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP,
846 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
847 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP,
848 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
849 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP,
850 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
851 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP,
852 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP,
853 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP,
854 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP,
855 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP,
856 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP,
857 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP,
858 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP,
859 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP,
860 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP,
861 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP,
862 };
863
864 /* Coprocessor 0 (rs field) */
865 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
866
867 enum {
868 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
869 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
870 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
871 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
872 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
873 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
874 OPC_MFTR = (0x08 << 21) | OPC_CP0,
875 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
876 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
877 OPC_MTTR = (0x0C << 21) | OPC_CP0,
878 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
879 OPC_C0 = (0x10 << 21) | OPC_CP0,
880 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
881 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
882 };
883
884 /* MFMC0 opcodes */
885 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
886
887 enum {
888 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
889 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
890 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
891 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
892 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
893 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
894 };
895
896 /* Coprocessor 0 (with rs == C0) */
897 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
898
899 enum {
900 OPC_TLBR = 0x01 | OPC_C0,
901 OPC_TLBWI = 0x02 | OPC_C0,
902 OPC_TLBINV = 0x03 | OPC_C0,
903 OPC_TLBINVF = 0x04 | OPC_C0,
904 OPC_TLBWR = 0x06 | OPC_C0,
905 OPC_TLBP = 0x08 | OPC_C0,
906 OPC_RFE = 0x10 | OPC_C0,
907 OPC_ERET = 0x18 | OPC_C0,
908 OPC_DERET = 0x1F | OPC_C0,
909 OPC_WAIT = 0x20 | OPC_C0,
910 };
911
912 /* Coprocessor 1 (rs field) */
913 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
914
915 /* Values for the fmt field in FP instructions */
916 enum {
917 /* 0 - 15 are reserved */
918 FMT_S = 16, /* single fp */
919 FMT_D = 17, /* double fp */
920 FMT_E = 18, /* extended fp */
921 FMT_Q = 19, /* quad fp */
922 FMT_W = 20, /* 32-bit fixed */
923 FMT_L = 21, /* 64-bit fixed */
924 FMT_PS = 22, /* paired single fp */
925 /* 23 - 31 are reserved */
926 };
927
928 enum {
929 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
930 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
931 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
932 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
933 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
934 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
935 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
936 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
937 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
938 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
939 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
940 OPC_BZ_V = (0x0B << 21) | OPC_CP1,
941 OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
942 OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
943 OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
944 OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
945 OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
946 OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
947 OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
948 OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
949 OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
950 OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
951 OPC_BZ_B = (0x18 << 21) | OPC_CP1,
952 OPC_BZ_H = (0x19 << 21) | OPC_CP1,
953 OPC_BZ_W = (0x1A << 21) | OPC_CP1,
954 OPC_BZ_D = (0x1B << 21) | OPC_CP1,
955 OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
956 OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
957 OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
958 OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
959 };
960
961 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
962 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
963
964 enum {
965 OPC_BC1F = (0x00 << 16) | OPC_BC1,
966 OPC_BC1T = (0x01 << 16) | OPC_BC1,
967 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
968 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
969 };
970
971 enum {
972 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
973 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
974 };
975
976 enum {
977 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
978 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
979 };
980
981 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
982
983 enum {
984 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
985 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
986 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
987 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
988 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
989 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
990 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
991 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
992 OPC_BC2 = (0x08 << 21) | OPC_CP2,
993 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
994 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
995 };
996
997 #define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
998
999 enum {
1000 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
1001 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2,
1002 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2,
1003 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2,
1004 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2,
1005 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2,
1006 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2,
1007 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2,
1008
1009 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2,
1010 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2,
1011 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2,
1012 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2,
1013 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2,
1014 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2,
1015 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2,
1016 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2,
1017
1018 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2,
1019 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2,
1020 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2,
1021 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2,
1022 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2,
1023 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2,
1024 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2,
1025 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2,
1026
1027 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2,
1028 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2,
1029 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2,
1030 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2,
1031 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2,
1032 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2,
1033 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2,
1034 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2,
1035
1036 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2,
1037 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2,
1038 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2,
1039 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2,
1040 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2,
1041 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2,
1042
1043 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2,
1044 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2,
1045 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2,
1046 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2,
1047 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2,
1048 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2,
1049
1050 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2,
1051 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2,
1052 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2,
1053 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2,
1054 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2,
1055 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2,
1056
1057 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2,
1058 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2,
1059 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2,
1060 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2,
1061 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2,
1062 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2,
1063
1064 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2,
1065 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2,
1066 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2,
1067 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2,
1068 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2,
1069 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2,
1070
1071 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2,
1072 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2,
1073 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2,
1074 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2,
1075 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2,
1076 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2,
1077
1078 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2,
1079 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2,
1080 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2,
1081 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2,
1082 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2,
1083 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2,
1084
1085 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2,
1086 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2,
1087 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2,
1088 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2,
1089 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2,
1090 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2,
1091 };
1092
1093
1094 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
1095
1096 enum {
1097 OPC_LWXC1 = 0x00 | OPC_CP3,
1098 OPC_LDXC1 = 0x01 | OPC_CP3,
1099 OPC_LUXC1 = 0x05 | OPC_CP3,
1100 OPC_SWXC1 = 0x08 | OPC_CP3,
1101 OPC_SDXC1 = 0x09 | OPC_CP3,
1102 OPC_SUXC1 = 0x0D | OPC_CP3,
1103 OPC_PREFX = 0x0F | OPC_CP3,
1104 OPC_ALNV_PS = 0x1E | OPC_CP3,
1105 OPC_MADD_S = 0x20 | OPC_CP3,
1106 OPC_MADD_D = 0x21 | OPC_CP3,
1107 OPC_MADD_PS = 0x26 | OPC_CP3,
1108 OPC_MSUB_S = 0x28 | OPC_CP3,
1109 OPC_MSUB_D = 0x29 | OPC_CP3,
1110 OPC_MSUB_PS = 0x2E | OPC_CP3,
1111 OPC_NMADD_S = 0x30 | OPC_CP3,
1112 OPC_NMADD_D = 0x31 | OPC_CP3,
1113 OPC_NMADD_PS= 0x36 | OPC_CP3,
1114 OPC_NMSUB_S = 0x38 | OPC_CP3,
1115 OPC_NMSUB_D = 0x39 | OPC_CP3,
1116 OPC_NMSUB_PS= 0x3E | OPC_CP3,
1117 };
1118
1119 /* MSA Opcodes */
1120 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1121 enum {
1122 OPC_MSA_I8_00 = 0x00 | OPC_MSA,
1123 OPC_MSA_I8_01 = 0x01 | OPC_MSA,
1124 OPC_MSA_I8_02 = 0x02 | OPC_MSA,
1125 OPC_MSA_I5_06 = 0x06 | OPC_MSA,
1126 OPC_MSA_I5_07 = 0x07 | OPC_MSA,
1127 OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
1128 OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
1129 OPC_MSA_3R_0D = 0x0D | OPC_MSA,
1130 OPC_MSA_3R_0E = 0x0E | OPC_MSA,
1131 OPC_MSA_3R_0F = 0x0F | OPC_MSA,
1132 OPC_MSA_3R_10 = 0x10 | OPC_MSA,
1133 OPC_MSA_3R_11 = 0x11 | OPC_MSA,
1134 OPC_MSA_3R_12 = 0x12 | OPC_MSA,
1135 OPC_MSA_3R_13 = 0x13 | OPC_MSA,
1136 OPC_MSA_3R_14 = 0x14 | OPC_MSA,
1137 OPC_MSA_3R_15 = 0x15 | OPC_MSA,
1138 OPC_MSA_ELM = 0x19 | OPC_MSA,
1139 OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
1140 OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
1141 OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
1142 OPC_MSA_VEC = 0x1E | OPC_MSA,
1143
1144 /* MI10 instruction */
1145 OPC_LD_B = (0x20) | OPC_MSA,
1146 OPC_LD_H = (0x21) | OPC_MSA,
1147 OPC_LD_W = (0x22) | OPC_MSA,
1148 OPC_LD_D = (0x23) | OPC_MSA,
1149 OPC_ST_B = (0x24) | OPC_MSA,
1150 OPC_ST_H = (0x25) | OPC_MSA,
1151 OPC_ST_W = (0x26) | OPC_MSA,
1152 OPC_ST_D = (0x27) | OPC_MSA,
1153 };
1154
1155 enum {
1156 /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
1157 OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
1158 OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
1159 OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
1160 OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
1161 OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
1162 OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
1163 OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
1164 OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
1165 OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
1166 OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
1167 OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
1168 OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
1169
1170 /* I8 instruction */
1171 OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
1172 OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
1173 OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
1174 OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
1175 OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
1176 OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
1177 OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
1178 OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
1179 OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
1180 OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
1181
1182 /* VEC/2R/2RF instruction */
1183 OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
1184 OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
1185 OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
1186 OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
1187 OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
1188 OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
1189 OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
1190
1191 OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
1192 OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
1193
1194 /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
1195 OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
1196 OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
1197 OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
1198 OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
1199
1200 /* 2RF instruction df(bit 16) = _w, _d */
1201 OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF,
1202 OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF,
1203 OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF,
1204 OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF,
1205 OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF,
1206 OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF,
1207 OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF,
1208 OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF,
1209 OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF,
1210 OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF,
1211 OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF,
1212 OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF,
1213 OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF,
1214 OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF,
1215 OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF,
1216 OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF,
1217
1218 /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
1219 OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
1220 OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
1221 OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
1222 OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
1223 OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
1224 OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
1225 OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
1226 OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
1227 OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
1228 OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
1229 OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
1230 OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
1231 OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
1232 OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
1233 OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
1234 OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
1235 OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
1236 OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
1237 OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
1238 OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
1239 OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
1240 OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
1241 OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
1242 OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
1243 OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
1244 OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
1245 OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
1246 OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
1247 OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
1248 OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
1249 OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
1250 OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
1251 OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
1252 OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
1253 OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
1254 OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
1255 OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
1256 OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
1257 OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
1258 OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
1259 OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
1260 OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
1261 OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
1262 OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
1263 OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
1264 OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
1265 OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
1266 OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
1267 OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
1268 OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
1269 OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
1270 OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
1271 OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
1272 OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
1273 OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
1274 OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
1275 OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
1276 OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
1277 OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
1278 OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
1279 OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
1280 OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
1281 OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
1282
1283 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
1284 OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1285 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1286 OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1287 OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1288 OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1289 OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
1290 OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1291 OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1292 OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
1293
1294 /* 3RF instruction _df(bit 21) = _w, _d */
1295 OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
1296 OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
1297 OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
1298 OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
1299 OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
1300 OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
1301 OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
1302 OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
1303 OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
1304 OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
1305 OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
1306 OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
1307 OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
1308 OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
1309 OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
1310 OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
1311 OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
1312 OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
1313 OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
1314 OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
1315 OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
1316 OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
1317 OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
1318 OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
1319 OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
1320 OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
1321 OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
1322 OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
1323 OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
1324 OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
1325 OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
1326 OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
1327 OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
1328 OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
1329 OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
1330 OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
1331 OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
1332 OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
1333 OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
1334 OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
1335 OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
1336
1337 /* BIT instruction df(bits 22..16) = _B _H _W _D */
1338 OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
1339 OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
1340 OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
1341 OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
1342 OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
1343 OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
1344 OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
1345 OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
1346 OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
1347 OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
1348 OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
1349 OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
1350 };
1351
1352 /* global register indices */
1353 static TCGv_ptr cpu_env;
1354 static TCGv cpu_gpr[32], cpu_PC;
1355 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
1356 static TCGv cpu_dspctrl, btarget, bcond;
1357 static TCGv_i32 hflags;
1358 static TCGv_i32 fpu_fcr0, fpu_fcr31;
1359 static TCGv_i64 fpu_f64[32];
1360 static TCGv_i64 msa_wr_d[64];
1361
1362 static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
1363 static target_ulong gen_opc_btarget[OPC_BUF_SIZE];
1364
1365 #include "exec/gen-icount.h"
1366
1367 #define gen_helper_0e0i(name, arg) do { \
1368 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
1369 gen_helper_##name(cpu_env, helper_tmp); \
1370 tcg_temp_free_i32(helper_tmp); \
1371 } while(0)
1372
1373 #define gen_helper_0e1i(name, arg1, arg2) do { \
1374 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1375 gen_helper_##name(cpu_env, arg1, helper_tmp); \
1376 tcg_temp_free_i32(helper_tmp); \
1377 } while(0)
1378
1379 #define gen_helper_1e0i(name, ret, arg1) do { \
1380 TCGv_i32 helper_tmp = tcg_const_i32(arg1); \
1381 gen_helper_##name(ret, cpu_env, helper_tmp); \
1382 tcg_temp_free_i32(helper_tmp); \
1383 } while(0)
1384
1385 #define gen_helper_1e1i(name, ret, arg1, arg2) do { \
1386 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
1387 gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \
1388 tcg_temp_free_i32(helper_tmp); \
1389 } while(0)
1390
1391 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
1392 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1393 gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \
1394 tcg_temp_free_i32(helper_tmp); \
1395 } while(0)
1396
1397 #define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \
1398 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
1399 gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \
1400 tcg_temp_free_i32(helper_tmp); \
1401 } while(0)
1402
1403 #define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \
1404 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
1405 gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \
1406 tcg_temp_free_i32(helper_tmp); \
1407 } while(0)
1408
1409 typedef struct DisasContext {
1410 struct TranslationBlock *tb;
1411 target_ulong pc, saved_pc;
1412 uint32_t opcode;
1413 int singlestep_enabled;
1414 int insn_flags;
1415 int32_t CP0_Config1;
1416 /* Routine used to access memory */
1417 int mem_idx;
1418 TCGMemOp default_tcg_memop_mask;
1419 uint32_t hflags, saved_hflags;
1420 int bstate;
1421 target_ulong btarget;
1422 bool ulri;
1423 int kscrexist;
1424 bool rxi;
1425 int ie;
1426 bool bi;
1427 bool bp;
1428 uint64_t PAMask;
1429 bool mvh;
1430 int CP0_LLAddr_shift;
1431 bool ps;
1432 } DisasContext;
1433
1434 enum {
1435 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
1436 * exception condition */
1437 BS_STOP = 1, /* We want to stop translation for any reason */
1438 BS_BRANCH = 2, /* We reached a branch condition */
1439 BS_EXCP = 3, /* We reached an exception condition */
1440 };
1441
1442 static const char * const regnames[] = {
1443 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
1444 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
1445 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1446 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
1447 };
1448
1449 static const char * const regnames_HI[] = {
1450 "HI0", "HI1", "HI2", "HI3",
1451 };
1452
1453 static const char * const regnames_LO[] = {
1454 "LO0", "LO1", "LO2", "LO3",
1455 };
1456
1457 static const char * const fregnames[] = {
1458 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1459 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1460 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1461 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1462 };
1463
1464 static const char * const msaregnames[] = {
1465 "w0.d0", "w0.d1", "w1.d0", "w1.d1",
1466 "w2.d0", "w2.d1", "w3.d0", "w3.d1",
1467 "w4.d0", "w4.d1", "w5.d0", "w5.d1",
1468 "w6.d0", "w6.d1", "w7.d0", "w7.d1",
1469 "w8.d0", "w8.d1", "w9.d0", "w9.d1",
1470 "w10.d0", "w10.d1", "w11.d0", "w11.d1",
1471 "w12.d0", "w12.d1", "w13.d0", "w13.d1",
1472 "w14.d0", "w14.d1", "w15.d0", "w15.d1",
1473 "w16.d0", "w16.d1", "w17.d0", "w17.d1",
1474 "w18.d0", "w18.d1", "w19.d0", "w19.d1",
1475 "w20.d0", "w20.d1", "w21.d0", "w21.d1",
1476 "w22.d0", "w22.d1", "w23.d0", "w23.d1",
1477 "w24.d0", "w24.d1", "w25.d0", "w25.d1",
1478 "w26.d0", "w26.d1", "w27.d0", "w27.d1",
1479 "w28.d0", "w28.d1", "w29.d0", "w29.d1",
1480 "w30.d0", "w30.d1", "w31.d0", "w31.d1",
1481 };
1482
1483 #define LOG_DISAS(...) \
1484 do { \
1485 if (MIPS_DEBUG_DISAS) { \
1486 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
1487 } \
1488 } while (0)
1489
1490 #define MIPS_INVAL(op) \
1491 do { \
1492 if (MIPS_DEBUG_DISAS) { \
1493 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
1494 TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
1495 ctx->pc, ctx->opcode, op, ctx->opcode >> 26, \
1496 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
1497 } \
1498 } while (0)
1499
1500 /* General purpose registers moves. */
1501 static inline void gen_load_gpr (TCGv t, int reg)
1502 {
1503 if (reg == 0)
1504 tcg_gen_movi_tl(t, 0);
1505 else
1506 tcg_gen_mov_tl(t, cpu_gpr[reg]);
1507 }
1508
1509 static inline void gen_store_gpr (TCGv t, int reg)
1510 {
1511 if (reg != 0)
1512 tcg_gen_mov_tl(cpu_gpr[reg], t);
1513 }
1514
1515 /* Moves to/from shadow registers. */
1516 static inline void gen_load_srsgpr (int from, int to)
1517 {
1518 TCGv t0 = tcg_temp_new();
1519
1520 if (from == 0)
1521 tcg_gen_movi_tl(t0, 0);
1522 else {
1523 TCGv_i32 t2 = tcg_temp_new_i32();
1524 TCGv_ptr addr = tcg_temp_new_ptr();
1525
1526 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1527 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1528 tcg_gen_andi_i32(t2, t2, 0xf);
1529 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1530 tcg_gen_ext_i32_ptr(addr, t2);
1531 tcg_gen_add_ptr(addr, cpu_env, addr);
1532
1533 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
1534 tcg_temp_free_ptr(addr);
1535 tcg_temp_free_i32(t2);
1536 }
1537 gen_store_gpr(t0, to);
1538 tcg_temp_free(t0);
1539 }
1540
1541 static inline void gen_store_srsgpr (int from, int to)
1542 {
1543 if (to != 0) {
1544 TCGv t0 = tcg_temp_new();
1545 TCGv_i32 t2 = tcg_temp_new_i32();
1546 TCGv_ptr addr = tcg_temp_new_ptr();
1547
1548 gen_load_gpr(t0, from);
1549 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1550 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1551 tcg_gen_andi_i32(t2, t2, 0xf);
1552 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1553 tcg_gen_ext_i32_ptr(addr, t2);
1554 tcg_gen_add_ptr(addr, cpu_env, addr);
1555
1556 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
1557 tcg_temp_free_ptr(addr);
1558 tcg_temp_free_i32(t2);
1559 tcg_temp_free(t0);
1560 }
1561 }
1562
1563 /* Tests */
1564 static inline void gen_save_pc(target_ulong pc)
1565 {
1566 tcg_gen_movi_tl(cpu_PC, pc);
1567 }
1568
1569 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
1570 {
1571 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
1572 if (do_save_pc && ctx->pc != ctx->saved_pc) {
1573 gen_save_pc(ctx->pc);
1574 ctx->saved_pc = ctx->pc;
1575 }
1576 if (ctx->hflags != ctx->saved_hflags) {
1577 tcg_gen_movi_i32(hflags, ctx->hflags);
1578 ctx->saved_hflags = ctx->hflags;
1579 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1580 case MIPS_HFLAG_BR:
1581 break;
1582 case MIPS_HFLAG_BC:
1583 case MIPS_HFLAG_BL:
1584 case MIPS_HFLAG_B:
1585 tcg_gen_movi_tl(btarget, ctx->btarget);
1586 break;
1587 }
1588 }
1589 }
1590
1591 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
1592 {
1593 ctx->saved_hflags = ctx->hflags;
1594 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1595 case MIPS_HFLAG_BR:
1596 break;
1597 case MIPS_HFLAG_BC:
1598 case MIPS_HFLAG_BL:
1599 case MIPS_HFLAG_B:
1600 ctx->btarget = env->btarget;
1601 break;
1602 }
1603 }
1604
1605 static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
1606 {
1607 TCGv_i32 texcp = tcg_const_i32(excp);
1608 TCGv_i32 terr = tcg_const_i32(err);
1609 save_cpu_state(ctx, 1);
1610 gen_helper_raise_exception_err(cpu_env, texcp, terr);
1611 tcg_temp_free_i32(terr);
1612 tcg_temp_free_i32(texcp);
1613 }
1614
1615 static inline void generate_exception(DisasContext *ctx, int excp)
1616 {
1617 save_cpu_state(ctx, 1);
1618 gen_helper_0e0i(raise_exception, excp);
1619 }
1620
1621 /* Floating point register moves. */
1622 static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1623 {
1624 if (ctx->hflags & MIPS_HFLAG_FRE) {
1625 generate_exception(ctx, EXCP_RI);
1626 }
1627 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
1628 }
1629
1630 static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1631 {
1632 TCGv_i64 t64;
1633 if (ctx->hflags & MIPS_HFLAG_FRE) {
1634 generate_exception(ctx, EXCP_RI);
1635 }
1636 t64 = tcg_temp_new_i64();
1637 tcg_gen_extu_i32_i64(t64, t);
1638 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
1639 tcg_temp_free_i64(t64);
1640 }
1641
1642 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1643 {
1644 if (ctx->hflags & MIPS_HFLAG_F64) {
1645 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
1646 } else {
1647 gen_load_fpr32(ctx, t, reg | 1);
1648 }
1649 }
1650
1651 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1652 {
1653 if (ctx->hflags & MIPS_HFLAG_F64) {
1654 TCGv_i64 t64 = tcg_temp_new_i64();
1655 tcg_gen_extu_i32_i64(t64, t);
1656 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
1657 tcg_temp_free_i64(t64);
1658 } else {
1659 gen_store_fpr32(ctx, t, reg | 1);
1660 }
1661 }
1662
1663 static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1664 {
1665 if (ctx->hflags & MIPS_HFLAG_F64) {
1666 tcg_gen_mov_i64(t, fpu_f64[reg]);
1667 } else {
1668 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
1669 }
1670 }
1671
1672 static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1673 {
1674 if (ctx->hflags & MIPS_HFLAG_F64) {
1675 tcg_gen_mov_i64(fpu_f64[reg], t);
1676 } else {
1677 TCGv_i64 t0;
1678 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
1679 t0 = tcg_temp_new_i64();
1680 tcg_gen_shri_i64(t0, t, 32);
1681 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
1682 tcg_temp_free_i64(t0);
1683 }
1684 }
1685
1686 static inline int get_fp_bit (int cc)
1687 {
1688 if (cc)
1689 return 24 + cc;
1690 else
1691 return 23;
1692 }
1693
1694 /* Addresses computation */
1695 static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
1696 {
1697 tcg_gen_add_tl(ret, arg0, arg1);
1698
1699 #if defined(TARGET_MIPS64)
1700 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1701 tcg_gen_ext32s_i64(ret, ret);
1702 }
1703 #endif
1704 }
1705
1706 /* Addresses computation (translation time) */
1707 static target_long addr_add(DisasContext *ctx, target_long base,
1708 target_long offset)
1709 {
1710 target_long sum = base + offset;
1711
1712 #if defined(TARGET_MIPS64)
1713 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1714 sum = (int32_t)sum;
1715 }
1716 #endif
1717 return sum;
1718 }
1719
1720 /* Sign-extract the low 32-bits to a target_long. */
1721 static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
1722 {
1723 #if defined(TARGET_MIPS64)
1724 tcg_gen_ext32s_i64(ret, arg);
1725 #else
1726 tcg_gen_extrl_i64_i32(ret, arg);
1727 #endif
1728 }
1729
1730 /* Sign-extract the high 32-bits to a target_long. */
1731 static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
1732 {
1733 #if defined(TARGET_MIPS64)
1734 tcg_gen_sari_i64(ret, arg, 32);
1735 #else
1736 tcg_gen_extrh_i64_i32(ret, arg);
1737 #endif
1738 }
1739
1740 static inline void check_cp0_enabled(DisasContext *ctx)
1741 {
1742 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
1743 generate_exception_err(ctx, EXCP_CpU, 0);
1744 }
1745
1746 static inline void check_cp1_enabled(DisasContext *ctx)
1747 {
1748 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
1749 generate_exception_err(ctx, EXCP_CpU, 1);
1750 }
1751
1752 /* Verify that the processor is running with COP1X instructions enabled.
1753 This is associated with the nabla symbol in the MIPS32 and MIPS64
1754 opcode tables. */
1755
1756 static inline void check_cop1x(DisasContext *ctx)
1757 {
1758 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
1759 generate_exception(ctx, EXCP_RI);
1760 }
1761
1762 /* Verify that the processor is running with 64-bit floating-point
1763 operations enabled. */
1764
1765 static inline void check_cp1_64bitmode(DisasContext *ctx)
1766 {
1767 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
1768 generate_exception(ctx, EXCP_RI);
1769 }
1770
1771 /*
1772 * Verify if floating point register is valid; an operation is not defined
1773 * if bit 0 of any register specification is set and the FR bit in the
1774 * Status register equals zero, since the register numbers specify an
1775 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1776 * in the Status register equals one, both even and odd register numbers
1777 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1778 *
1779 * Multiple 64 bit wide registers can be checked by calling
1780 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1781 */
1782 static inline void check_cp1_registers(DisasContext *ctx, int regs)
1783 {
1784 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
1785 generate_exception(ctx, EXCP_RI);
1786 }
1787
1788 /* Verify that the processor is running with DSP instructions enabled.
1789 This is enabled by CP0 Status register MX(24) bit.
1790 */
1791
1792 static inline void check_dsp(DisasContext *ctx)
1793 {
1794 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
1795 if (ctx->insn_flags & ASE_DSP) {
1796 generate_exception(ctx, EXCP_DSPDIS);
1797 } else {
1798 generate_exception(ctx, EXCP_RI);
1799 }
1800 }
1801 }
1802
1803 static inline void check_dspr2(DisasContext *ctx)
1804 {
1805 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
1806 if (ctx->insn_flags & ASE_DSP) {
1807 generate_exception(ctx, EXCP_DSPDIS);
1808 } else {
1809 generate_exception(ctx, EXCP_RI);
1810 }
1811 }
1812 }
1813
1814 /* This code generates a "reserved instruction" exception if the
1815 CPU does not support the instruction set corresponding to flags. */
1816 static inline void check_insn(DisasContext *ctx, int flags)
1817 {
1818 if (unlikely(!(ctx->insn_flags & flags))) {
1819 generate_exception(ctx, EXCP_RI);
1820 }
1821 }
1822
1823 /* This code generates a "reserved instruction" exception if the
1824 CPU has corresponding flag set which indicates that the instruction
1825 has been removed. */
1826 static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
1827 {
1828 if (unlikely(ctx->insn_flags & flags)) {
1829 generate_exception(ctx, EXCP_RI);
1830 }
1831 }
1832
1833 /* This code generates a "reserved instruction" exception if the
1834 CPU does not support 64-bit paired-single (PS) floating point data type */
1835 static inline void check_ps(DisasContext *ctx)
1836 {
1837 if (unlikely(!ctx->ps)) {
1838 generate_exception(ctx, EXCP_RI);
1839 }
1840 check_cp1_64bitmode(ctx);
1841 }
1842
1843 #ifdef TARGET_MIPS64
1844 /* This code generates a "reserved instruction" exception if 64-bit
1845 instructions are not enabled. */
1846 static inline void check_mips_64(DisasContext *ctx)
1847 {
1848 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
1849 generate_exception(ctx, EXCP_RI);
1850 }
1851 #endif
1852
1853 #ifndef CONFIG_USER_ONLY
1854 static inline void check_mvh(DisasContext *ctx)
1855 {
1856 if (unlikely(!ctx->mvh)) {
1857 generate_exception(ctx, EXCP_RI);
1858 }
1859 }
1860 #endif
1861
1862 /* Define small wrappers for gen_load_fpr* so that we have a uniform
1863 calling interface for 32 and 64-bit FPRs. No sense in changing
1864 all callers for gen_load_fpr32 when we need the CTX parameter for
1865 this one use. */
1866 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1867 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1868 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1869 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1870 int ft, int fs, int cc) \
1871 { \
1872 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
1873 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
1874 switch (ifmt) { \
1875 case FMT_PS: \
1876 check_ps(ctx); \
1877 break; \
1878 case FMT_D: \
1879 if (abs) { \
1880 check_cop1x(ctx); \
1881 } \
1882 check_cp1_registers(ctx, fs | ft); \
1883 break; \
1884 case FMT_S: \
1885 if (abs) { \
1886 check_cop1x(ctx); \
1887 } \
1888 break; \
1889 } \
1890 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
1891 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
1892 switch (n) { \
1893 case 0: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
1894 case 1: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
1895 case 2: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
1896 case 3: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
1897 case 4: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
1898 case 5: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
1899 case 6: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
1900 case 7: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
1901 case 8: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
1902 case 9: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
1903 case 10: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
1904 case 11: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
1905 case 12: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
1906 case 13: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
1907 case 14: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
1908 case 15: gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
1909 default: abort(); \
1910 } \
1911 tcg_temp_free_i##bits (fp0); \
1912 tcg_temp_free_i##bits (fp1); \
1913 }
1914
1915 FOP_CONDS(, 0, d, FMT_D, 64)
1916 FOP_CONDS(abs, 1, d, FMT_D, 64)
1917 FOP_CONDS(, 0, s, FMT_S, 32)
1918 FOP_CONDS(abs, 1, s, FMT_S, 32)
1919 FOP_CONDS(, 0, ps, FMT_PS, 64)
1920 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
1921 #undef FOP_CONDS
1922
1923 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1924 static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n, \
1925 int ft, int fs, int fd) \
1926 { \
1927 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1928 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1929 if (ifmt == FMT_D) { \
1930 check_cp1_registers(ctx, fs | ft | fd); \
1931 } \
1932 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1933 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1934 switch (n) { \
1935 case 0: \
1936 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \
1937 break; \
1938 case 1: \
1939 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \
1940 break; \
1941 case 2: \
1942 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \
1943 break; \
1944 case 3: \
1945 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \
1946 break; \
1947 case 4: \
1948 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \
1949 break; \
1950 case 5: \
1951 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \
1952 break; \
1953 case 6: \
1954 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \
1955 break; \
1956 case 7: \
1957 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \
1958 break; \
1959 case 8: \
1960 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \
1961 break; \
1962 case 9: \
1963 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \
1964 break; \
1965 case 10: \
1966 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \
1967 break; \
1968 case 11: \
1969 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \
1970 break; \
1971 case 12: \
1972 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \
1973 break; \
1974 case 13: \
1975 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \
1976 break; \
1977 case 14: \
1978 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \
1979 break; \
1980 case 15: \
1981 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \
1982 break; \
1983 case 17: \
1984 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \
1985 break; \
1986 case 18: \
1987 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \
1988 break; \
1989 case 19: \
1990 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \
1991 break; \
1992 case 25: \
1993 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \
1994 break; \
1995 case 26: \
1996 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \
1997 break; \
1998 case 27: \
1999 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \
2000 break; \
2001 default: \
2002 abort(); \
2003 } \
2004 STORE; \
2005 tcg_temp_free_i ## bits (fp0); \
2006 tcg_temp_free_i ## bits (fp1); \
2007 }
2008
2009 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
2010 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
2011 #undef FOP_CONDNS
2012 #undef gen_ldcmp_fpr32
2013 #undef gen_ldcmp_fpr64
2014
2015 /* load/store instructions. */
2016 #ifdef CONFIG_USER_ONLY
2017 #define OP_LD_ATOMIC(insn,fname) \
2018 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
2019 { \
2020 TCGv t0 = tcg_temp_new(); \
2021 tcg_gen_mov_tl(t0, arg1); \
2022 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
2023 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2024 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
2025 tcg_temp_free(t0); \
2026 }
2027 #else
2028 #define OP_LD_ATOMIC(insn,fname) \
2029 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
2030 { \
2031 gen_helper_1e1i(insn, ret, arg1, ctx->mem_idx); \
2032 }
2033 #endif
2034 OP_LD_ATOMIC(ll,ld32s);
2035 #if defined(TARGET_MIPS64)
2036 OP_LD_ATOMIC(lld,ld64);
2037 #endif
2038 #undef OP_LD_ATOMIC
2039
2040 #ifdef CONFIG_USER_ONLY
2041 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2042 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2043 { \
2044 TCGv t0 = tcg_temp_new(); \
2045 TCGLabel *l1 = gen_new_label(); \
2046 TCGLabel *l2 = gen_new_label(); \
2047 \
2048 tcg_gen_andi_tl(t0, arg2, almask); \
2049 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
2050 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
2051 generate_exception(ctx, EXCP_AdES); \
2052 gen_set_label(l1); \
2053 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
2054 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
2055 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
2056 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
2057 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
2058 gen_helper_0e0i(raise_exception, EXCP_SC); \
2059 gen_set_label(l2); \
2060 tcg_gen_movi_tl(t0, 0); \
2061 gen_store_gpr(t0, rt); \
2062 tcg_temp_free(t0); \
2063 }
2064 #else
2065 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
2066 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
2067 { \
2068 TCGv t0 = tcg_temp_new(); \
2069 gen_helper_1e2i(insn, t0, arg1, arg2, ctx->mem_idx); \
2070 gen_store_gpr(t0, rt); \
2071 tcg_temp_free(t0); \
2072 }
2073 #endif
2074 OP_ST_ATOMIC(sc,st32,ld32s,0x3);
2075 #if defined(TARGET_MIPS64)
2076 OP_ST_ATOMIC(scd,st64,ld64,0x7);
2077 #endif
2078 #undef OP_ST_ATOMIC
2079
2080 static void gen_base_offset_addr (DisasContext *ctx, TCGv addr,
2081 int base, int16_t offset)
2082 {
2083 if (base == 0) {
2084 tcg_gen_movi_tl(addr, offset);
2085 } else if (offset == 0) {
2086 gen_load_gpr(addr, base);
2087 } else {
2088 tcg_gen_movi_tl(addr, offset);
2089 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
2090 }
2091 }
2092
2093 static target_ulong pc_relative_pc (DisasContext *ctx)
2094 {
2095 target_ulong pc = ctx->pc;
2096
2097 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2098 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
2099
2100 pc -= branch_bytes;
2101 }
2102
2103 pc &= ~(target_ulong)3;
2104 return pc;
2105 }
2106
2107 /* Load */
2108 static void gen_ld(DisasContext *ctx, uint32_t opc,
2109 int rt, int base, int16_t offset)
2110 {
2111 TCGv t0, t1, t2;
2112
2113 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
2114 /* Loongson CPU uses a load to zero register for prefetch.
2115 We emulate it as a NOP. On other CPU we must perform the
2116 actual memory access. */
2117 return;
2118 }
2119
2120 t0 = tcg_temp_new();
2121 gen_base_offset_addr(ctx, t0, base, offset);
2122
2123 switch (opc) {
2124 #if defined(TARGET_MIPS64)
2125 case OPC_LWU:
2126 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL |
2127 ctx->default_tcg_memop_mask);
2128 gen_store_gpr(t0, rt);
2129 break;
2130 case OPC_LD:
2131 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
2132 ctx->default_tcg_memop_mask);
2133 gen_store_gpr(t0, rt);
2134 break;
2135 case OPC_LLD:
2136 case R6_OPC_LLD:
2137 save_cpu_state(ctx, 1);
2138 op_ld_lld(t0, t0, ctx);
2139 gen_store_gpr(t0, rt);
2140 break;
2141 case OPC_LDL:
2142 t1 = tcg_temp_new();
2143 /* Do a byte access to possibly trigger a page
2144 fault with the unaligned address. */
2145 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2146 tcg_gen_andi_tl(t1, t0, 7);
2147 #ifndef TARGET_WORDS_BIGENDIAN
2148 tcg_gen_xori_tl(t1, t1, 7);
2149 #endif
2150 tcg_gen_shli_tl(t1, t1, 3);
2151 tcg_gen_andi_tl(t0, t0, ~7);
2152 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2153 tcg_gen_shl_tl(t0, t0, t1);
2154 t2 = tcg_const_tl(-1);
2155 tcg_gen_shl_tl(t2, t2, t1);
2156 gen_load_gpr(t1, rt);
2157 tcg_gen_andc_tl(t1, t1, t2);
2158 tcg_temp_free(t2);
2159 tcg_gen_or_tl(t0, t0, t1);
2160 tcg_temp_free(t1);
2161 gen_store_gpr(t0, rt);
2162 break;
2163 case OPC_LDR:
2164 t1 = tcg_temp_new();
2165 /* Do a byte access to possibly trigger a page
2166 fault with the unaligned address. */
2167 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2168 tcg_gen_andi_tl(t1, t0, 7);
2169 #ifdef TARGET_WORDS_BIGENDIAN
2170 tcg_gen_xori_tl(t1, t1, 7);
2171 #endif
2172 tcg_gen_shli_tl(t1, t1, 3);
2173 tcg_gen_andi_tl(t0, t0, ~7);
2174 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2175 tcg_gen_shr_tl(t0, t0, t1);
2176 tcg_gen_xori_tl(t1, t1, 63);
2177 t2 = tcg_const_tl(0xfffffffffffffffeull);
2178 tcg_gen_shl_tl(t2, t2, t1);
2179 gen_load_gpr(t1, rt);
2180 tcg_gen_and_tl(t1, t1, t2);
2181 tcg_temp_free(t2);
2182 tcg_gen_or_tl(t0, t0, t1);
2183 tcg_temp_free(t1);
2184 gen_store_gpr(t0, rt);
2185 break;
2186 case OPC_LDPC:
2187 t1 = tcg_const_tl(pc_relative_pc(ctx));
2188 gen_op_addr_add(ctx, t0, t0, t1);
2189 tcg_temp_free(t1);
2190 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
2191 gen_store_gpr(t0, rt);
2192 break;
2193 #endif
2194 case OPC_LWPC:
2195 t1 = tcg_const_tl(pc_relative_pc(ctx));
2196 gen_op_addr_add(ctx, t0, t0, t1);
2197 tcg_temp_free(t1);
2198 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
2199 gen_store_gpr(t0, rt);
2200 break;
2201 case OPC_LW:
2202 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
2203 ctx->default_tcg_memop_mask);
2204 gen_store_gpr(t0, rt);
2205 break;
2206 case OPC_LH:
2207 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
2208 ctx->default_tcg_memop_mask);
2209 gen_store_gpr(t0, rt);
2210 break;
2211 case OPC_LHU:
2212 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW |
2213 ctx->default_tcg_memop_mask);
2214 gen_store_gpr(t0, rt);
2215 break;
2216 case OPC_LB:
2217 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
2218 gen_store_gpr(t0, rt);
2219 break;
2220 case OPC_LBU:
2221 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
2222 gen_store_gpr(t0, rt);
2223 break;
2224 case OPC_LWL:
2225 t1 = tcg_temp_new();
2226 /* Do a byte access to possibly trigger a page
2227 fault with the unaligned address. */
2228 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2229 tcg_gen_andi_tl(t1, t0, 3);
2230 #ifndef TARGET_WORDS_BIGENDIAN
2231 tcg_gen_xori_tl(t1, t1, 3);
2232 #endif
2233 tcg_gen_shli_tl(t1, t1, 3);
2234 tcg_gen_andi_tl(t0, t0, ~3);
2235 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
2236 tcg_gen_shl_tl(t0, t0, t1);
2237 t2 = tcg_const_tl(-1);
2238 tcg_gen_shl_tl(t2, t2, t1);
2239 gen_load_gpr(t1, rt);
2240 tcg_gen_andc_tl(t1, t1, t2);
2241 tcg_temp_free(t2);
2242 tcg_gen_or_tl(t0, t0, t1);
2243 tcg_temp_free(t1);
2244 tcg_gen_ext32s_tl(t0, t0);
2245 gen_store_gpr(t0, rt);
2246 break;
2247 case OPC_LWR:
2248 t1 = tcg_temp_new();
2249 /* Do a byte access to possibly trigger a page
2250 fault with the unaligned address. */
2251 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
2252 tcg_gen_andi_tl(t1, t0, 3);
2253 #ifdef TARGET_WORDS_BIGENDIAN
2254 tcg_gen_xori_tl(t1, t1, 3);
2255 #endif
2256 tcg_gen_shli_tl(t1, t1, 3);
2257 tcg_gen_andi_tl(t0, t0, ~3);
2258 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
2259 tcg_gen_shr_tl(t0, t0, t1);
2260 tcg_gen_xori_tl(t1, t1, 31);
2261 t2 = tcg_const_tl(0xfffffffeull);
2262 tcg_gen_shl_tl(t2, t2, t1);
2263 gen_load_gpr(t1, rt);
2264 tcg_gen_and_tl(t1, t1, t2);
2265 tcg_temp_free(t2);
2266 tcg_gen_or_tl(t0, t0, t1);
2267 tcg_temp_free(t1);
2268 tcg_gen_ext32s_tl(t0, t0);
2269 gen_store_gpr(t0, rt);
2270 break;
2271 case OPC_LL:
2272 case R6_OPC_LL:
2273 save_cpu_state(ctx, 1);
2274 op_ld_ll(t0, t0, ctx);
2275 gen_store_gpr(t0, rt);
2276 break;
2277 }
2278 tcg_temp_free(t0);
2279 }
2280
2281 /* Store */
2282 static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
2283 int base, int16_t offset)
2284 {
2285 TCGv t0 = tcg_temp_new();
2286 TCGv t1 = tcg_temp_new();
2287
2288 gen_base_offset_addr(ctx, t0, base, offset);
2289 gen_load_gpr(t1, rt);
2290 switch (opc) {
2291 #if defined(TARGET_MIPS64)
2292 case OPC_SD:
2293 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
2294 ctx->default_tcg_memop_mask);
2295 break;
2296 case OPC_SDL:
2297 save_cpu_state(ctx, 1);
2298 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
2299 break;
2300 case OPC_SDR:
2301 save_cpu_state(ctx, 1);
2302 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
2303 break;
2304 #endif
2305 case OPC_SW:
2306 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
2307 ctx->default_tcg_memop_mask);
2308 break;
2309 case OPC_SH:
2310 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
2311 ctx->default_tcg_memop_mask);
2312 break;
2313 case OPC_SB:
2314 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
2315 break;
2316 case OPC_SWL:
2317 save_cpu_state(ctx, 1);
2318 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
2319 break;
2320 case OPC_SWR:
2321 save_cpu_state(ctx, 1);
2322 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
2323 break;
2324 }
2325 tcg_temp_free(t0);
2326 tcg_temp_free(t1);
2327 }
2328
2329
2330 /* Store conditional */
2331 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
2332 int base, int16_t offset)
2333 {
2334 TCGv t0, t1;
2335
2336 #ifdef CONFIG_USER_ONLY
2337 t0 = tcg_temp_local_new();
2338 t1 = tcg_temp_local_new();
2339 #else
2340 t0 = tcg_temp_new();
2341 t1 = tcg_temp_new();
2342 #endif
2343 gen_base_offset_addr(ctx, t0, base, offset);
2344 gen_load_gpr(t1, rt);
2345 switch (opc) {
2346 #if defined(TARGET_MIPS64)
2347 case OPC_SCD:
2348 case R6_OPC_SCD:
2349 save_cpu_state(ctx, 1);
2350 op_st_scd(t1, t0, rt, ctx);
2351 break;
2352 #endif
2353 case OPC_SC:
2354 case R6_OPC_SC:
2355 save_cpu_state(ctx, 1);
2356 op_st_sc(t1, t0, rt, ctx);
2357 break;
2358 }
2359 tcg_temp_free(t1);
2360 tcg_temp_free(t0);
2361 }
2362
2363 /* Load and store */
2364 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
2365 int base, int16_t offset)
2366 {
2367 TCGv t0 = tcg_temp_new();
2368
2369 gen_base_offset_addr(ctx, t0, base, offset);
2370 /* Don't do NOP if destination is zero: we must perform the actual
2371 memory access. */
2372 switch (opc) {
2373 case OPC_LWC1:
2374 {
2375 TCGv_i32 fp0 = tcg_temp_new_i32();
2376 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
2377 ctx->default_tcg_memop_mask);
2378 gen_store_fpr32(ctx, fp0, ft);
2379 tcg_temp_free_i32(fp0);
2380 }
2381 break;
2382 case OPC_SWC1:
2383 {
2384 TCGv_i32 fp0 = tcg_temp_new_i32();
2385 gen_load_fpr32(ctx, fp0, ft);
2386 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
2387 ctx->default_tcg_memop_mask);
2388 tcg_temp_free_i32(fp0);
2389 }
2390 break;
2391 case OPC_LDC1:
2392 {
2393 TCGv_i64 fp0 = tcg_temp_new_i64();
2394 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2395 ctx->default_tcg_memop_mask);
2396 gen_store_fpr64(ctx, fp0, ft);
2397 tcg_temp_free_i64(fp0);
2398 }
2399 break;
2400 case OPC_SDC1:
2401 {
2402 TCGv_i64 fp0 = tcg_temp_new_i64();
2403 gen_load_fpr64(ctx, fp0, ft);
2404 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
2405 ctx->default_tcg_memop_mask);
2406 tcg_temp_free_i64(fp0);
2407 }
2408 break;
2409 default:
2410 MIPS_INVAL("flt_ldst");
2411 generate_exception(ctx, EXCP_RI);
2412 goto out;
2413 }
2414 out:
2415 tcg_temp_free(t0);
2416 }
2417
2418 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
2419 int rs, int16_t imm)
2420 {
2421 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2422 check_cp1_enabled(ctx);
2423 switch (op) {
2424 case OPC_LDC1:
2425 case OPC_SDC1:
2426 check_insn(ctx, ISA_MIPS2);
2427 /* Fallthrough */
2428 default:
2429 gen_flt_ldst(ctx, op, rt, rs, imm);
2430 }
2431 } else {
2432 generate_exception_err(ctx, EXCP_CpU, 1);
2433 }
2434 }
2435
2436 /* Arithmetic with immediate operand */
2437 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
2438 int rt, int rs, int16_t imm)
2439 {
2440 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2441
2442 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
2443 /* If no destination, treat it as a NOP.
2444 For addi, we must generate the overflow exception when needed. */
2445 return;
2446 }
2447 switch (opc) {
2448 case OPC_ADDI:
2449 {
2450 TCGv t0 = tcg_temp_local_new();
2451 TCGv t1 = tcg_temp_new();
2452 TCGv t2 = tcg_temp_new();
2453 TCGLabel *l1 = gen_new_label();
2454
2455 gen_load_gpr(t1, rs);
2456 tcg_gen_addi_tl(t0, t1, uimm);
2457 tcg_gen_ext32s_tl(t0, t0);
2458
2459 tcg_gen_xori_tl(t1, t1, ~uimm);
2460 tcg_gen_xori_tl(t2, t0, uimm);
2461 tcg_gen_and_tl(t1, t1, t2);
2462 tcg_temp_free(t2);
2463 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2464 tcg_temp_free(t1);
2465 /* operands of same sign, result different sign */
2466 generate_exception(ctx, EXCP_OVERFLOW);
2467 gen_set_label(l1);
2468 tcg_gen_ext32s_tl(t0, t0);
2469 gen_store_gpr(t0, rt);
2470 tcg_temp_free(t0);
2471 }
2472 break;
2473 case OPC_ADDIU:
2474 if (rs != 0) {
2475 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2476 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2477 } else {
2478 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2479 }
2480 break;
2481 #if defined(TARGET_MIPS64)
2482 case OPC_DADDI:
2483 {
2484 TCGv t0 = tcg_temp_local_new();
2485 TCGv t1 = tcg_temp_new();
2486 TCGv t2 = tcg_temp_new();
2487 TCGLabel *l1 = gen_new_label();
2488
2489 gen_load_gpr(t1, rs);
2490 tcg_gen_addi_tl(t0, t1, uimm);
2491
2492 tcg_gen_xori_tl(t1, t1, ~uimm);
2493 tcg_gen_xori_tl(t2, t0, uimm);
2494 tcg_gen_and_tl(t1, t1, t2);
2495 tcg_temp_free(t2);
2496 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2497 tcg_temp_free(t1);
2498 /* operands of same sign, result different sign */
2499 generate_exception(ctx, EXCP_OVERFLOW);
2500 gen_set_label(l1);
2501 gen_store_gpr(t0, rt);
2502 tcg_temp_free(t0);
2503 }
2504 break;
2505 case OPC_DADDIU:
2506 if (rs != 0) {
2507 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2508 } else {
2509 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2510 }
2511 break;
2512 #endif
2513 }
2514 }
2515
2516 /* Logic with immediate operand */
2517 static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
2518 int rt, int rs, int16_t imm)
2519 {
2520 target_ulong uimm;
2521
2522 if (rt == 0) {
2523 /* If no destination, treat it as a NOP. */
2524 return;
2525 }
2526 uimm = (uint16_t)imm;
2527 switch (opc) {
2528 case OPC_ANDI:
2529 if (likely(rs != 0))
2530 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2531 else
2532 tcg_gen_movi_tl(cpu_gpr[rt], 0);
2533 break;
2534 case OPC_ORI:
2535 if (rs != 0)
2536 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2537 else
2538 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2539 break;
2540 case OPC_XORI:
2541 if (likely(rs != 0))
2542 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2543 else
2544 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2545 break;
2546 case OPC_LUI:
2547 if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
2548 /* OPC_AUI */
2549 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
2550 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2551 } else {
2552 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
2553 }
2554 break;
2555
2556 default:
2557 break;
2558 }
2559 }
2560
2561 /* Set on less than with immediate operand */
2562 static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
2563 int rt, int rs, int16_t imm)
2564 {
2565 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2566 TCGv t0;
2567
2568 if (rt == 0) {
2569 /* If no destination, treat it as a NOP. */
2570 return;
2571 }
2572 t0 = tcg_temp_new();
2573 gen_load_gpr(t0, rs);
2574 switch (opc) {
2575 case OPC_SLTI:
2576 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
2577 break;
2578 case OPC_SLTIU:
2579 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
2580 break;
2581 }
2582 tcg_temp_free(t0);
2583 }
2584
2585 /* Shifts with immediate operand */
2586 static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
2587 int rt, int rs, int16_t imm)
2588 {
2589 target_ulong uimm = ((uint16_t)imm) & 0x1f;
2590 TCGv t0;
2591
2592 if (rt == 0) {
2593 /* If no destination, treat it as a NOP. */
2594 return;
2595 }
2596
2597 t0 = tcg_temp_new();
2598 gen_load_gpr(t0, rs);
2599 switch (opc) {
2600 case OPC_SLL:
2601 tcg_gen_shli_tl(t0, t0, uimm);
2602 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2603 break;
2604 case OPC_SRA:
2605 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2606 break;
2607 case OPC_SRL:
2608 if (uimm != 0) {
2609 tcg_gen_ext32u_tl(t0, t0);
2610 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2611 } else {
2612 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2613 }
2614 break;
2615 case OPC_ROTR:
2616 if (uimm != 0) {
2617 TCGv_i32 t1 = tcg_temp_new_i32();
2618
2619 tcg_gen_trunc_tl_i32(t1, t0);
2620 tcg_gen_rotri_i32(t1, t1, uimm);
2621 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
2622 tcg_temp_free_i32(t1);
2623 } else {
2624 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2625 }
2626 break;
2627 #if defined(TARGET_MIPS64)
2628 case OPC_DSLL:
2629 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
2630 break;
2631 case OPC_DSRA:
2632 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2633 break;
2634 case OPC_DSRL:
2635 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2636 break;
2637 case OPC_DROTR:
2638 if (uimm != 0) {
2639 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
2640 } else {
2641 tcg_gen_mov_tl(cpu_gpr[rt], t0);
2642 }
2643 break;
2644 case OPC_DSLL32:
2645 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
2646 break;
2647 case OPC_DSRA32:
2648 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
2649 break;
2650 case OPC_DSRL32:
2651 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
2652 break;
2653 case OPC_DROTR32:
2654 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
2655 break;
2656 #endif
2657 }
2658 tcg_temp_free(t0);
2659 }
2660
2661 /* Arithmetic */
2662 static void gen_arith(DisasContext *ctx, uint32_t opc,
2663 int rd, int rs, int rt)
2664 {
2665 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
2666 && opc != OPC_DADD && opc != OPC_DSUB) {
2667 /* If no destination, treat it as a NOP.
2668 For add & sub, we must generate the overflow exception when needed. */
2669 return;
2670 }
2671
2672 switch (opc) {
2673 case OPC_ADD:
2674 {
2675 TCGv t0 = tcg_temp_local_new();
2676 TCGv t1 = tcg_temp_new();
2677 TCGv t2 = tcg_temp_new();
2678 TCGLabel *l1 = gen_new_label();
2679
2680 gen_load_gpr(t1, rs);
2681 gen_load_gpr(t2, rt);
2682 tcg_gen_add_tl(t0, t1, t2);
2683 tcg_gen_ext32s_tl(t0, t0);
2684 tcg_gen_xor_tl(t1, t1, t2);
2685 tcg_gen_xor_tl(t2, t0, t2);
2686 tcg_gen_andc_tl(t1, t2, t1);
2687 tcg_temp_free(t2);
2688 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2689 tcg_temp_free(t1);
2690 /* operands of same sign, result different sign */
2691 generate_exception(ctx, EXCP_OVERFLOW);
2692 gen_set_label(l1);
2693 gen_store_gpr(t0, rd);
2694 tcg_temp_free(t0);
2695 }
2696 break;
2697 case OPC_ADDU:
2698 if (rs != 0 && rt != 0) {
2699 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2700 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2701 } else if (rs == 0 && rt != 0) {
2702 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2703 } else if (rs != 0 && rt == 0) {
2704 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2705 } else {
2706 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2707 }
2708 break;
2709 case OPC_SUB:
2710 {
2711 TCGv t0 = tcg_temp_local_new();
2712 TCGv t1 = tcg_temp_new();
2713 TCGv t2 = tcg_temp_new();
2714 TCGLabel *l1 = gen_new_label();
2715
2716 gen_load_gpr(t1, rs);
2717 gen_load_gpr(t2, rt);
2718 tcg_gen_sub_tl(t0, t1, t2);
2719 tcg_gen_ext32s_tl(t0, t0);
2720 tcg_gen_xor_tl(t2, t1, t2);
2721 tcg_gen_xor_tl(t1, t0, t1);
2722 tcg_gen_and_tl(t1, t1, t2);
2723 tcg_temp_free(t2);
2724 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2725 tcg_temp_free(t1);
2726 /* operands of different sign, first operand and result different sign */
2727 generate_exception(ctx, EXCP_OVERFLOW);
2728 gen_set_label(l1);
2729 gen_store_gpr(t0, rd);
2730 tcg_temp_free(t0);
2731 }
2732 break;
2733 case OPC_SUBU:
2734 if (rs != 0 && rt != 0) {
2735 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2736 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2737 } else if (rs == 0 && rt != 0) {
2738 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2739 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2740 } else if (rs != 0 && rt == 0) {
2741 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2742 } else {
2743 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2744 }
2745 break;
2746 #if defined(TARGET_MIPS64)
2747 case OPC_DADD:
2748 {
2749 TCGv t0 = tcg_temp_local_new();
2750 TCGv t1 = tcg_temp_new();
2751 TCGv t2 = tcg_temp_new();
2752 TCGLabel *l1 = gen_new_label();
2753
2754 gen_load_gpr(t1, rs);
2755 gen_load_gpr(t2, rt);
2756 tcg_gen_add_tl(t0, t1, t2);
2757 tcg_gen_xor_tl(t1, t1, t2);
2758 tcg_gen_xor_tl(t2, t0, t2);
2759 tcg_gen_andc_tl(t1, t2, t1);
2760 tcg_temp_free(t2);
2761 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2762 tcg_temp_free(t1);
2763 /* operands of same sign, result different sign */
2764 generate_exception(ctx, EXCP_OVERFLOW);
2765 gen_set_label(l1);
2766 gen_store_gpr(t0, rd);
2767 tcg_temp_free(t0);
2768 }
2769 break;
2770 case OPC_DADDU:
2771 if (rs != 0 && rt != 0) {
2772 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2773 } else if (rs == 0 && rt != 0) {
2774 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2775 } else if (rs != 0 && rt == 0) {
2776 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2777 } else {
2778 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2779 }
2780 break;
2781 case OPC_DSUB:
2782 {
2783 TCGv t0 = tcg_temp_local_new();
2784 TCGv t1 = tcg_temp_new();
2785 TCGv t2 = tcg_temp_new();
2786 TCGLabel *l1 = gen_new_label();
2787
2788 gen_load_gpr(t1, rs);
2789 gen_load_gpr(t2, rt);
2790 tcg_gen_sub_tl(t0, t1, t2);
2791 tcg_gen_xor_tl(t2, t1, t2);
2792 tcg_gen_xor_tl(t1, t0, t1);
2793 tcg_gen_and_tl(t1, t1, t2);
2794 tcg_temp_free(t2);
2795 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2796 tcg_temp_free(t1);
2797 /* operands of different sign, first operand and result different sign */
2798 generate_exception(ctx, EXCP_OVERFLOW);
2799 gen_set_label(l1);
2800 gen_store_gpr(t0, rd);
2801 tcg_temp_free(t0);
2802 }
2803 break;
2804 case OPC_DSUBU:
2805 if (rs != 0 && rt != 0) {
2806 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2807 } else if (rs == 0 && rt != 0) {
2808 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2809 } else if (rs != 0 && rt == 0) {
2810 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2811 } else {
2812 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2813 }
2814 break;
2815 #endif
2816 case OPC_MUL:
2817 if (likely(rs != 0 && rt != 0)) {
2818 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2819 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2820 } else {
2821 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2822 }
2823 break;
2824 }
2825 }
2826
2827 /* Conditional move */
2828 static void gen_cond_move(DisasContext *ctx, uint32_t opc,
2829 int rd, int rs, int rt)
2830 {
2831 TCGv t0, t1, t2;
2832
2833 if (rd == 0) {
2834 /* If no destination, treat it as a NOP. */
2835 return;
2836 }
2837
2838 t0 = tcg_temp_new();
2839 gen_load_gpr(t0, rt);
2840 t1 = tcg_const_tl(0);
2841 t2 = tcg_temp_new();
2842 gen_load_gpr(t2, rs);
2843 switch (opc) {
2844 case OPC_MOVN:
2845 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2846 break;
2847 case OPC_MOVZ:
2848 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2849 break;
2850 case OPC_SELNEZ:
2851 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
2852 break;
2853 case OPC_SELEQZ:
2854 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
2855 break;
2856 }
2857 tcg_temp_free(t2);
2858 tcg_temp_free(t1);
2859 tcg_temp_free(t0);
2860 }
2861
2862 /* Logic */
2863 static void gen_logic(DisasContext *ctx, uint32_t opc,
2864 int rd, int rs, int rt)
2865 {
2866 if (rd == 0) {
2867 /* If no destination, treat it as a NOP. */
2868 return;
2869 }
2870
2871 switch (opc) {
2872 case OPC_AND:
2873 if (likely(rs != 0 && rt != 0)) {
2874 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2875 } else {
2876 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2877 }
2878 break;
2879 case OPC_NOR:
2880 if (rs != 0 && rt != 0) {
2881 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2882 } else if (rs == 0 && rt != 0) {
2883 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
2884 } else if (rs != 0 && rt == 0) {
2885 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
2886 } else {
2887 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
2888 }
2889 break;
2890 case OPC_OR:
2891 if (likely(rs != 0 && rt != 0)) {
2892 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2893 } else if (rs == 0 && rt != 0) {
2894 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2895 } else if (rs != 0 && rt == 0) {
2896 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2897 } else {
2898 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2899 }
2900 break;
2901 case OPC_XOR:
2902 if (likely(rs != 0 && rt != 0)) {
2903 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2904 } else if (rs == 0 && rt != 0) {
2905 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2906 } else if (rs != 0 && rt == 0) {
2907 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2908 } else {
2909 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2910 }
2911 break;
2912 }
2913 }
2914
2915 /* Set on lower than */
2916 static void gen_slt(DisasContext *ctx, uint32_t opc,
2917 int rd, int rs, int rt)
2918 {
2919 TCGv t0, t1;
2920
2921 if (rd == 0) {
2922 /* If no destination, treat it as a NOP. */
2923 return;
2924 }
2925
2926 t0 = tcg_temp_new();
2927 t1 = tcg_temp_new();
2928 gen_load_gpr(t0, rs);
2929 gen_load_gpr(t1, rt);
2930 switch (opc) {
2931 case OPC_SLT:
2932 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
2933 break;
2934 case OPC_SLTU:
2935 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
2936 break;
2937 }
2938 tcg_temp_free(t0);
2939 tcg_temp_free(t1);
2940 }
2941
2942 /* Shifts */
2943 static void gen_shift(DisasContext *ctx, uint32_t opc,
2944 int rd, int rs, int rt)
2945 {
2946 TCGv t0, t1;
2947
2948 if (rd == 0) {
2949 /* If no destination, treat it as a NOP.
2950 For add & sub, we must generate the overflow exception when needed. */
2951 return;
2952 }
2953
2954 t0 = tcg_temp_new();
2955 t1 = tcg_temp_new();
2956 gen_load_gpr(t0, rs);
2957 gen_load_gpr(t1, rt);
2958 switch (opc) {
2959 case OPC_SLLV:
2960 tcg_gen_andi_tl(t0, t0, 0x1f);
2961 tcg_gen_shl_tl(t0, t1, t0);
2962 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2963 break;
2964 case OPC_SRAV:
2965 tcg_gen_andi_tl(t0, t0, 0x1f);
2966 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2967 break;
2968 case OPC_SRLV:
2969 tcg_gen_ext32u_tl(t1, t1);
2970 tcg_gen_andi_tl(t0, t0, 0x1f);
2971 tcg_gen_shr_tl(t0, t1, t0);
2972 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2973 break;
2974 case OPC_ROTRV:
2975 {
2976 TCGv_i32 t2 = tcg_temp_new_i32();
2977 TCGv_i32 t3 = tcg_temp_new_i32();
2978
2979 tcg_gen_trunc_tl_i32(t2, t0);
2980 tcg_gen_trunc_tl_i32(t3, t1);
2981 tcg_gen_andi_i32(t2, t2, 0x1f);
2982 tcg_gen_rotr_i32(t2, t3, t2);
2983 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
2984 tcg_temp_free_i32(t2);
2985 tcg_temp_free_i32(t3);
2986 }
2987 break;
2988 #if defined(TARGET_MIPS64)
2989 case OPC_DSLLV:
2990 tcg_gen_andi_tl(t0, t0, 0x3f);
2991 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
2992 break;
2993 case OPC_DSRAV:
2994 tcg_gen_andi_tl(t0, t0, 0x3f);
2995 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2996 break;
2997 case OPC_DSRLV:
2998 tcg_gen_andi_tl(t0, t0, 0x3f);
2999 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
3000 break;
3001 case OPC_DROTRV:
3002 tcg_gen_andi_tl(t0, t0, 0x3f);
3003 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
3004 break;
3005 #endif
3006 }
3007 tcg_temp_free(t0);
3008 tcg_temp_free(t1);
3009 }
3010
3011 /* Arithmetic on HI/LO registers */
3012 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
3013 {
3014 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
3015 /* Treat as NOP. */
3016 return;
3017 }
3018
3019 if (acc != 0) {
3020 check_dsp(ctx);
3021 }
3022
3023 switch (opc) {
3024 case OPC_MFHI:
3025 #if defined(TARGET_MIPS64)
3026 if (acc != 0) {
3027 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
3028 } else
3029 #endif
3030 {
3031 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
3032 }
3033 break;
3034 case OPC_MFLO:
3035 #if defined(TARGET_MIPS64)
3036 if (acc != 0) {
3037 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
3038 } else
3039 #endif
3040 {
3041 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
3042 }
3043 break;
3044 case OPC_MTHI:
3045 if (reg != 0) {
3046 #if defined(TARGET_MIPS64)
3047 if (acc != 0) {
3048 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
3049 } else
3050 #endif
3051 {
3052 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
3053 }
3054 } else {
3055 tcg_gen_movi_tl(cpu_HI[acc], 0);
3056 }
3057 break;
3058 case OPC_MTLO:
3059 if (reg != 0) {
3060 #if defined(TARGET_MIPS64)
3061 if (acc != 0) {
3062 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
3063 } else
3064 #endif
3065 {
3066 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
3067 }
3068 } else {
3069 tcg_gen_movi_tl(cpu_LO[acc], 0);
3070 }
3071 break;
3072 }
3073 }
3074
3075 static inline void gen_r6_ld(target_long addr, int reg, int memidx,
3076 TCGMemOp memop)
3077 {
3078 TCGv t0 = tcg_const_tl(addr);
3079 tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
3080 gen_store_gpr(t0, reg);
3081 tcg_temp_free(t0);
3082 }
3083
3084 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
3085 int rs)
3086 {
3087 target_long offset;
3088 target_long addr;
3089
3090 switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
3091 case OPC_ADDIUPC:
3092 if (rs != 0) {
3093 offset = sextract32(ctx->opcode << 2, 0, 21);
3094 addr = addr_add(ctx, pc, offset);
3095 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3096 }
3097 break;
3098 case R6_OPC_LWPC:
3099 offset = sextract32(ctx->opcode << 2, 0, 21);
3100 addr = addr_add(ctx, pc, offset);
3101 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
3102 break;
3103 #if defined(TARGET_MIPS64)
3104 case OPC_LWUPC:
3105 check_mips_64(ctx);
3106 offset = sextract32(ctx->opcode << 2, 0, 21);
3107 addr = addr_add(ctx, pc, offset);
3108 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
3109 break;
3110 #endif
3111 default:
3112 switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
3113 case OPC_AUIPC:
3114 if (rs != 0) {
3115 offset = sextract32(ctx->opcode, 0, 16) << 16;
3116 addr = addr_add(ctx, pc, offset);
3117 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3118 }
3119 break;
3120 case OPC_ALUIPC:
3121 if (rs != 0) {
3122 offset = sextract32(ctx->opcode, 0, 16) << 16;
3123 addr = ~0xFFFF & addr_add(ctx, pc, offset);
3124 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3125 }
3126 break;
3127 #if defined(TARGET_MIPS64)
3128 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
3129 case R6_OPC_LDPC + (1 << 16):
3130 case R6_OPC_LDPC + (2 << 16):
3131 case R6_OPC_LDPC + (3 << 16):
3132 check_mips_64(ctx);
3133 offset = sextract32(ctx->opcode << 3, 0, 21);
3134 addr = addr_add(ctx, (pc & ~0x7), offset);
3135 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEQ);
3136 break;
3137 #endif
3138 default:
3139 MIPS_INVAL("OPC_PCREL");
3140 generate_exception(ctx, EXCP_RI);
3141 break;
3142 }
3143 break;
3144 }
3145 }
3146
3147 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
3148 {
3149 TCGv t0, t1;
3150
3151 if (rd == 0) {
3152 /* Treat as NOP. */
3153 return;
3154 }
3155
3156 t0 = tcg_temp_new();
3157 t1 = tcg_temp_new();
3158
3159 gen_load_gpr(t0, rs);
3160 gen_load_gpr(t1, rt);
3161
3162 switch (opc) {
3163 case R6_OPC_DIV:
3164 {
3165 TCGv t2 = tcg_temp_new();
3166 TCGv t3 = tcg_temp_new();
3167 tcg_gen_ext32s_tl(t0, t0);
3168 tcg_gen_ext32s_tl(t1, t1);
3169 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3170 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3171 tcg_gen_and_tl(t2, t2, t3);
3172 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3173 tcg_gen_or_tl(t2, t2, t3);
3174 tcg_gen_movi_tl(t3, 0);
3175 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3176 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3177 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3178 tcg_temp_free(t3);
3179 tcg_temp_free(t2);
3180 }
3181 break;
3182 case R6_OPC_MOD:
3183 {
3184 TCGv t2 = tcg_temp_new();
3185 TCGv t3 = tcg_temp_new();
3186 tcg_gen_ext32s_tl(t0, t0);
3187 tcg_gen_ext32s_tl(t1, t1);
3188 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3189 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3190 tcg_gen_and_tl(t2, t2, t3);
3191 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3192 tcg_gen_or_tl(t2, t2, t3);
3193 tcg_gen_movi_tl(t3, 0);
3194 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3195 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3196 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3197 tcg_temp_free(t3);
3198 tcg_temp_free(t2);
3199 }
3200 break;
3201 case R6_OPC_DIVU:
3202 {
3203 TCGv t2 = tcg_const_tl(0);
3204 TCGv t3 = tcg_const_tl(1);
3205 tcg_gen_ext32u_tl(t0, t0);
3206 tcg_gen_ext32u_tl(t1, t1);
3207 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3208 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3209 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3210 tcg_temp_free(t3);
3211 tcg_temp_free(t2);
3212 }
3213 break;
3214 case R6_OPC_MODU:
3215 {
3216 TCGv t2 = tcg_const_tl(0);
3217 TCGv t3 = tcg_const_tl(1);
3218 tcg_gen_ext32u_tl(t0, t0);
3219 tcg_gen_ext32u_tl(t1, t1);
3220 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3221 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3222 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3223 tcg_temp_free(t3);
3224 tcg_temp_free(t2);
3225 }
3226 break;
3227 case R6_OPC_MUL:
3228 {
3229 TCGv_i32 t2 = tcg_temp_new_i32();
3230 TCGv_i32 t3 = tcg_temp_new_i32();
3231 tcg_gen_trunc_tl_i32(t2, t0);
3232 tcg_gen_trunc_tl_i32(t3, t1);
3233 tcg_gen_mul_i32(t2, t2, t3);
3234 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3235 tcg_temp_free_i32(t2);
3236 tcg_temp_free_i32(t3);
3237 }
3238 break;
3239 case R6_OPC_MUH:
3240 {
3241 TCGv_i32 t2 = tcg_temp_new_i32();
3242 TCGv_i32 t3 = tcg_temp_new_i32();
3243 tcg_gen_trunc_tl_i32(t2, t0);
3244 tcg_gen_trunc_tl_i32(t3, t1);
3245 tcg_gen_muls2_i32(t2, t3, t2, t3);
3246 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3247 tcg_temp_free_i32(t2);
3248 tcg_temp_free_i32(t3);
3249 }
3250 break;
3251 case R6_OPC_MULU:
3252 {
3253 TCGv_i32 t2 = tcg_temp_new_i32();
3254 TCGv_i32 t3 = tcg_temp_new_i32();
3255 tcg_gen_trunc_tl_i32(t2, t0);
3256 tcg_gen_trunc_tl_i32(t3, t1);
3257 tcg_gen_mul_i32(t2, t2, t3);
3258 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3259 tcg_temp_free_i32(t2);
3260 tcg_temp_free_i32(t3);
3261 }
3262 break;
3263 case R6_OPC_MUHU:
3264 {
3265 TCGv_i32 t2 = tcg_temp_new_i32();
3266 TCGv_i32 t3 = tcg_temp_new_i32();
3267 tcg_gen_trunc_tl_i32(t2, t0);
3268 tcg_gen_trunc_tl_i32(t3, t1);
3269 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3270 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3271 tcg_temp_free_i32(t2);
3272 tcg_temp_free_i32(t3);
3273 }
3274 break;
3275 #if defined(TARGET_MIPS64)
3276 case R6_OPC_DDIV:
3277 {
3278 TCGv t2 = tcg_temp_new();
3279 TCGv t3 = tcg_temp_new();
3280 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3281 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3282 tcg_gen_and_tl(t2, t2, t3);
3283 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3284 tcg_gen_or_tl(t2, t2, t3);
3285 tcg_gen_movi_tl(t3, 0);
3286 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3287 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3288 tcg_temp_free(t3);
3289 tcg_temp_free(t2);
3290 }
3291 break;
3292 case R6_OPC_DMOD:
3293 {
3294 TCGv t2 = tcg_temp_new();
3295 TCGv t3 = tcg_temp_new();
3296 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3297 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3298 tcg_gen_and_tl(t2, t2, t3);
3299 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3300 tcg_gen_or_tl(t2, t2, t3);
3301 tcg_gen_movi_tl(t3, 0);
3302 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3303 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3304 tcg_temp_free(t3);
3305 tcg_temp_free(t2);
3306 }
3307 break;
3308 case R6_OPC_DDIVU:
3309 {
3310 TCGv t2 = tcg_const_tl(0);
3311 TCGv t3 = tcg_const_tl(1);
3312 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3313 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
3314 tcg_temp_free(t3);
3315 tcg_temp_free(t2);
3316 }
3317 break;
3318 case R6_OPC_DMODU:
3319 {
3320 TCGv t2 = tcg_const_tl(0);
3321 TCGv t3 = tcg_const_tl(1);
3322 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3323 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
3324 tcg_temp_free(t3);
3325 tcg_temp_free(t2);
3326 }
3327 break;
3328 case R6_OPC_DMUL:
3329 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3330 break;
3331 case R6_OPC_DMUH:
3332 {
3333 TCGv t2 = tcg_temp_new();
3334 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
3335 tcg_temp_free(t2);
3336 }
3337 break;
3338 case R6_OPC_DMULU:
3339 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3340 break;
3341 case R6_OPC_DMUHU:
3342 {
3343 TCGv t2 = tcg_temp_new();
3344 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
3345 tcg_temp_free(t2);
3346 }
3347 break;
3348 #endif
3349 default:
3350 MIPS_INVAL("r6 mul/div");
3351 generate_exception(ctx, EXCP_RI);
3352 goto out;
3353 }
3354 out:
3355 tcg_temp_free(t0);
3356 tcg_temp_free(t1);
3357 }
3358
3359 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
3360 int acc, int rs, int rt)
3361 {
3362 TCGv t0, t1;
3363
3364 t0 = tcg_temp_new();
3365 t1 = tcg_temp_new();
3366
3367 gen_load_gpr(t0, rs);
3368 gen_load_gpr(t1, rt);
3369
3370 if (acc != 0) {
3371 check_dsp(ctx);
3372 }
3373
3374 switch (opc) {
3375 case OPC_DIV:
3376 {
3377 TCGv t2 = tcg_temp_new();
3378 TCGv t3 = tcg_temp_new();
3379 tcg_gen_ext32s_tl(t0, t0);
3380 tcg_gen_ext32s_tl(t1, t1);
3381 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3382 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3383 tcg_gen_and_tl(t2, t2, t3);
3384 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3385 tcg_gen_or_tl(t2, t2, t3);
3386 tcg_gen_movi_tl(t3, 0);
3387 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3388 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3389 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3390 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3391 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3392 tcg_temp_free(t3);
3393 tcg_temp_free(t2);
3394 }
3395 break;
3396 case OPC_DIVU:
3397 {
3398 TCGv t2 = tcg_const_tl(0);
3399 TCGv t3 = tcg_const_tl(1);
3400 tcg_gen_ext32u_tl(t0, t0);
3401 tcg_gen_ext32u_tl(t1, t1);
3402 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3403 tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
3404 tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
3405 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3406 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3407 tcg_temp_free(t3);
3408 tcg_temp_free(t2);
3409 }
3410 break;
3411 case OPC_MULT:
3412 {
3413 TCGv_i32 t2 = tcg_temp_new_i32();
3414 TCGv_i32 t3 = tcg_temp_new_i32();
3415 tcg_gen_trunc_tl_i32(t2, t0);
3416 tcg_gen_trunc_tl_i32(t3, t1);
3417 tcg_gen_muls2_i32(t2, t3, t2, t3);
3418 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3419 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3420 tcg_temp_free_i32(t2);
3421 tcg_temp_free_i32(t3);
3422 }
3423 break;
3424 case OPC_MULTU:
3425 {
3426 TCGv_i32 t2 = tcg_temp_new_i32();
3427 TCGv_i32 t3 = tcg_temp_new_i32();
3428 tcg_gen_trunc_tl_i32(t2, t0);
3429 tcg_gen_trunc_tl_i32(t3, t1);
3430 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3431 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3432 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3433 tcg_temp_free_i32(t2);
3434 tcg_temp_free_i32(t3);
3435 }
3436 break;
3437 #if defined(TARGET_MIPS64)
3438 case OPC_DDIV:
3439 {
3440 TCGv t2 = tcg_temp_new();
3441 TCGv t3 = tcg_temp_new();
3442 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3443 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3444 tcg_gen_and_tl(t2, t2, t3);
3445 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3446 tcg_gen_or_tl(t2, t2, t3);
3447 tcg_gen_movi_tl(t3, 0);
3448 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
3449 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3450 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3451 tcg_temp_free(t3);
3452 tcg_temp_free(t2);
3453 }
3454 break;
3455 case OPC_DDIVU:
3456 {
3457 TCGv t2 = tcg_const_tl(0);
3458 TCGv t3 = tcg_const_tl(1);
3459 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3460 tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
3461 tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
3462 tcg_temp_free(t3);
3463 tcg_temp_free(t2);
3464 }
3465 break;
3466 case OPC_DMULT:
3467 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3468 break;
3469 case OPC_DMULTU:
3470 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3471 break;
3472 #endif
3473 case OPC_MADD:
3474 {
3475 TCGv_i64 t2 = tcg_temp_new_i64();
3476 TCGv_i64 t3 = tcg_temp_new_i64();
3477
3478 tcg_gen_ext_tl_i64(t2, t0);
3479 tcg_gen_ext_tl_i64(t3, t1);
3480 tcg_gen_mul_i64(t2, t2, t3);
3481 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3482 tcg_gen_add_i64(t2, t2, t3);
3483 tcg_temp_free_i64(t3);
3484 gen_move_low32(cpu_LO[acc], t2);
3485 gen_move_high32(cpu_HI[acc], t2);
3486 tcg_temp_free_i64(t2);
3487 }
3488 break;
3489 case OPC_MADDU:
3490 {
3491 TCGv_i64 t2 = tcg_temp_new_i64();
3492 TCGv_i64 t3 = tcg_temp_new_i64();
3493
3494 tcg_gen_ext32u_tl(t0, t0);
3495 tcg_gen_ext32u_tl(t1, t1);
3496 tcg_gen_extu_tl_i64(t2, t0);
3497 tcg_gen_extu_tl_i64(t3, t1);
3498 tcg_gen_mul_i64(t2, t2, t3);
3499 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3500 tcg_gen_add_i64(t2, t2, t3);
3501 tcg_temp_free_i64(t3);
3502 gen_move_low32(cpu_LO[acc], t2);
3503 gen_move_high32(cpu_HI[acc], t2);
3504 tcg_temp_free_i64(t2);
3505 }
3506 break;
3507 case OPC_MSUB:
3508 {
3509 TCGv_i64 t2 = tcg_temp_new_i64();
3510 TCGv_i64 t3 = tcg_temp_new_i64();
3511
3512 tcg_gen_ext_tl_i64(t2, t0);
3513 tcg_gen_ext_tl_i64(t3, t1);
3514 tcg_gen_mul_i64(t2, t2, t3);
3515 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3516 tcg_gen_sub_i64(t2, t3, t2);
3517 tcg_temp_free_i64(t3);
3518 gen_move_low32(cpu_LO[acc], t2);
3519 gen_move_high32(cpu_HI[acc], t2);
3520 tcg_temp_free_i64(t2);
3521 }
3522 break;
3523 case OPC_MSUBU:
3524 {
3525 TCGv_i64 t2 = tcg_temp_new_i64();
3526 TCGv_i64 t3 = tcg_temp_new_i64();
3527
3528 tcg_gen_ext32u_tl(t0, t0);
3529 tcg_gen_ext32u_tl(t1, t1);
3530 tcg_gen_extu_tl_i64(t2, t0);
3531 tcg_gen_extu_tl_i64(t3, t1);
3532 tcg_gen_mul_i64(t2, t2, t3);
3533 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3534 tcg_gen_sub_i64(t2, t3, t2);
3535 tcg_temp_free_i64(t3);
3536 gen_move_low32(cpu_LO[acc], t2);
3537 gen_move_high32(cpu_HI[acc], t2);
3538 tcg_temp_free_i64(t2);
3539 }
3540 break;
3541 default:
3542 MIPS_INVAL("mul/div");
3543 generate_exception(ctx, EXCP_RI);
3544 goto out;
3545 }
3546 out:
3547 tcg_temp_free(t0);
3548 tcg_temp_free(t1);
3549 }
3550
3551 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
3552 int rd, int rs, int rt)
3553 {
3554 TCGv t0 = tcg_temp_new();
3555 TCGv t1 = tcg_temp_new();
3556
3557 gen_load_gpr(t0, rs);
3558 gen_load_gpr(t1, rt);
3559
3560 switch (opc) {
3561 case OPC_VR54XX_MULS:
3562 gen_helper_muls(t0, cpu_env, t0, t1);
3563 break;
3564 case OPC_VR54XX_MULSU:
3565 gen_helper_mulsu(t0, cpu_env, t0, t1);
3566 break;
3567 case OPC_VR54XX_MACC:
3568 gen_helper_macc(t0, cpu_env, t0, t1);
3569 break;
3570 case OPC_VR54XX_MACCU:
3571 gen_helper_maccu(t0, cpu_env, t0, t1);
3572 break;
3573 case OPC_VR54XX_MSAC:
3574 gen_helper_msac(t0, cpu_env, t0, t1);
3575 break;
3576 case OPC_VR54XX_MSACU:
3577 gen_helper_msacu(t0, cpu_env, t0, t1);
3578 break;
3579 case OPC_VR54XX_MULHI:
3580 gen_helper_mulhi(t0, cpu_env, t0, t1);
3581 break;
3582 case OPC_VR54XX_MULHIU:
3583 gen_helper_mulhiu(t0, cpu_env, t0, t1);
3584 break;
3585 case OPC_VR54XX_MULSHI:
3586 gen_helper_mulshi(t0, cpu_env, t0, t1);
3587 break;
3588 case OPC_VR54XX_MULSHIU:
3589 gen_helper_mulshiu(t0, cpu_env, t0, t1);
3590 break;
3591 case OPC_VR54XX_MACCHI:
3592 gen_helper_macchi(t0, cpu_env, t0, t1);
3593 break;
3594 case OPC_VR54XX_MACCHIU:
3595 gen_helper_macchiu(t0, cpu_env, t0, t1);
3596 break;
3597 case OPC_VR54XX_MSACHI:
3598 gen_helper_msachi(t0, cpu_env, t0, t1);
3599 break;
3600 case OPC_VR54XX_MSACHIU:
3601 gen_helper_msachiu(t0, cpu_env, t0, t1);
3602 break;
3603 default:
3604 MIPS_INVAL("mul vr54xx");
3605 generate_exception(ctx, EXCP_RI);
3606 goto out;
3607 }
3608 gen_store_gpr(t0, rd);
3609
3610 out:
3611 tcg_temp_free(t0);
3612 tcg_temp_free(t1);
3613 }
3614
3615 static void gen_cl (DisasContext *ctx, uint32_t opc,
3616 int rd, int rs)
3617 {
3618 TCGv t0;
3619
3620 if (rd == 0) {
3621 /* Treat as NOP. */
3622 return;
3623 }
3624 t0 = tcg_temp_new();
3625 gen_load_gpr(t0, rs);
3626 switch (opc) {
3627 case OPC_CLO:
3628 case R6_OPC_CLO:
3629 gen_helper_clo(cpu_gpr[rd], t0);
3630 break;
3631 case OPC_CLZ:
3632 case R6_OPC_CLZ:
3633 gen_helper_clz(cpu_gpr[rd], t0);
3634 break;
3635 #if defined(TARGET_MIPS64)
3636 case OPC_DCLO:
3637 case R6_OPC_DCLO:
3638 gen_helper_dclo(cpu_gpr[rd], t0);
3639 break;
3640 case OPC_DCLZ:
3641 case R6_OPC_DCLZ:
3642 gen_helper_dclz(cpu_gpr[rd], t0);
3643 break;
3644 #endif
3645 }
3646 tcg_temp_free(t0);
3647 }
3648
3649 /* Godson integer instructions */
3650 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
3651 int rd, int rs, int rt)
3652 {
3653 TCGv t0, t1;
3654
3655 if (rd == 0) {
3656 /* Treat as NOP. */
3657 return;
3658 }
3659
3660 switch (opc) {
3661 case OPC_MULT_G_2E:
3662 case OPC_MULT_G_2F:
3663 case OPC_MULTU_G_2E:
3664 case OPC_MULTU_G_2F:
3665 #if defined(TARGET_MIPS64)
3666 case OPC_DMULT_G_2E:
3667 case OPC_DMULT_G_2F:
3668 case OPC_DMULTU_G_2E:
3669 case OPC_DMULTU_G_2F:
3670 #endif
3671 t0 = tcg_temp_new();
3672 t1 = tcg_temp_new();
3673 break;
3674 default:
3675 t0 = tcg_temp_local_new();
3676 t1 = tcg_temp_local_new();
3677 break;
3678 }
3679
3680 gen_load_gpr(t0, rs);
3681 gen_load_gpr(t1, rt);
3682
3683 switch (opc) {
3684 case OPC_MULT_G_2E:
3685 case OPC_MULT_G_2F:
3686 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3687 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3688 break;
3689 case OPC_MULTU_G_2E:
3690 case OPC_MULTU_G_2F:
3691 tcg_gen_ext32u_tl(t0, t0);
3692 tcg_gen_ext32u_tl(t1, t1);
3693 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3694 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3695 break;
3696 case OPC_DIV_G_2E:
3697 case OPC_DIV_G_2F:
3698 {
3699 TCGLabel *l1 = gen_new_label();
3700 TCGLabel *l2 = gen_new_label();
3701 TCGLabel *l3 = gen_new_label();
3702 tcg_gen_ext32s_tl(t0, t0);
3703 tcg_gen_ext32s_tl(t1, t1);
3704 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3705 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3706 tcg_gen_br(l3);
3707 gen_set_label(l1);
3708 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3709 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3710 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3711 tcg_gen_br(l3);
3712 gen_set_label(l2);
3713 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3714 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3715 gen_set_label(l3);
3716 }
3717 break;
3718 case OPC_DIVU_G_2E:
3719 case OPC_DIVU_G_2F:
3720 {
3721 TCGLabel *l1 = gen_new_label();
3722 TCGLabel *l2 = gen_new_label();
3723 tcg_gen_ext32u_tl(t0, t0);
3724 tcg_gen_ext32u_tl(t1, t1);
3725 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3726 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3727 tcg_gen_br(l2);
3728 gen_set_label(l1);
3729 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3730 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3731 gen_set_label(l2);
3732 }
3733 break;
3734 case OPC_MOD_G_2E:
3735 case OPC_MOD_G_2F:
3736 {
3737 TCGLabel *l1 = gen_new_label();
3738 TCGLabel *l2 = gen_new_label();
3739 TCGLabel *l3 = gen_new_label();
3740 tcg_gen_ext32u_tl(t0, t0);
3741 tcg_gen_ext32u_tl(t1, t1);
3742 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3743 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3744 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3745 gen_set_label(l1);
3746 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3747 tcg_gen_br(l3);
3748 gen_set_label(l2);
3749 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3750 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3751 gen_set_label(l3);
3752 }
3753 break;
3754 case OPC_MODU_G_2E:
3755 case OPC_MODU_G_2F:
3756 {
3757 TCGLabel *l1 = gen_new_label();
3758 TCGLabel *l2 = gen_new_label();
3759 tcg_gen_ext32u_tl(t0, t0);
3760 tcg_gen_ext32u_tl(t1, t1);
3761 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3762 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3763 tcg_gen_br(l2);
3764 gen_set_label(l1);
3765 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3766 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3767 gen_set_label(l2);
3768 }
3769 break;
3770 #if defined(TARGET_MIPS64)
3771 case OPC_DMULT_G_2E:
3772 case OPC_DMULT_G_2F:
3773 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3774 break;
3775 case OPC_DMULTU_G_2E:
3776 case OPC_DMULTU_G_2F:
3777 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3778 break;
3779 case OPC_DDIV_G_2E:
3780 case OPC_DDIV_G_2F:
3781 {
3782 TCGLabel *l1 = gen_new_label();
3783 TCGLabel *l2 = gen_new_label();
3784 TCGLabel *l3 = gen_new_label();
3785 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3786 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3787 tcg_gen_br(l3);
3788 gen_set_label(l1);
3789 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3790 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3791 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3792 tcg_gen_br(l3);
3793 gen_set_label(l2);
3794 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3795 gen_set_label(l3);
3796 }
3797 break;
3798 case OPC_DDIVU_G_2E:
3799 case OPC_DDIVU_G_2F:
3800 {
3801 TCGLabel *l1 = gen_new_label();
3802 TCGLabel *l2 = gen_new_label();
3803 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3804 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3805 tcg_gen_br(l2);
3806 gen_set_label(l1);
3807 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3808 gen_set_label(l2);
3809 }
3810 break;
3811 case OPC_DMOD_G_2E:
3812 case OPC_DMOD_G_2F:
3813 {
3814 TCGLabel *l1 = gen_new_label();
3815 TCGLabel *l2 = gen_new_label();
3816 TCGLabel *l3 = gen_new_label();
3817 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3818 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3819 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3820 gen_set_label(l1);
3821 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3822 tcg_gen_br(l3);
3823 gen_set_label(l2);
3824 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3825 gen_set_label(l3);
3826 }
3827 break;
3828 case OPC_DMODU_G_2E:
3829 case OPC_DMODU_G_2F:
3830 {
3831 TCGLabel *l1 = gen_new_label();
3832 TCGLabel *l2 = gen_new_label();
3833 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3834 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3835 tcg_gen_br(l2);
3836 gen_set_label(l1);
3837 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3838 gen_set_label(l2);
3839 }
3840 break;
3841 #endif
3842 }
3843
3844 tcg_temp_free(t0);
3845 tcg_temp_free(t1);
3846 }
3847
3848 /* Loongson multimedia instructions */
3849 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
3850 {
3851 uint32_t opc, shift_max;
3852 TCGv_i64 t0, t1;
3853
3854 opc = MASK_LMI(ctx->opcode);
3855 switch (opc) {
3856 case OPC_ADD_CP2:
3857 case OPC_SUB_CP2:
3858 case OPC_DADD_CP2:
3859 case OPC_DSUB_CP2:
3860 t0 = tcg_temp_local_new_i64();
3861 t1 = tcg_temp_local_new_i64();
3862 break;
3863 default:
3864 t0 = tcg_temp_new_i64();
3865 t1 = tcg_temp_new_i64();
3866 break;
3867 }
3868
3869 gen_load_fpr64(ctx, t0, rs);
3870 gen_load_fpr64(ctx, t1, rt);
3871
3872 #define LMI_HELPER(UP, LO) \
3873 case OPC_##UP: gen_helper_##LO(t0, t0, t1); break
3874 #define LMI_HELPER_1(UP, LO) \
3875 case OPC_##UP: gen_helper_##LO(t0, t0); break
3876 #define LMI_DIRECT(UP, LO, OP) \
3877 case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); break
3878
3879 switch (opc) {
3880 LMI_HELPER(PADDSH, paddsh);
3881 LMI_HELPER(PADDUSH, paddush);
3882 LMI_HELPER(PADDH, paddh);
3883 LMI_HELPER(PADDW, paddw);
3884 LMI_HELPER(PADDSB, paddsb);
3885 LMI_HELPER(PADDUSB, paddusb);
3886 LMI_HELPER(PADDB, paddb);
3887
3888 LMI_HELPER(PSUBSH, psubsh);
3889 LMI_HELPER(PSUBUSH, psubush);
3890 LMI_HELPER(PSUBH, psubh);
3891 LMI_HELPER(PSUBW, psubw);
3892 LMI_HELPER(PSUBSB, psubsb);
3893 LMI_HELPER(PSUBUSB, psubusb);
3894 LMI_HELPER(PSUBB, psubb);
3895
3896 LMI_HELPER(PSHUFH, pshufh);
3897 LMI_HELPER(PACKSSWH, packsswh);
3898 LMI_HELPER(PACKSSHB, packsshb);
3899 LMI_HELPER(PACKUSHB, packushb);
3900
3901 LMI_HELPER(PUNPCKLHW, punpcklhw);
3902 LMI_HELPER(PUNPCKHHW, punpckhhw);
3903 LMI_HELPER(PUNPCKLBH, punpcklbh);
3904 LMI_HELPER(PUNPCKHBH, punpckhbh);
3905 LMI_HELPER(PUNPCKLWD, punpcklwd);
3906 LMI_HELPER(PUNPCKHWD, punpckhwd);
3907
3908 LMI_HELPER(PAVGH, pavgh);
3909 LMI_HELPER(PAVGB, pavgb);
3910 LMI_HELPER(PMAXSH, pmaxsh);
3911 LMI_HELPER(PMINSH, pminsh);
3912 LMI_HELPER(PMAXUB, pmaxub);
3913 LMI_HELPER(PMINUB, pminub);
3914
3915 LMI_HELPER(PCMPEQW, pcmpeqw);
3916 LMI_HELPER(PCMPGTW, pcmpgtw);
3917 LMI_HELPER(PCMPEQH, pcmpeqh);
3918 LMI_HELPER(PCMPGTH, pcmpgth);
3919 LMI_HELPER(PCMPEQB, pcmpeqb);
3920 LMI_HELPER(PCMPGTB, pcmpgtb);
3921
3922 LMI_HELPER(PSLLW, psllw);
3923 LMI_HELPER(PSLLH, psllh);
3924 LMI_HELPER(PSRLW, psrlw);
3925 LMI_HELPER(PSRLH, psrlh);
3926 LMI_HELPER(PSRAW, psraw);
3927 LMI_HELPER(PSRAH, psrah);
3928
3929 LMI_HELPER(PMULLH, pmullh);
3930 LMI_HELPER(PMULHH, pmulhh);
3931 LMI_HELPER(PMULHUH, pmulhuh);
3932 LMI_HELPER(PMADDHW, pmaddhw);
3933
3934 LMI_HELPER(PASUBUB, pasubub);
3935 LMI_HELPER_1(BIADD, biadd);
3936 LMI_HELPER_1(PMOVMSKB, pmovmskb);
3937
3938 LMI_DIRECT(PADDD, paddd, add);
3939 LMI_DIRECT(PSUBD, psubd, sub);
3940 LMI_DIRECT(XOR_CP2, xor, xor);
3941 LMI_DIRECT(NOR_CP2, nor, nor);
3942 LMI_DIRECT(AND_CP2, and, and);
3943 LMI_DIRECT(PANDN, pandn, andc);
3944 LMI_DIRECT(OR, or, or);
3945
3946 case OPC_PINSRH_0:
3947 tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
3948 break;
3949 case OPC_PINSRH_1:
3950 tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
3951 break;
3952 case OPC_PINSRH_2:
3953 tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
3954 break;
3955 case OPC_PINSRH_3:
3956 tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
3957 break;
3958
3959 case OPC_PEXTRH:
3960 tcg_gen_andi_i64(t1, t1, 3);
3961 tcg_gen_shli_i64(t1, t1, 4);
3962 tcg_gen_shr_i64(t0, t0, t1);
3963 tcg_gen_ext16u_i64(t0, t0);
3964 break;
3965
3966 case OPC_ADDU_CP2:
3967 tcg_gen_add_i64(t0, t0, t1);
3968 tcg_gen_ext32s_i64(t0, t0);
3969 break;
3970 case OPC_SUBU_CP2:
3971 tcg_gen_sub_i64(t0, t0, t1);
3972 tcg_gen_ext32s_i64(t0, t0);
3973 break;
3974
3975 case OPC_SLL_CP2:
3976 shift_max = 32;
3977 goto do_shift;
3978 case OPC_SRL_CP2:
3979 shift_max = 32;
3980 goto do_shift;
3981 case OPC_SRA_CP2:
3982 shift_max = 32;
3983 goto do_shift;
3984 case OPC_DSLL_CP2:
3985 shift_max = 64;
3986 goto do_shift;
3987 case OPC_DSRL_CP2:
3988 shift_max = 64;
3989 goto do_shift;
3990 case OPC_DSRA_CP2:
3991 shift_max = 64;
3992 goto do_shift;
3993 do_shift:
3994 /* Make sure shift count isn't TCG undefined behaviour. */
3995 tcg_gen_andi_i64(t1, t1, shift_max - 1);
3996
3997 switch (opc) {
3998 case OPC_SLL_CP2:
3999 case OPC_DSLL_CP2:
4000 tcg_gen_shl_i64(t0, t0, t1);
4001 break;
4002 case OPC_SRA_CP2:
4003 case OPC_DSRA_CP2:
4004 /* Since SRA is UndefinedResult without sign-extended inputs,
4005 we can treat SRA and DSRA the same. */
4006 tcg_gen_sar_i64(t0, t0, t1);
4007 break;
4008 case OPC_SRL_CP2:
4009 /* We want to shift in zeros for SRL; zero-extend first. */
4010 tcg_gen_ext32u_i64(t0, t0);
4011 /* FALLTHRU */
4012 case OPC_DSRL_CP2:
4013 tcg_gen_shr_i64(t0, t0, t1);
4014 break;
4015 }
4016
4017 if (shift_max == 32) {
4018 tcg_gen_ext32s_i64(t0, t0);
4019 }
4020
4021 /* Shifts larger than MAX produce zero. */
4022 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
4023 tcg_gen_neg_i64(t1, t1);
4024 tcg_gen_and_i64(t0, t0, t1);
4025 break;
4026
4027 case OPC_ADD_CP2:
4028 case OPC_DADD_CP2:
4029 {
4030 TCGv_i64 t2 = tcg_temp_new_i64();
4031 TCGLabel *lab = gen_new_label();
4032
4033 tcg_gen_mov_i64(t2, t0);
4034 tcg_gen_add_i64(t0, t1, t2);
4035 if (opc == OPC_ADD_CP2) {
4036 tcg_gen_ext32s_i64(t0, t0);
4037 }
4038 tcg_gen_xor_i64(t1, t1, t2);
4039 tcg_gen_xor_i64(t2, t2, t0);
4040 tcg_gen_andc_i64(t1, t2, t1);
4041 tcg_temp_free_i64(t2);
4042 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4043 generate_exception(ctx, EXCP_OVERFLOW);
4044 gen_set_label(lab);
4045 break;
4046 }
4047
4048 case OPC_SUB_CP2:
4049 case OPC_DSUB_CP2:
4050 {
4051 TCGv_i64 t2 = tcg_temp_new_i64();
4052 TCGLabel *lab = gen_new_label();
4053
4054 tcg_gen_mov_i64(t2, t0);
4055 tcg_gen_sub_i64(t0, t1, t2);
4056 if (opc == OPC_SUB_CP2) {
4057 tcg_gen_ext32s_i64(t0, t0);
4058 }
4059 tcg_gen_xor_i64(t1, t1, t2);
4060 tcg_gen_xor_i64(t2, t2, t0);
4061 tcg_gen_and_i64(t1, t1, t2);
4062 tcg_temp_free_i64(t2);
4063 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4064 generate_exception(ctx, EXCP_OVERFLOW);
4065 gen_set_label(lab);
4066 break;
4067 }
4068
4069 case OPC_PMULUW:
4070 tcg_gen_ext32u_i64(t0, t0);
4071 tcg_gen_ext32u_i64(t1, t1);
4072 tcg_gen_mul_i64(t0, t0, t1);
4073 break;
4074
4075 case OPC_SEQU_CP2:
4076 case OPC_SEQ_CP2:
4077 case OPC_SLTU_CP2:
4078 case OPC_SLT_CP2:
4079 case OPC_SLEU_CP2:
4080 case OPC_SLE_CP2:
4081 /* ??? Document is unclear: Set FCC[CC]. Does that mean the
4082 FD field is the CC field? */
4083 default:
4084 MIPS_INVAL("loongson_cp2");
4085 generate_exception(ctx, EXCP_RI);
4086 return;
4087 }
4088
4089 #undef LMI_HELPER
4090 #undef LMI_DIRECT
4091
4092 gen_store_fpr64(ctx, t0, rd);
4093
4094 tcg_temp_free_i64(t0);
4095 tcg_temp_free_i64(t1);
4096 }
4097
4098 /* Traps */
4099 static void gen_trap (DisasContext *ctx, uint32_t opc,
4100 int rs, int rt, int16_t imm)
4101 {
4102 int cond;
4103 TCGv t0 = tcg_temp_new();
4104 TCGv t1 = tcg_temp_new();
4105
4106 cond = 0;
4107 /* Load needed operands */
4108 switch (opc) {
4109 case OPC_TEQ:
4110 case OPC_TGE:
4111 case OPC_TGEU:
4112 case OPC_TLT:
4113 case OPC_TLTU:
4114 case OPC_TNE:
4115 /* Compare two registers */
4116 if (rs != rt) {
4117 gen_load_gpr(t0, rs);
4118 gen_load_gpr(t1, rt);
4119 cond = 1;
4120 }
4121 break;
4122 case OPC_TEQI:
4123 case OPC_TGEI:
4124 case OPC_TGEIU:
4125 case OPC_TLTI:
4126 case OPC_TLTIU:
4127 case OPC_TNEI:
4128 /* Compare register to immediate */
4129 if (rs != 0 || imm != 0) {
4130 gen_load_gpr(t0, rs);
4131 tcg_gen_movi_tl(t1, (int32_t)imm);
4132 cond = 1;
4133 }
4134 break;
4135 }
4136 if (cond == 0) {
4137 switch (opc) {
4138 case OPC_TEQ: /* rs == rs */
4139 case OPC_TEQI: /* r0 == 0 */
4140 case OPC_TGE: /* rs >= rs */
4141 case OPC_TGEI: /* r0 >= 0 */
4142 case OPC_TGEU: /* rs >= rs unsigned */
4143 case OPC_TGEIU: /* r0 >= 0 unsigned */
4144 /* Always trap */
4145 generate_exception(ctx, EXCP_TRAP);
4146 break;
4147 case OPC_TLT: /* rs < rs */
4148 case OPC_TLTI: /* r0 < 0 */
4149 case OPC_TLTU: /* rs < rs unsigned */
4150 case OPC_TLTIU: /* r0 < 0 unsigned */
4151 case OPC_TNE: /* rs != rs */
4152 case OPC_TNEI: /* r0 != 0 */
4153 /* Never trap: treat as NOP. */
4154 break;
4155 }
4156 } else {
4157 TCGLabel *l1 = gen_new_label();
4158
4159 switch (opc) {
4160 case OPC_TEQ:
4161 case OPC_TEQI:
4162 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
4163 break;
4164 case OPC_TGE:
4165 case OPC_TGEI:
4166 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
4167 break;
4168 case OPC_TGEU:
4169 case OPC_TGEIU:
4170 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
4171 break;
4172 case OPC_TLT:
4173 case OPC_TLTI:
4174 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4175 break;
4176 case OPC_TLTU:
4177 case OPC_TLTIU:
4178 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
4179 break;
4180 case OPC_TNE:
4181 case OPC_TNEI:
4182 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
4183 break;
4184 }
4185 generate_exception(ctx, EXCP_TRAP);
4186 gen_set_label(l1);
4187 }
4188 tcg_temp_free(t0);
4189 tcg_temp_free(t1);
4190 }
4191
4192 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4193 {
4194 TranslationBlock *tb;
4195 tb = ctx->tb;
4196 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
4197 likely(!ctx->singlestep_enabled)) {
4198 tcg_gen_goto_tb(n);
4199 gen_save_pc(dest);
4200 tcg_gen_exit_tb((uintptr_t)tb + n);
4201 } else {
4202 gen_save_pc(dest);
4203 if (ctx->singlestep_enabled) {
4204 save_cpu_state(ctx, 0);
4205 gen_helper_0e0i(raise_exception, EXCP_DEBUG);
4206 }
4207 tcg_gen_exit_tb(0);
4208 }
4209 }
4210
4211 /* Branches (before delay slot) */
4212 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
4213 int insn_bytes,
4214 int rs, int rt, int32_t offset,
4215 int delayslot_size)
4216 {
4217 target_ulong btgt = -1;
4218 int blink = 0;
4219 int bcond_compute = 0;
4220 TCGv t0 = tcg_temp_new();
4221 TCGv t1 = tcg_temp_new();
4222
4223 if (ctx->hflags & MIPS_HFLAG_BMASK) {
4224 #ifdef MIPS_DEBUG_DISAS
4225 LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
4226 TARGET_FMT_lx "\n", ctx->pc);
4227 #endif
4228 generate_exception(ctx, EXCP_RI);
4229 goto out;
4230 }
4231
4232 /* Load needed operands */
4233 switch (opc) {
4234 case OPC_BEQ:
4235 case OPC_BEQL:
4236 case OPC_BNE:
4237 case OPC_BNEL:
4238 /* Compare two registers */
4239 if (rs != rt) {
4240 gen_load_gpr(t0, rs);
4241 gen_load_gpr(t1, rt);
4242 bcond_compute = 1;
4243 }
4244 btgt = ctx->pc + insn_bytes + offset;
4245 break;
4246 case OPC_BGEZ:
4247 case OPC_BGEZAL:
4248 case OPC_BGEZALL:
4249 case OPC_BGEZL:
4250 case OPC_BGTZ:
4251 case OPC_BGTZL:
4252 case OPC_BLEZ:
4253 case OPC_BLEZL:
4254 case OPC_BLTZ:
4255 case OPC_BLTZAL:
4256 case OPC_BLTZALL:
4257 case OPC_BLTZL:
4258 /* Compare to zero */
4259 if (rs != 0) {
4260 gen_load_gpr(t0, rs);
4261 bcond_compute = 1;
4262 }
4263 btgt = ctx->pc + insn_bytes + offset;
4264 break;
4265 case OPC_BPOSGE32:
4266 #if defined(TARGET_MIPS64)
4267 case OPC_BPOSGE64:
4268 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
4269 #else
4270 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
4271 #endif
4272 bcond_compute = 1;
4273 btgt = ctx->pc + insn_bytes + offset;
4274 break;
4275 case OPC_J:
4276 case OPC_JAL:
4277 case OPC_JALX:
4278 /* Jump to immediate */
4279 btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) | (uint32_t)offset;
4280 break;
4281 case OPC_JR:
4282 case OPC_JALR:
4283 /* Jump to register */
4284 if (offset != 0 && offset != 16) {
4285 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
4286 others are reserved. */
4287 MIPS_INVAL("jump hint");
4288 generate_exception(ctx, EXCP_RI);
4289 goto out;
4290 }
4291 gen_load_gpr(btarget, rs);
4292 break;
4293 default:
4294 MIPS_INVAL("branch/jump");
4295 generate_exception(ctx, EXCP_RI);
4296 goto out;
4297 }
4298 if (bcond_compute == 0) {
4299 /* No condition to be computed */
4300 switch (opc) {
4301 case OPC_BEQ: /* rx == rx */
4302 case OPC_BEQL: /* rx == rx likely */
4303 case OPC_BGEZ: /* 0 >= 0 */
4304 case OPC_BGEZL: /* 0 >= 0 likely */
4305 case OPC_BLEZ: /* 0 <= 0 */
4306 case OPC_BLEZL: /* 0 <= 0 likely */
4307 /* Always take */
4308 ctx->hflags |= MIPS_HFLAG_B;
4309 break;
4310 case OPC_BGEZAL: /* 0 >= 0 */
4311 case OPC_BGEZALL: /* 0 >= 0 likely */
4312 /* Always take and link */
4313 blink = 31;
4314 ctx->hflags |= MIPS_HFLAG_B;
4315 break;
4316 case OPC_BNE: /* rx != rx */
4317 case OPC_BGTZ: /* 0 > 0 */
4318 case OPC_BLTZ: /* 0 < 0 */
4319 /* Treat as NOP. */
4320 goto out;
4321 case OPC_BLTZAL: /* 0 < 0 */
4322 /* Handle as an unconditional branch to get correct delay
4323 slot checking. */
4324 blink = 31;
4325 btgt = ctx->pc + insn_bytes + delayslot_size;
4326 ctx->hflags |= MIPS_HFLAG_B;
4327 break;
4328 case OPC_BLTZALL: /* 0 < 0 likely */
4329 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
4330 /* Skip the instruction in the delay slot */
4331 ctx->pc += 4;
4332 goto out;
4333 case OPC_BNEL: /* rx != rx likely */
4334 case OPC_BGTZL: /* 0 > 0 likely */
4335 case OPC_BLTZL: /* 0 < 0 likely */
4336 /* Skip the instruction in the delay slot */
4337 ctx->pc += 4;
4338 goto out;
4339 case OPC_J:
4340 ctx->hflags |= MIPS_HFLAG_B;
4341 break;
4342 case OPC_JALX:
4343 ctx->hflags |= MIPS_HFLAG_BX;
4344 /* Fallthrough */
4345 case OPC_JAL:
4346 blink = 31;
4347 ctx->hflags |= MIPS_HFLAG_B;
4348 break;
4349 case OPC_JR:
4350 ctx->hflags |= MIPS_HFLAG_BR;
4351 break;
4352 case OPC_JALR:
4353 blink = rt;
4354 ctx->hflags |= MIPS_HFLAG_BR;
4355 break;
4356 default:
4357 MIPS_INVAL("branch/jump");
4358 generate_exception(ctx, EXCP_RI);
4359 goto out;
4360 }
4361 } else {
4362 switch (opc) {
4363 case OPC_BEQ:
4364 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4365 goto not_likely;
4366 case OPC_BEQL:
4367 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4368 goto likely;
4369 case OPC_BNE:
4370 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4371 goto not_likely;
4372 case OPC_BNEL:
4373 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4374 goto likely;
4375 case OPC_BGEZ:
4376 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4377 goto not_likely;
4378 case OPC_BGEZL:
4379 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4380 goto likely;
4381 case OPC_BGEZAL:
4382 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4383 blink = 31;
4384 goto not_likely;
4385 case OPC_BGEZALL:
4386 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4387 blink = 31;
4388 goto likely;
4389 case OPC_BGTZ:
4390 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4391 goto not_likely;
4392 case OPC_BGTZL:
4393 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4394 goto likely;
4395 case OPC_BLEZ:
4396 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4397 goto not_likely;
4398 case OPC_BLEZL:
4399 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4400 goto likely;
4401 case OPC_BLTZ:
4402 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4403 goto not_likely;
4404 case OPC_BLTZL:
4405 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4406 goto likely;
4407 case OPC_BPOSGE32:
4408 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
4409 goto not_likely;
4410 #if defined(TARGET_MIPS64)
4411 case OPC_BPOSGE64:
4412 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
4413 goto not_likely;
4414 #endif
4415 case OPC_BLTZAL:
4416 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4417 blink = 31;
4418 not_likely:
4419 ctx->hflags |= MIPS_HFLAG_BC;
4420 break;
4421 case OPC_BLTZALL:
4422 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4423 blink = 31;
4424 likely:
4425 ctx->hflags |= MIPS_HFLAG_BL;
4426 break;
4427 default:
4428 MIPS_INVAL("conditional branch/jump");
4429 generate_exception(ctx, EXCP_RI);
4430 goto out;
4431 }
4432 }
4433
4434 ctx->btarget = btgt;
4435
4436 switch (delayslot_size) {
4437 case 2:
4438 ctx->hflags |= MIPS_HFLAG_BDS16;
4439 break;
4440 case 4:
4441 ctx->hflags |= MIPS_HFLAG_BDS32;
4442 break;
4443 }
4444
4445 if (blink > 0) {
4446 int post_delay = insn_bytes + delayslot_size;
4447 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
4448
4449 tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + post_delay + lowbit);
4450 }
4451
4452 out:
4453 if (insn_bytes == 2)
4454 ctx->hflags |= MIPS_HFLAG_B16;
4455 tcg_temp_free(t0);
4456 tcg_temp_free(t1);
4457 }
4458
4459 /* special3 bitfield operations */
4460 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
4461 int rs, int lsb, int msb)
4462 {
4463 TCGv t0 = tcg_temp_new();
4464 TCGv t1 = tcg_temp_new();
4465
4466 gen_load_gpr(t1, rs);
4467 switch (opc) {
4468 case OPC_EXT:
4469 if (lsb + msb > 31) {
4470 goto fail;
4471 }
4472 tcg_gen_shri_tl(t0, t1, lsb);
4473 if (msb != 31) {
4474 tcg_gen_andi_tl(t0, t0, (1U << (msb + 1)) - 1);
4475 } else {
4476 tcg_gen_ext32s_tl(t0, t0);
4477 }
4478 break;
4479 #if defined(TARGET_MIPS64)
4480 case OPC_DEXTU:
4481 lsb += 32;
4482 goto do_dext;
4483 case OPC_DEXTM:
4484 msb += 32;
4485 goto do_dext;
4486 case OPC_DEXT:
4487 do_dext:
4488 if (lsb + msb > 63) {
4489 goto fail;
4490 }
4491 tcg_gen_shri_tl(t0, t1, lsb);
4492 if (msb != 63) {
4493 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
4494 }
4495 break;
4496 #endif
4497 case OPC_INS:
4498 if (lsb > msb) {
4499 goto fail;
4500 }
4501 gen_load_gpr(t0, rt);
4502 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4503 tcg_gen_ext32s_tl(t0, t0);
4504 break;
4505 #if defined(TARGET_MIPS64)
4506 case OPC_DINSU:
4507 lsb += 32;
4508 /* FALLTHRU */
4509 case OPC_DINSM:
4510 msb += 32;
4511 /* FALLTHRU */
4512 case OPC_DINS:
4513 if (lsb > msb) {
4514 goto fail;
4515 }
4516 gen_load_gpr(t0, rt);
4517 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4518 break;
4519 #endif
4520 default:
4521 fail:
4522 MIPS_INVAL("bitops");
4523 generate_exception(ctx, EXCP_RI);
4524 tcg_temp_free(t0);
4525 tcg_temp_free(t1);
4526 return;
4527 }
4528 gen_store_gpr(t0, rt);
4529 tcg_temp_free(t0);
4530 tcg_temp_free(t1);
4531 }
4532
4533 static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
4534 {
4535 TCGv t0;
4536
4537 if (rd == 0) {
4538 /* If no destination, treat it as a NOP. */
4539 return;
4540 }
4541
4542 t0 = tcg_temp_new();
4543 gen_load_gpr(t0, rt);
4544 switch (op2) {
4545 case OPC_WSBH:
4546 {
4547 TCGv t1 = tcg_temp_new();
4548
4549 tcg_gen_shri_tl(t1, t0, 8);
4550 tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
4551 tcg_gen_shli_tl(t0, t0, 8);
4552 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
4553 tcg_gen_or_tl(t0, t0, t1);
4554 tcg_temp_free(t1);
4555 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4556 }
4557 break;
4558 case OPC_SEB:
4559 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
4560 break;
4561 case OPC_SEH:
4562 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
4563 break;
4564 #if defined(TARGET_MIPS64)
4565 case OPC_DSBH:
4566 {
4567 TCGv t1 = tcg_temp_new();
4568
4569 tcg_gen_shri_tl(t1, t0, 8);
4570 tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
4571 tcg_gen_shli_tl(t0, t0, 8);
4572 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
4573 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4574 tcg_temp_free(t1);
4575 }
4576 break;
4577 case OPC_DSHD:
4578 {
4579 TCGv t1 = tcg_temp_new();
4580
4581 tcg_gen_shri_tl(t1, t0, 16);
4582 tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
4583 tcg_gen_shli_tl(t0, t0, 16);
4584 tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
4585 tcg_gen_or_tl(t0, t0, t1);
4586 tcg_gen_shri_tl(t1, t0, 32);
4587 tcg_gen_shli_tl(t0, t0, 32);
4588 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4589 tcg_temp_free(t1);
4590 }
4591 break;
4592 #endif
4593 default:
4594 MIPS_INVAL("bsfhl");
4595 generate_exception(ctx, EXCP_RI);
4596 tcg_temp_free(t0);
4597 return;
4598 }
4599 tcg_temp_free(t0);
4600 }
4601
4602 static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
4603 int imm2)
4604 {
4605 TCGv t0;
4606 TCGv t1;
4607 if (rd == 0) {
4608 /* Treat as NOP. */
4609 return;
4610 }
4611 t0 = tcg_temp_new();
4612 t1 = tcg_temp_new();
4613 gen_load_gpr(t0, rs);
4614 gen_load_gpr(t1, rt);
4615 tcg_gen_shli_tl(t0, t0, imm2 + 1);
4616 tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
4617 if (opc == OPC_LSA) {
4618 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
4619 }
4620
4621 tcg_temp_free(t1);
4622 tcg_temp_free(t0);
4623
4624 return;
4625 }
4626
4627 static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
4628 int bp)
4629 {
4630 TCGv t0;
4631 if (rd == 0) {
4632 /* Treat as NOP. */
4633 return;
4634 }
4635 t0 = tcg_temp_new();
4636 gen_load_gpr(t0, rt);
4637 if (bp == 0) {
4638 tcg_gen_mov_tl(cpu_gpr[rd], t0);
4639 } else {
4640 TCGv t1 = tcg_temp_new();
4641 gen_load_gpr(t1, rs);
4642 switch (opc) {
4643 case OPC_ALIGN:
4644 {
4645 TCGv_i64 t2 = tcg_temp_new_i64();
4646 tcg_gen_concat_tl_i64(t2, t1, t0);
4647 tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
4648 gen_move_low32(cpu_gpr[rd], t2);
4649 tcg_temp_free_i64(t2);
4650 }
4651 break;
4652 #if defined(TARGET_MIPS64)
4653 case OPC_DALIGN:
4654 tcg_gen_shli_tl(t0, t0, 8 * bp);
4655 tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
4656 tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
4657 break;
4658 #endif
4659 }
4660 tcg_temp_free(t1);
4661 }
4662
4663 tcg_temp_free(t0);
4664 }
4665
4666 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
4667 {
4668 TCGv t0;
4669 if (rd == 0) {
4670 /* Treat as NOP. */
4671 return;
4672 }
4673 t0 = tcg_temp_new();
4674 gen_load_gpr(t0, rt);
4675 switch (opc) {
4676 case OPC_BITSWAP:
4677 gen_helper_bitswap(cpu_gpr[rd], t0);
4678 break;
4679 #if defined(TARGET_MIPS64)
4680 case OPC_DBITSWAP:
4681 gen_helper_dbitswap(cpu_gpr[rd], t0);
4682 break;
4683 #endif
4684 }
4685 tcg_temp_free(t0);
4686 }
4687
4688 #ifndef CONFIG_USER_ONLY
4689 /* CP0 (MMU and control) */
4690 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
4691 {
4692 TCGv_i64 t0 = tcg_temp_new_i64();
4693 TCGv_i64 t1 = tcg_temp_new_i64();
4694
4695 tcg_gen_ext_tl_i64(t0, arg);
4696 tcg_gen_ld_i64(t1, cpu_env, off);
4697 #if defined(TARGET_MIPS64)
4698 tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
4699 #else
4700 tcg_gen_concat32_i64(t1, t1, t0);
4701 #endif
4702 tcg_gen_st_i64(t1, cpu_env, off);
4703 tcg_temp_free_i64(t1);
4704 tcg_temp_free_i64(t0);
4705 }
4706
4707 static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
4708 {
4709 TCGv_i64 t0 = tcg_temp_new_i64();
4710 TCGv_i64 t1 = tcg_temp_new_i64();
4711
4712 tcg_gen_ext_tl_i64(t0, arg);
4713 tcg_gen_ld_i64(t1, cpu_env, off);
4714 tcg_gen_concat32_i64(t1, t1, t0);
4715 tcg_gen_st_i64(t1, cpu_env, off);
4716 tcg_temp_free_i64(t1);
4717 tcg_temp_free_i64(t0);
4718 }
4719
4720 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
4721 {
4722 TCGv_i64 t0 = tcg_temp_new_i64();
4723
4724 tcg_gen_ld_i64(t0, cpu_env, off);
4725 #if defined(TARGET_MIPS64)
4726 tcg_gen_shri_i64(t0, t0, 30);
4727 #else
4728 tcg_gen_shri_i64(t0, t0, 32);
4729 #endif
4730 gen_move_low32(arg, t0);
4731 tcg_temp_free_i64(t0);
4732 }
4733
4734 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
4735 {
4736 TCGv_i64 t0 = tcg_temp_new_i64();
4737
4738 tcg_gen_ld_i64(t0, cpu_env, off);
4739 tcg_gen_shri_i64(t0, t0, 32 + shift);
4740 gen_move_low32(arg, t0);
4741 tcg_temp_free_i64(t0);
4742 }
4743
4744 static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
4745 {
4746 TCGv_i32 t0 = tcg_temp_new_i32();
4747
4748 tcg_gen_ld_i32(t0, cpu_env, off);
4749 tcg_gen_ext_i32_tl(arg, t0);
4750 tcg_temp_free_i32(t0);
4751 }
4752
4753 static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
4754 {
4755 tcg_gen_ld_tl(arg, cpu_env, off);
4756 tcg_gen_ext32s_tl(arg, arg);
4757 }
4758
4759 static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
4760 {
4761 TCGv_i32 t0 = tcg_temp_new_i32();
4762
4763 tcg_gen_trunc_tl_i32(t0, arg);
4764 tcg_gen_st_i32(t0, cpu_env, off);
4765 tcg_temp_free_i32(t0);
4766 }
4767
4768 static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
4769 {
4770 tcg_gen_ext32s_tl(arg, arg);
4771 tcg_gen_st_tl(arg, cpu_env, off);
4772 }
4773
4774 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4775 {
4776 const char *rn = "invalid";
4777
4778 if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
4779 goto mfhc0_read_zero;
4780 }
4781
4782 switch (reg) {
4783 case 2:
4784 switch (sel) {
4785 case 0:
4786 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
4787 rn = "EntryLo0";
4788 break;
4789 default:
4790 goto mfhc0_read_zero;
4791 }
4792 break;
4793 case 3:
4794 switch (sel) {
4795 case 0:
4796 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
4797 rn = "EntryLo1";
4798 break;
4799 default:
4800 goto mfhc0_read_zero;
4801 }
4802 break;
4803 case 17:
4804 switch (sel) {
4805 case 0:
4806 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
4807 ctx->CP0_LLAddr_shift);
4808 rn = "LLAddr";
4809 break;
4810 default:
4811 goto mfhc0_read_zero;
4812 }
4813 break;
4814 case 28:
4815 switch (sel) {
4816 case 0:
4817 case 2:
4818 case 4:
4819 case 6:
4820 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
4821 rn = "TagLo";
4822 break;
4823 default:
4824 goto mfhc0_read_zero;
4825 }
4826 break;
4827 default:
4828 goto mfhc0_read_zero;
4829 }
4830
4831 (void)rn; /* avoid a compiler warning */
4832 LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
4833 return;
4834
4835 mfhc0_read_zero:
4836 LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
4837 tcg_gen_movi_tl(arg, 0);
4838 }
4839
4840 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4841 {
4842 const char *rn = "invalid";
4843 uint64_t mask = ctx->PAMask >> 36;
4844
4845 if (!(ctx->hflags & MIPS_HFLAG_ELPA)) {
4846 goto mthc0_nop;
4847 }
4848
4849 switch (reg) {
4850 case 2:
4851 switch (sel) {
4852 case 0:
4853 tcg_gen_andi_tl(arg, arg, mask);
4854 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
4855 rn = "EntryLo0";
4856 break;
4857 default:
4858 goto mthc0_nop;
4859 }
4860 break;
4861 case 3:
4862 switch (sel) {
4863 case 0:
4864 tcg_gen_andi_tl(arg, arg, mask);
4865 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
4866 rn = "EntryLo1";
4867 break;
4868 default:
4869 goto mthc0_nop;
4870 }
4871 break;
4872 case 17:
4873 switch (sel) {
4874 case 0:
4875 /* LLAddr is read-only (the only exception is bit 0 if LLB is
4876 supported); the CP0_LLAddr_rw_bitmask does not seem to be
4877 relevant for modern MIPS cores supporting MTHC0, therefore
4878 treating MTHC0 to LLAddr as NOP. */
4879 rn = "LLAddr";
4880 break;
4881 default:
4882 goto mthc0_nop;
4883 }
4884 break;
4885 case 28:
4886 switch (sel) {
4887 case 0:
4888 case 2:
4889 case 4:
4890 case 6:
4891 tcg_gen_andi_tl(arg, arg, mask);
4892 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
4893 rn = "TagLo";
4894 break;
4895 default:
4896 goto mthc0_nop;
4897 }
4898 break;
4899 default:
4900 goto mthc0_nop;
4901 }
4902
4903 (void)rn; /* avoid a compiler warning */
4904 mthc0_nop:
4905 LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
4906 }
4907
4908 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
4909 {
4910 if (ctx->insn_flags & ISA_MIPS32R6) {
4911 tcg_gen_movi_tl(arg, 0);
4912 } else {
4913 tcg_gen_movi_tl(arg, ~0);
4914 }
4915 }
4916
4917 #define CP0_CHECK(c) \
4918 do { \
4919 if (!(c)) { \
4920 goto cp0_unimplemented; \
4921 } \
4922 } while (0)
4923
4924 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
4925 {
4926 const char *rn = "invalid";
4927
4928 if (sel != 0)
4929 check_insn(ctx, ISA_MIPS32);
4930
4931 switch (reg) {
4932 case 0:
4933 switch (sel) {
4934 case 0:
4935 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
4936 rn = "Index";
4937 break;
4938 case 1:
4939 CP0_CHECK(ctx->insn_flags & ASE_MT);
4940 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
4941 rn = "MVPControl";
4942 break;
4943 case 2:
4944 CP0_CHECK(ctx->insn_flags & ASE_MT);
4945 gen_helper_mfc0_mvpconf0(arg, cpu_env);
4946 rn = "MVPConf0";
4947 break;
4948 case 3:
4949 CP0_CHECK(ctx->insn_flags & ASE_MT);
4950 gen_helper_mfc0_mvpconf1(arg, cpu_env);
4951 rn = "MVPConf1";
4952 break;
4953 default:
4954 goto cp0_unimplemented;
4955 }
4956 break;
4957 case 1:
4958 switch (sel) {
4959 case 0:
4960 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
4961 gen_helper_mfc0_random(arg, cpu_env);
4962 rn = "Random";
4963 break;
4964 case 1:
4965 CP0_CHECK(ctx->insn_flags & ASE_MT);
4966 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
4967 rn = "VPEControl";
4968 break;
4969 case 2:
4970 CP0_CHECK(ctx->insn_flags & ASE_MT);
4971 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
4972 rn = "VPEConf0";
4973 break;
4974 case 3:
4975 CP0_CHECK(ctx->insn_flags & ASE_MT);
4976 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
4977 rn = "VPEConf1";
4978 break;
4979 case 4:
4980 CP0_CHECK(ctx->insn_flags & ASE_MT);
4981 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
4982 rn = "YQMask";
4983 break;
4984 case 5:
4985 CP0_CHECK(ctx->insn_flags & ASE_MT);
4986 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
4987 rn = "VPESchedule";
4988 break;
4989 case 6:
4990 CP0_CHECK(ctx->insn_flags & ASE_MT);
4991 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
4992 rn = "VPEScheFBack";
4993 break;
4994 case 7:
4995 CP0_CHECK(ctx->insn_flags & ASE_MT);
4996 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
4997 rn = "VPEOpt";
4998 break;
4999 default:
5000 goto cp0_unimplemented;
5001 }
5002 break;
5003 case 2:
5004 switch (sel) {
5005 case 0:
5006 {
5007 TCGv_i64 tmp = tcg_temp_new_i64();
5008 tcg_gen_ld_i64(tmp, cpu_env,
5009 offsetof(CPUMIPSState, CP0_EntryLo0));
5010 #if defined(TARGET_MIPS64)
5011 if (ctx->rxi) {
5012 /* Move RI/XI fields to bits 31:30 */
5013 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5014 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5015 }
5016 #endif
5017 gen_move_low32(arg, tmp);
5018 tcg_temp_free_i64(tmp);
5019 }
5020 rn = "EntryLo0";
5021 break;
5022 case 1:
5023 CP0_CHECK(ctx->insn_flags & ASE_MT);
5024 gen_helper_mfc0_tcstatus(arg, cpu_env);
5025 rn = "TCStatus";
5026 break;
5027 case 2:
5028 CP0_CHECK(ctx->insn_flags & ASE_MT);
5029 gen_helper_mfc0_tcbind(arg, cpu_env);
5030 rn = "TCBind";
5031 break;
5032 case 3:
5033 CP0_CHECK(ctx->insn_flags & ASE_MT);
5034 gen_helper_mfc0_tcrestart(arg, cpu_env);
5035 rn = "TCRestart";
5036 break;
5037 case 4:
5038 CP0_CHECK(ctx->insn_flags & ASE_MT);
5039 gen_helper_mfc0_tchalt(arg, cpu_env);
5040 rn = "TCHalt";
5041 break;
5042 case 5:
5043 CP0_CHECK(ctx->insn_flags & ASE_MT);
5044 gen_helper_mfc0_tccontext(arg, cpu_env);
5045 rn = "TCContext";
5046 break;
5047 case 6:
5048 CP0_CHECK(ctx->insn_flags & ASE_MT);
5049 gen_helper_mfc0_tcschedule(arg, cpu_env);
5050 rn = "TCSchedule";
5051 break;
5052 case 7:
5053 CP0_CHECK(ctx->insn_flags & ASE_MT);
5054 gen_helper_mfc0_tcschefback(arg, cpu_env);
5055 rn = "TCScheFBack";
5056 break;
5057 default:
5058 goto cp0_unimplemented;
5059 }
5060 break;
5061 case 3:
5062 switch (sel) {
5063 case 0:
5064 {
5065 TCGv_i64 tmp = tcg_temp_new_i64();
5066 tcg_gen_ld_i64(tmp, cpu_env,
5067 offsetof(CPUMIPSState, CP0_EntryLo1));
5068 #if defined(TARGET_MIPS64)
5069 if (ctx->rxi) {
5070 /* Move RI/XI fields to bits 31:30 */
5071 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5072 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5073 }
5074 #endif
5075 gen_move_low32(arg, tmp);
5076 tcg_temp_free_i64(tmp);
5077 }
5078 rn = "EntryLo1";
5079 break;
5080 default:
5081 goto cp0_unimplemented;
5082 }
5083 break;
5084 case 4:
5085 switch (sel) {
5086 case 0:
5087 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
5088 tcg_gen_ext32s_tl(arg, arg);
5089 rn = "Context";
5090 break;
5091 case 1:
5092 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
5093 rn = "ContextConfig";
5094 goto cp0_unimplemented;
5095 // break;
5096 case 2:
5097 CP0_CHECK(ctx->ulri);
5098 tcg_gen_ld32s_tl(arg, cpu_env,
5099 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5100 rn = "UserLocal";
5101 break;
5102 default:
5103 goto cp0_unimplemented;
5104 }
5105 break;
5106 case 5:
5107 switch (sel) {
5108 case 0:
5109 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
5110 rn = "PageMask";
5111 break;
5112 case 1:
5113 check_insn(ctx, ISA_MIPS32R2);
5114 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
5115 rn = "PageGrain";
5116 break;
5117 default:
5118 goto cp0_unimplemented;
5119 }
5120 break;
5121 case 6:
5122 switch (sel) {
5123 case 0:
5124 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
5125 rn = "Wired";
5126 break;
5127 case 1:
5128 check_insn(ctx, ISA_MIPS32R2);
5129 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
5130 rn = "SRSConf0";
5131 break;
5132 case 2:
5133 check_insn(ctx, ISA_MIPS32R2);
5134 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
5135 rn = "SRSConf1";
5136 break;
5137 case 3:
5138 check_insn(ctx, ISA_MIPS32R2);
5139 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
5140 rn = "SRSConf2";
5141 break;
5142 case 4:
5143 check_insn(ctx, ISA_MIPS32R2);
5144 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
5145 rn = "SRSConf3";
5146 break;
5147 case 5:
5148 check_insn(ctx, ISA_MIPS32R2);
5149 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
5150 rn = "SRSConf4";
5151 break;
5152 default:
5153 goto cp0_unimplemented;
5154 }
5155 break;
5156 case 7:
5157 switch (sel) {
5158 case 0:
5159 check_insn(ctx, ISA_MIPS32R2);
5160 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
5161 rn = "HWREna";
5162 break;
5163 default:
5164 goto cp0_unimplemented;
5165 }
5166 break;
5167 case 8:
5168 switch (sel) {
5169 case 0:
5170 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
5171 tcg_gen_ext32s_tl(arg, arg);
5172 rn = "BadVAddr";
5173 break;
5174 case 1:
5175 CP0_CHECK(ctx->bi);
5176 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
5177 rn = "BadInstr";
5178 break;
5179 case 2:
5180 CP0_CHECK(ctx->bp);
5181 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
5182 rn = "BadInstrP";
5183 break;
5184 default:
5185 goto cp0_unimplemented;
5186 }
5187 break;
5188 case 9:
5189 switch (sel) {
5190 case 0:
5191 /* Mark as an IO operation because we read the time. */
5192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5193 gen_io_start();
5194 }
5195 gen_helper_mfc0_count(arg, cpu_env);
5196 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5197 gen_io_end();
5198 }
5199 /* Break the TB to be able to take timer interrupts immediately
5200 after reading count. */
5201 ctx->bstate = BS_STOP;
5202 rn = "Count";
5203 break;
5204 /* 6,7 are implementation dependent */
5205 default:
5206 goto cp0_unimplemented;
5207 }
5208 break;
5209 case 10:
5210 switch (sel) {
5211 case 0:
5212 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
5213 tcg_gen_ext32s_tl(arg, arg);
5214 rn = "EntryHi";
5215 break;
5216 default:
5217 goto cp0_unimplemented;
5218 }
5219 break;
5220 case 11:
5221 switch (sel) {
5222 case 0:
5223 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
5224 rn = "Compare";
5225 break;
5226 /* 6,7 are implementation dependent */
5227 default:
5228 goto cp0_unimplemented;
5229 }
5230 break;
5231 case 12:
5232 switch (sel) {
5233 case 0:
5234 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
5235 rn = "Status";
5236 break;
5237 case 1:
5238 check_insn(ctx, ISA_MIPS32R2);
5239 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
5240 rn = "IntCtl";
5241 break;
5242 case 2:
5243 check_insn(ctx, ISA_MIPS32R2);
5244 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
5245 rn = "SRSCtl";
5246 break;
5247 case 3:
5248 check_insn(ctx, ISA_MIPS32R2);
5249 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
5250 rn = "SRSMap";
5251 break;
5252 default:
5253 goto cp0_unimplemented;
5254 }
5255 break;
5256 case 13:
5257 switch (sel) {
5258 case 0:
5259 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
5260 rn = "Cause";
5261 break;
5262 default:
5263 goto cp0_unimplemented;
5264 }
5265 break;
5266 case 14:
5267 switch (sel) {
5268 case 0:
5269 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
5270 tcg_gen_ext32s_tl(arg, arg);
5271 rn = "EPC";
5272 break;
5273 default:
5274 goto cp0_unimplemented;
5275 }
5276 break;
5277 case 15:
5278 switch (sel) {
5279 case 0:
5280 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
5281 rn = "PRid";
5282 break;
5283 case 1:
5284 check_insn(ctx, ISA_MIPS32R2);
5285 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
5286 rn = "EBase";
5287 break;
5288 default:
5289 goto cp0_unimplemented;
5290 }
5291 break;
5292 case 16:
5293 switch (sel) {
5294 case 0:
5295 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
5296 rn = "Config";
5297 break;
5298 case 1:
5299 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
5300 rn = "Config1";
5301 break;
5302 case 2:
5303 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
5304 rn = "Config2";
5305 break;
5306 case 3:
5307 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
5308 rn = "Config3";
5309 break;
5310 case 4:
5311 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
5312 rn = "Config4";
5313 break;
5314 case 5:
5315 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
5316 rn = "Config5";
5317 break;
5318 /* 6,7 are implementation dependent */
5319 case 6:
5320 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
5321 rn = "Config6";
5322 break;
5323 case 7:
5324 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
5325 rn = "Config7";
5326 break;
5327 default:
5328 goto cp0_unimplemented;
5329 }
5330 break;
5331 case 17:
5332 switch (sel) {
5333 case 0:
5334 gen_helper_mfc0_lladdr(arg, cpu_env);
5335 rn = "LLAddr";
5336 break;
5337 default:
5338 goto cp0_unimplemented;
5339 }
5340 break;
5341 case 18:
5342 switch (sel) {
5343 case 0 ... 7:
5344 gen_helper_1e0i(mfc0_watchlo, arg, sel);
5345 rn = "WatchLo";
5346 break;
5347 default:
5348 goto cp0_unimplemented;
5349 }
5350 break;
5351 case 19:
5352 switch (sel) {
5353 case 0 ...7:
5354 gen_helper_1e0i(mfc0_watchhi, arg, sel);
5355 rn = "WatchHi";
5356 break;
5357 default:
5358 goto cp0_unimplemented;
5359 }
5360 break;
5361 case 20:
5362 switch (sel) {
5363 case 0:
5364 #if defined(TARGET_MIPS64)
5365 check_insn(ctx, ISA_MIPS3);
5366 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
5367 tcg_gen_ext32s_tl(arg, arg);
5368 rn = "XContext";
5369 break;
5370 #endif
5371 default:
5372 goto cp0_unimplemented;
5373 }
5374 break;
5375 case 21:
5376 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5377 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
5378 switch (sel) {
5379 case 0:
5380 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
5381 rn = "Framemask";
5382 break;
5383 default:
5384 goto cp0_unimplemented;
5385 }
5386 break;
5387 case 22:
5388 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5389 rn = "'Diagnostic"; /* implementation dependent */
5390 break;
5391 case 23:
5392 switch (sel) {
5393 case 0:
5394 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
5395 rn = "Debug";
5396 break;
5397 case 1:
5398 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
5399 rn = "TraceControl";
5400 // break;
5401 case 2:
5402 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
5403 rn = "TraceControl2";
5404 // break;
5405 case 3:
5406 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
5407 rn = "UserTraceData";
5408 // break;
5409 case 4:
5410 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
5411 rn = "TraceBPC";
5412 // break;
5413 default:
5414 goto cp0_unimplemented;
5415 }
5416 break;
5417 case 24:
5418 switch (sel) {
5419 case 0:
5420 /* EJTAG support */
5421 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
5422 tcg_gen_ext32s_tl(arg, arg);
5423 rn = "DEPC";
5424 break;
5425 default:
5426 goto cp0_unimplemented;
5427 }
5428 break;
5429 case 25:
5430 switch (sel) {
5431 case 0:
5432 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
5433 rn = "Performance0";
5434 break;
5435 case 1:
5436 // gen_helper_mfc0_performance1(arg);
5437 rn = "Performance1";
5438 // break;
5439 case 2:
5440 // gen_helper_mfc0_performance2(arg);
5441 rn = "Performance2";
5442 // break;
5443 case 3:
5444 // gen_helper_mfc0_performance3(arg);
5445 rn = "Performance3";
5446 // break;
5447 case 4:
5448 // gen_helper_mfc0_performance4(arg);
5449 rn = "Performance4";
5450 // break;
5451 case 5:
5452 // gen_helper_mfc0_performance5(arg);
5453 rn = "Performance5";
5454 // break;
5455 case 6:
5456 // gen_helper_mfc0_performance6(arg);
5457 rn = "Performance6";
5458 // break;
5459 case 7:
5460 // gen_helper_mfc0_performance7(arg);
5461 rn = "Performance7";
5462 // break;
5463 default:
5464 goto cp0_unimplemented;
5465 }
5466 break;
5467 case 26:
5468 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5469 rn = "ECC";
5470 break;
5471 case 27:
5472 switch (sel) {
5473 case 0 ... 3:
5474 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5475 rn = "CacheErr";
5476 break;
5477 default:
5478 goto cp0_unimplemented;
5479 }
5480 break;
5481 case 28:
5482 switch (sel) {
5483 case 0:
5484 case 2:
5485 case 4:
5486 case 6:
5487 {
5488 TCGv_i64 tmp = tcg_temp_new_i64();
5489 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
5490 gen_move_low32(arg, tmp);
5491 tcg_temp_free_i64(tmp);
5492 }
5493 rn = "TagLo";
5494 break;
5495 case 1:
5496 case 3:
5497 case 5:
5498 case 7:
5499 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
5500 rn = "DataLo";
5501 break;
5502 default:
5503 goto cp0_unimplemented;
5504 }
5505 break;
5506 case 29:
5507 switch (sel) {
5508 case 0:
5509 case 2:
5510 case 4:
5511 case 6:
5512 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
5513 rn = "TagHi";
5514 break;
5515 case 1:
5516 case 3:
5517 case 5:
5518 case 7:
5519 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
5520 rn = "DataHi";
5521 break;
5522 default:
5523 goto cp0_unimplemented;
5524 }
5525 break;
5526 case 30:
5527 switch (sel) {
5528 case 0:
5529 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
5530 tcg_gen_ext32s_tl(arg, arg);
5531 rn = "ErrorEPC";
5532 break;
5533 default:
5534 goto cp0_unimplemented;
5535 }
5536 break;
5537 case 31:
5538 switch (sel) {
5539 case 0:
5540 /* EJTAG support */
5541 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
5542 rn = "DESAVE";
5543 break;
5544 case 2 ... 7:
5545 CP0_CHECK(ctx->kscrexist & (1 << sel));
5546 tcg_gen_ld_tl(arg, cpu_env,
5547 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
5548 tcg_gen_ext32s_tl(arg, arg);
5549 rn = "KScratch";
5550 break;
5551 default:
5552 goto cp0_unimplemented;
5553 }
5554 break;
5555 default:
5556 goto cp0_unimplemented;
5557 }
5558 (void)rn; /* avoid a compiler warning */
5559 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
5560 return;
5561
5562 cp0_unimplemented:
5563 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
5564 gen_mfc0_unimplemented(ctx, arg);
5565 }
5566
5567 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5568 {
5569 const char *rn = "invalid";
5570
5571 if (sel != 0)
5572 check_insn(ctx, ISA_MIPS32);
5573
5574 if (ctx->tb->cflags & CF_USE_ICOUNT) {
5575 gen_io_start();
5576 }
5577
5578 switch (reg) {
5579 case 0:
5580 switch (sel) {
5581 case 0:
5582 gen_helper_mtc0_index(cpu_env, arg);
5583 rn = "Index";
5584 break;
5585 case 1:
5586 CP0_CHECK(ctx->insn_flags & ASE_MT);
5587 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
5588 rn = "MVPControl";
5589 break;
5590 case 2:
5591 CP0_CHECK(ctx->insn_flags & ASE_MT);
5592 /* ignored */
5593 rn = "MVPConf0";
5594 break;
5595 case 3:
5596 CP0_CHECK(ctx->insn_flags & ASE_MT);
5597 /* ignored */
5598 rn = "MVPConf1";
5599 break;
5600 default:
5601 goto cp0_unimplemented;
5602 }
5603 break;
5604 case 1:
5605 switch (sel) {
5606 case 0:
5607 /* ignored */
5608 rn = "Random";
5609 break;
5610 case 1:
5611 CP0_CHECK(ctx->insn_flags & ASE_MT);
5612 gen_helper_mtc0_vpecontrol(cpu_env, arg);
5613 rn = "VPEControl";
5614 break;
5615 case 2:
5616 CP0_CHECK(ctx->insn_flags & ASE_MT);
5617 gen_helper_mtc0_vpeconf0(cpu_env, arg);
5618 rn = "VPEConf0";
5619 break;
5620 case 3:
5621 CP0_CHECK(ctx->insn_flags & ASE_MT);
5622 gen_helper_mtc0_vpeconf1(cpu_env, arg);
5623 rn = "VPEConf1";
5624 break;
5625 case 4:
5626 CP0_CHECK(ctx->insn_flags & ASE_MT);
5627 gen_helper_mtc0_yqmask(cpu_env, arg);
5628 rn = "YQMask";
5629 break;
5630 case 5:
5631 CP0_CHECK(ctx->insn_flags & ASE_MT);
5632 gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
5633 rn = "VPESchedule";
5634 break;
5635 case 6:
5636 CP0_CHECK(ctx->insn_flags & ASE_MT);
5637 gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
5638 rn = "VPEScheFBack";
5639 break;
5640 case 7:
5641 CP0_CHECK(ctx->insn_flags & ASE_MT);
5642 gen_helper_mtc0_vpeopt(cpu_env, arg);
5643 rn = "VPEOpt";
5644 break;
5645 default:
5646 goto cp0_unimplemented;
5647 }
5648 break;
5649 case 2:
5650 switch (sel) {
5651 case 0:
5652 gen_helper_mtc0_entrylo0(cpu_env, arg);
5653 rn = "EntryLo0";
5654 break;
5655 case 1:
5656 CP0_CHECK(ctx->insn_flags & ASE_MT);
5657 gen_helper_mtc0_tcstatus(cpu_env, arg);
5658 rn = "TCStatus";
5659 break;
5660 case 2:
5661 CP0_CHECK(ctx->insn_flags & ASE_MT);
5662 gen_helper_mtc0_tcbind(cpu_env, arg);
5663 rn = "TCBind";
5664 break;
5665 case 3:
5666 CP0_CHECK(ctx->insn_flags & ASE_MT);
5667 gen_helper_mtc0_tcrestart(cpu_env, arg);
5668 rn = "TCRestart";
5669 break;
5670 case 4:
5671 CP0_CHECK(ctx->insn_flags & ASE_MT);
5672 gen_helper_mtc0_tchalt(cpu_env, arg);
5673 rn = "TCHalt";
5674 break;
5675 case 5:
5676 CP0_CHECK(ctx->insn_flags & ASE_MT);
5677 gen_helper_mtc0_tccontext(cpu_env, arg);
5678 rn = "TCContext";
5679 break;
5680 case 6:
5681 CP0_CHECK(ctx->insn_flags & ASE_MT);
5682 gen_helper_mtc0_tcschedule(cpu_env, arg);
5683 rn = "TCSchedule";
5684 break;
5685 case 7:
5686 CP0_CHECK(ctx->insn_flags & ASE_MT);
5687 gen_helper_mtc0_tcschefback(cpu_env, arg);
5688 rn = "TCScheFBack";
5689 break;
5690 default:
5691 goto cp0_unimplemented;
5692 }
5693 break;
5694 case 3:
5695 switch (sel) {
5696 case 0:
5697 gen_helper_mtc0_entrylo1(cpu_env, arg);
5698 rn = "EntryLo1";
5699 break;
5700 default:
5701 goto cp0_unimplemented;
5702 }
5703 break;
5704 case 4:
5705 switch (sel) {
5706 case 0:
5707 gen_helper_mtc0_context(cpu_env, arg);
5708 rn = "Context";
5709 break;
5710 case 1:
5711 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
5712 rn = "ContextConfig";
5713 goto cp0_unimplemented;
5714 // break;
5715 case 2:
5716 CP0_CHECK(ctx->ulri);
5717 tcg_gen_st_tl(arg, cpu_env,
5718 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5719 rn = "UserLocal";
5720 break;
5721 default:
5722 goto cp0_unimplemented;
5723 }
5724 break;
5725 case 5:
5726 switch (sel) {
5727 case 0:
5728 gen_helper_mtc0_pagemask(cpu_env, arg);
5729 rn = "PageMask";
5730 break;
5731 case 1:
5732 check_insn(ctx, ISA_MIPS32R2);
5733 gen_helper_mtc0_pagegrain(cpu_env, arg);
5734 rn = "PageGrain";
5735 ctx->bstate = BS_STOP;
5736 break;
5737 default:
5738 goto cp0_unimplemented;
5739 }
5740 break;
5741 case 6:
5742 switch (sel) {
5743 case 0:
5744 gen_helper_mtc0_wired(cpu_env, arg);
5745 rn = "Wired";
5746 break;
5747 case 1:
5748 check_insn(ctx, ISA_MIPS32R2);
5749 gen_helper_mtc0_srsconf0(cpu_env, arg);
5750 rn = "SRSConf0";
5751 break;
5752 case 2:
5753 check_insn(ctx, ISA_MIPS32R2);
5754 gen_helper_mtc0_srsconf1(cpu_env, arg);
5755 rn = "SRSConf1";
5756 break;
5757 case 3:
5758 check_insn(ctx, ISA_MIPS32R2);
5759 gen_helper_mtc0_srsconf2(cpu_env, arg);
5760 rn = "SRSConf2";
5761 break;
5762 case 4:
5763 check_insn(ctx, ISA_MIPS32R2);
5764 gen_helper_mtc0_srsconf3(cpu_env, arg);
5765 rn = "SRSConf3";
5766 break;
5767 case 5:
5768 check_insn(ctx, ISA_MIPS32R2);
5769 gen_helper_mtc0_srsconf4(cpu_env, arg);
5770 rn = "SRSConf4";
5771 break;
5772 default:
5773 goto cp0_unimplemented;
5774 }
5775 break;
5776 case 7:
5777 switch (sel) {
5778 case 0:
5779 check_insn(ctx, ISA_MIPS32R2);
5780 gen_helper_mtc0_hwrena(cpu_env, arg);
5781 ctx->bstate = BS_STOP;
5782 rn = "HWREna";
5783 break;
5784 default:
5785 goto cp0_unimplemented;
5786 }
5787 break;
5788 case 8:
5789 switch (sel) {
5790 case 0:
5791 /* ignored */
5792 rn = "BadVAddr";
5793 break;
5794 case 1:
5795 /* ignored */
5796 rn = "BadInstr";
5797 break;
5798 case 2:
5799 /* ignored */
5800 rn = "BadInstrP";
5801 break;
5802 default:
5803 goto cp0_unimplemented;
5804 }
5805 break;
5806 case 9:
5807 switch (sel) {
5808 case 0:
5809 gen_helper_mtc0_count(cpu_env, arg);
5810 rn = "Count";
5811 break;
5812 /* 6,7 are implementation dependent */
5813 default:
5814 goto cp0_unimplemented;
5815 }
5816 break;
5817 case 10:
5818 switch (sel) {
5819 case 0:
5820 gen_helper_mtc0_entryhi(cpu_env, arg);
5821 rn = "EntryHi";
5822 break;
5823 default:
5824 goto cp0_unimplemented;
5825 }
5826 break;
5827 case 11:
5828 switch (sel) {
5829 case 0:
5830 gen_helper_mtc0_compare(cpu_env, arg);
5831 rn = "Compare";
5832 break;
5833 /* 6,7 are implementation dependent */
5834 default:
5835 goto cp0_unimplemented;
5836 }
5837 break;
5838 case 12:
5839 switch (sel) {
5840 case 0:
5841 save_cpu_state(ctx, 1);
5842 gen_helper_mtc0_status(cpu_env, arg);
5843 /* BS_STOP isn't good enough here, hflags may have changed. */
5844 gen_save_pc(ctx->pc + 4);
5845 ctx->bstate = BS_EXCP;
5846 rn = "Status";
5847 break;
5848 case 1:
5849 check_insn(ctx, ISA_MIPS32R2);
5850 gen_helper_mtc0_intctl(cpu_env, arg);
5851 /* Stop translation as we may have switched the execution mode */
5852 ctx->bstate = BS_STOP;
5853 rn = "IntCtl";
5854 break;
5855 case 2:
5856 check_insn(ctx, ISA_MIPS32R2);
5857 gen_helper_mtc0_srsctl(cpu_env, arg);
5858 /* Stop translation as we may have switched the execution mode */
5859 ctx->bstate = BS_STOP;
5860 rn = "SRSCtl";
5861 break;
5862 case 3:
5863 check_insn(ctx, ISA_MIPS32R2);
5864 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
5865 /* Stop translation as we may have switched the execution mode */
5866 ctx->bstate = BS_STOP;
5867 rn = "SRSMap";
5868 break;
5869 default:
5870 goto cp0_unimplemented;
5871 }
5872 break;
5873 case 13:
5874 switch (sel) {
5875 case 0:
5876 save_cpu_state(ctx, 1);
5877 gen_helper_mtc0_cause(cpu_env, arg);
5878 rn = "Cause";
5879 break;
5880 default:
5881 goto cp0_unimplemented;
5882 }
5883 break;
5884 case 14:
5885 switch (sel) {
5886 case 0:
5887 gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
5888 rn = "EPC";
5889 break;
5890 default:
5891 goto cp0_unimplemented;
5892 }
5893 break;
5894 case 15:
5895 switch (sel) {
5896 case 0:
5897 /* ignored */
5898 rn = "PRid";
5899 break;
5900 case 1:
5901 check_insn(ctx, ISA_MIPS32R2);
5902 gen_helper_mtc0_ebase(cpu_env, arg);
5903 rn = "EBase";
5904 break;
5905 default:
5906 goto cp0_unimplemented;
5907 }
5908 break;
5909 case 16:
5910 switch (sel) {
5911 case 0:
5912 gen_helper_mtc0_config0(cpu_env, arg);
5913 rn = "Config";
5914 /* Stop translation as we may have switched the execution mode */
5915 ctx->bstate = BS_STOP;
5916 break;
5917 case 1:
5918 /* ignored, read only */
5919 rn = "Config1";
5920 break;
5921 case 2:
5922 gen_helper_mtc0_config2(cpu_env, arg);
5923 rn = "Config2";
5924 /* Stop translation as we may have switched the execution mode */
5925 ctx->bstate = BS_STOP;
5926 break;
5927 case 3:
5928 gen_helper_mtc0_config3(cpu_env, arg);
5929 rn = "Config3";
5930 /* Stop translation as we may have switched the execution mode */
5931 ctx->bstate = BS_STOP;
5932 break;
5933 case 4:
5934 gen_helper_mtc0_config4(cpu_env, arg);
5935 rn = "Config4";
5936 ctx->bstate = BS_STOP;
5937 break;
5938 case 5:
5939 gen_helper_mtc0_config5(cpu_env, arg);
5940 rn = "Config5";
5941 /* Stop translation as we may have switched the execution mode */
5942 ctx->bstate = BS_STOP;
5943 break;
5944 /* 6,7 are implementation dependent */
5945 case 6:
5946 /* ignored */
5947 rn = "Config6";
5948 break;
5949 case 7:
5950 /* ignored */
5951 rn = "Config7";
5952 break;
5953 default:
5954 rn = "Invalid config selector";
5955 goto cp0_unimplemented;
5956 }
5957 break;
5958 case 17:
5959 switch (sel) {
5960 case 0:
5961 gen_helper_mtc0_lladdr(cpu_env, arg);
5962 rn = "LLAddr";
5963 break;
5964 default:
5965 goto cp0_unimplemented;
5966 }
5967 break;
5968 case 18:
5969 switch (sel) {
5970 case 0 ... 7:
5971 gen_helper_0e1i(mtc0_watchlo, arg, sel);
5972 rn = "WatchLo";
5973 break;
5974 default:
5975 goto cp0_unimplemented;
5976 }
5977 break;
5978 case 19:
5979 switch (sel) {
5980 case 0 ... 7:
5981 gen_helper_0e1i(mtc0_watchhi, arg, sel);
5982 rn = "WatchHi";
5983 break;
5984 default:
5985 goto cp0_unimplemented;
5986 }
5987 break;
5988 case 20:
5989 switch (sel) {
5990 case 0:
5991 #if defined(TARGET_MIPS64)
5992 check_insn(ctx, ISA_MIPS3);
5993 gen_helper_mtc0_xcontext(cpu_env, arg);
5994 rn = "XContext";
5995 break;
5996 #endif
5997 default:
5998 goto cp0_unimplemented;
5999 }
6000 break;
6001 case 21:
6002 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6003 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6004 switch (sel) {
6005 case 0:
6006 gen_helper_mtc0_framemask(cpu_env, arg);
6007 rn = "Framemask";
6008 break;
6009 default:
6010 goto cp0_unimplemented;
6011 }
6012 break;
6013 case 22:
6014 /* ignored */
6015 rn = "Diagnostic"; /* implementation dependent */
6016 break;
6017 case 23:
6018 switch (sel) {
6019 case 0:
6020 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
6021 /* BS_STOP isn't good enough here, hflags may have changed. */
6022 gen_save_pc(ctx->pc + 4);
6023 ctx->bstate = BS_EXCP;
6024 rn = "Debug";
6025 break;
6026 case 1:
6027 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
6028 rn = "TraceControl";
6029 /* Stop translation as we may have switched the execution mode */
6030 ctx->bstate = BS_STOP;
6031 // break;
6032 case 2:
6033 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
6034 rn = "TraceControl2";
6035 /* Stop translation as we may have switched the execution mode */
6036 ctx->bstate = BS_STOP;
6037 // break;
6038 case 3:
6039 /* Stop translation as we may have switched the execution mode */
6040 ctx->bstate = BS_STOP;
6041 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
6042 rn = "UserTraceData";
6043 /* Stop translation as we may have switched the execution mode */
6044 ctx->bstate = BS_STOP;
6045 // break;
6046 case 4:
6047 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
6048 /* Stop translation as we may have switched the execution mode */
6049 ctx->bstate = BS_STOP;
6050 rn = "TraceBPC";
6051 // break;
6052 default:
6053 goto cp0_unimplemented;
6054 }
6055 break;
6056 case 24:
6057 switch (sel) {
6058 case 0:
6059 /* EJTAG support */
6060 gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
6061 rn = "DEPC";
6062 break;
6063 default:
6064 goto cp0_unimplemented;
6065 }
6066 break;
6067 case 25:
6068 switch (sel) {
6069 case 0:
6070 gen_helper_mtc0_performance0(cpu_env, arg);
6071 rn = "Performance0";
6072 break;
6073 case 1:
6074 // gen_helper_mtc0_performance1(arg);
6075 rn = "Performance1";
6076 // break;
6077 case 2:
6078 // gen_helper_mtc0_performance2(arg);
6079 rn = "Performance2";
6080 // break;
6081 case 3:
6082 // gen_helper_mtc0_performance3(arg);
6083 rn = "Performance3";
6084 // break;
6085 case 4:
6086 // gen_helper_mtc0_performance4(arg);
6087 rn = "Performance4";
6088 // break;
6089 case 5:
6090 // gen_helper_mtc0_performance5(arg);
6091 rn = "Performance5";
6092 // break;
6093 case 6:
6094 // gen_helper_mtc0_performance6(arg);
6095 rn = "Performance6";
6096 // break;
6097 case 7:
6098 // gen_helper_mtc0_performance7(arg);
6099 rn = "Performance7";
6100 // break;
6101 default:
6102 goto cp0_unimplemented;
6103 }
6104 break;
6105 case 26:
6106 /* ignored */
6107 rn = "ECC";
6108 break;
6109 case 27:
6110 switch (sel) {
6111 case 0 ... 3:
6112 /* ignored */
6113 rn = "CacheErr";
6114 break;
6115 default:
6116 goto cp0_unimplemented;
6117 }
6118 break;
6119 case 28:
6120 switch (sel) {
6121 case 0:
6122 case 2:
6123 case 4:
6124 case 6:
6125 gen_helper_mtc0_taglo(cpu_env, arg);
6126 rn = "TagLo";
6127 break;
6128 case 1:
6129 case 3:
6130 case 5:
6131 case 7:
6132 gen_helper_mtc0_datalo(cpu_env, arg);
6133 rn = "DataLo";
6134 break;
6135 default:
6136 goto cp0_unimplemented;
6137 }
6138 break;
6139 case 29:
6140 switch (sel) {
6141 case 0:
6142 case 2:
6143 case 4:
6144 case 6:
6145 gen_helper_mtc0_taghi(cpu_env, arg);
6146 rn = "TagHi";
6147 break;
6148 case 1:
6149 case 3:
6150 case 5:
6151 case 7:
6152 gen_helper_mtc0_datahi(cpu_env, arg);
6153 rn = "DataHi";
6154 break;
6155 default:
6156 rn = "invalid sel";
6157 goto cp0_unimplemented;
6158 }
6159 break;
6160 case 30:
6161 switch (sel) {
6162 case 0:
6163 gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
6164 rn = "ErrorEPC";
6165 break;
6166 default:
6167 goto cp0_unimplemented;
6168 }
6169 break;
6170 case 31:
6171 switch (sel) {
6172 case 0:
6173 /* EJTAG support */
6174 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6175 rn = "DESAVE";
6176 break;
6177 case 2 ... 7:
6178 CP0_CHECK(ctx->kscrexist & (1 << sel));
6179 tcg_gen_st_tl(arg, cpu_env,
6180 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
6181 rn = "KScratch";
6182 break;
6183 default:
6184 goto cp0_unimplemented;
6185 }
6186 /* Stop translation as we may have switched the execution mode */
6187 ctx->bstate = BS_STOP;
6188 break;
6189 default:
6190 goto cp0_unimplemented;
6191 }
6192 (void)rn; /* avoid a compiler warning */
6193 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
6194 /* For simplicity assume that all writes can cause interrupts. */
6195 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6196 gen_io_end();
6197 ctx->bstate = BS_STOP;
6198 }
6199 return;
6200
6201 cp0_unimplemented:
6202 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
6203 }
6204
6205 #if defined(TARGET_MIPS64)
6206 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6207 {
6208 const char *rn = "invalid";
6209
6210 if (sel != 0)
6211 check_insn(ctx, ISA_MIPS64);
6212
6213 switch (reg) {
6214 case 0:
6215 switch (sel) {
6216 case 0:
6217 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
6218 rn = "Index";
6219 break;
6220 case 1:
6221 CP0_CHECK(ctx->insn_flags & ASE_MT);
6222 gen_helper_mfc0_mvpcontrol(arg, cpu_env);
6223 rn = "MVPControl";
6224 break;
6225 case 2:
6226 CP0_CHECK(ctx->insn_flags & ASE_MT);
6227 gen_helper_mfc0_mvpconf0(arg, cpu_env);
6228 rn = "MVPConf0";
6229 break;
6230 case 3:
6231 CP0_CHECK(ctx->insn_flags & ASE_MT);
6232 gen_helper_mfc0_mvpconf1(arg, cpu_env);
6233 rn = "MVPConf1";
6234 break;
6235 default:
6236 goto cp0_unimplemented;
6237 }
6238 break;
6239 case 1:
6240 switch (sel) {
6241 case 0:
6242 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6243 gen_helper_mfc0_random(arg, cpu_env);
6244 rn = "Random";
6245 break;
6246 case 1:
6247 CP0_CHECK(ctx->insn_flags & ASE_MT);
6248 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
6249 rn = "VPEControl";
6250 break;
6251 case 2:
6252 CP0_CHECK(ctx->insn_flags & ASE_MT);
6253 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
6254 rn = "VPEConf0";
6255 break;
6256 case 3:
6257 CP0_CHECK(ctx->insn_flags & ASE_MT);
6258 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
6259 rn = "VPEConf1";
6260 break;
6261 case 4:
6262 CP0_CHECK(ctx->insn_flags & ASE_MT);
6263 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
6264 rn = "YQMask";
6265 break;
6266 case 5:
6267 CP0_CHECK(ctx->insn_flags & ASE_MT);
6268 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
6269 rn = "VPESchedule";
6270 break;
6271 case 6:
6272 CP0_CHECK(ctx->insn_flags & ASE_MT);
6273 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
6274 rn = "VPEScheFBack";
6275 break;
6276 case 7:
6277 CP0_CHECK(ctx->insn_flags & ASE_MT);
6278 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
6279 rn = "VPEOpt";
6280 break;
6281 default:
6282 goto cp0_unimplemented;
6283 }
6284 break;
6285 case 2:
6286 switch (sel) {
6287 case 0:
6288 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
6289 rn = "EntryLo0";
6290 break;
6291 case 1:
6292 CP0_CHECK(ctx->insn_flags & ASE_MT);
6293 gen_helper_mfc0_tcstatus(arg, cpu_env);
6294 rn = "TCStatus";
6295 break;
6296 case 2:
6297 CP0_CHECK(ctx->insn_flags & ASE_MT);
6298 gen_helper_mfc0_tcbind(arg, cpu_env);
6299 rn = "TCBind";
6300 break;
6301 case 3:
6302 CP0_CHECK(ctx->insn_flags & ASE_MT);
6303 gen_helper_dmfc0_tcrestart(arg, cpu_env);
6304 rn = "TCRestart";
6305 break;
6306 case 4:
6307 CP0_CHECK(ctx->insn_flags & ASE_MT);
6308 gen_helper_dmfc0_tchalt(arg, cpu_env);
6309 rn = "TCHalt";
6310 break;
6311 case 5:
6312 CP0_CHECK(ctx->insn_flags & ASE_MT);
6313 gen_helper_dmfc0_tccontext(arg, cpu_env);
6314 rn = "TCContext";
6315 break;
6316 case 6:
6317 CP0_CHECK(ctx->insn_flags & ASE_MT);
6318 gen_helper_dmfc0_tcschedule(arg, cpu_env);
6319 rn = "TCSchedule";
6320 break;
6321 case 7:
6322 CP0_CHECK(ctx->insn_flags & ASE_MT);
6323 gen_helper_dmfc0_tcschefback(arg, cpu_env);
6324 rn = "TCScheFBack";
6325 break;
6326 default:
6327 goto cp0_unimplemented;
6328 }
6329 break;
6330 case 3:
6331 switch (sel) {
6332 case 0:
6333 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
6334 rn = "EntryLo1";
6335 break;
6336 default:
6337 goto cp0_unimplemented;
6338 }
6339 break;
6340 case 4:
6341 switch (sel) {
6342 case 0:
6343 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
6344 rn = "Context";
6345 break;
6346 case 1:
6347 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
6348 rn = "ContextConfig";
6349 goto cp0_unimplemented;
6350 // break;
6351 case 2:
6352 CP0_CHECK(ctx->ulri);
6353 tcg_gen_ld_tl(arg, cpu_env,
6354 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6355 rn = "UserLocal";
6356 break;
6357 default:
6358 goto cp0_unimplemented;
6359 }
6360 break;
6361 case 5:
6362 switch (sel) {
6363 case 0:
6364 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
6365 rn = "PageMask";
6366 break;
6367 case 1:
6368 check_insn(ctx, ISA_MIPS32R2);
6369 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
6370 rn = "PageGrain";
6371 break;
6372 default:
6373 goto cp0_unimplemented;
6374 }
6375 break;
6376 case 6:
6377 switch (sel) {
6378 case 0:
6379 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
6380 rn = "Wired";
6381 break;
6382 case 1:
6383 check_insn(ctx, ISA_MIPS32R2);
6384 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
6385 rn = "SRSConf0";
6386 break;
6387 case 2:
6388 check_insn(ctx, ISA_MIPS32R2);
6389 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
6390 rn = "SRSConf1";
6391 break;
6392 case 3:
6393 check_insn(ctx, ISA_MIPS32R2);
6394 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
6395 rn = "SRSConf2";
6396 break;
6397 case 4:
6398 check_insn(ctx, ISA_MIPS32R2);
6399 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
6400 rn = "SRSConf3";
6401 break;
6402 case 5:
6403 check_insn(ctx, ISA_MIPS32R2);
6404 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
6405 rn = "SRSConf4";
6406 break;
6407 default:
6408 goto cp0_unimplemented;
6409 }
6410 break;
6411 case 7:
6412 switch (sel) {
6413 case 0:
6414 check_insn(ctx, ISA_MIPS32R2);
6415 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
6416 rn = "HWREna";
6417 break;
6418 default:
6419 goto cp0_unimplemented;
6420 }
6421 break;
6422 case 8:
6423 switch (sel) {
6424 case 0:
6425 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
6426 rn = "BadVAddr";
6427 break;
6428 case 1:
6429 CP0_CHECK(ctx->bi);
6430 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
6431 rn = "BadInstr";
6432 break;
6433 case 2:
6434 CP0_CHECK(ctx->bp);
6435 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
6436 rn = "BadInstrP";
6437 break;
6438 default:
6439 goto cp0_unimplemented;
6440 }
6441 break;
6442 case 9:
6443 switch (sel) {
6444 case 0:
6445 /* Mark as an IO operation because we read the time. */
6446 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6447 gen_io_start();
6448 }
6449 gen_helper_mfc0_count(arg, cpu_env);
6450 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6451 gen_io_end();
6452 }
6453 /* Break the TB to be able to take timer interrupts immediately
6454 after reading count. */
6455 ctx->bstate = BS_STOP;
6456 rn = "Count";
6457 break;
6458 /* 6,7 are implementation dependent */
6459 default:
6460 goto cp0_unimplemented;
6461 }
6462 break;
6463 case 10:
6464 switch (sel) {
6465 case 0:
6466 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
6467 rn = "EntryHi";
6468 break;
6469 default:
6470 goto cp0_unimplemented;
6471 }
6472 break;
6473 case 11:
6474 switch (sel) {
6475 case 0:
6476 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
6477 rn = "Compare";
6478 break;
6479 /* 6,7 are implementation dependent */
6480 default:
6481 goto cp0_unimplemented;
6482 }
6483 break;
6484 case 12:
6485 switch (sel) {
6486 case 0:
6487 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
6488 rn = "Status";
6489 break;
6490 case 1:
6491 check_insn(ctx, ISA_MIPS32R2);
6492 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
6493 rn = "IntCtl";
6494 break;
6495 case 2:
6496 check_insn(ctx, ISA_MIPS32R2);
6497 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
6498 rn = "SRSCtl";
6499 break;
6500 case 3:
6501 check_insn(ctx, ISA_MIPS32R2);
6502 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6503 rn = "SRSMap";
6504 break;
6505 default:
6506 goto cp0_unimplemented;
6507 }
6508 break;
6509 case 13:
6510 switch (sel) {
6511 case 0:
6512 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
6513 rn = "Cause";
6514 break;
6515 default:
6516 goto cp0_unimplemented;
6517 }
6518 break;
6519 case 14:
6520 switch (sel) {
6521 case 0:
6522 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
6523 rn = "EPC";
6524 break;
6525 default:
6526 goto cp0_unimplemented;
6527 }
6528 break;
6529 case 15:
6530 switch (sel) {
6531 case 0:
6532 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
6533 rn = "PRid";
6534 break;
6535 case 1:
6536 check_insn(ctx, ISA_MIPS32R2);
6537 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
6538 rn = "EBase";
6539 break;
6540 default:
6541 goto cp0_unimplemented;
6542 }
6543 break;
6544 case 16:
6545 switch (sel) {
6546 case 0:
6547 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
6548 rn = "Config";
6549 break;
6550 case 1:
6551 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
6552 rn = "Config1";
6553 break;
6554 case 2:
6555 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
6556 rn = "Config2";
6557 break;
6558 case 3:
6559 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
6560 rn = "Config3";
6561 break;
6562 case 4:
6563 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
6564 rn = "Config4";
6565 break;
6566 case 5:
6567 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
6568 rn = "Config5";
6569 break;
6570 /* 6,7 are implementation dependent */
6571 case 6:
6572 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
6573 rn = "Config6";
6574 break;
6575 case 7:
6576 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
6577 rn = "Config7";
6578 break;
6579 default:
6580 goto cp0_unimplemented;
6581 }
6582 break;
6583 case 17:
6584 switch (sel) {
6585 case 0:
6586 gen_helper_dmfc0_lladdr(arg, cpu_env);
6587 rn = "LLAddr";
6588 break;
6589 default:
6590 goto cp0_unimplemented;
6591 }
6592 break;
6593 case 18:
6594 switch (sel) {
6595 case 0 ... 7:
6596 gen_helper_1e0i(dmfc0_watchlo, arg, sel);
6597 rn = "WatchLo";
6598 break;
6599 default:
6600 goto cp0_unimplemented;
6601 }
6602 break;
6603 case 19:
6604 switch (sel) {
6605 case 0 ... 7:
6606 gen_helper_1e0i(mfc0_watchhi, arg, sel);
6607 rn = "WatchHi";
6608 break;
6609 default:
6610 goto cp0_unimplemented;
6611 }
6612 break;
6613 case 20:
6614 switch (sel) {
6615 case 0:
6616 check_insn(ctx, ISA_MIPS3);
6617 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
6618 rn = "XContext";
6619 break;
6620 default:
6621 goto cp0_unimplemented;
6622 }
6623 break;
6624 case 21:
6625 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6626 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
6627 switch (sel) {
6628 case 0:
6629 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
6630 rn = "Framemask";
6631 break;
6632 default:
6633 goto cp0_unimplemented;
6634 }
6635 break;
6636 case 22:
6637 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6638 rn = "'Diagnostic"; /* implementation dependent */
6639 break;
6640 case 23:
6641 switch (sel) {
6642 case 0:
6643 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
6644 rn = "Debug";
6645 break;
6646 case 1:
6647 // gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
6648 rn = "TraceControl";
6649 // break;
6650 case 2:
6651 // gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
6652 rn = "TraceControl2";
6653 // break;
6654 case 3:
6655 // gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
6656 rn = "UserTraceData";
6657 // break;
6658 case 4:
6659 // gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
6660 rn = "TraceBPC";
6661 // break;
6662 default:
6663 goto cp0_unimplemented;
6664 }
6665 break;
6666 case 24:
6667 switch (sel) {
6668 case 0:
6669 /* EJTAG support */
6670 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
6671 rn = "DEPC";
6672 break;
6673 default:
6674 goto cp0_unimplemented;
6675 }
6676 break;
6677 case 25:
6678 switch (sel) {
6679 case 0:
6680 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
6681 rn = "Performance0";
6682 break;
6683 case 1:
6684 // gen_helper_dmfc0_performance1(arg);
6685 rn = "Performance1";
6686 // break;
6687 case 2:
6688 // gen_helper_dmfc0_performance2(arg);
6689 rn = "Performance2";
6690 // break;
6691 case 3:
6692 // gen_helper_dmfc0_performance3(arg);
6693 rn = "Performance3";
6694 // break;
6695 case 4:
6696 // gen_helper_dmfc0_performance4(arg);
6697 rn = "Performance4";
6698 // break;
6699 case 5:
6700 // gen_helper_dmfc0_performance5(arg);
6701 rn = "Performance5";
6702 // break;
6703 case 6:
6704 // gen_helper_dmfc0_performance6(arg);
6705 rn = "Performance6";
6706 // break;
6707 case 7:
6708 // gen_helper_dmfc0_performance7(arg);
6709 rn = "Performance7";
6710 // break;
6711 default:
6712 goto cp0_unimplemented;
6713 }
6714 break;
6715 case 26:
6716 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6717 rn = "ECC";
6718 break;
6719 case 27:
6720 switch (sel) {
6721 /* ignored */
6722 case 0 ... 3:
6723 tcg_gen_movi_tl(arg, 0); /* unimplemented */
6724 rn = "CacheErr";
6725 break;
6726 default:
6727 goto cp0_unimplemented;
6728 }
6729 break;
6730 case 28:
6731 switch (sel) {
6732 case 0:
6733 case 2:
6734 case 4:
6735 case 6:
6736 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
6737 rn = "TagLo";
6738 break;
6739 case 1:
6740 case 3:
6741 case 5:
6742 case 7:
6743 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
6744 rn = "DataLo";
6745 break;
6746 default:
6747 goto cp0_unimplemented;
6748 }
6749 break;
6750 case 29:
6751 switch (sel) {
6752 case 0:
6753 case 2:
6754 case 4:
6755 case 6:
6756 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
6757 rn = "TagHi";
6758 break;
6759 case 1:
6760 case 3:
6761 case 5:
6762 case 7:
6763 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
6764 rn = "DataHi";
6765 break;
6766 default:
6767 goto cp0_unimplemented;
6768 }
6769 break;
6770 case 30:
6771 switch (sel) {
6772 case 0:
6773 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6774 rn = "ErrorEPC";
6775 break;
6776 default:
6777 goto cp0_unimplemented;
6778 }
6779 break;
6780 case 31:
6781 switch (sel) {
6782 case 0:
6783 /* EJTAG support */
6784 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6785 rn = "DESAVE";
6786 break;
6787 case 2 ... 7:
6788 CP0_CHECK(ctx->kscrexist & (1 << sel));
6789 tcg_gen_ld_tl(arg, cpu_env,
6790 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
6791 rn = "KScratch";
6792 break;
6793 default:
6794 goto cp0_unimplemented;
6795 }
6796 break;
6797 default:
6798 goto cp0_unimplemented;
6799 }
6800 (void)rn; /* avoid a compiler warning */
6801 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
6802 return;
6803
6804 cp0_unimplemented:
6805 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
6806 gen_mfc0_unimplemented(ctx, arg);
6807 }
6808
6809 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6810 {
6811 const char *rn = "invalid";
6812
6813 if (sel != 0)
6814 check_insn(ctx, ISA_MIPS64);
6815
6816 if (ctx->tb->cflags & CF_USE_ICOUNT) {
6817 gen_io_start();
6818 }
6819
6820 switch (reg) {
6821 case 0:
6822 switch (sel) {
6823 case 0:
6824 gen_helper_mtc0_index(cpu_env, arg);
6825 rn = "Index";
6826 break;
6827 case 1:
6828 CP0_CHECK(ctx->insn_flags & ASE_MT);
6829 gen_helper_mtc0_mvpcontrol(cpu_env, arg);
6830 rn = "MVPControl";
6831 break;
6832 case 2:
6833 CP0_CHECK(ctx->insn_flags & ASE_MT);
6834 /* ignored */
6835 rn = "MVPConf0";
6836 break;
6837 case 3:
6838 CP0_CHECK(ctx->insn_flags & ASE_MT);
6839 /* ignored */
6840 rn = "MVPConf1";
6841 break;
6842 default:
6843 goto cp0_unimplemented;
6844 }
6845 break;
6846 case 1:
6847 switch (sel) {
6848 case 0:
6849 /* ignored */
6850 rn = "Random";
6851 break;
6852 case 1:
6853 CP0_CHECK(ctx->insn_flags & ASE_MT);
6854 gen_helper_mtc0_vpecontrol(cpu_env, arg);
6855 rn = "VPEControl";
6856 break;
6857 case 2:
6858 CP0_CHECK(ctx->insn_flags & ASE_MT);
6859 gen_helper_mtc0_vpeconf0(cpu_env, arg);
6860 rn = "VPEConf0";
6861 break;
6862 case 3:
6863 CP0_CHECK(ctx->insn_flags & ASE_MT);
6864 gen_helper_mtc0_vpeconf1(cpu_env, arg);
6865 rn = "VPEConf1";
6866 break;
6867 case 4:
6868 CP0_CHECK(ctx->insn_flags & ASE_MT);
6869 gen_helper_mtc0_yqmask(cpu_env, arg);
6870 rn = "YQMask";
6871 break;
6872 case 5:
6873 CP0_CHECK(ctx->insn_flags & ASE_MT);
6874 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
6875 rn = "VPESchedule";
6876 break;
6877 case 6:
6878 CP0_CHECK(ctx->insn_flags & ASE_MT);
6879 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
6880 rn = "VPEScheFBack";
6881 break;
6882 case 7:
6883 CP0_CHECK(ctx->insn_flags & ASE_MT);
6884 gen_helper_mtc0_vpeopt(cpu_env, arg);
6885 rn = "VPEOpt";
6886 break;
6887 default:
6888 goto cp0_unimplemented;
6889 }
6890 break;
6891 case 2:
6892 switch (sel) {
6893 case 0:
6894 gen_helper_dmtc0_entrylo0(cpu_env, arg);
6895 rn = "EntryLo0";
6896 break;
6897 case 1:
6898 CP0_CHECK(ctx->insn_flags & ASE_MT);
6899 gen_helper_mtc0_tcstatus(cpu_env, arg);
6900 rn = "TCStatus";
6901 break;
6902 case 2:
6903 CP0_CHECK(ctx->insn_flags & ASE_MT);
6904 gen_helper_mtc0_tcbind(cpu_env, arg);
6905 rn = "TCBind";
6906 break;
6907 case 3:
6908 CP0_CHECK(ctx->insn_flags & ASE_MT);
6909 gen_helper_mtc0_tcrestart(cpu_env, arg);
6910 rn = "TCRestart";
6911 break;
6912 case 4:
6913 CP0_CHECK(ctx->insn_flags & ASE_MT);
6914 gen_helper_mtc0_tchalt(cpu_env, arg);
6915 rn = "TCHalt";
6916 break;
6917 case 5:
6918 CP0_CHECK(ctx->insn_flags & ASE_MT);
6919 gen_helper_mtc0_tccontext(cpu_env, arg);
6920 rn = "TCContext";
6921 break;
6922 case 6:
6923 CP0_CHECK(ctx->insn_flags & ASE_MT);
6924 gen_helper_mtc0_tcschedule(cpu_env, arg);
6925 rn = "TCSchedule";
6926 break;
6927 case 7:
6928 CP0_CHECK(ctx->insn_flags & ASE_MT);
6929 gen_helper_mtc0_tcschefback(cpu_env, arg);
6930 rn = "TCScheFBack";
6931 break;
6932 default:
6933 goto cp0_unimplemented;
6934 }
6935 break;
6936 case 3:
6937 switch (sel) {
6938 case 0:
6939 gen_helper_dmtc0_entrylo1(cpu_env, arg);
6940 rn = "EntryLo1";
6941 break;
6942 default:
6943 goto cp0_unimplemented;
6944 }
6945 break;
6946 case 4:
6947 switch (sel) {
6948 case 0:
6949 gen_helper_mtc0_context(cpu_env, arg);
6950 rn = "Context";
6951 break;
6952 case 1:
6953 // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
6954 rn = "ContextConfig";
6955 goto cp0_unimplemented;
6956 // break;
6957 case 2:
6958 CP0_CHECK(ctx->ulri);
6959 tcg_gen_st_tl(arg, cpu_env,
6960 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6961 rn = "UserLocal";
6962 break;
6963 default:
6964 goto cp0_unimplemented;
6965 }
6966 break;
6967 case 5:
6968 switch (sel) {
6969 case 0:
6970 gen_helper_mtc0_pagemask(cpu_env, arg);
6971 rn = "PageMask";
6972 break;
6973 case 1:
6974 check_insn(ctx, ISA_MIPS32R2);
6975 gen_helper_mtc0_pagegrain(cpu_env, arg);
6976 rn = "PageGrain";
6977 break;
6978 default:
6979 goto cp0_unimplemented;
6980 }
6981 break;
6982 case 6:
6983 switch (sel) {
6984 case 0:
6985 gen_helper_mtc0_wired(cpu_env, arg);
6986 rn = "Wired";
6987 break;
6988 case 1:
6989 check_insn(ctx, ISA_MIPS32R2);
6990 gen_helper_mtc0_srsconf0(cpu_env, arg);
6991 rn = "SRSConf0";
6992 break;
6993 case 2:
6994 check_insn(ctx, ISA_MIPS32R2);
6995 gen_helper_mtc0_srsconf1(cpu_env, arg);
6996 rn = "SRSConf1";
6997 break;
6998 case 3:
6999 check_insn(ctx, ISA_MIPS32R2);
7000 gen_helper_mtc0_srsconf2(cpu_env, arg);
7001 rn = "SRSConf2";
7002 break;
7003 case 4:
7004 check_insn(ctx, ISA_MIPS32R2);
7005 gen_helper_mtc0_srsconf3(cpu_env, arg);
7006 rn = "SRSConf3";
7007 break;
7008 case 5:
7009 check_insn(ctx, ISA_MIPS32R2);
7010 gen_helper_mtc0_srsconf4(cpu_env, arg);
7011 rn = "SRSConf4";
7012 break;
7013 default:
7014 goto cp0_unimplemented;
7015 }
7016 break;
7017 case 7:
7018 switch (sel) {
7019 case 0:
7020 check_insn(ctx, ISA_MIPS32R2);
7021 gen_helper_mtc0_hwrena(cpu_env, arg);
7022 ctx->bstate = BS_STOP;
7023 rn = "HWREna";
7024 break;
7025 default:
7026 goto cp0_unimplemented;
7027 }
7028 break;
7029 case 8:
7030 switch (sel) {
7031 case 0:
7032 /* ignored */
7033 rn = "BadVAddr";
7034 break;
7035 case 1:
7036 /* ignored */
7037 rn = "BadInstr";
7038 break;
7039 case 2:
7040 /* ignored */
7041 rn = "BadInstrP";
7042 break;
7043 default:
7044 goto cp0_unimplemented;
7045 }
7046 break;
7047 case 9:
7048 switch (sel) {
7049 case 0:
7050 gen_helper_mtc0_count(cpu_env, arg);
7051 rn = "Count";
7052 break;
7053 /* 6,7 are implementation dependent */
7054 default:
7055 goto cp0_unimplemented;
7056 }
7057 /* Stop translation as we may have switched the execution mode */
7058 ctx->bstate = BS_STOP;
7059 break;
7060 case 10:
7061 switch (sel) {
7062 case 0:
7063 gen_helper_mtc0_entryhi(cpu_env, arg);
7064 rn = "EntryHi";
7065 break;
7066 default:
7067 goto cp0_unimplemented;
7068 }
7069 break;
7070 case 11:
7071 switch (sel) {
7072 case 0:
7073 gen_helper_mtc0_compare(cpu_env, arg);
7074 rn = "Compare";
7075 break;
7076 /* 6,7 are implementation dependent */
7077 default:
7078 goto cp0_unimplemented;
7079 }
7080 /* Stop translation as we may have switched the execution mode */
7081 ctx->bstate = BS_STOP;
7082 break;
7083 case 12:
7084 switch (sel) {
7085 case 0:
7086 save_cpu_state(ctx, 1);
7087 gen_helper_mtc0_status(cpu_env, arg);
7088 /* BS_STOP isn't good enough here, hflags may have changed. */
7089 gen_save_pc(ctx->pc + 4);
7090 ctx->bstate = BS_EXCP;
7091 rn = "Status";
7092 break;
7093 case 1:
7094 check_insn(ctx, ISA_MIPS32R2);
7095 gen_helper_mtc0_intctl(cpu_env, arg);
7096 /* Stop translation as we may have switched the execution mode */
7097 ctx->bstate = BS_STOP;
7098 rn = "IntCtl";
7099 break;
7100 case 2:
7101 check_insn(ctx, ISA_MIPS32R2);
7102 gen_helper_mtc0_srsctl(cpu_env, arg);
7103 /* Stop translation as we may have switched the execution mode */
7104 ctx->bstate = BS_STOP;
7105 rn = "SRSCtl";
7106 break;
7107 case 3:
7108 check_insn(ctx, ISA_MIPS32R2);
7109 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7110 /* Stop translation as we may have switched the execution mode */
7111 ctx->bstate = BS_STOP;
7112 rn = "SRSMap";
7113 break;
7114 default:
7115 goto cp0_unimplemented;
7116 }
7117 break;
7118 case 13:
7119 switch (sel) {
7120 case 0:
7121 save_cpu_state(ctx, 1);
7122 /* Mark as an IO operation because we may trigger a software
7123 interrupt. */
7124 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7125 gen_io_start();
7126 }
7127 gen_helper_mtc0_cause(cpu_env, arg);
7128 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7129 gen_io_end();
7130 }
7131 /* Stop translation as we may have triggered an intetrupt */
7132 ctx->bstate = BS_STOP;
7133 rn = "Cause";
7134 break;
7135 default:
7136 goto cp0_unimplemented;
7137 }
7138 break;
7139 case 14:
7140 switch (sel) {
7141 case 0:
7142 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
7143 rn = "EPC";
7144 break;
7145 default:
7146 goto cp0_unimplemented;
7147 }
7148 break;
7149 case 15:
7150 switch (sel) {
7151 case 0:
7152 /* ignored */
7153 rn = "PRid";
7154 break;
7155 case 1:
7156 check_insn(ctx, ISA_MIPS32R2);
7157 gen_helper_mtc0_ebase(cpu_env, arg);
7158 rn = "EBase";
7159 break;
7160 default:
7161 goto cp0_unimplemented;
7162 }
7163 break;
7164 case 16:
7165 switch (sel) {
7166 case 0:
7167 gen_helper_mtc0_config0(cpu_env, arg);
7168 rn = "Config";
7169 /* Stop translation as we may have switched the execution mode */
7170 ctx->bstate = BS_STOP;
7171 break;
7172 case 1:
7173 /* ignored, read only */
7174 rn = "Config1";
7175 break;
7176 case 2:
7177 gen_helper_mtc0_config2(cpu_env, arg);
7178 rn = "Config2";
7179 /* Stop translation as we may have switched the execution mode */
7180 ctx->bstate = BS_STOP;
7181 break;
7182 case 3:
7183 gen_helper_mtc0_config3(cpu_env, arg);
7184 rn = "Config3";
7185 /* Stop translation as we may have switched the execution mode */
7186 ctx->bstate = BS_STOP;
7187 break;
7188 case 4:
7189 /* currently ignored */
7190 rn = "Config4";
7191 break;
7192 case 5:
7193 gen_helper_mtc0_config5(cpu_env, arg);
7194 rn = "Config5";
7195 /* Stop translation as we may have switched the execution mode */
7196 ctx->bstate = BS_STOP;
7197 break;
7198 /* 6,7 are implementation dependent */
7199 default:
7200 rn = "Invalid config selector";
7201 goto cp0_unimplemented;
7202 }
7203 break;
7204 case 17:
7205 switch (sel) {
7206 case 0:
7207 gen_helper_mtc0_lladdr(cpu_env, arg);
7208 rn = "LLAddr";
7209 break;
7210 default:
7211 goto cp0_unimplemented;
7212 }
7213 break;
7214 case 18:
7215 switch (sel) {
7216 case 0 ... 7:
7217 gen_helper_0e1i(mtc0_watchlo, arg, sel);
7218 rn = "WatchLo";
7219 break;
7220 default:
7221 goto cp0_unimplemented;
7222 }
7223 break;
7224 case 19:
7225 switch (sel) {
7226 case 0 ... 7:
7227 gen_helper_0e1i(mtc0_watchhi, arg, sel);
7228 rn = "WatchHi";
7229 break;
7230 default:
7231 goto cp0_unimplemented;
7232 }
7233 break;
7234 case 20:
7235 switch (sel) {
7236 case 0:
7237 check_insn(ctx, ISA_MIPS3);
7238 gen_helper_mtc0_xcontext(cpu_env, arg);
7239 rn = "XContext";
7240 break;
7241 default:
7242 goto cp0_unimplemented;
7243 }
7244 break;
7245 case 21:
7246 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7247 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
7248 switch (sel) {
7249 case 0:
7250 gen_helper_mtc0_framemask(cpu_env, arg);
7251 rn = "Framemask";
7252 break;
7253 default:
7254 goto cp0_unimplemented;
7255 }
7256 break;
7257 case 22:
7258 /* ignored */
7259 rn = "Diagnostic"; /* implementation dependent */
7260 break;
7261 case 23:
7262 switch (sel) {
7263 case 0:
7264 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
7265 /* BS_STOP isn't good enough here, hflags may have changed. */
7266 gen_save_pc(ctx->pc + 4);
7267 ctx->bstate = BS_EXCP;
7268 rn = "Debug";
7269 break;
7270 case 1:
7271 // gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
7272 /* Stop translation as we may have switched the execution mode */
7273 ctx->bstate = BS_STOP;
7274 rn = "TraceControl";
7275 // break;
7276 case 2:
7277 // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
7278 /* Stop translation as we may have switched the execution mode */
7279 ctx->bstate = BS_STOP;
7280 rn = "TraceControl2";
7281 // break;
7282 case 3:
7283 // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
7284 /* Stop translation as we may have switched the execution mode */
7285 ctx->bstate = BS_STOP;
7286 rn = "UserTraceData";
7287 // break;
7288 case 4:
7289 // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
7290 /* Stop translation as we may have switched the execution mode */
7291 ctx->bstate = BS_STOP;
7292 rn = "TraceBPC";
7293 // break;
7294 default:
7295 goto cp0_unimplemented;
7296 }
7297 break;
7298 case 24:
7299 switch (sel) {
7300 case 0:
7301 /* EJTAG support */
7302 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
7303 rn = "DEPC";
7304 break;
7305 default:
7306 goto cp0_unimplemented;
7307 }
7308 break;
7309 case 25:
7310 switch (sel) {
7311 case 0:
7312 gen_helper_mtc0_performance0(cpu_env, arg);
7313 rn = "Performance0";
7314 break;
7315 case 1:
7316 // gen_helper_mtc0_performance1(cpu_env, arg);
7317 rn = "Performance1";
7318 // break;
7319 case 2:
7320 // gen_helper_mtc0_performance2(cpu_env, arg);
7321 rn = "Performance2";
7322 // break;
7323 case 3:
7324 // gen_helper_mtc0_performance3(cpu_env, arg);
7325 rn = "Performance3";
7326 // break;
7327 case 4:
7328 // gen_helper_mtc0_performance4(cpu_env, arg);
7329 rn = "Performance4";
7330 // break;
7331 case 5:
7332 // gen_helper_mtc0_performance5(cpu_env, arg);
7333 rn = "Performance5";
7334 // break;
7335 case 6:
7336 // gen_helper_mtc0_performance6(cpu_env, arg);
7337 rn = "Performance6";
7338 // break;
7339 case 7:
7340 // gen_helper_mtc0_performance7(cpu_env, arg);
7341 rn = "Performance7";
7342 // break;
7343 default:
7344 goto cp0_unimplemented;
7345 }
7346 break;
7347 case 26:
7348 /* ignored */
7349 rn = "ECC";
7350 break;
7351 case 27:
7352 switch (sel) {
7353 case 0 ... 3:
7354 /* ignored */
7355 rn = "CacheErr";
7356 break;
7357 default:
7358 goto cp0_unimplemented;
7359 }
7360 break;
7361 case 28:
7362 switch (sel) {
7363 case 0:
7364 case 2:
7365 case 4:
7366 case 6:
7367 gen_helper_mtc0_taglo(cpu_env, arg);
7368 rn = "TagLo";
7369 break;
7370 case 1:
7371 case 3:
7372 case 5:
7373 case 7:
7374 gen_helper_mtc0_datalo(cpu_env, arg);
7375 rn = "DataLo";
7376 break;
7377 default:
7378 goto cp0_unimplemented;
7379 }
7380 break;
7381 case 29:
7382 switch (sel) {
7383 case 0:
7384 case 2:
7385 case 4:
7386 case 6:
7387 gen_helper_mtc0_taghi(cpu_env, arg);
7388 rn = "TagHi";
7389 break;
7390 case 1:
7391 case 3:
7392 case 5:
7393 case 7:
7394 gen_helper_mtc0_datahi(cpu_env, arg);
7395 rn = "DataHi";
7396 break;
7397 default:
7398 rn = "invalid sel";
7399 goto cp0_unimplemented;
7400 }
7401 break;
7402 case 30:
7403 switch (sel) {
7404 case 0:
7405 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7406 rn = "ErrorEPC";
7407 break;
7408 default:
7409 goto cp0_unimplemented;
7410 }
7411 break;
7412 case 31:
7413 switch (sel) {
7414 case 0:
7415 /* EJTAG support */
7416 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7417 rn = "DESAVE";
7418 break;
7419 case 2 ... 7:
7420 CP0_CHECK(ctx->kscrexist & (1 << sel));
7421 tcg_gen_st_tl(arg, cpu_env,
7422 offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
7423 rn = "KScratch";
7424 break;
7425 default:
7426 goto cp0_unimplemented;
7427 }
7428 /* Stop translation as we may have switched the execution mode */
7429 ctx->bstate = BS_STOP;
7430 break;
7431 default:
7432 goto cp0_unimplemented;
7433 }
7434 (void)rn; /* avoid a compiler warning */
7435 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
7436 /* For simplicity assume that all writes can cause interrupts. */
7437 if (ctx->tb->cflags & CF_USE_ICOUNT) {
7438 gen_io_end();
7439 ctx->bstate = BS_STOP;
7440 }
7441 return;
7442
7443 cp0_unimplemented:
7444 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
7445 }
7446 #endif /* TARGET_MIPS64 */
7447
7448 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
7449 int u, int sel, int h)
7450 {
7451 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
7452 TCGv t0 = tcg_temp_local_new();
7453
7454 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
7455 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
7456 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
7457 tcg_gen_movi_tl(t0, -1);
7458 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
7459 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
7460 tcg_gen_movi_tl(t0, -1);
7461 else if (u == 0) {
7462 switch (rt) {
7463 case 1:
7464 switch (sel) {
7465 case 1:
7466 gen_helper_mftc0_vpecontrol(t0, cpu_env);
7467 break;
7468 case 2:
7469 gen_helper_mftc0_vpeconf0(t0, cpu_env);
7470 break;
7471 default:
7472 goto die;
7473 break;
7474 }
7475 break;
7476 case 2:
7477 switch (sel) {
7478 case 1:
7479 gen_helper_mftc0_tcstatus(t0, cpu_env);
7480 break;
7481 case 2:
7482 gen_helper_mftc0_tcbind(t0, cpu_env);
7483 break;
7484 case 3:
7485 gen_helper_mftc0_tcrestart(t0, cpu_env);
7486 break;
7487 case 4:
7488 gen_helper_mftc0_tchalt(t0, cpu_env);
7489 break;
7490 case 5:
7491 gen_helper_mftc0_tccontext(t0, cpu_env);
7492 break;
7493 case 6:
7494 gen_helper_mftc0_tcschedule(t0, cpu_env);
7495 break;
7496 case 7:
7497 gen_helper_mftc0_tcschefback(t0, cpu_env);
7498 break;
7499 default:
7500 gen_mfc0(ctx, t0, rt, sel);
7501 break;
7502 }
7503 break;
7504 case 10:
7505 switch (sel) {
7506 case 0:
7507 gen_helper_mftc0_entryhi(t0, cpu_env);
7508 break;
7509 default:
7510 gen_mfc0(ctx, t0, rt, sel);
7511 break;
7512 }
7513 case 12:
7514 switch (sel) {
7515 case 0:
7516 gen_helper_mftc0_status(t0, cpu_env);
7517 break;
7518 default:
7519 gen_mfc0(ctx, t0, rt, sel);
7520 break;
7521 }
7522 case 13:
7523 switch (sel) {
7524 case 0:
7525 gen_helper_mftc0_cause(t0, cpu_env);
7526 break;
7527 default:
7528 goto die;
7529 break;
7530 }
7531 break;
7532 case 14:
7533 switch (sel) {
7534 case 0:
7535 gen_helper_mftc0_epc(t0, cpu_env);
7536 break;
7537 default:
7538 goto die;
7539 break;
7540 }
7541 break;
7542 case 15:
7543 switch (sel) {
7544 case 1:
7545 gen_helper_mftc0_ebase(t0, cpu_env);
7546 break;
7547 default:
7548 goto die;
7549 break;
7550 }
7551 break;
7552 case 16:
7553 switch (sel) {
7554 case 0 ... 7:
7555 gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel));
7556 break;
7557 default:
7558 goto die;
7559 break;
7560 }
7561 break;
7562 case 23:
7563 switch (sel) {
7564 case 0:
7565 gen_helper_mftc0_debug(t0, cpu_env);
7566 break;
7567 default:
7568 gen_mfc0(ctx, t0, rt, sel);
7569 break;
7570 }
7571 break;
7572 default:
7573 gen_mfc0(ctx, t0, rt, sel);
7574 }
7575 } else switch (sel) {
7576 /* GPR registers. */
7577 case 0:
7578 gen_helper_1e0i(mftgpr, t0, rt);
7579 break;
7580 /* Auxiliary CPU registers */
7581 case 1:
7582 switch (rt) {
7583 case 0:
7584 gen_helper_1e0i(mftlo, t0, 0);
7585 break;
7586 case 1:
7587 gen_helper_1e0i(mfthi, t0, 0);
7588 break;
7589 case 2:
7590 gen_helper_1e0i(mftacx, t0, 0);
7591 break;
7592 case 4:
7593 gen_helper_1e0i(mftlo, t0, 1);
7594 break;
7595 case 5:
7596 gen_helper_1e0i(mfthi, t0, 1);
7597 break;
7598 case 6:
7599 gen_helper_1e0i(mftacx, t0, 1);
7600 break;
7601 case 8:
7602 gen_helper_1e0i(mftlo, t0, 2);
7603 break;
7604 case 9:
7605 gen_helper_1e0i(mfthi, t0, 2);
7606 break;
7607 case 10:
7608 gen_helper_1e0i(mftacx, t0, 2);
7609 break;
7610 case 12:
7611 gen_helper_1e0i(mftlo, t0, 3);
7612 break;
7613 case 13:
7614 gen_helper_1e0i(mfthi, t0, 3);
7615 break;
7616 case 14:
7617 gen_helper_1e0i(mftacx, t0, 3);
7618 break;
7619 case 16:
7620 gen_helper_mftdsp(t0, cpu_env);
7621 break;
7622 default:
7623 goto die;
7624 }
7625 break;
7626 /* Floating point (COP1). */
7627 case 2:
7628 /* XXX: For now we support only a single FPU context. */
7629 if (h == 0) {
7630 TCGv_i32 fp0 = tcg_temp_new_i32();
7631
7632 gen_load_fpr32(ctx, fp0, rt);
7633 tcg_gen_ext_i32_tl(t0, fp0);
7634 tcg_temp_free_i32(fp0);
7635 } else {
7636 TCGv_i32 fp0 = tcg_temp_new_i32();
7637
7638 gen_load_fpr32h(ctx, fp0, rt);
7639 tcg_gen_ext_i32_tl(t0, fp0);
7640 tcg_temp_free_i32(fp0);
7641 }
7642 break;
7643 case 3:
7644 /* XXX: For now we support only a single FPU context. */
7645 gen_helper_1e0i(cfc1, t0, rt);
7646 break;
7647 /* COP2: Not implemented. */
7648 case 4:
7649 case 5:
7650 /* fall through */
7651 default:
7652 goto die;
7653 }
7654 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
7655 gen_store_gpr(t0, rd);
7656 tcg_temp_free(t0);
7657 return;
7658
7659 die:
7660 tcg_temp_free(t0);
7661 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
7662 generate_exception(ctx, EXCP_RI);
7663 }
7664
7665 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
7666 int u, int sel, int h)
7667 {
7668 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
7669 TCGv t0 = tcg_temp_local_new();
7670
7671 gen_load_gpr(t0, rt);
7672 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
7673 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
7674 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
7675 /* NOP */ ;
7676 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
7677 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
7678 /* NOP */ ;
7679 else if (u == 0) {
7680 switch (rd) {
7681 case 1:
7682 switch (sel) {
7683 case 1:
7684 gen_helper_mttc0_vpecontrol(cpu_env, t0);
7685 break;
7686 case 2:
7687 gen_helper_mttc0_vpeconf0(cpu_env, t0);
7688 break;
7689 default:
7690 goto die;
7691 break;
7692 }
7693 break;
7694 case 2:
7695 switch (sel) {
7696 case 1:
7697 gen_helper_mttc0_tcstatus(cpu_env, t0);
7698 break;
7699 case 2:
7700 gen_helper_mttc0_tcbind(cpu_env, t0);
7701 break;
7702 case 3:
7703 gen_helper_mttc0_tcrestart(cpu_env, t0);
7704 break;
7705 case 4:
7706 gen_helper_mttc0_tchalt(cpu_env, t0);
7707 break;
7708 case 5:
7709 gen_helper_mttc0_tccontext(cpu_env, t0);
7710 break;
7711 case 6:
7712 gen_helper_mttc0_tcschedule(cpu_env, t0);
7713 break;
7714 case 7:
7715 gen_helper_mttc0_tcschefback(cpu_env, t0);
7716 break;
7717 default:
7718 gen_mtc0(ctx, t0, rd, sel);
7719 break;
7720 }
7721 break;
7722 case 10:
7723 switch (sel) {
7724 case 0:
7725 gen_helper_mttc0_entryhi(cpu_env, t0);
7726 break;
7727 default:
7728 gen_mtc0(ctx, t0, rd, sel);
7729 break;
7730 }
7731 case 12:
7732 switch (sel) {
7733 case 0:
7734 gen_helper_mttc0_status(cpu_env, t0);
7735 break;
7736 default:
7737 gen_mtc0(ctx, t0, rd, sel);
7738 break;
7739 }
7740 case 13:
7741 switch (sel) {
7742 case 0:
7743 gen_helper_mttc0_cause(cpu_env, t0);
7744 break;
7745 default:
7746 goto die;
7747 break;
7748 }
7749 break;
7750 case 15:
7751 switch (sel) {
7752 case 1:
7753 gen_helper_mttc0_ebase(cpu_env, t0);
7754 break;
7755 default:
7756 goto die;
7757 break;
7758 }
7759 break;
7760 case 23:
7761 switch (sel) {
7762 case 0:
7763 gen_helper_mttc0_debug(cpu_env, t0);
7764 break;
7765 default:
7766 gen_mtc0(ctx, t0, rd, sel);
7767 break;
7768 }
7769 break;
7770 default:
7771 gen_mtc0(ctx, t0, rd, sel);
7772 }
7773 } else switch (sel) {
7774 /* GPR registers. */
7775 case 0:
7776 gen_helper_0e1i(mttgpr, t0, rd);
7777 break;
7778 /* Auxiliary CPU registers */
7779 case 1:
7780 switch (rd) {
7781 case 0:
7782 gen_helper_0e1i(mttlo, t0, 0);
7783 break;
7784 case 1:
7785 gen_helper_0e1i(mtthi, t0, 0);
7786 break;
7787 case 2:
7788 gen_helper_0e1i(mttacx, t0, 0);
7789 break;
7790 case 4:
7791 gen_helper_0e1i(mttlo, t0, 1);
7792 break;
7793 case 5:
7794 gen_helper_0e1i(mtthi, t0, 1);
7795 break;
7796 case 6:
7797 gen_helper_0e1i(mttacx, t0, 1);
7798 break;
7799 case 8:
7800 gen_helper_0e1i(mttlo, t0, 2);
7801 break;
7802 case 9:
7803 gen_helper_0e1i(mtthi, t0, 2);
7804 break;
7805 case 10:
7806 gen_helper_0e1i(mttacx, t0, 2);
7807 break;
7808 case 12:
7809 gen_helper_0e1i(mttlo, t0, 3);
7810 break;
7811 case 13:
7812 gen_helper_0e1i(mtthi, t0, 3);
7813 break;
7814 case 14:
7815 gen_helper_0e1i(mttacx, t0, 3);
7816 break;
7817 case 16:
7818 gen_helper_mttdsp(cpu_env, t0);
7819 break;
7820 default:
7821 goto die;
7822 }
7823 break;
7824 /* Floating point (COP1). */
7825 case 2:
7826 /* XXX: For now we support only a single FPU context. */
7827 if (h == 0) {
7828 TCGv_i32 fp0 = tcg_temp_new_i32();
7829
7830 tcg_gen_trunc_tl_i32(fp0, t0);
7831 gen_store_fpr32(ctx, fp0, rd);
7832 tcg_temp_free_i32(fp0);
7833 } else {
7834 TCGv_i32 fp0 = tcg_temp_new_i32();
7835
7836 tcg_gen_trunc_tl_i32(fp0, t0);
7837 gen_store_fpr32h(ctx, fp0, rd);
7838 tcg_temp_free_i32(fp0);
7839 }
7840 break;
7841 case 3:
7842 /* XXX: For now we support only a single FPU context. */
7843 save_cpu_state(ctx, 1);
7844 {
7845 TCGv_i32 fs_tmp = tcg_const_i32(rd);
7846
7847 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
7848 tcg_temp_free_i32(fs_tmp);
7849 }
7850 /* Stop translation as we may have changed hflags */
7851 ctx->bstate = BS_STOP;
7852 break;
7853 /* COP2: Not implemented. */
7854 case 4:
7855 case 5:
7856 /* fall through */
7857 default:
7858 goto die;
7859 }
7860 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
7861 tcg_temp_free(t0);
7862 return;
7863
7864 die:
7865 tcg_temp_free(t0);
7866 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
7867 generate_exception(ctx, EXCP_RI);
7868 }
7869
7870 static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
7871 {
7872 const char *opn = "ldst";
7873
7874 check_cp0_enabled(ctx);
7875 switch (opc) {
7876 case OPC_MFC0:
7877 if (rt == 0) {
7878 /* Treat as NOP. */
7879 return;
7880 }
7881 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
7882 opn = "mfc0";
7883 break;
7884 case OPC_MTC0:
7885 {
7886 TCGv t0 = tcg_temp_new();
7887
7888 gen_load_gpr(t0, rt);
7889 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
7890 tcg_temp_free(t0);
7891 }
7892 opn = "mtc0";
7893 break;
7894 #if defined(TARGET_MIPS64)
7895 case OPC_DMFC0:
7896 check_insn(ctx, ISA_MIPS3);
7897 if (rt == 0) {
7898 /* Treat as NOP. */
7899 return;
7900 }
7901 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
7902 opn = "dmfc0";
7903 break;
7904 case OPC_DMTC0:
7905 check_insn(ctx, ISA_MIPS3);
7906 {
7907 TCGv t0 = tcg_temp_new();
7908
7909 gen_load_gpr(t0, rt);
7910 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
7911 tcg_temp_free(t0);
7912 }
7913 opn = "dmtc0";
7914 break;
7915 #endif
7916 case OPC_MFHC0:
7917 check_mvh(ctx);
7918 if (rt == 0) {
7919 /* Treat as NOP. */
7920 return;
7921 }
7922 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
7923 opn = "mfhc0";
7924 break;
7925 case OPC_MTHC0:
7926 check_mvh(ctx);
7927 {
7928 TCGv t0 = tcg_temp_new();
7929 gen_load_gpr(t0, rt);
7930 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
7931 tcg_temp_free(t0);
7932 }
7933 opn = "mthc0";
7934 break;
7935 case OPC_MFTR:
7936 check_insn(ctx, ASE_MT);
7937 if (rd == 0) {
7938 /* Treat as NOP. */
7939 return;
7940 }
7941 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
7942 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
7943 opn = "mftr";
7944 break;
7945 case OPC_MTTR:
7946 check_insn(ctx, ASE_MT);
7947 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
7948 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
7949 opn = "mttr";
7950 break;
7951 case OPC_TLBWI:
7952 opn = "tlbwi";
7953 if (!env->tlb->helper_tlbwi)
7954 goto die;
7955 gen_helper_tlbwi(cpu_env);
7956 break;
7957 case OPC_TLBINV:
7958 opn = "tlbinv";
7959 if (ctx->ie >= 2) {
7960 if (!env->tlb->helper_tlbinv) {
7961 goto die;
7962 }
7963 gen_helper_tlbinv(cpu_env);
7964 } /* treat as nop if TLBINV not supported */
7965 break;
7966 case OPC_TLBINVF:
7967 opn = "tlbinvf";
7968 if (ctx->ie >= 2) {
7969 if (!env->tlb->helper_tlbinvf) {
7970 goto die;
7971 }
7972 gen_helper_tlbinvf(cpu_env);
7973 } /* treat as nop if TLBINV not supported */
7974 break;
7975 case OPC_TLBWR:
7976 opn = "tlbwr";
7977 if (!env->tlb->helper_tlbwr)
7978 goto die;
7979 gen_helper_tlbwr(cpu_env);
7980 break;
7981 case OPC_TLBP:
7982 opn = "tlbp";
7983 if (!env->tlb->helper_tlbp)
7984 goto die;
7985 gen_helper_tlbp(cpu_env);
7986 break;
7987 case OPC_TLBR:
7988 opn = "tlbr";
7989 if (!env->tlb->helper_tlbr)
7990 goto die;
7991 gen_helper_tlbr(cpu_env);
7992 break;
7993 case OPC_ERET: /* OPC_ERETNC */
7994 if ((ctx->insn_flags & ISA_MIPS32R6) &&
7995 (ctx->hflags & MIPS_HFLAG_BMASK)) {
7996 goto die;
7997 } else {
7998 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6;
7999 if (ctx->opcode & (1 << bit_shift)) {
8000 /* OPC_ERETNC */
8001 opn = "eretnc";
8002 check_insn(ctx, ISA_MIPS32R5);
8003 gen_helper_eretnc(cpu_env);
8004 } else {
8005 /* OPC_ERET */
8006 opn = "eret";
8007 check_insn(ctx, ISA_MIPS2);
8008 gen_helper_eret(cpu_env);
8009 }
8010 ctx->bstate = BS_EXCP;
8011 }
8012 break;
8013 case OPC_DERET:
8014 opn = "deret";
8015 check_insn(ctx, ISA_MIPS32);
8016 if ((ctx->insn_flags & ISA_MIPS32R6) &&
8017 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8018 goto die;
8019 }
8020 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
8021 MIPS_INVAL(opn);
8022 generate_exception(ctx, EXCP_RI);
8023 } else {
8024 gen_helper_deret(cpu_env);
8025 ctx->bstate = BS_EXCP;
8026 }
8027 break;
8028 case OPC_WAIT:
8029 opn = "wait";
8030 check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
8031 if ((ctx->insn_flags & ISA_MIPS32R6) &&
8032 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8033 goto die;
8034 }
8035 /* If we get an exception, we want to restart at next instruction */
8036 ctx->pc += 4;
8037 save_cpu_state(ctx, 1);
8038 ctx->pc -= 4;
8039 gen_helper_wait(cpu_env);
8040 ctx->bstate = BS_EXCP;
8041 break;
8042 default:
8043 die:
8044 MIPS_INVAL(opn);
8045 generate_exception(ctx, EXCP_RI);
8046 return;
8047 }
8048 (void)opn; /* avoid a compiler warning */
8049 }
8050 #endif /* !CONFIG_USER_ONLY */
8051
8052 /* CP1 Branches (before delay slot) */
8053 static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
8054 int32_t cc, int32_t offset)
8055 {
8056 target_ulong btarget;
8057 TCGv_i32 t0 = tcg_temp_new_i32();
8058
8059 if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
8060 generate_exception(ctx, EXCP_RI);
8061 goto out;
8062 }
8063
8064 if (cc != 0)
8065 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
8066
8067 btarget = ctx->pc + 4 + offset;
8068
8069 switch (op) {
8070 case OPC_BC1F:
8071 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8072 tcg_gen_not_i32(t0, t0);
8073 tcg_gen_andi_i32(t0, t0, 1);
8074 tcg_gen_extu_i32_tl(bcond, t0);
8075 goto not_likely;
8076 case OPC_BC1FL:
8077 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8078 tcg_gen_not_i32(t0, t0);
8079 tcg_gen_andi_i32(t0, t0, 1);
8080 tcg_gen_extu_i32_tl(bcond, t0);
8081 goto likely;
8082 case OPC_BC1T:
8083 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8084 tcg_gen_andi_i32(t0, t0, 1);
8085 tcg_gen_extu_i32_tl(bcond, t0);
8086 goto not_likely;
8087 case OPC_BC1TL:
8088 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8089 tcg_gen_andi_i32(t0, t0, 1);
8090 tcg_gen_extu_i32_tl(bcond, t0);
8091 likely:
8092 ctx->hflags |= MIPS_HFLAG_BL;
8093 break;
8094 case OPC_BC1FANY2:
8095 {
8096 TCGv_i32 t1 = tcg_temp_new_i32();
8097 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8098 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8099 tcg_gen_nand_i32(t0, t0, t1);
8100 tcg_temp_free_i32(t1);
8101 tcg_gen_andi_i32(t0, t0, 1);
8102 tcg_gen_extu_i32_tl(bcond, t0);
8103 }
8104 goto not_likely;
8105 case OPC_BC1TANY2:
8106 {
8107 TCGv_i32 t1 = tcg_temp_new_i32();
8108 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8109 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8110 tcg_gen_or_i32(t0, t0, t1);
8111 tcg_temp_free_i32(t1);
8112 tcg_gen_andi_i32(t0, t0, 1);
8113 tcg_gen_extu_i32_tl(bcond, t0);
8114 }
8115 goto not_likely;
8116 case OPC_BC1FANY4:
8117 {
8118 TCGv_i32 t1 = tcg_temp_new_i32();
8119 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8120 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8121 tcg_gen_and_i32(t0, t0, t1);
8122 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
8123 tcg_gen_and_i32(t0, t0, t1);
8124 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
8125 tcg_gen_nand_i32(t0, t0, t1);
8126 tcg_temp_free_i32(t1);
8127 tcg_gen_andi_i32(t0, t0, 1);
8128 tcg_gen_extu_i32_tl(bcond, t0);
8129 }
8130 goto not_likely;
8131 case OPC_BC1TANY4:
8132 {
8133 TCGv_i32 t1 = tcg_temp_new_i32();
8134 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8135 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
8136 tcg_gen_or_i32(t0, t0, t1);
8137 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
8138 tcg_gen_or_i32(t0, t0, t1);
8139 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
8140 tcg_gen_or_i32(t0, t0, t1);
8141 tcg_temp_free_i32(t1);
8142 tcg_gen_andi_i32(t0, t0, 1);
8143 tcg_gen_extu_i32_tl(bcond, t0);
8144 }
8145 not_likely:
8146 ctx->hflags |= MIPS_HFLAG_BC;
8147 break;
8148 default:
8149 MIPS_INVAL("cp1 cond branch");
8150 generate_exception (ctx, EXCP_RI);
8151 goto out;
8152 }
8153 ctx->btarget = btarget;
8154 ctx->hflags |= MIPS_HFLAG_BDS32;
8155 out:
8156 tcg_temp_free_i32(t0);
8157 }
8158
8159 /* R6 CP1 Branches */
8160 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
8161 int32_t ft, int32_t offset,
8162 int delayslot_size)
8163 {
8164 target_ulong btarget;
8165 TCGv_i64 t0 = tcg_temp_new_i64();
8166
8167 if (ctx->hflags & MIPS_HFLAG_BMASK) {
8168 #ifdef MIPS_DEBUG_DISAS
8169 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
8170 "\n", ctx->pc);
8171 #endif
8172 generate_exception(ctx, EXCP_RI);
8173 goto out;
8174 }
8175
8176 gen_load_fpr64(ctx, t0, ft);
8177 tcg_gen_andi_i64(t0, t0, 1);
8178
8179 btarget = addr_add(ctx, ctx->pc + 4, offset);
8180
8181 switch (op) {
8182 case OPC_BC1EQZ:
8183 tcg_gen_xori_i64(t0, t0, 1);
8184 ctx->hflags |= MIPS_HFLAG_BC;
8185 break;
8186 case OPC_BC1NEZ:
8187 /* t0 already set */
8188 ctx->hflags |= MIPS_HFLAG_BC;
8189 break;
8190 default:
8191 MIPS_INVAL("cp1 cond branch");
8192 generate_exception(ctx, EXCP_RI);
8193 goto out;
8194 }
8195
8196 tcg_gen_trunc_i64_tl(bcond, t0);
8197
8198 ctx->btarget = btarget;
8199
8200 switch (delayslot_size) {
8201 case 2:
8202 ctx->hflags |= MIPS_HFLAG_BDS16;
8203 break;
8204 case 4:
8205 ctx->hflags |= MIPS_HFLAG_BDS32;
8206 break;
8207 }
8208
8209 out:
8210 tcg_temp_free_i64(t0);
8211 }
8212
8213 /* Coprocessor 1 (FPU) */
8214
8215 #define FOP(func, fmt) (((fmt) << 21) | (func))
8216
8217 enum fopcode {
8218 OPC_ADD_S = FOP(0, FMT_S),
8219 OPC_SUB_S = FOP(1, FMT_S),
8220 OPC_MUL_S = FOP(2, FMT_S),
8221 OPC_DIV_S = FOP(3, FMT_S),
8222 OPC_SQRT_S = FOP(4, FMT_S),
8223 OPC_ABS_S = FOP(5, FMT_S),
8224 OPC_MOV_S = FOP(6, FMT_S),
8225 OPC_NEG_S = FOP(7, FMT_S),
8226 OPC_ROUND_L_S = FOP(8, FMT_S),
8227 OPC_TRUNC_L_S = FOP(9, FMT_S),
8228 OPC_CEIL_L_S = FOP(10, FMT_S),
8229 OPC_FLOOR_L_S = FOP(11, FMT_S),
8230 OPC_ROUND_W_S = FOP(12, FMT_S),
8231 OPC_TRUNC_W_S = FOP(13, FMT_S),
8232 OPC_CEIL_W_S = FOP(14, FMT_S),
8233 OPC_FLOOR_W_S = FOP(15, FMT_S),
8234 OPC_SEL_S = FOP(16, FMT_S),
8235 OPC_MOVCF_S = FOP(17, FMT_S),
8236 OPC_MOVZ_S = FOP(18, FMT_S),
8237 OPC_MOVN_S = FOP(19, FMT_S),
8238 OPC_SELEQZ_S = FOP(20, FMT_S),
8239 OPC_RECIP_S = FOP(21, FMT_S),
8240 OPC_RSQRT_S = FOP(22, FMT_S),
8241 OPC_SELNEZ_S = FOP(23, FMT_S),
8242 OPC_MADDF_S = FOP(24, FMT_S),
8243 OPC_MSUBF_S = FOP(25, FMT_S),
8244 OPC_RINT_S = FOP(26, FMT_S),
8245 OPC_CLASS_S = FOP(27, FMT_S),
8246 OPC_MIN_S = FOP(28, FMT_S),
8247 OPC_RECIP2_S = FOP(28, FMT_S),
8248 OPC_MINA_S = FOP(29, FMT_S),
8249 OPC_RECIP1_S = FOP(29, FMT_S),
8250 OPC_MAX_S = FOP(30, FMT_S),
8251 OPC_RSQRT1_S = FOP(30, FMT_S),
8252 OPC_MAXA_S = FOP(31, FMT_S),
8253 OPC_RSQRT2_S = FOP(31, FMT_S),
8254 OPC_CVT_D_S = FOP(33, FMT_S),
8255 OPC_CVT_W_S = FOP(36, FMT_S),
8256 OPC_CVT_L_S = FOP(37, FMT_S),
8257 OPC_CVT_PS_S = FOP(38, FMT_S),
8258 OPC_CMP_F_S = FOP (48, FMT_S),
8259 OPC_CMP_UN_S = FOP (49, FMT_S),
8260 OPC_CMP_EQ_S = FOP (50, FMT_S),
8261 OPC_CMP_UEQ_S = FOP (51, FMT_S),
8262 OPC_CMP_OLT_S = FOP (52, FMT_S),
8263 OPC_CMP_ULT_S = FOP (53, FMT_S),
8264 OPC_CMP_OLE_S = FOP (54, FMT_S),
8265 OPC_CMP_ULE_S = FOP (55, FMT_S),
8266 OPC_CMP_SF_S = FOP (56, FMT_S),
8267 OPC_CMP_NGLE_S = FOP (57, FMT_S),
8268 OPC_CMP_SEQ_S = FOP (58, FMT_S),
8269 OPC_CMP_NGL_S = FOP (59, FMT_S),
8270 OPC_CMP_LT_S = FOP (60, FMT_S),
8271 OPC_CMP_NGE_S = FOP (61, FMT_S),
8272 OPC_CMP_LE_S = FOP (62, FMT_S),
8273 OPC_CMP_NGT_S = FOP (63, FMT_S),
8274
8275 OPC_ADD_D = FOP(0, FMT_D),
8276 OPC_SUB_D = FOP(1, FMT_D),
8277 OPC_MUL_D = FOP(2, FMT_D),
8278 OPC_DIV_D = FOP(3, FMT_D),
8279 OPC_SQRT_D = FOP(4, FMT_D),
8280 OPC_ABS_D = FOP(5, FMT_D),
8281 OPC_MOV_D = FOP(6, FMT_D),
8282 OPC_NEG_D = FOP(7, FMT_D),
8283 OPC_ROUND_L_D = FOP(8, FMT_D),
8284 OPC_TRUNC_L_D = FOP(9, FMT_D),
8285 OPC_CEIL_L_D = FOP(10, FMT_D),
8286 OPC_FLOOR_L_D = FOP(11, FMT_D),
8287 OPC_ROUND_W_D = FOP(12, FMT_D),
8288 OPC_TRUNC_W_D = FOP(13, FMT_D),
8289 OPC_CEIL_W_D = FOP(14, FMT_D),
8290 OPC_FLOOR_W_D = FOP(15, FMT_D),
8291 OPC_SEL_D = FOP(16, FMT_D),
8292 OPC_MOVCF_D = FOP(17, FMT_D),
8293 OPC_MOVZ_D = FOP(18, FMT_D),
8294 OPC_MOVN_D = FOP(19, FMT_D),
8295 OPC_SELEQZ_D = FOP(20, FMT_D),
8296 OPC_RECIP_D = FOP(21, FMT_D),
8297 OPC_RSQRT_D = FOP(22, FMT_D),
8298 OPC_SELNEZ_D = FOP(23, FMT_D),
8299 OPC_MADDF_D = FOP(24, FMT_D),
8300 OPC_MSUBF_D = FOP(25, FMT_D),
8301 OPC_RINT_D = FOP(26, FMT_D),
8302 OPC_CLASS_D = FOP(27, FMT_D),
8303 OPC_MIN_D = FOP(28, FMT_D),
8304 OPC_RECIP2_D = FOP(28, FMT_D),
8305 OPC_MINA_D = FOP(29, FMT_D),
8306 OPC_RECIP1_D = FOP(29, FMT_D),
8307 OPC_MAX_D = FOP(30, FMT_D),
8308 OPC_RSQRT1_D = FOP(30, FMT_D),
8309 OPC_MAXA_D = FOP(31, FMT_D),
8310 OPC_RSQRT2_D = FOP(31, FMT_D),
8311 OPC_CVT_S_D = FOP(32, FMT_D),
8312 OPC_CVT_W_D = FOP(36, FMT_D),
8313 OPC_CVT_L_D = FOP(37, FMT_D),
8314 OPC_CMP_F_D = FOP (48, FMT_D),
8315 OPC_CMP_UN_D = FOP (49, FMT_D),
8316 OPC_CMP_EQ_D = FOP (50, FMT_D),
8317 OPC_CMP_UEQ_D = FOP (51, FMT_D),
8318 OPC_CMP_OLT_D = FOP (52, FMT_D),
8319 OPC_CMP_ULT_D = FOP (53, FMT_D),
8320 OPC_CMP_OLE_D = FOP (54, FMT_D),
8321 OPC_CMP_ULE_D = FOP (55, FMT_D),
8322 OPC_CMP_SF_D = FOP (56, FMT_D),
8323 OPC_CMP_NGLE_D = FOP (57, FMT_D),
8324 OPC_CMP_SEQ_D = FOP (58, FMT_D),
8325 OPC_CMP_NGL_D = FOP (59, FMT_D),
8326 OPC_CMP_LT_D = FOP (60, FMT_D),
8327 OPC_CMP_NGE_D = FOP (61, FMT_D),
8328 OPC_CMP_LE_D = FOP (62, FMT_D),
8329 OPC_CMP_NGT_D = FOP (63, FMT_D),
8330
8331 OPC_CVT_S_W = FOP(32, FMT_W),
8332 OPC_CVT_D_W = FOP(33, FMT_W),
8333 OPC_CVT_S_L = FOP(32, FMT_L),
8334 OPC_CVT_D_L = FOP(33, FMT_L),
8335 OPC_CVT_PS_PW = FOP(38, FMT_W),
8336
8337 OPC_ADD_PS = FOP(0, FMT_PS),
8338 OPC_SUB_PS = FOP(1, FMT_PS),
8339 OPC_MUL_PS = FOP(2, FMT_PS),
8340 OPC_DIV_PS = FOP(3, FMT_PS),
8341 OPC_ABS_PS = FOP(5, FMT_PS),
8342 OPC_MOV_PS = FOP(6, FMT_PS),
8343 OPC_NEG_PS = FOP(7, FMT_PS),
8344 OPC_MOVCF_PS = FOP(17, FMT_PS),
8345 OPC_MOVZ_PS = FOP(18, FMT_PS),
8346 OPC_MOVN_PS = FOP(19, FMT_PS),
8347 OPC_ADDR_PS = FOP(24, FMT_PS),
8348 OPC_MULR_PS = FOP(26, FMT_PS),
8349 OPC_RECIP2_PS = FOP(28, FMT_PS),
8350 OPC_RECIP1_PS = FOP(29, FMT_PS),
8351 OPC_RSQRT1_PS = FOP(30, FMT_PS),
8352 OPC_RSQRT2_PS = FOP(31, FMT_PS),
8353
8354 OPC_CVT_S_PU = FOP(32, FMT_PS),
8355 OPC_CVT_PW_PS = FOP(36, FMT_PS),
8356 OPC_CVT_S_PL = FOP(40, FMT_PS),
8357 OPC_PLL_PS = FOP(44, FMT_PS),
8358 OPC_PLU_PS = FOP(45, FMT_PS),
8359 OPC_PUL_PS = FOP(46, FMT_PS),
8360 OPC_PUU_PS = FOP(47, FMT_PS),
8361 OPC_CMP_F_PS = FOP (48, FMT_PS),
8362 OPC_CMP_UN_PS = FOP (49, FMT_PS),
8363 OPC_CMP_EQ_PS = FOP (50, FMT_PS),
8364 OPC_CMP_UEQ_PS = FOP (51, FMT_PS),
8365 OPC_CMP_OLT_PS = FOP (52, FMT_PS),
8366 OPC_CMP_ULT_PS = FOP (53, FMT_PS),
8367 OPC_CMP_OLE_PS = FOP (54, FMT_PS),
8368 OPC_CMP_ULE_PS = FOP (55, FMT_PS),
8369 OPC_CMP_SF_PS = FOP (56, FMT_PS),
8370 OPC_CMP_NGLE_PS = FOP (57, FMT_PS),
8371 OPC_CMP_SEQ_PS = FOP (58, FMT_PS),
8372 OPC_CMP_NGL_PS = FOP (59, FMT_PS),
8373 OPC_CMP_LT_PS = FOP (60, FMT_PS),
8374 OPC_CMP_NGE_PS = FOP (61, FMT_PS),
8375 OPC_CMP_LE_PS = FOP (62, FMT_PS),
8376 OPC_CMP_NGT_PS = FOP (63, FMT_PS),
8377 };
8378
8379 enum r6_f_cmp_op {
8380 R6_OPC_CMP_AF_S = FOP(0, FMT_W),
8381 R6_OPC_CMP_UN_S = FOP(1, FMT_W),
8382 R6_OPC_CMP_EQ_S = FOP(2, FMT_W),
8383 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W),
8384 R6_OPC_CMP_LT_S = FOP(4, FMT_W),
8385 R6_OPC_CMP_ULT_S = FOP(5, FMT_W),
8386 R6_OPC_CMP_LE_S = FOP(6, FMT_W),
8387 R6_OPC_CMP_ULE_S = FOP(7, FMT_W),
8388 R6_OPC_CMP_SAF_S = FOP(8, FMT_W),
8389 R6_OPC_CMP_SUN_S = FOP(9, FMT_W),
8390 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W),
8391 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W),
8392 R6_OPC_CMP_SLT_S = FOP(12, FMT_W),
8393 R6_OPC_CMP_SULT_S = FOP(13, FMT_W),
8394 R6_OPC_CMP_SLE_S = FOP(14, FMT_W),
8395 R6_OPC_CMP_SULE_S = FOP(15, FMT_W),
8396 R6_OPC_CMP_OR_S = FOP(17, FMT_W),
8397 R6_OPC_CMP_UNE_S = FOP(18, FMT_W),
8398 R6_OPC_CMP_NE_S = FOP(19, FMT_W),
8399 R6_OPC_CMP_SOR_S = FOP(25, FMT_W),
8400 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W),
8401 R6_OPC_CMP_SNE_S = FOP(27, FMT_W),
8402
8403 R6_OPC_CMP_AF_D = FOP(0, FMT_L),
8404 R6_OPC_CMP_UN_D = FOP(1, FMT_L),
8405 R6_OPC_CMP_EQ_D = FOP(2, FMT_L),
8406 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L),
8407 R6_OPC_CMP_LT_D = FOP(4, FMT_L),
8408 R6_OPC_CMP_ULT_D = FOP(5, FMT_L),
8409 R6_OPC_CMP_LE_D = FOP(6, FMT_L),
8410 R6_OPC_CMP_ULE_D = FOP(7, FMT_L),
8411 R6_OPC_CMP_SAF_D = FOP(8, FMT_L),
8412 R6_OPC_CMP_SUN_D = FOP(9, FMT_L),
8413 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L),
8414 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L),
8415 R6_OPC_CMP_SLT_D = FOP(12, FMT_L),
8416 R6_OPC_CMP_SULT_D = FOP(13, FMT_L),
8417 R6_OPC_CMP_SLE_D = FOP(14, FMT_L),
8418 R6_OPC_CMP_SULE_D = FOP(15, FMT_L),
8419 R6_OPC_CMP_OR_D = FOP(17, FMT_L),
8420 R6_OPC_CMP_UNE_D = FOP(18, FMT_L),
8421 R6_OPC_CMP_NE_D = FOP(19, FMT_L),
8422 R6_OPC_CMP_SOR_D = FOP(25, FMT_L),
8423 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
8424 R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
8425 };
8426 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
8427 {
8428 TCGv t0 = tcg_temp_new();
8429
8430 switch (opc) {
8431 case OPC_MFC1:
8432 {
8433 TCGv_i32 fp0 = tcg_temp_new_i32();
8434
8435 gen_load_fpr32(ctx, fp0, fs);
8436 tcg_gen_ext_i32_tl(t0, fp0);
8437 tcg_temp_free_i32(fp0);
8438 }
8439 gen_store_gpr(t0, rt);
8440 break;
8441 case OPC_MTC1:
8442 gen_load_gpr(t0, rt);
8443 {
8444 TCGv_i32 fp0 = tcg_temp_new_i32();
8445
8446 tcg_gen_trunc_tl_i32(fp0, t0);
8447 gen_store_fpr32(ctx, fp0, fs);
8448 tcg_temp_free_i32(fp0);
8449 }
8450 break;
8451 case OPC_CFC1:
8452 gen_helper_1e0i(cfc1, t0, fs);
8453 gen_store_gpr(t0, rt);
8454 break;
8455 case OPC_CTC1:
8456 gen_load_gpr(t0, rt);
8457 save_cpu_state(ctx, 1);
8458 {
8459 TCGv_i32 fs_tmp = tcg_const_i32(fs);
8460
8461 gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
8462 tcg_temp_free_i32(fs_tmp);
8463 }
8464 /* Stop translation as we may have changed hflags */
8465 ctx->bstate = BS_STOP;
8466 break;
8467 #if defined(TARGET_MIPS64)
8468 case OPC_DMFC1:
8469 gen_load_fpr64(ctx, t0, fs);
8470 gen_store_gpr(t0, rt);
8471 break;
8472 case OPC_DMTC1:
8473 gen_load_gpr(t0, rt);
8474 gen_store_fpr64(ctx, t0, fs);
8475 break;
8476 #endif
8477 case OPC_MFHC1:
8478 {
8479 TCGv_i32 fp0 = tcg_temp_new_i32();
8480
8481 gen_load_fpr32h(ctx, fp0, fs);
8482 tcg_gen_ext_i32_tl(t0, fp0);
8483 tcg_temp_free_i32(fp0);
8484 }
8485 gen_store_gpr(t0, rt);
8486 break;
8487 case OPC_MTHC1:
8488 gen_load_gpr(t0, rt);
8489 {
8490 TCGv_i32 fp0 = tcg_temp_new_i32();
8491
8492 tcg_gen_trunc_tl_i32(fp0, t0);
8493 gen_store_fpr32h(ctx, fp0, fs);
8494 tcg_temp_free_i32(fp0);
8495 }
8496 break;
8497 default:
8498 MIPS_INVAL("cp1 move");
8499 generate_exception (ctx, EXCP_RI);
8500 goto out;
8501 }
8502
8503 out:
8504 tcg_temp_free(t0);
8505 }
8506
8507 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
8508 {
8509 TCGLabel *l1;
8510 TCGCond cond;
8511 TCGv_i32 t0;
8512
8513 if (rd == 0) {
8514 /* Treat as NOP. */
8515 return;
8516 }
8517
8518 if (tf)
8519 cond = TCG_COND_EQ;
8520 else
8521 cond = TCG_COND_NE;
8522
8523 l1 = gen_new_label();
8524 t0 = tcg_temp_new_i32();
8525 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8526 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8527 tcg_temp_free_i32(t0);
8528 if (rs == 0) {
8529 tcg_gen_movi_tl(cpu_gpr[rd], 0);
8530 } else {
8531 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
8532 }
8533 gen_set_label(l1);
8534 }
8535
8536 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
8537 int tf)
8538 {
8539 int cond;
8540 TCGv_i32 t0 = tcg_temp_new_i32();
8541 TCGLabel *l1 = gen_new_label();
8542
8543 if (tf)
8544 cond = TCG_COND_EQ;
8545 else
8546 cond = TCG_COND_NE;
8547
8548 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8549 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8550 gen_load_fpr32(ctx, t0, fs);
8551 gen_store_fpr32(ctx, t0, fd);
8552 gen_set_label(l1);
8553 tcg_temp_free_i32(t0);
8554 }
8555
8556 static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
8557 {
8558 int cond;
8559 TCGv_i32 t0 = tcg_temp_new_i32();
8560 TCGv_i64 fp0;
8561 TCGLabel *l1 = gen_new_label();
8562
8563 if (tf)
8564 cond = TCG_COND_EQ;
8565 else
8566 cond = TCG_COND_NE;
8567
8568 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8569 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8570 tcg_temp_free_i32(t0);
8571 fp0 = tcg_temp_new_i64();
8572 gen_load_fpr64(ctx, fp0, fs);
8573 gen_store_fpr64(ctx, fp0, fd);
8574 tcg_temp_free_i64(fp0);
8575 gen_set_label(l1);
8576 }
8577
8578 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
8579 int cc, int tf)
8580 {
8581 int cond;
8582 TCGv_i32 t0 = tcg_temp_new_i32();
8583 TCGLabel *l1 = gen_new_label();
8584 TCGLabel *l2 = gen_new_label();
8585
8586 if (tf)
8587 cond = TCG_COND_EQ;
8588 else
8589 cond = TCG_COND_NE;
8590
8591 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
8592 tcg_gen_brcondi_i32(cond, t0, 0, l1);
8593 gen_load_fpr32(ctx, t0, fs);
8594 gen_store_fpr32(ctx, t0, fd);
8595 gen_set_label(l1);
8596
8597 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
8598 tcg_gen_brcondi_i32(cond, t0, 0, l2);
8599 gen_load_fpr32h(ctx, t0, fs);
8600 gen_store_fpr32h(ctx, t0, fd);
8601 tcg_temp_free_i32(t0);
8602 gen_set_label(l2);
8603 }
8604
8605 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
8606 int fs)
8607 {
8608 TCGv_i32 t1 = tcg_const_i32(0);
8609 TCGv_i32 fp0 = tcg_temp_new_i32();
8610 TCGv_i32 fp1 = tcg_temp_new_i32();
8611 TCGv_i32 fp2 = tcg_temp_new_i32();
8612 gen_load_fpr32(ctx, fp0, fd);
8613 gen_load_fpr32(ctx, fp1, ft);
8614 gen_load_fpr32(ctx, fp2, fs);
8615
8616 switch (op1) {
8617 case OPC_SEL_S:
8618 tcg_gen_andi_i32(fp0, fp0, 1);
8619 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
8620 break;
8621 case OPC_SELEQZ_S:
8622 tcg_gen_andi_i32(fp1, fp1, 1);
8623 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
8624 break;
8625 case OPC_SELNEZ_S:
8626 tcg_gen_andi_i32(fp1, fp1, 1);
8627 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
8628 break;
8629 default:
8630 MIPS_INVAL("gen_sel_s");
8631 generate_exception (ctx, EXCP_RI);
8632 break;
8633 }
8634
8635 gen_store_fpr32(ctx, fp0, fd);
8636 tcg_temp_free_i32(fp2);
8637 tcg_temp_free_i32(fp1);
8638 tcg_temp_free_i32(fp0);
8639 tcg_temp_free_i32(t1);
8640 }
8641
8642 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
8643 int fs)
8644 {
8645 TCGv_i64 t1 = tcg_const_i64(0);
8646 TCGv_i64 fp0 = tcg_temp_new_i64();
8647 TCGv_i64 fp1 = tcg_temp_new_i64();
8648 TCGv_i64 fp2 = tcg_temp_new_i64();
8649 gen_load_fpr64(ctx, fp0, fd);
8650 gen_load_fpr64(ctx, fp1, ft);
8651 gen_load_fpr64(ctx, fp2, fs);
8652
8653 switch (op1) {
8654 case OPC_SEL_D:
8655 tcg_gen_andi_i64(fp0, fp0, 1);
8656 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
8657 break;
8658 case OPC_SELEQZ_D:
8659 tcg_gen_andi_i64(fp1, fp1, 1);
8660 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
8661 break;
8662 case OPC_SELNEZ_D:
8663 tcg_gen_andi_i64(fp1, fp1, 1);
8664 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
8665 break;
8666 default:
8667 MIPS_INVAL("gen_sel_d");
8668 generate_exception (ctx, EXCP_RI);
8669 break;
8670 }
8671
8672 gen_store_fpr64(ctx, fp0, fd);
8673 tcg_temp_free_i64(fp2);
8674 tcg_temp_free_i64(fp1);
8675 tcg_temp_free_i64(fp0);
8676 tcg_temp_free_i64(t1);
8677 }
8678
8679 static void gen_farith (DisasContext *ctx, enum fopcode op1,
8680 int ft, int fs, int fd, int cc)
8681 {
8682 uint32_t func = ctx->opcode & 0x3f;
8683 switch (op1) {
8684 case OPC_ADD_S:
8685 {
8686 TCGv_i32 fp0 = tcg_temp_new_i32();
8687 TCGv_i32 fp1 = tcg_temp_new_i32();
8688
8689 gen_load_fpr32(ctx, fp0, fs);
8690 gen_load_fpr32(ctx, fp1, ft);
8691 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1);
8692 tcg_temp_free_i32(fp1);
8693 gen_store_fpr32(ctx, fp0, fd);
8694 tcg_temp_free_i32(fp0);
8695 }
8696 break;
8697 case OPC_SUB_S:
8698 {
8699 TCGv_i32 fp0 = tcg_temp_new_i32();
8700 TCGv_i32 fp1 = tcg_temp_new_i32();
8701
8702 gen_load_fpr32(ctx, fp0, fs);
8703 gen_load_fpr32(ctx, fp1, ft);
8704 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1);
8705 tcg_temp_free_i32(fp1);
8706 gen_store_fpr32(ctx, fp0, fd);
8707 tcg_temp_free_i32(fp0);
8708 }
8709 break;
8710 case OPC_MUL_S:
8711 {
8712 TCGv_i32 fp0 = tcg_temp_new_i32();
8713 TCGv_i32 fp1 = tcg_temp_new_i32();
8714
8715 gen_load_fpr32(ctx, fp0, fs);
8716 gen_load_fpr32(ctx, fp1, ft);
8717 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1);
8718 tcg_temp_free_i32(fp1);
8719 gen_store_fpr32(ctx, fp0, fd);
8720 tcg_temp_free_i32(fp0);
8721 }
8722 break;
8723 case OPC_DIV_S:
8724 {
8725 TCGv_i32 fp0 = tcg_temp_new_i32();
8726 TCGv_i32 fp1 = tcg_temp_new_i32();
8727
8728 gen_load_fpr32(ctx, fp0, fs);
8729 gen_load_fpr32(ctx, fp1, ft);
8730 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1);
8731 tcg_temp_free_i32(fp1);
8732 gen_store_fpr32(ctx, fp0, fd);
8733 tcg_temp_free_i32(fp0);
8734 }
8735 break;
8736 case OPC_SQRT_S:
8737 {
8738 TCGv_i32 fp0 = tcg_temp_new_i32();
8739
8740 gen_load_fpr32(ctx, fp0, fs);
8741 gen_helper_float_sqrt_s(fp0, cpu_env, fp0);
8742 gen_store_fpr32(ctx, fp0, fd);
8743 tcg_temp_free_i32(fp0);
8744 }
8745 break;
8746 case OPC_ABS_S:
8747 {
8748 TCGv_i32 fp0 = tcg_temp_new_i32();
8749
8750 gen_load_fpr32(ctx, fp0, fs);
8751 gen_helper_float_abs_s(fp0, fp0);
8752 gen_store_fpr32(ctx, fp0, fd);
8753 tcg_temp_free_i32(fp0);
8754 }
8755 break;
8756 case OPC_MOV_S:
8757 {
8758 TCGv_i32 fp0 = tcg_temp_new_i32();
8759
8760 gen_load_fpr32(ctx, fp0, fs);
8761 gen_store_fpr32(ctx, fp0, fd);
8762 tcg_temp_free_i32(fp0);
8763 }
8764 break;
8765 case OPC_NEG_S:
8766 {
8767 TCGv_i32 fp0 = tcg_temp_new_i32();
8768
8769 gen_load_fpr32(ctx, fp0, fs);
8770 gen_helper_float_chs_s(fp0, fp0);
8771 gen_store_fpr32(ctx, fp0, fd);
8772 tcg_temp_free_i32(fp0);
8773 }
8774 break;
8775 case OPC_ROUND_L_S:
8776 check_cp1_64bitmode(ctx);
8777 {
8778 TCGv_i32 fp32 = tcg_temp_new_i32();
8779 TCGv_i64 fp64 = tcg_temp_new_i64();
8780
8781 gen_load_fpr32(ctx, fp32, fs);
8782 gen_helper_float_roundl_s(fp64, cpu_env, fp32);
8783 tcg_temp_free_i32(fp32);
8784 gen_store_fpr64(ctx, fp64, fd);
8785 tcg_temp_free_i64(fp64);
8786 }
8787 break;
8788 case OPC_TRUNC_L_S:
8789 check_cp1_64bitmode(ctx);
8790 {
8791 TCGv_i32 fp32 = tcg_temp_new_i32();
8792 TCGv_i64 fp64 = tcg_temp_new_i64();
8793
8794 gen_load_fpr32(ctx, fp32, fs);
8795 gen_helper_float_truncl_s(fp64, cpu_env, fp32);
8796 tcg_temp_free_i32(fp32);
8797 gen_store_fpr64(ctx, fp64, fd);
8798 tcg_temp_free_i64(fp64);
8799 }
8800 break;
8801 case OPC_CEIL_L_S:
8802 check_cp1_64bitmode(ctx);
8803 {
8804 TCGv_i32 fp32 = tcg_temp_new_i32();
8805 TCGv_i64 fp64 = tcg_temp_new_i64();
8806
8807 gen_load_fpr32(ctx, fp32, fs);
8808 gen_helper_float_ceill_s(fp64, cpu_env, fp32);
8809 tcg_temp_free_i32(fp32);
8810 gen_store_fpr64(ctx, fp64, fd);
8811 tcg_temp_free_i64(fp64);
8812 }
8813 break;
8814 case OPC_FLOOR_L_S:
8815 check_cp1_64bitmode(ctx);
8816 {
8817 TCGv_i32 fp32 = tcg_temp_new_i32();
8818 TCGv_i64 fp64 = tcg_temp_new_i64();
8819
8820 gen_load_fpr32(ctx, fp32, fs);
8821 gen_helper_float_floorl_s(fp64, cpu_env, fp32);
8822 tcg_temp_free_i32(fp32);
8823 gen_store_fpr64(ctx, fp64, fd);
8824 tcg_temp_free_i64(fp64);
8825 }
8826 break;
8827 case OPC_ROUND_W_S:
8828 {
8829 TCGv_i32 fp0 = tcg_temp_new_i32();
8830
8831 gen_load_fpr32(ctx, fp0, fs);
8832 gen_helper_float_roundw_s(fp0, cpu_env, fp0);
8833 gen_store_fpr32(ctx, fp0, fd);
8834 tcg_temp_free_i32(fp0);
8835 }
8836 break;
8837 case OPC_TRUNC_W_S:
8838 {
8839 TCGv_i32 fp0 = tcg_temp_new_i32();
8840
8841 gen_load_fpr32(ctx, fp0, fs);
8842 gen_helper_float_truncw_s(fp0, cpu_env, fp0);
8843 gen_store_fpr32(ctx, fp0, fd);
8844 tcg_temp_free_i32(fp0);
8845 }
8846 break;
8847 case OPC_CEIL_W_S:
8848 {
8849 TCGv_i32 fp0 = tcg_temp_new_i32();
8850
8851 gen_load_fpr32(ctx, fp0, fs);
8852 gen_helper_float_ceilw_s(fp0, cpu_env, fp0);
8853 gen_store_fpr32(ctx, fp0, fd);
8854 tcg_temp_free_i32(fp0);
8855 }
8856 break;
8857 case OPC_FLOOR_W_S:
8858 {
8859 TCGv_i32 fp0 = tcg_temp_new_i32();
8860
8861 gen_load_fpr32(ctx, fp0, fs);
8862 gen_helper_float_floorw_s(fp0, cpu_env, fp0);
8863 gen_store_fpr32(ctx, fp0, fd);
8864 tcg_temp_free_i32(fp0);
8865 }
8866 break;
8867 case OPC_SEL_S:
8868 check_insn(ctx, ISA_MIPS32R6);
8869 gen_sel_s(ctx, op1, fd, ft, fs);
8870 break;
8871 case OPC_SELEQZ_S:
8872 check_insn(ctx, ISA_MIPS32R6);
8873 gen_sel_s(ctx, op1, fd, ft, fs);
8874 break;
8875 case OPC_SELNEZ_S:
8876 check_insn(ctx, ISA_MIPS32R6);
8877 gen_sel_s(ctx, op1, fd, ft, fs);
8878 break;
8879 case OPC_MOVCF_S:
8880 check_insn_opc_removed(ctx, ISA_MIPS32R6);
8881 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
8882 break;
8883 case OPC_MOVZ_S:
8884 check_insn_opc_removed(ctx, ISA_MIPS32R6);
8885 {
8886 TCGLabel *l1 = gen_new_label();
8887 TCGv_i32 fp0;
8888
8889 if (ft != 0) {
8890 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
8891 }
8892 fp0 = tcg_temp_new_i32();
8893 gen_load_fpr32(ctx, fp0, fs);
8894 gen_store_fpr32(ctx, fp0, fd);
8895 tcg_temp_free_i32(fp0);
8896 gen_set_label(l1);
8897 }
8898 break;
8899 case OPC_MOVN_S:
8900 check_insn_opc_removed(ctx, ISA_MIPS32R6);
8901 {
8902 TCGLabel *l1 = gen_new_label();
8903 TCGv_i32 fp0;
8904
8905 if (ft != 0) {
8906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
8907 fp0 = tcg_temp_new_i32();
8908 gen_load_fpr32(ctx, fp0, fs);
8909 gen_store_fpr32(ctx, fp0, fd);
8910 tcg_temp_free_i32(fp0);
8911 gen_set_label(l1);
8912 }
8913 }
8914 break;
8915 case OPC_RECIP_S:
8916 {
8917 TCGv_i32 fp0 = tcg_temp_new_i32();
8918
8919 gen_load_fpr32(ctx, fp0, fs);
8920 gen_helper_float_recip_s(fp0, cpu_env, fp0);
8921 gen_store_fpr32(ctx, fp0, fd);
8922 tcg_temp_free_i32(fp0);
8923 }
8924 break;
8925 case OPC_RSQRT_S:
8926 {
8927 TCGv_i32 fp0 = tcg_temp_new_i32();
8928
8929 gen_load_fpr32(ctx, fp0, fs);
8930 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0);
8931 gen_store_fpr32(ctx, fp0, fd);
8932 tcg_temp_free_i32(fp0);
8933 }
8934 break;
8935 case OPC_MADDF_S:
8936 check_insn(ctx, ISA_MIPS32R6);
8937 {
8938 TCGv_i32 fp0 = tcg_temp_new_i32();
8939 TCGv_i32 fp1 = tcg_temp_new_i32();
8940 TCGv_i32 fp2 = tcg_temp_new_i32();
8941 gen_load_fpr32(ctx, fp0, fs);
8942 gen_load_fpr32(ctx, fp1, ft);
8943 gen_load_fpr32(ctx, fp2, fd);
8944 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2);
8945 gen_store_fpr32(ctx, fp2, fd);
8946 tcg_temp_free_i32(fp2);
8947 tcg_temp_free_i32(fp1);
8948 tcg_temp_free_i32(fp0);
8949 }
8950 break;
8951 case OPC_MSUBF_S:
8952 check_insn(ctx, ISA_MIPS32R6);
8953 {
8954 TCGv_i32 fp0 = tcg_temp_new_i32();
8955 TCGv_i32 fp1 = tcg_temp_new_i32();
8956 TCGv_i32 fp2 = tcg_temp_new_i32();
8957 gen_load_fpr32(ctx, fp0, fs);
8958 gen_load_fpr32(ctx, fp1, ft);
8959 gen_load_fpr32(ctx, fp2, fd);
8960 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2);
8961 gen_store_fpr32(ctx, fp2, fd);
8962 tcg_temp_free_i32(fp2);
8963 tcg_temp_free_i32(fp1);
8964 tcg_temp_free_i32(fp0);
8965 }
8966 break;
8967 case OPC_RINT_S:
8968 check_insn(ctx, ISA_MIPS32R6);
8969 {
8970 TCGv_i32 fp0 = tcg_temp_new_i32();
8971 gen_load_fpr32(ctx, fp0, fs);
8972 gen_helper_float_rint_s(fp0, cpu_env, fp0);
8973 gen_store_fpr32(ctx, fp0, fd);
8974 tcg_temp_free_i32(fp0);
8975 }
8976 break;
8977 case OPC_CLASS_S:
8978 check_insn(ctx, ISA_MIPS32R6);
8979 {
8980 TCGv_i32 fp0 = tcg_temp_new_i32();
8981 gen_load_fpr32(ctx, fp0, fs);
8982 gen_helper_float_class_s(fp0, fp0);
8983 gen_store_fpr32(ctx, fp0, fd);
8984 tcg_temp_free_i32(fp0);
8985 }
8986 break;
8987 case OPC_MIN_S: /* OPC_RECIP2_S */
8988 if (ctx->insn_flags & ISA_MIPS32R6) {
8989 /* OPC_MIN_S */
8990 TCGv_i32 fp0 = tcg_temp_new_i32();
8991 TCGv_i32 fp1 = tcg_temp_new_i32();
8992 TCGv_i32 fp2 = tcg_temp_new_i32();
8993 gen_load_fpr32(ctx, fp0, fs);
8994 gen_load_fpr32(ctx, fp1, ft);
8995 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1);
8996 gen_store_fpr32(ctx, fp2, fd);
8997 tcg_temp_free_i32(fp2);
8998 tcg_temp_free_i32(fp1);
8999 tcg_temp_free_i32(fp0);
9000 } else {
9001 /* OPC_RECIP2_S */
9002 check_cp1_64bitmode(ctx);
9003 {
9004 TCGv_i32 fp0 = tcg_temp_new_i32();
9005 TCGv_i32 fp1 = tcg_temp_new_i32();
9006
9007 gen_load_fpr32(ctx, fp0, fs);
9008 gen_load_fpr32(ctx, fp1, ft);
9009 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1);
9010 tcg_temp_free_i32(fp1);
9011 gen_store_fpr32(ctx, fp0, fd);
9012 tcg_temp_free_i32(fp0);
9013 }
9014 }
9015 break;
9016 case OPC_MINA_S: /* OPC_RECIP1_S */
9017 if (ctx->insn_flags & ISA_MIPS32R6) {
9018 /* OPC_MINA_S */
9019 TCGv_i32 fp0 = tcg_temp_new_i32();
9020 TCGv_i32 fp1 = tcg_temp_new_i32();
9021 TCGv_i32 fp2 = tcg_temp_new_i32();
9022 gen_load_fpr32(ctx, fp0, fs);
9023 gen_load_fpr32(ctx, fp1, ft);
9024 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1);
9025 gen_store_fpr32(ctx, fp2, fd);
9026 tcg_temp_free_i32(fp2);
9027 tcg_temp_free_i32(fp1);
9028 tcg_temp_free_i32(fp0);
9029 } else {
9030 /* OPC_RECIP1_S */
9031 check_cp1_64bitmode(ctx);
9032 {
9033 TCGv_i32 fp0 = tcg_temp_new_i32();
9034
9035 gen_load_fpr32(ctx, fp0, fs);
9036 gen_helper_float_recip1_s(fp0, cpu_env, fp0);
9037 gen_store_fpr32(ctx, fp0, fd);
9038 tcg_temp_free_i32(fp0);
9039 }
9040 }
9041 break;
9042 case OPC_MAX_S: /* OPC_RSQRT1_S */
9043 if (ctx->insn_flags & ISA_MIPS32R6) {
9044 /* OPC_MAX_S */
9045 TCGv_i32 fp0 = tcg_temp_new_i32();
9046 TCGv_i32 fp1 = tcg_temp_new_i32();
9047 gen_load_fpr32(ctx, fp0, fs);
9048 gen_load_fpr32(ctx, fp1, ft);
9049 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1);
9050 gen_store_fpr32(ctx, fp1, fd);
9051 tcg_temp_free_i32(fp1);
9052 tcg_temp_free_i32(fp0);
9053 } else {
9054 /* OPC_RSQRT1_S */
9055 check_cp1_64bitmode(ctx);
9056 {
9057 TCGv_i32 fp0 = tcg_temp_new_i32();
9058
9059 gen_load_fpr32(ctx, fp0, fs);
9060 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0);
9061 gen_store_fpr32(ctx, fp0, fd);
9062 tcg_temp_free_i32(fp0);
9063 }
9064 }
9065 break;
9066 case OPC_MAXA_S: /* OPC_RSQRT2_S */
9067 if (ctx->insn_flags & ISA_MIPS32R6) {
9068 /* OPC_MAXA_S */
9069 TCGv_i32 fp0 = tcg_temp_new_i32();
9070 TCGv_i32 fp1 = tcg_temp_new_i32();
9071 gen_load_fpr32(ctx, fp0, fs);
9072 gen_load_fpr32(ctx, fp1, ft);
9073 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1);
9074 gen_store_fpr32(ctx, fp1, fd);
9075 tcg_temp_free_i32(fp1);
9076 tcg_temp_free_i32(fp0);
9077 } else {
9078 /* OPC_RSQRT2_S */
9079 check_cp1_64bitmode(ctx);
9080 {
9081 TCGv_i32 fp0 = tcg_temp_new_i32();
9082 TCGv_i32 fp1 = tcg_temp_new_i32();
9083
9084 gen_load_fpr32(ctx, fp0, fs);
9085 gen_load_fpr32(ctx, fp1, ft);
9086 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1);
9087 tcg_temp_free_i32(fp1);
9088 gen_store_fpr32(ctx, fp0, fd);
9089 tcg_temp_free_i32(fp0);
9090 }
9091 }
9092 break;
9093 case OPC_CVT_D_S:
9094 check_cp1_registers(ctx, fd);
9095 {
9096 TCGv_i32 fp32 = tcg_temp_new_i32();
9097 TCGv_i64 fp64 = tcg_temp_new_i64();
9098
9099 gen_load_fpr32(ctx, fp32, fs);
9100 gen_helper_float_cvtd_s(fp64, cpu_env, fp32);
9101 tcg_temp_free_i32(fp32);
9102 gen_store_fpr64(ctx, fp64, fd);
9103 tcg_temp_free_i64(fp64);
9104 }
9105 break;
9106 case OPC_CVT_W_S:
9107 {
9108 TCGv_i32 fp0 = tcg_temp_new_i32();
9109
9110 gen_load_fpr32(ctx, fp0, fs);
9111 gen_helper_float_cvtw_s(fp0, cpu_env, fp0);
9112 gen_store_fpr32(ctx, fp0, fd);
9113 tcg_temp_free_i32(fp0);
9114 }
9115 break;
9116 case OPC_CVT_L_S:
9117 check_cp1_64bitmode(ctx);
9118 {
9119 TCGv_i32 fp32 = tcg_temp_new_i32();
9120 TCGv_i64 fp64 = tcg_temp_new_i64();
9121
9122 gen_load_fpr32(ctx, fp32, fs);
9123 gen_helper_float_cvtl_s(fp64, cpu_env, fp32);
9124 tcg_temp_free_i32(fp32);
9125 gen_store_fpr64(ctx, fp64, fd);
9126 tcg_temp_free_i64(fp64);
9127 }
9128 break;
9129 case OPC_CVT_PS_S:
9130 check_ps(ctx);
9131 {
9132 TCGv_i64 fp64 = tcg_temp_new_i64();
9133 TCGv_i32 fp32_0 = tcg_temp_new_i32();
9134 TCGv_i32 fp32_1 = tcg_temp_new_i32();
9135
9136 gen_load_fpr32(ctx, fp32_0, fs);
9137 gen_load_fpr32(ctx, fp32_1, ft);
9138 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
9139 tcg_temp_free_i32(fp32_1);
9140 tcg_temp_free_i32(fp32_0);
9141 gen_store_fpr64(ctx, fp64, fd);
9142 tcg_temp_free_i64(fp64);
9143 }
9144 break;
9145 case OPC_CMP_F_S:
9146 case OPC_CMP_UN_S:
9147 case OPC_CMP_EQ_S:
9148 case OPC_CMP_UEQ_S:
9149 case OPC_CMP_OLT_S:
9150 case OPC_CMP_ULT_S:
9151 case OPC_CMP_OLE_S:
9152 case OPC_CMP_ULE_S:
9153 case OPC_CMP_SF_S:
9154 case OPC_CMP_NGLE_S:
9155 case OPC_CMP_SEQ_S:
9156 case OPC_CMP_NGL_S:
9157 case OPC_CMP_LT_S:
9158 case OPC_CMP_NGE_S:
9159 case OPC_CMP_LE_S:
9160 case OPC_CMP_NGT_S:
9161 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9162 if (ctx->opcode & (1 << 6)) {
9163 gen_cmpabs_s(ctx, func-48, ft, fs, cc);
9164 } else {
9165 gen_cmp_s(ctx, func-48, ft, fs, cc);
9166 }
9167 break;
9168 case OPC_ADD_D:
9169 check_cp1_registers(ctx, fs | ft | fd);
9170 {
9171 TCGv_i64 fp0 = tcg_temp_new_i64();
9172 TCGv_i64 fp1 = tcg_temp_new_i64();
9173
9174 gen_load_fpr64(ctx, fp0, fs);
9175 gen_load_fpr64(ctx, fp1, ft);
9176 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1);
9177 tcg_temp_free_i64(fp1);
9178 gen_store_fpr64(ctx, fp0, fd);
9179 tcg_temp_free_i64(fp0);
9180 }
9181 break;
9182 case OPC_SUB_D:
9183 check_cp1_registers(ctx, fs | ft | fd);
9184 {
9185 TCGv_i64 fp0 = tcg_temp_new_i64();
9186 TCGv_i64 fp1 = tcg_temp_new_i64();
9187
9188 gen_load_fpr64(ctx, fp0, fs);
9189 gen_load_fpr64(ctx, fp1, ft);
9190 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1);
9191 tcg_temp_free_i64(fp1);
9192 gen_store_fpr64(ctx, fp0, fd);
9193 tcg_temp_free_i64(fp0);
9194 }
9195 break;
9196 case OPC_MUL_D:
9197 check_cp1_registers(ctx, fs | ft | fd);
9198 {
9199 TCGv_i64 fp0 = tcg_temp_new_i64();
9200 TCGv_i64 fp1 = tcg_temp_new_i64();
9201
9202 gen_load_fpr64(ctx, fp0, fs);
9203 gen_load_fpr64(ctx, fp1, ft);
9204 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1);
9205 tcg_temp_free_i64(fp1);
9206 gen_store_fpr64(ctx, fp0, fd);
9207 tcg_temp_free_i64(fp0);
9208 }
9209 break;
9210 case OPC_DIV_D:
9211 check_cp1_registers(ctx, fs | ft | fd);
9212 {
9213 TCGv_i64 fp0 = tcg_temp_new_i64();
9214 TCGv_i64 fp1 = tcg_temp_new_i64();
9215
9216 gen_load_fpr64(ctx, fp0, fs);
9217 gen_load_fpr64(ctx, fp1, ft);
9218 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1);
9219 tcg_temp_free_i64(fp1);
9220 gen_store_fpr64(ctx, fp0, fd);
9221 tcg_temp_free_i64(fp0);
9222 }
9223 break;
9224 case OPC_SQRT_D:
9225 check_cp1_registers(ctx, fs | fd);
9226 {
9227 TCGv_i64 fp0 = tcg_temp_new_i64();
9228
9229 gen_load_fpr64(ctx, fp0, fs);
9230 gen_helper_float_sqrt_d(fp0, cpu_env, fp0);
9231 gen_store_fpr64(ctx, fp0, fd);
9232 tcg_temp_free_i64(fp0);
9233 }
9234 break;
9235 case OPC_ABS_D:
9236 check_cp1_registers(ctx, fs | fd);
9237 {
9238 TCGv_i64 fp0 = tcg_temp_new_i64();
9239
9240 gen_load_fpr64(ctx, fp0, fs);
9241 gen_helper_float_abs_d(fp0, fp0);
9242 gen_store_fpr64(ctx, fp0, fd);
9243 tcg_temp_free_i64(fp0);
9244 }
9245 break;
9246 case OPC_MOV_D:
9247 check_cp1_registers(ctx, fs | fd);
9248 {
9249 TCGv_i64 fp0 = tcg_temp_new_i64();
9250
9251 gen_load_fpr64(ctx, fp0, fs);
9252 gen_store_fpr64(ctx, fp0, fd);
9253 tcg_temp_free_i64(fp0);
9254 }
9255 break;
9256 case OPC_NEG_D:
9257 check_cp1_registers(ctx, fs | fd);
9258 {
9259 TCGv_i64 fp0 = tcg_temp_new_i64();
9260
9261 gen_load_fpr64(ctx, fp0, fs);
9262 gen_helper_float_chs_d(fp0, fp0);
9263 gen_store_fpr64(ctx, fp0, fd);
9264 tcg_temp_free_i64(fp0);
9265 }
9266 break;
9267 case OPC_ROUND_L_D:
9268 check_cp1_64bitmode(ctx);
9269 {
9270 TCGv_i64 fp0 = tcg_temp_new_i64();
9271
9272 gen_load_fpr64(ctx, fp0, fs);
9273 gen_helper_float_roundl_d(fp0, cpu_env, fp0);
9274 gen_store_fpr64(ctx, fp0, fd);
9275 tcg_temp_free_i64(fp0);
9276 }
9277 break;
9278 case OPC_TRUNC_L_D:
9279 check_cp1_64bitmode(ctx);
9280 {
9281 TCGv_i64 fp0 = tcg_temp_new_i64();
9282
9283 gen_load_fpr64(ctx, fp0, fs);
9284 gen_helper_float_truncl_d(fp0, cpu_env, fp0);
9285 gen_store_fpr64(ctx, fp0, fd);
9286 tcg_temp_free_i64(fp0);
9287 }
9288 break;
9289 case OPC_CEIL_L_D:
9290 check_cp1_64bitmode(ctx);
9291 {
9292 TCGv_i64 fp0 = tcg_temp_new_i64();
9293
9294 gen_load_fpr64(ctx, fp0, fs);
9295 gen_helper_float_ceill_d(fp0, cpu_env, fp0);
9296 gen_store_fpr64(ctx, fp0, fd);
9297 tcg_temp_free_i64(fp0);
9298 }
9299 break;
9300 case OPC_FLOOR_L_D:
9301 check_cp1_64bitmode(ctx);
9302 {
9303 TCGv_i64 fp0 = tcg_temp_new_i64();
9304
9305 gen_load_fpr64(ctx, fp0, fs);
9306 gen_helper_float_floorl_d(fp0, cpu_env, fp0);
9307 gen_store_fpr64(ctx, fp0, fd);
9308 tcg_temp_free_i64(fp0);
9309 }
9310 break;
9311 case OPC_ROUND_W_D:
9312 check_cp1_registers(ctx, fs);
9313 {
9314 TCGv_i32 fp32 = tcg_temp_new_i32();
9315 TCGv_i64 fp64 = tcg_temp_new_i64();
9316
9317 gen_load_fpr64(ctx, fp64, fs);
9318 gen_helper_float_roundw_d(fp32, cpu_env, fp64);
9319 tcg_temp_free_i64(fp64);
9320 gen_store_fpr32(ctx, fp32, fd);
9321 tcg_temp_free_i32(fp32);
9322 }
9323 break;
9324 case OPC_TRUNC_W_D:
9325 check_cp1_registers(ctx, fs);
9326 {
9327 TCGv_i32 fp32 = tcg_temp_new_i32();
9328 TCGv_i64 fp64 = tcg_temp_new_i64();
9329
9330 gen_load_fpr64(ctx, fp64, fs);
9331 gen_helper_float_truncw_d(fp32, cpu_env, fp64);
9332 tcg_temp_free_i64(fp64);
9333 gen_store_fpr32(ctx, fp32, fd);
9334 tcg_temp_free_i32(fp32);
9335 }
9336 break;
9337 case OPC_CEIL_W_D:
9338 check_cp1_registers(ctx, fs);
9339 {
9340 TCGv_i32 fp32 = tcg_temp_new_i32();
9341 TCGv_i64 fp64 = tcg_temp_new_i64();
9342
9343 gen_load_fpr64(ctx, fp64, fs);
9344 gen_helper_float_ceilw_d(fp32, cpu_env, fp64);
9345 tcg_temp_free_i64(fp64);
9346 gen_store_fpr32(ctx, fp32, fd);
9347 tcg_temp_free_i32(fp32);
9348 }
9349 break;
9350 case OPC_FLOOR_W_D:
9351 check_cp1_registers(ctx, fs);
9352 {
9353 TCGv_i32 fp32 = tcg_temp_new_i32();
9354 TCGv_i64 fp64 = tcg_temp_new_i64();
9355
9356 gen_load_fpr64(ctx, fp64, fs);
9357 gen_helper_float_floorw_d(fp32, cpu_env, fp64);
9358 tcg_temp_free_i64(fp64);
9359 gen_store_fpr32(ctx, fp32, fd);
9360 tcg_temp_free_i32(fp32);
9361 }
9362 break;
9363 case OPC_SEL_D:
9364 check_insn(ctx, ISA_MIPS32R6);
9365 gen_sel_d(ctx, op1, fd, ft, fs);
9366 break;
9367 case OPC_SELEQZ_D:
9368 check_insn(ctx, ISA_MIPS32R6);
9369 gen_sel_d(ctx, op1, fd, ft, fs);
9370 break;
9371 case OPC_SELNEZ_D:
9372 check_insn(ctx, ISA_MIPS32R6);
9373 gen_sel_d(ctx, op1, fd, ft, fs);
9374 break;
9375 case OPC_MOVCF_D:
9376 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9377 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
9378 break;
9379 case OPC_MOVZ_D:
9380 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9381 {
9382 TCGLabel *l1 = gen_new_label();
9383 TCGv_i64 fp0;
9384
9385 if (ft != 0) {
9386 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
9387 }
9388 fp0 = tcg_temp_new_i64();
9389 gen_load_fpr64(ctx, fp0, fs);
9390 gen_store_fpr64(ctx, fp0, fd);
9391 tcg_temp_free_i64(fp0);
9392 gen_set_label(l1);
9393 }
9394 break;
9395 case OPC_MOVN_D:
9396 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9397 {
9398 TCGLabel *l1 = gen_new_label();
9399 TCGv_i64 fp0;
9400
9401 if (ft != 0) {
9402 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
9403 fp0 = tcg_temp_new_i64();
9404 gen_load_fpr64(ctx, fp0, fs);
9405 gen_store_fpr64(ctx, fp0, fd);
9406 tcg_temp_free_i64(fp0);
9407 gen_set_label(l1);
9408 }
9409 }
9410 break;
9411 case OPC_RECIP_D:
9412 check_cp1_registers(ctx, fs | fd);
9413 {
9414 TCGv_i64 fp0 = tcg_temp_new_i64();
9415
9416 gen_load_fpr64(ctx, fp0, fs);
9417 gen_helper_float_recip_d(fp0, cpu_env, fp0);
9418 gen_store_fpr64(ctx, fp0, fd);
9419 tcg_temp_free_i64(fp0);
9420 }
9421 break;
9422 case OPC_RSQRT_D:
9423 check_cp1_registers(ctx, fs | fd);
9424 {
9425 TCGv_i64 fp0 = tcg_temp_new_i64();
9426
9427 gen_load_fpr64(ctx, fp0, fs);
9428 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0);
9429 gen_store_fpr64(ctx, fp0, fd);
9430 tcg_temp_free_i64(fp0);
9431 }
9432 break;
9433 case OPC_MADDF_D:
9434 check_insn(ctx, ISA_MIPS32R6);
9435 {
9436 TCGv_i64 fp0 = tcg_temp_new_i64();
9437 TCGv_i64 fp1 = tcg_temp_new_i64();
9438 TCGv_i64 fp2 = tcg_temp_new_i64();
9439 gen_load_fpr64(ctx, fp0, fs);
9440 gen_load_fpr64(ctx, fp1, ft);
9441 gen_load_fpr64(ctx, fp2, fd);
9442 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2);
9443 gen_store_fpr64(ctx, fp2, fd);
9444 tcg_temp_free_i64(fp2);
9445 tcg_temp_free_i64(fp1);
9446 tcg_temp_free_i64(fp0);
9447 }
9448 break;
9449 case OPC_MSUBF_D:
9450 check_insn(ctx, ISA_MIPS32R6);
9451 {
9452 TCGv_i64 fp0 = tcg_temp_new_i64();
9453 TCGv_i64 fp1 = tcg_temp_new_i64();
9454 TCGv_i64 fp2 = tcg_temp_new_i64();
9455 gen_load_fpr64(ctx, fp0, fs);
9456 gen_load_fpr64(ctx, fp1, ft);
9457 gen_load_fpr64(ctx, fp2, fd);
9458 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2);
9459 gen_store_fpr64(ctx, fp2, fd);
9460 tcg_temp_free_i64(fp2);
9461 tcg_temp_free_i64(fp1);
9462 tcg_temp_free_i64(fp0);
9463 }
9464 break;
9465 case OPC_RINT_D:
9466 check_insn(ctx, ISA_MIPS32R6);
9467 {
9468 TCGv_i64 fp0 = tcg_temp_new_i64();
9469 gen_load_fpr64(ctx, fp0, fs);
9470 gen_helper_float_rint_d(fp0, cpu_env, fp0);
9471 gen_store_fpr64(ctx, fp0, fd);
9472 tcg_temp_free_i64(fp0);
9473 }
9474 break;
9475 case OPC_CLASS_D:
9476 check_insn(ctx, ISA_MIPS32R6);
9477 {
9478 TCGv_i64 fp0 = tcg_temp_new_i64();
9479 gen_load_fpr64(ctx, fp0, fs);
9480 gen_helper_float_class_d(fp0, fp0);
9481 gen_store_fpr64(ctx, fp0, fd);
9482 tcg_temp_free_i64(fp0);
9483 }
9484 break;
9485 case OPC_MIN_D: /* OPC_RECIP2_D */
9486 if (ctx->insn_flags & ISA_MIPS32R6) {
9487 /* OPC_MIN_D */
9488 TCGv_i64 fp0 = tcg_temp_new_i64();
9489 TCGv_i64 fp1 = tcg_temp_new_i64();
9490 gen_load_fpr64(ctx, fp0, fs);
9491 gen_load_fpr64(ctx, fp1, ft);
9492 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1);
9493 gen_store_fpr64(ctx, fp1, fd);
9494 tcg_temp_free_i64(fp1);
9495 tcg_temp_free_i64(fp0);
9496 } else {
9497 /* OPC_RECIP2_D */
9498 check_cp1_64bitmode(ctx);
9499 {
9500 TCGv_i64 fp0 = tcg_temp_new_i64();
9501 TCGv_i64 fp1 = tcg_temp_new_i64();
9502
9503 gen_load_fpr64(ctx, fp0, fs);
9504 gen_load_fpr64(ctx, fp1, ft);
9505 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1);
9506 tcg_temp_free_i64(fp1);
9507 gen_store_fpr64(ctx, fp0, fd);
9508 tcg_temp_free_i64(fp0);
9509 }
9510 }
9511 break;
9512 case OPC_MINA_D: /* OPC_RECIP1_D */
9513 if (ctx->insn_flags & ISA_MIPS32R6) {
9514 /* OPC_MINA_D */
9515 TCGv_i64 fp0 = tcg_temp_new_i64();
9516 TCGv_i64 fp1 = tcg_temp_new_i64();
9517 gen_load_fpr64(ctx, fp0, fs);
9518 gen_load_fpr64(ctx, fp1, ft);
9519 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1);
9520 gen_store_fpr64(ctx, fp1, fd);
9521 tcg_temp_free_i64(fp1);
9522 tcg_temp_free_i64(fp0);
9523 } else {
9524 /* OPC_RECIP1_D */
9525 check_cp1_64bitmode(ctx);
9526 {
9527 TCGv_i64 fp0 = tcg_temp_new_i64();
9528
9529 gen_load_fpr64(ctx, fp0, fs);
9530 gen_helper_float_recip1_d(fp0, cpu_env, fp0);
9531 gen_store_fpr64(ctx, fp0, fd);
9532 tcg_temp_free_i64(fp0);
9533 }
9534 }
9535 break;
9536 case OPC_MAX_D: /* OPC_RSQRT1_D */
9537 if (ctx->insn_flags & ISA_MIPS32R6) {
9538 /* OPC_MAX_D */
9539 TCGv_i64 fp0 = tcg_temp_new_i64();
9540 TCGv_i64 fp1 = tcg_temp_new_i64();
9541 gen_load_fpr64(ctx, fp0, fs);
9542 gen_load_fpr64(ctx, fp1, ft);
9543 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1);
9544 gen_store_fpr64(ctx, fp1, fd);
9545 tcg_temp_free_i64(fp1);
9546 tcg_temp_free_i64(fp0);
9547 } else {
9548 /* OPC_RSQRT1_D */
9549 check_cp1_64bitmode(ctx);
9550 {
9551 TCGv_i64 fp0 = tcg_temp_new_i64();
9552
9553 gen_load_fpr64(ctx, fp0, fs);
9554 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0);
9555 gen_store_fpr64(ctx, fp0, fd);
9556 tcg_temp_free_i64(fp0);
9557 }
9558 }
9559 break;
9560 case OPC_MAXA_D: /* OPC_RSQRT2_D */
9561 if (ctx->insn_flags & ISA_MIPS32R6) {
9562 /* OPC_MAXA_D */
9563 TCGv_i64 fp0 = tcg_temp_new_i64();
9564 TCGv_i64 fp1 = tcg_temp_new_i64();
9565 gen_load_fpr64(ctx, fp0, fs);
9566 gen_load_fpr64(ctx, fp1, ft);
9567 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1);
9568 gen_store_fpr64(ctx, fp1, fd);
9569 tcg_temp_free_i64(fp1);
9570 tcg_temp_free_i64(fp0);
9571 } else {
9572 /* OPC_RSQRT2_D */
9573 check_cp1_64bitmode(ctx);
9574 {
9575 TCGv_i64 fp0 = tcg_temp_new_i64();
9576 TCGv_i64 fp1 = tcg_temp_new_i64();
9577
9578 gen_load_fpr64(ctx, fp0, fs);
9579 gen_load_fpr64(ctx, fp1, ft);
9580 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1);
9581 tcg_temp_free_i64(fp1);
9582 gen_store_fpr64(ctx, fp0, fd);
9583 tcg_temp_free_i64(fp0);
9584 }
9585 }
9586 break;
9587 case OPC_CMP_F_D:
9588 case OPC_CMP_UN_D:
9589 case OPC_CMP_EQ_D:
9590 case OPC_CMP_UEQ_D:
9591 case OPC_CMP_OLT_D:
9592 case OPC_CMP_ULT_D:
9593 case OPC_CMP_OLE_D:
9594 case OPC_CMP_ULE_D:
9595 case OPC_CMP_SF_D:
9596 case OPC_CMP_NGLE_D:
9597 case OPC_CMP_SEQ_D:
9598 case OPC_CMP_NGL_D:
9599 case OPC_CMP_LT_D:
9600 case OPC_CMP_NGE_D:
9601 case OPC_CMP_LE_D:
9602 case OPC_CMP_NGT_D:
9603 check_insn_opc_removed(ctx, ISA_MIPS32R6);
9604 if (ctx->opcode & (1 << 6)) {
9605 gen_cmpabs_d(ctx, func-48, ft, fs, cc);
9606 } else {
9607 gen_cmp_d(ctx, func-48, ft, fs, cc);
9608 }
9609 break;
9610 case OPC_CVT_S_D:
9611 check_cp1_registers(ctx, fs);
9612 {
9613 TCGv_i32 fp32 = tcg_temp_new_i32();
9614 TCGv_i64 fp64 = tcg_temp_new_i64();
9615
9616 gen_load_fpr64(ctx, fp64, fs);
9617 gen_helper_float_cvts_d(fp32, cpu_env, fp64);
9618 tcg_temp_free_i64(fp64);
9619 gen_store_fpr32(ctx, fp32, fd);
9620 tcg_temp_free_i32(fp32);
9621 }
9622 break;
9623 case OPC_CVT_W_D:
9624 check_cp1_registers(ctx, fs);
9625 {
9626 TCGv_i32 fp32 = tcg_temp_new_i32();
9627 TCGv_i64 fp64 = tcg_temp_new_i64();
9628
9629 gen_load_fpr64(ctx, fp64, fs);
9630 gen_helper_float_cvtw_d(fp32, cpu_env, fp64);
9631 tcg_temp_free_i64(fp64);
9632 gen_store_fpr32(ctx, fp32, fd);
9633 tcg_temp_free_i32(fp32);
9634 }
9635 break;
9636 case OPC_CVT_L_D:
9637 check_cp1_64bitmode(ctx);
9638 {
9639 TCGv_i64 fp0 = tcg_temp_new_i64();
9640
9641 gen_load_fpr64(ctx, fp0, fs);
9642 gen_helper_float_cvtl_d(fp0, cpu_env, fp0);
9643 gen_store_fpr64(ctx, fp0, fd);
9644 tcg_temp_free_i64(fp0);
9645 }
9646 break;
9647 case OPC_CVT_S_W:
9648 {
9649 TCGv_i32 fp0 = tcg_temp_new_i32();
9650
9651 gen_load_fpr32(ctx, fp0, fs);
9652 gen_helper_float_cvts_w(fp0, cpu_env, fp0);
9653 gen_store_fpr32(ctx, fp0, fd);
9654 tcg_temp_free_i32(fp0);
9655 }
9656 break;
9657 case OPC_CVT_D_W:
9658 check_cp1_registers(ctx, fd);
9659 {
9660 TCGv_i32 fp32 = tcg_temp_new_i32();
9661 TCGv_i64 fp64 = tcg_temp_new_i64();
9662
9663 gen_load_fpr32(ctx, fp32, fs);
9664 gen_helper_float_cvtd_w(fp64, cpu_env, fp32);
9665 tcg_temp_free_i32(fp32);
9666 gen_store_fpr64(ctx, fp64, fd);
9667 tcg_temp_free_i64(fp64);
9668 }
9669 break;
9670 case OPC_CVT_S_L:
9671 check_cp1_64bitmode(ctx);
9672 {
9673 TCGv_i32 fp32 = tcg_temp_new_i32();
9674 TCGv_i64 fp64 = tcg_temp_new_i64();
9675
9676 gen_load_fpr64(ctx, fp64, fs);
9677 gen_helper_float_cvts_l(fp32, cpu_env, fp64);
9678 tcg_temp_free_i64(fp64);
9679 gen_store_fpr32(ctx, fp32, fd);
9680 tcg_temp_free_i32(fp32);
9681 }
9682 break;
9683 case OPC_CVT_D_L:
9684 check_cp1_64bitmode(ctx);
9685 {
9686 TCGv_i64 fp0 = tcg_temp_new_i64();
9687
9688 gen_load_fpr64(ctx, fp0, fs);
9689 gen_helper_float_cvtd_l(fp0, cpu_env, fp0);
9690 gen_store_fpr64(ctx, fp0, fd);
9691 tcg_temp_free_i64(fp0);
9692 }
9693 break;
9694 case OPC_CVT_PS_PW:
9695 check_ps(ctx);
9696 {
9697 TCGv_i64 fp0 = tcg_temp_new_i64();
9698
9699 gen_load_fpr64(ctx, fp0, fs);
9700 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0);
9701 gen_store_fpr64(ctx, fp0, fd);
9702 tcg_temp_free_i64(fp0);
9703 }
9704 break;
9705 case OPC_ADD_PS:
9706 check_ps(ctx);
9707 {
9708 TCGv_i64 fp0 = tcg_temp_new_i64();
9709 TCGv_i64 fp1 = tcg_temp_new_i64();
9710
9711 gen_load_fpr64(ctx, fp0, fs);
9712 gen_load_fpr64(ctx, fp1, ft);
9713 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1);
9714 tcg_temp_free_i64(fp1);
9715 gen_store_fpr64(ctx, fp0, fd);
9716 tcg_temp_free_i64(fp0);
9717 }
9718 break;
9719 case OPC_SUB_PS:
9720 check_ps(ctx);
9721 {
9722 TCGv_i64 fp0 = tcg_temp_new_i64();
9723 TCGv_i64 fp1 = tcg_temp_new_i64();
9724
9725 gen_load_fpr64(ctx, fp0, fs);
9726 gen_load_fpr64(ctx, fp1, ft);
9727 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1);
9728 tcg_temp_free_i64(fp1);
9729 gen_store_fpr64(ctx, fp0, fd);
9730 tcg_temp_free_i64(fp0);
9731 }
9732 break;
9733 case OPC_MUL_PS:
9734 check_ps(ctx);
9735 {
9736 TCGv_i64 fp0 = tcg_temp_new_i64();
9737 TCGv_i64 fp1 = tcg_temp_new_i64();
9738
9739 gen_load_fpr64(ctx, fp0, fs);
9740 gen_load_fpr64(ctx, fp1, ft);
9741 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1);
9742 tcg_temp_free_i64(fp1);
9743 gen_store_fpr64(ctx, fp0, fd);
9744 tcg_temp_free_i64(fp0);
9745 }
9746 break;
9747 case OPC_ABS_PS:
9748 check_ps(ctx);
9749 {
9750 TCGv_i64 fp0 = tcg_temp_new_i64();
9751
9752 gen_load_fpr64(ctx, fp0, fs);
9753 gen_helper_float_abs_ps(fp0, fp0);
9754 gen_store_fpr64(ctx, fp0, fd);
9755 tcg_temp_free_i64(fp0);
9756 }
9757 break;
9758 case OPC_MOV_PS:
9759 check_ps(ctx);
9760 {
9761 TCGv_i64 fp0 = tcg_temp_new_i64();
9762
9763 gen_load_fpr64(ctx, fp0, fs);
9764 gen_store_fpr64(ctx, fp0, fd);
9765 tcg_temp_free_i64(fp0);
9766 }
9767 break;
9768 case OPC_NEG_PS:
9769 check_ps(ctx);
9770 {
9771 TCGv_i64 fp0 = tcg_temp_new_i64();
9772
9773 gen_load_fpr64(ctx, fp0, fs);
9774 gen_helper_float_chs_ps(fp0, fp0);
9775 gen_store_fpr64(ctx, fp0, fd);
9776 tcg_temp_free_i64(fp0);
9777 }
9778 break;
9779 case OPC_MOVCF_PS:
9780 check_ps(ctx);
9781 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
9782 break;
9783 case OPC_MOVZ_PS:
9784 check_ps(ctx);
9785 {
9786 TCGLabel *l1 = gen_new_label();
9787 TCGv_i64 fp0;
9788
9789 if (ft != 0)
9790 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
9791 fp0 = tcg_temp_new_i64();
9792 gen_load_fpr64(ctx, fp0, fs);
9793 gen_store_fpr64(ctx, fp0, fd);
9794 tcg_temp_free_i64(fp0);
9795 gen_set_label(l1);
9796 }
9797 break;
9798 case OPC_MOVN_PS:
9799 check_ps(ctx);
9800 {
9801 TCGLabel *l1 = gen_new_label();
9802 TCGv_i64 fp0;
9803
9804 if (ft != 0) {
9805 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
9806 fp0 = tcg_temp_new_i64();
9807 gen_load_fpr64(ctx, fp0, fs);
9808 gen_store_fpr64(ctx, fp0, fd);
9809 tcg_temp_free_i64(fp0);
9810 gen_set_label(l1);
9811 }
9812 }
9813 break;
9814 case OPC_ADDR_PS:
9815 check_ps(ctx);
9816 {
9817 TCGv_i64 fp0 = tcg_temp_new_i64();
9818 TCGv_i64 fp1 = tcg_temp_new_i64();
9819
9820 gen_load_fpr64(ctx, fp0, ft);
9821 gen_load_fpr64(ctx, fp1, fs);
9822 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1);
9823 tcg_temp_free_i64(fp1);
9824 gen_store_fpr64(ctx, fp0, fd);
9825 tcg_temp_free_i64(fp0);
9826 }
9827 break;
9828 case OPC_MULR_PS:
9829 check_ps(ctx);
9830 {
9831 TCGv_i64 fp0 = tcg_temp_new_i64();
9832 TCGv_i64 fp1 = tcg_temp_new_i64();
9833
9834 gen_load_fpr64(ctx, fp0, ft);
9835 gen_load_fpr64(ctx, fp1, fs);
9836 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1);
9837 tcg_temp_free_i64(fp1);
9838 gen_store_fpr64(ctx, fp0, fd);
9839 tcg_temp_free_i64(fp0);
9840 }
9841 break;
9842 case OPC_RECIP2_PS:
9843 check_ps(ctx);
9844 {
9845 TCGv_i64 fp0 = tcg_temp_new_i64();
9846 TCGv_i64 fp1 = tcg_temp_new_i64();
9847
9848 gen_load_fpr64(ctx, fp0, fs);
9849 gen_load_fpr64(ctx, fp1, ft);
9850 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1);
9851 tcg_temp_free_i64(fp1);
9852 gen_store_fpr64(ctx, fp0, fd);
9853 tcg_temp_free_i64(fp0);
9854 }
9855 break;
9856 case OPC_RECIP1_PS:
9857 check_ps(ctx);
9858 {
9859 TCGv_i64 fp0 = tcg_temp_new_i64();
9860
9861 gen_load_fpr64(ctx, fp0, fs);
9862 gen_helper_float_recip1_ps(fp0, cpu_env, fp0);
9863 gen_store_fpr64(ctx, fp0, fd);
9864 tcg_temp_free_i64(fp0);
9865 }
9866 break;
9867 case OPC_RSQRT1_PS:
9868 check_ps(ctx);
9869 {
9870 TCGv_i64 fp0 = tcg_temp_new_i64();
9871
9872 gen_load_fpr64(ctx, fp0, fs);
9873 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0);
9874 gen_store_fpr64(ctx, fp0, fd);
9875 tcg_temp_free_i64(fp0);
9876 }
9877 break;
9878 case OPC_RSQRT2_PS:
9879 check_ps(ctx);
9880 {
9881 TCGv_i64 fp0 = tcg_temp_new_i64();
9882 TCGv_i64 fp1 = tcg_temp_new_i64();
9883
9884 gen_load_fpr64(ctx, fp0, fs);
9885 gen_load_fpr64(ctx, fp1, ft);
9886 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1);
9887 tcg_temp_free_i64(fp1);
9888 gen_store_fpr64(ctx, fp0, fd);
9889 tcg_temp_free_i64(fp0);
9890 }
9891 break;
9892 case OPC_CVT_S_PU:
9893 check_cp1_64bitmode(ctx);
9894 {
9895 TCGv_i32 fp0 = tcg_temp_new_i32();
9896
9897 gen_load_fpr32h(ctx, fp0, fs);
9898 gen_helper_float_cvts_pu(fp0, cpu_env, fp0);
9899 gen_store_fpr32(ctx, fp0, fd);
9900 tcg_temp_free_i32(fp0);
9901 }
9902 break;
9903 case OPC_CVT_PW_PS:
9904 check_ps(ctx);
9905 {
9906 TCGv_i64 fp0 = tcg_temp_new_i64();
9907
9908 gen_load_fpr64(ctx, fp0, fs);
9909 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0);
9910 gen_store_fpr64(ctx, fp0, fd);
9911 tcg_temp_free_i64(fp0);
9912 }
9913 break;
9914 case OPC_CVT_S_PL:
9915 check_cp1_64bitmode(ctx);
9916 {
9917 TCGv_i32 fp0 = tcg_temp_new_i32();
9918
9919 gen_load_fpr32(ctx, fp0, fs);
9920 gen_helper_float_cvts_pl(fp0, cpu_env, fp0);
9921 gen_store_fpr32(ctx, fp0, fd);
9922 tcg_temp_free_i32(fp0);
9923 }
9924 break;
9925 case OPC_PLL_PS:
9926 check_ps(ctx);
9927 {
9928 TCGv_i32 fp0 = tcg_temp_new_i32();
9929 TCGv_i32 fp1 = tcg_temp_new_i32();
9930
9931 gen_load_fpr32(ctx, fp0, fs);
9932 gen_load_fpr32(ctx, fp1, ft);
9933 gen_store_fpr32h(ctx, fp0, fd);
9934 gen_store_fpr32(ctx, fp1, fd);
9935 tcg_temp_free_i32(fp0);
9936 tcg_temp_free_i32(fp1);
9937 }
9938 break;
9939 case OPC_PLU_PS:
9940 check_ps(ctx);
9941 {
9942 TCGv_i32 fp0 = tcg_temp_new_i32();
9943 TCGv_i32 fp1 = tcg_temp_new_i32();
9944
9945 gen_load_fpr32(ctx, fp0, fs);
9946 gen_load_fpr32h(ctx, fp1, ft);
9947 gen_store_fpr32(ctx, fp1, fd);
9948 gen_store_fpr32h(ctx, fp0, fd);
9949 tcg_temp_free_i32(fp0);
9950 tcg_temp_free_i32(fp1);
9951 }
9952 break;
9953 case OPC_PUL_PS:
9954 check_ps(ctx);
9955 {
9956 TCGv_i32 fp0 = tcg_temp_new_i32();
9957 TCGv_i32 fp1 = tcg_temp_new_i32();
9958
9959 gen_load_fpr32h(ctx, fp0, fs);
9960 gen_load_fpr32(ctx, fp1, ft);
9961 gen_store_fpr32(ctx, fp1, fd);
9962 gen_store_fpr32h(ctx, fp0, fd);
9963 tcg_temp_free_i32(fp0);
9964 tcg_temp_free_i32(fp1);
9965 }
9966 break;
9967 case OPC_PUU_PS:
9968 check_ps(ctx);
9969 {
9970 TCGv_i32 fp0 = tcg_temp_new_i32();
9971 TCGv_i32 fp1 = tcg_temp_new_i32();
9972
9973 gen_load_fpr32h(ctx, fp0, fs);
9974 gen_load_fpr32h(ctx, fp1, ft);
9975 gen_store_fpr32(ctx, fp1, fd);
9976 gen_store_fpr32h(ctx, fp0, fd);
9977 tcg_temp_free_i32(fp0);
9978 tcg_temp_free_i32(fp1);
9979 }
9980 break;
9981 case OPC_CMP_F_PS:
9982 case OPC_CMP_UN_PS:
9983 case OPC_CMP_EQ_PS:
9984 case OPC_CMP_UEQ_PS:
9985 case OPC_CMP_OLT_PS:
9986 case OPC_CMP_ULT_PS:
9987 case OPC_CMP_OLE_PS:
9988 case OPC_CMP_ULE_PS:
9989 case OPC_CMP_SF_PS:
9990 case OPC_CMP_NGLE_PS:
9991 case OPC_CMP_SEQ_PS:
9992 case OPC_CMP_NGL_PS:
9993 case OPC_CMP_LT_PS:
9994 case OPC_CMP_NGE_PS:
9995 case OPC_CMP_LE_PS:
9996 case OPC_CMP_NGT_PS:
9997 if (ctx->opcode & (1 << 6)) {
9998 gen_cmpabs_ps(ctx, func-48, ft, fs, cc);
9999 } else {
10000 gen_cmp_ps(ctx, func-48, ft, fs, cc);
10001 }
10002 break;
10003 default:
10004 MIPS_INVAL("farith");
10005 generate_exception (ctx, EXCP_RI);
10006 return;
10007 }
10008 }
10009
10010 /* Coprocessor 3 (FPU) */
10011 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
10012 int fd, int fs, int base, int index)
10013 {
10014 TCGv t0 = tcg_temp_new();
10015
10016 if (base == 0) {
10017 gen_load_gpr(t0, index);
10018 } else if (index == 0) {
10019 gen_load_gpr(t0, base);
10020 } else {
10021 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
10022 }
10023 /* Don't do NOP if destination is zero: we must perform the actual
10024 memory access. */
10025 switch (opc) {
10026 case OPC_LWXC1:
10027 check_cop1x(ctx);
10028 {
10029 TCGv_i32 fp0 = tcg_temp_new_i32();
10030
10031 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
10032 tcg_gen_trunc_tl_i32(fp0, t0);
10033 gen_store_fpr32(ctx, fp0, fd);
10034 tcg_temp_free_i32(fp0);
10035 }
10036 break;
10037 case OPC_LDXC1:
10038 check_cop1x(ctx);
10039 check_cp1_registers(ctx, fd);
10040 {
10041 TCGv_i64 fp0 = tcg_temp_new_i64();
10042 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10043 gen_store_fpr64(ctx, fp0, fd);
10044 tcg_temp_free_i64(fp0);
10045 }
10046 break;
10047 case OPC_LUXC1:
10048 check_cp1_64bitmode(ctx);
10049 tcg_gen_andi_tl(t0, t0, ~0x7);
10050 {
10051 TCGv_i64 fp0 = tcg_temp_new_i64();
10052
10053 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10054 gen_store_fpr64(ctx, fp0, fd);
10055 tcg_temp_free_i64(fp0);
10056 }
10057 break;
10058 case OPC_SWXC1:
10059 check_cop1x(ctx);
10060 {
10061 TCGv_i32 fp0 = tcg_temp_new_i32();
10062 gen_load_fpr32(ctx, fp0, fs);
10063 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
10064 tcg_temp_free_i32(fp0);
10065 }
10066 break;
10067 case OPC_SDXC1:
10068 check_cop1x(ctx);
10069 check_cp1_registers(ctx, fs);
10070 {
10071 TCGv_i64 fp0 = tcg_temp_new_i64();
10072 gen_load_fpr64(ctx, fp0, fs);
10073 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10074 tcg_temp_free_i64(fp0);
10075 }
10076 break;
10077 case OPC_SUXC1:
10078 check_cp1_64bitmode(ctx);
10079 tcg_gen_andi_tl(t0, t0, ~0x7);
10080 {
10081 TCGv_i64 fp0 = tcg_temp_new_i64();
10082 gen_load_fpr64(ctx, fp0, fs);
10083 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
10084 tcg_temp_free_i64(fp0);
10085 }
10086 break;
10087 }
10088 tcg_temp_free(t0);
10089 }
10090
10091 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
10092 int fd, int fr, int fs, int ft)
10093 {
10094 switch (opc) {
10095 case OPC_ALNV_PS:
10096 check_ps(ctx);
10097 {
10098 TCGv t0 = tcg_temp_local_new();
10099 TCGv_i32 fp = tcg_temp_new_i32();
10100 TCGv_i32 fph = tcg_temp_new_i32();
10101 TCGLabel *l1 = gen_new_label();
10102 TCGLabel *l2 = gen_new_label();
10103
10104 gen_load_gpr(t0, fr);
10105 tcg_gen_andi_tl(t0, t0, 0x7);
10106
10107 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
10108 gen_load_fpr32(ctx, fp, fs);
10109 gen_load_fpr32h(ctx, fph, fs);
10110 gen_store_fpr32(ctx, fp, fd);
10111 gen_store_fpr32h(ctx, fph, fd);
10112 tcg_gen_br(l2);
10113 gen_set_label(l1);
10114 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
10115 tcg_temp_free(t0);
10116 #ifdef TARGET_WORDS_BIGENDIAN
10117 gen_load_fpr32(ctx, fp, fs);
10118 gen_load_fpr32h(ctx, fph, ft);
10119 gen_store_fpr32h(ctx, fp, fd);
10120 gen_store_fpr32(ctx, fph, fd);
10121 #else
10122 gen_load_fpr32h(ctx, fph, fs);
10123 gen_load_fpr32(ctx, fp, ft);
10124 gen_store_fpr32(ctx, fph, fd);
10125 gen_store_fpr32h(ctx, fp, fd);
10126 #endif
10127 gen_set_label(l2);
10128 tcg_temp_free_i32(fp);
10129 tcg_temp_free_i32(fph);
10130 }
10131 break;
10132 case OPC_MADD_S:
10133 check_cop1x(ctx);
10134 {
10135 TCGv_i32 fp0 = tcg_temp_new_i32();
10136 TCGv_i32 fp1 = tcg_temp_new_i32();
10137 TCGv_i32 fp2 = tcg_temp_new_i32();
10138
10139 gen_load_fpr32(ctx, fp0, fs);
10140 gen_load_fpr32(ctx, fp1, ft);
10141 gen_load_fpr32(ctx, fp2, fr);
10142 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);
10143 tcg_temp_free_i32(fp0);
10144 tcg_temp_free_i32(fp1);
10145 gen_store_fpr32(ctx, fp2, fd);
10146 tcg_temp_free_i32(fp2);
10147 }
10148 break;
10149 case OPC_MADD_D:
10150 check_cop1x(ctx);
10151 check_cp1_registers(ctx, fd | fs | ft | fr);
10152 {
10153 TCGv_i64 fp0 = tcg_temp_new_i64();
10154 TCGv_i64 fp1 = tcg_temp_new_i64();
10155 TCGv_i64 fp2 = tcg_temp_new_i64();
10156
10157 gen_load_fpr64(ctx, fp0, fs);
10158 gen_load_fpr64(ctx, fp1, ft);
10159 gen_load_fpr64(ctx, fp2, fr);
10160 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);
10161 tcg_temp_free_i64(fp0);
10162 tcg_temp_free_i64(fp1);
10163 gen_store_fpr64(ctx, fp2, fd);
10164 tcg_temp_free_i64(fp2);
10165 }
10166 break;
10167 case OPC_MADD_PS:
10168 check_ps(ctx);
10169 {
10170 TCGv_i64 fp0 = tcg_temp_new_i64();
10171 TCGv_i64 fp1 = tcg_temp_new_i64();
10172 TCGv_i64 fp2 = tcg_temp_new_i64();
10173
10174 gen_load_fpr64(ctx, fp0, fs);
10175 gen_load_fpr64(ctx, fp1, ft);
10176 gen_load_fpr64(ctx, fp2, fr);
10177 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);
10178 tcg_temp_free_i64(fp0);
10179 tcg_temp_free_i64(fp1);
10180 gen_store_fpr64(ctx, fp2, fd);
10181 tcg_temp_free_i64(fp2);
10182 }
10183 break;
10184 case OPC_MSUB_S:
10185 check_cop1x(ctx);
10186 {
10187 TCGv_i32 fp0 = tcg_temp_new_i32();
10188 TCGv_i32 fp1 = tcg_temp_new_i32();
10189 TCGv_i32 fp2 = tcg_temp_new_i32();
10190
10191 gen_load_fpr32(ctx, fp0, fs);
10192 gen_load_fpr32(ctx, fp1, ft);
10193 gen_load_fpr32(ctx, fp2, fr);
10194 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);
10195 tcg_temp_free_i32(fp0);
10196 tcg_temp_free_i32(fp1);
10197 gen_store_fpr32(ctx, fp2, fd);
10198 tcg_temp_free_i32(fp2);
10199 }
10200 break;
10201 case OPC_MSUB_D:
10202 check_cop1x(ctx);
10203 check_cp1_registers(ctx, fd | fs | ft | fr);
10204 {
10205 TCGv_i64 fp0 = tcg_temp_new_i64();
10206 TCGv_i64 fp1 = tcg_temp_new_i64();
10207 TCGv_i64 fp2 = tcg_temp_new_i64();
10208
10209 gen_load_fpr64(ctx, fp0, fs);
10210 gen_load_fpr64(ctx, fp1, ft);
10211 gen_load_fpr64(ctx, fp2, fr);
10212 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);
10213 tcg_temp_free_i64(fp0);
10214 tcg_temp_free_i64(fp1);
10215 gen_store_fpr64(ctx, fp2, fd);
10216 tcg_temp_free_i64(fp2);
10217 }
10218 break;
10219 case OPC_MSUB_PS:
10220 check_ps(ctx);
10221 {
10222 TCGv_i64 fp0 = tcg_temp_new_i64();
10223 TCGv_i64 fp1 = tcg_temp_new_i64();
10224 TCGv_i64 fp2 = tcg_temp_new_i64();
10225
10226 gen_load_fpr64(ctx, fp0, fs);
10227 gen_load_fpr64(ctx, fp1, ft);
10228 gen_load_fpr64(ctx, fp2, fr);
10229 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);
10230 tcg_temp_free_i64(fp0);
10231 tcg_temp_free_i64(fp1);
10232 gen_store_fpr64(ctx, fp2, fd);
10233 tcg_temp_free_i64(fp2);
10234 }
10235 break;
10236 case OPC_NMADD_S:
10237 check_cop1x(ctx);
10238 {
10239 TCGv_i32 fp0 = tcg_temp_new_i32();
10240 TCGv_i32 fp1 = tcg_temp_new_i32();
10241 TCGv_i32 fp2 = tcg_temp_new_i32();
10242
10243 gen_load_fpr32(ctx, fp0, fs);
10244 gen_load_fpr32(ctx, fp1, ft);
10245 gen_load_fpr32(ctx, fp2, fr);
10246 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);
10247 tcg_temp_free_i32(fp0);
10248 tcg_temp_free_i32(fp1);
10249 gen_store_fpr32(ctx, fp2, fd);
10250 tcg_temp_free_i32(fp2);
10251 }
10252 break;
10253 case OPC_NMADD_D:
10254 check_cop1x(ctx);
10255 check_cp1_registers(ctx, fd | fs | ft | fr);
10256 {
10257 TCGv_i64 fp0 = tcg_temp_new_i64();
10258 TCGv_i64 fp1 = tcg_temp_new_i64();
10259 TCGv_i64 fp2 = tcg_temp_new_i64();
10260
10261 gen_load_fpr64(ctx, fp0, fs);
10262 gen_load_fpr64(ctx, fp1, ft);
10263 gen_load_fpr64(ctx, fp2, fr);
10264 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);
10265 tcg_temp_free_i64(fp0);
10266 tcg_temp_free_i64(fp1);
10267 gen_store_fpr64(ctx, fp2, fd);
10268 tcg_temp_free_i64(fp2);
10269 }
10270 break;
10271 case OPC_NMADD_PS:
10272 check_ps(ctx);
10273 {
10274 TCGv_i64 fp0 = tcg_temp_new_i64();
10275 TCGv_i64 fp1 = tcg_temp_new_i64();
10276 TCGv_i64 fp2 = tcg_temp_new_i64();
10277
10278 gen_load_fpr64(ctx, fp0, fs);
10279 gen_load_fpr64(ctx, fp1, ft);
10280 gen_load_fpr64(ctx, fp2, fr);
10281 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);
10282 tcg_temp_free_i64(fp0);
10283 tcg_temp_free_i64(fp1);
10284 gen_store_fpr64(ctx, fp2, fd);
10285 tcg_temp_free_i64(fp2);
10286 }
10287 break;
10288 case OPC_NMSUB_S:
10289 check_cop1x(ctx);
10290 {
10291 TCGv_i32 fp0 = tcg_temp_new_i32();
10292 TCGv_i32 fp1 = tcg_temp_new_i32();
10293 TCGv_i32 fp2 = tcg_temp_new_i32();
10294
10295 gen_load_fpr32(ctx, fp0, fs);
10296 gen_load_fpr32(ctx, fp1, ft);
10297 gen_load_fpr32(ctx, fp2, fr);
10298 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);
10299 tcg_temp_free_i32(fp0);
10300 tcg_temp_free_i32(fp1);
10301 gen_store_fpr32(ctx, fp2, fd);
10302 tcg_temp_free_i32(fp2);
10303 }
10304 break;
10305 case OPC_NMSUB_D:
10306 check_cop1x(ctx);
10307 check_cp1_registers(ctx, fd | fs | ft | fr);
10308 {
10309 TCGv_i64 fp0 = tcg_temp_new_i64();
10310 TCGv_i64 fp1 = tcg_temp_new_i64();
10311 TCGv_i64 fp2 = tcg_temp_new_i64();
10312
10313 gen_load_fpr64(ctx, fp0, fs);
10314 gen_load_fpr64(ctx, fp1, ft);
10315 gen_load_fpr64(ctx, fp2, fr);
10316 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);
10317 tcg_temp_free_i64(fp0);
10318 tcg_temp_free_i64(fp1);
10319 gen_store_fpr64(ctx, fp2, fd);
10320 tcg_temp_free_i64(fp2);
10321 }
10322 break;
10323 case OPC_NMSUB_PS:
10324 check_ps(ctx);
10325 {
10326 TCGv_i64 fp0 = tcg_temp_new_i64();
10327 TCGv_i64 fp1 = tcg_temp_new_i64();
10328 TCGv_i64 fp2 = tcg_temp_new_i64();
10329
10330 gen_load_fpr64(ctx, fp0, fs);
10331 gen_load_fpr64(ctx, fp1, ft);
10332 gen_load_fpr64(ctx, fp2, fr);
10333 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);
10334 tcg_temp_free_i64(fp0);
10335 tcg_temp_free_i64(fp1);
10336 gen_store_fpr64(ctx, fp2, fd);
10337 tcg_temp_free_i64(fp2);
10338 }
10339 break;
10340 default:
10341 MIPS_INVAL("flt3_arith");
10342 generate_exception (ctx, EXCP_RI);
10343 return;
10344 }
10345 }
10346
10347 static void gen_rdhwr(DisasContext *ctx, int rt, int rd)
10348 {
10349 TCGv t0;
10350
10351 #if !defined(CONFIG_USER_ONLY)
10352 /* The Linux kernel will emulate rdhwr if it's not supported natively.
10353 Therefore only check the ISA in system mode. */
10354 check_insn(ctx, ISA_MIPS32R2);
10355 #endif
10356 t0 = tcg_temp_new();
10357
10358 switch (rd) {
10359 case 0:
10360 save_cpu_state(ctx, 1);
10361 gen_helper_rdhwr_cpunum(t0, cpu_env);
10362 gen_store_gpr(t0, rt);
10363 break;
10364 case 1:
10365 save_cpu_state(ctx, 1);
10366 gen_helper_rdhwr_synci_step(t0, cpu_env);
10367 gen_store_gpr(t0, rt);
10368 break;
10369 case 2:
10370 save_cpu_state(ctx, 1);
10371 gen_helper_rdhwr_cc(t0, cpu_env);
10372 gen_store_gpr(t0, rt);
10373 break;
10374 case 3:
10375 save_cpu_state(ctx, 1);
10376 gen_helper_rdhwr_ccres(t0, cpu_env);
10377 gen_store_gpr(t0, rt);
10378 break;
10379 case 29:
10380 #if defined(CONFIG_USER_ONLY)
10381 tcg_gen_ld_tl(t0, cpu_env,
10382 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
10383 gen_store_gpr(t0, rt);
10384 break;
10385 #else
10386 if ((ctx->hflags & MIPS_HFLAG_CP0) ||
10387 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
10388 tcg_gen_ld_tl(t0, cpu_env,
10389 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
10390 gen_store_gpr(t0, rt);
10391 } else {
10392 generate_exception(ctx, EXCP_RI);
10393 }
10394 break;
10395 #endif
10396 default: /* Invalid */
10397 MIPS_INVAL("rdhwr");
10398 generate_exception(ctx, EXCP_RI);
10399 break;
10400 }
10401 tcg_temp_free(t0);
10402 }
10403
10404 static inline void clear_branch_hflags(DisasContext *ctx)
10405 {
10406 ctx->hflags &= ~MIPS_HFLAG_BMASK;
10407 if (ctx->bstate == BS_NONE) {
10408 save_cpu_state(ctx, 0);
10409 } else {
10410 /* it is not safe to save ctx->hflags as hflags may be changed
10411 in execution time by the instruction in delay / forbidden slot. */
10412 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK);
10413 }
10414 }
10415
10416 static void gen_branch(DisasContext *ctx, int insn_bytes)
10417 {
10418 if (ctx->hflags & MIPS_HFLAG_BMASK) {
10419 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
10420 /* Branches completion */
10421 clear_branch_hflags(ctx);
10422 ctx->bstate = BS_BRANCH;
10423 /* FIXME: Need to clear can_do_io. */
10424 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
10425 case MIPS_HFLAG_FBNSLOT:
10426 gen_goto_tb(ctx, 0, ctx->pc + insn_bytes);
10427 break;
10428 case MIPS_HFLAG_B:
10429 /* unconditional branch */
10430 if (proc_hflags & MIPS_HFLAG_BX) {
10431 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
10432 }
10433 gen_goto_tb(ctx, 0, ctx->btarget);
10434 break;
10435 case MIPS_HFLAG_BL:
10436 /* blikely taken case */
10437 gen_goto_tb(ctx, 0, ctx->btarget);
10438 break;
10439 case MIPS_HFLAG_BC:
10440 /* Conditional branch */
10441 {
10442 TCGLabel *l1 = gen_new_label();
10443
10444 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
10445 gen_goto_tb(ctx, 1, ctx->pc + insn_bytes);
10446 gen_set_label(l1);
10447 gen_goto_tb(ctx, 0, ctx->btarget);
10448 }
10449 break;
10450 case MIPS_HFLAG_BR:
10451 /* unconditional branch to register */
10452 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
10453 TCGv t0 = tcg_temp_new();
10454 TCGv_i32 t1 = tcg_temp_new_i32();
10455
10456 tcg_gen_andi_tl(t0, btarget, 0x1);
10457 tcg_gen_trunc_tl_i32(t1, t0);
10458 tcg_temp_free(t0);
10459 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
10460 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
10461 tcg_gen_or_i32(hflags, hflags, t1);
10462 tcg_temp_free_i32(t1);
10463
10464 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
10465 } else {
10466 tcg_gen_mov_tl(cpu_PC, btarget);
10467 }
10468 if (ctx->singlestep_enabled) {
10469 save_cpu_state(ctx, 0);
10470 gen_helper_0e0i(raise_exception, EXCP_DEBUG);
10471 }
10472 tcg_gen_exit_tb(0);
10473 break;
10474 default:
10475 fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
10476 abort();
10477 }
10478 }
10479 }
10480
10481 /* Compact Branches */
10482 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
10483 int rs, int rt, int32_t offset)
10484 {
10485 int bcond_compute = 0;
10486 TCGv t0 = tcg_temp_new();
10487 TCGv t1 = tcg_temp_new();
10488 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
10489
10490 if (ctx->hflags & MIPS_HFLAG_BMASK) {
10491 #ifdef MIPS_DEBUG_DISAS
10492 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
10493 "\n", ctx->pc);
10494 #endif
10495 generate_exception(ctx, EXCP_RI);
10496 goto out;
10497 }
10498
10499 /* Load needed operands and calculate btarget */
10500 switch (opc) {
10501 /* compact branch */
10502 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
10503 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
10504 gen_load_gpr(t0, rs);
10505 gen_load_gpr(t1, rt);
10506 bcond_compute = 1;
10507 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10508 if (rs <= rt && rs == 0) {
10509 /* OPC_BEQZALC, OPC_BNEZALC */
10510 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10511 }
10512 break;
10513 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
10514 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
10515 gen_load_gpr(t0, rs);
10516 gen_load_gpr(t1, rt);
10517 bcond_compute = 1;
10518 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10519 break;
10520 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
10521 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
10522 if (rs == 0 || rs == rt) {
10523 /* OPC_BLEZALC, OPC_BGEZALC */
10524 /* OPC_BGTZALC, OPC_BLTZALC */
10525 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10526 }
10527 gen_load_gpr(t0, rs);
10528 gen_load_gpr(t1, rt);
10529 bcond_compute = 1;
10530 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10531 break;
10532 case OPC_BC:
10533 case OPC_BALC:
10534 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10535 break;
10536 case OPC_BEQZC:
10537 case OPC_BNEZC:
10538 if (rs != 0) {
10539 /* OPC_BEQZC, OPC_BNEZC */
10540 gen_load_gpr(t0, rs);
10541 bcond_compute = 1;
10542 ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
10543 } else {
10544 /* OPC_JIC, OPC_JIALC */
10545 TCGv tbase = tcg_temp_new();
10546 TCGv toffset = tcg_temp_new();
10547
10548 gen_load_gpr(tbase, rt);
10549 tcg_gen_movi_tl(toffset, offset);
10550 gen_op_addr_add(ctx, btarget, tbase, toffset);
10551 tcg_temp_free(tbase);
10552 tcg_temp_free(toffset);
10553 }
10554 break;
10555 default:
10556 MIPS_INVAL("Compact branch/jump");
10557 generate_exception(ctx, EXCP_RI);
10558 goto out;
10559 }
10560
10561 if (bcond_compute == 0) {
10562 /* Uncoditional compact branch */
10563 switch (opc) {
10564 case OPC_JIALC:
10565 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10566 /* Fallthrough */
10567 case OPC_JIC:
10568 ctx->hflags |= MIPS_HFLAG_BR;
10569 break;
10570 case OPC_BALC:
10571 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4 + m16_lowbit);
10572 /* Fallthrough */
10573 case OPC_BC:
10574 ctx->hflags |= MIPS_HFLAG_B;
10575 break;
10576 default:
10577 MIPS_INVAL("Compact branch/jump");
10578 generate_exception(ctx, EXCP_RI);
10579 goto out;
10580 }
10581
10582 /* Generating branch here as compact branches don't have delay slot */
10583 gen_branch(ctx, 4);
10584 } else {
10585 /* Conditional compact branch */
10586 TCGLabel *fs = gen_new_label();
10587 save_cpu_state(ctx, 0);
10588
10589 switch (opc) {
10590 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
10591 if (rs == 0 && rt != 0) {
10592 /* OPC_BLEZALC */
10593 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
10594 } else if (rs != 0 && rt != 0 && rs == rt) {
10595 /* OPC_BGEZALC */
10596 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
10597 } else {
10598 /* OPC_BGEUC */
10599 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
10600 }
10601 break;
10602 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
10603 if (rs == 0 && rt != 0) {
10604 /* OPC_BGTZALC */
10605 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
10606 } else if (rs != 0 && rt != 0 && rs == rt) {
10607 /* OPC_BLTZALC */
10608 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
10609 } else {
10610 /* OPC_BLTUC */
10611 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
10612 }
10613 break;
10614 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
10615 if (rs == 0 && rt != 0) {
10616 /* OPC_BLEZC */
10617 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
10618 } else if (rs != 0 && rt != 0 && rs == rt) {
10619 /* OPC_BGEZC */
10620 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
10621 } else {
10622 /* OPC_BGEC */
10623 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
10624 }
10625 break;
10626 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
10627 if (rs == 0 && rt != 0) {
10628 /* OPC_BGTZC */
10629 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
10630 } else if (rs != 0 && rt != 0 && rs == rt) {
10631 /* OPC_BLTZC */
10632 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
10633 } else {
10634 /* OPC_BLTC */
10635 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
10636 }
10637 break;
10638 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
10639 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
10640 if (rs >= rt) {
10641 /* OPC_BOVC, OPC_BNVC */
10642 TCGv t2 = tcg_temp_new();
10643 TCGv t3 = tcg_temp_new();
10644 TCGv t4 = tcg_temp_new();
10645 TCGv input_overflow = tcg_temp_new();
10646
10647 gen_load_gpr(t0, rs);
10648 gen_load_gpr(t1, rt);
10649 tcg_gen_ext32s_tl(t2, t0);
10650 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
10651 tcg_gen_ext32s_tl(t3, t1);
10652 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
10653 tcg_gen_or_tl(input_overflow, input_overflow, t4);
10654
10655 tcg_gen_add_tl(t4, t2, t3);
10656 tcg_gen_ext32s_tl(t4, t4);
10657 tcg_gen_xor_tl(t2, t2, t3);
10658 tcg_gen_xor_tl(t3, t4, t3);
10659 tcg_gen_andc_tl(t2, t3, t2);
10660 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
10661 tcg_gen_or_tl(t4, t4, input_overflow);
10662 if (opc == OPC_BOVC) {
10663 /* OPC_BOVC */
10664 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
10665 } else {
10666 /* OPC_BNVC */
10667 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
10668 }
10669 tcg_temp_free(input_overflow);
10670 tcg_temp_free(t4);
10671 tcg_temp_free(t3);
10672 tcg_temp_free(t2);
10673 } else if (rs < rt && rs == 0) {
10674 /* OPC_BEQZALC, OPC_BNEZALC */
10675 if (opc == OPC_BEQZALC) {
10676 /* OPC_BEQZALC */
10677 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
10678 } else {
10679 /* OPC_BNEZALC */
10680 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
10681 }
10682 } else {
10683 /* OPC_BEQC, OPC_BNEC */
10684 if (opc == OPC_BEQC) {
10685 /* OPC_BEQC */
10686 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
10687 } else {
10688 /* OPC_BNEC */
10689 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
10690 }
10691 }
10692 break;
10693 case OPC_BEQZC:
10694 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
10695 break;
10696 case OPC_BNEZC:
10697 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
10698 break;
10699 default:
10700 MIPS_INVAL("Compact conditional branch/jump");
10701 generate_exception(ctx, EXCP_RI);
10702 goto out;
10703 }
10704
10705 /* Generating branch here as compact branches don't have delay slot */
10706 gen_goto_tb(ctx, 1, ctx->btarget);
10707 gen_set_label(fs);
10708
10709 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
10710 }
10711
10712 out:
10713 tcg_temp_free(t0);
10714 tcg_temp_free(t1);
10715 }
10716
10717 /* ISA extensions (ASEs) */
10718 /* MIPS16 extension to MIPS32 */
10719
10720 /* MIPS16 major opcodes */
10721 enum {
10722 M16_OPC_ADDIUSP = 0x00,
10723 M16_OPC_ADDIUPC = 0x01,
10724 M16_OPC_B = 0x02,
10725 M16_OPC_JAL = 0x03,
10726 M16_OPC_BEQZ = 0x04,
10727 M16_OPC_BNEQZ = 0x05,
10728 M16_OPC_SHIFT = 0x06,
10729 M16_OPC_LD = 0x07,
10730 M16_OPC_RRIA = 0x08,
10731 M16_OPC_ADDIU8 = 0x09,
10732 M16_OPC_SLTI = 0x0a,
10733 M16_OPC_SLTIU = 0x0b,
10734 M16_OPC_I8 = 0x0c,
10735 M16_OPC_LI = 0x0d,
10736 M16_OPC_CMPI = 0x0e,
10737 M16_OPC_SD = 0x0f,
10738 M16_OPC_LB = 0x10,
10739 M16_OPC_LH = 0x11,
10740 M16_OPC_LWSP = 0x12,
10741 M16_OPC_LW = 0x13,
10742 M16_OPC_LBU = 0x14,
10743 M16_OPC_LHU = 0x15,
10744 M16_OPC_LWPC = 0x16,
10745 M16_OPC_LWU = 0x17,
10746 M16_OPC_SB = 0x18,
10747 M16_OPC_SH = 0x19,
10748 M16_OPC_SWSP = 0x1a,
10749 M16_OPC_SW = 0x1b,
10750 M16_OPC_RRR = 0x1c,
10751 M16_OPC_RR = 0x1d,
10752 M16_OPC_EXTEND = 0x1e,
10753 M16_OPC_I64 = 0x1f
10754 };
10755
10756 /* I8 funct field */
10757 enum {
10758 I8_BTEQZ = 0x0,
10759 I8_BTNEZ = 0x1,
10760 I8_SWRASP = 0x2,
10761 I8_ADJSP = 0x3,
10762 I8_SVRS = 0x4,
10763 I8_MOV32R = 0x5,
10764 I8_MOVR32 = 0x7
10765 };
10766
10767 /* RRR f field */
10768 enum {
10769 RRR_DADDU = 0x0,
10770 RRR_ADDU = 0x1,
10771 RRR_DSUBU = 0x2,
10772 RRR_SUBU = 0x3
10773 };
10774
10775 /* RR funct field */
10776 enum {
10777 RR_JR = 0x00,
10778 RR_SDBBP = 0x01,
10779 RR_SLT = 0x02,
10780 RR_SLTU = 0x03,
10781 RR_SLLV = 0x04,
10782 RR_BREAK = 0x05,
10783 RR_SRLV = 0x06,
10784 RR_SRAV = 0x07,
10785 RR_DSRL = 0x08,
10786 RR_CMP = 0x0a,
10787 RR_NEG = 0x0b,
10788 RR_AND = 0x0c,
10789 RR_OR = 0x0d,
10790 RR_XOR = 0x0e,
10791 RR_NOT = 0x0f,
10792 RR_MFHI = 0x10,
10793 RR_CNVT = 0x11,
10794 RR_MFLO = 0x12,
10795 RR_DSRA = 0x13,
10796 RR_DSLLV = 0x14,
10797 RR_DSRLV = 0x16,
10798 RR_DSRAV = 0x17,
10799 RR_MULT = 0x18,
10800 RR_MULTU = 0x19,
10801 RR_DIV = 0x1a,
10802 RR_DIVU = 0x1b,
10803 RR_DMULT = 0x1c,
10804 RR_DMULTU = 0x1d,
10805 RR_DDIV = 0x1e,
10806 RR_DDIVU = 0x1f
10807 };
10808
10809 /* I64 funct field */
10810 enum {
10811 I64_LDSP = 0x0,
10812 I64_SDSP = 0x1,
10813 I64_SDRASP = 0x2,
10814 I64_DADJSP = 0x3,
10815 I64_LDPC = 0x4,
10816 I64_DADDIU5 = 0x5,
10817 I64_DADDIUPC = 0x6,
10818 I64_DADDIUSP = 0x7
10819 };
10820
10821 /* RR ry field for CNVT */
10822 enum {
10823 RR_RY_CNVT_ZEB = 0x0,
10824 RR_RY_CNVT_ZEH = 0x1,
10825 RR_RY_CNVT_ZEW = 0x2,
10826 RR_RY_CNVT_SEB = 0x4,
10827 RR_RY_CNVT_SEH = 0x5,
10828 RR_RY_CNVT_SEW = 0x6,
10829 };
10830
10831 static int xlat (int r)
10832 {
10833 static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
10834
10835 return map[r];
10836 }
10837
10838 static void gen_mips16_save (DisasContext *ctx,
10839 int xsregs, int aregs,
10840 int do_ra, int do_s0, int do_s1,
10841 int framesize)
10842 {
10843 TCGv t0 = tcg_temp_new();
10844 TCGv t1 = tcg_temp_new();
10845 TCGv t2 = tcg_temp_new();
10846 int args, astatic;
10847
10848 switch (aregs) {
10849 case 0:
10850 case 1:
10851 case 2:
10852 case 3:
10853 case 11:
10854 args = 0;
10855 break;
10856 case 4:
10857 case 5:
10858 case 6:
10859 case 7:
10860 args = 1;
10861 break;
10862 case 8:
10863 case 9:
10864 case 10:
10865 args = 2;
10866 break;
10867 case 12:
10868 case 13:
10869 args = 3;
10870 break;
10871 case 14:
10872 args = 4;
10873 break;
10874 default:
10875 generate_exception(ctx, EXCP_RI);
10876 return;
10877 }
10878
10879 switch (args) {
10880 case 4:
10881 gen_base_offset_addr(ctx, t0, 29, 12);
10882 gen_load_gpr(t1, 7);
10883 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
10884 /* Fall through */
10885 case 3:
10886 gen_base_offset_addr(ctx, t0, 29, 8);
10887 gen_load_gpr(t1, 6);
10888 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
10889 /* Fall through */
10890 case 2:
10891 gen_base_offset_addr(ctx, t0, 29, 4);
10892 gen_load_gpr(t1, 5);
10893 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
10894 /* Fall through */
10895 case 1:
10896 gen_base_offset_addr(ctx, t0, 29, 0);
10897 gen_load_gpr(t1, 4);
10898 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
10899 }
10900
10901 gen_load_gpr(t0, 29);
10902
10903 #define DECR_AND_STORE(reg) do { \
10904 tcg_gen_movi_tl(t2, -4); \
10905 gen_op_addr_add(ctx, t0, t0, t2); \
10906 gen_load_gpr(t1, reg); \
10907 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
10908 } while (0)
10909
10910 if (do_ra) {
10911 DECR_AND_STORE(31);
10912 }
10913
10914 switch (xsregs) {
10915 case 7:
10916 DECR_AND_STORE(30);
10917 /* Fall through */
10918 case 6:
10919 DECR_AND_STORE(23);
10920 /* Fall through */
10921 case 5:
10922 DECR_AND_STORE(22);
10923 /* Fall through */
10924 case 4:
10925 DECR_AND_STORE(21);
10926 /* Fall through */
10927 case 3:
10928 DECR_AND_STORE(20);
10929 /* Fall through */
10930 case 2:
10931 DECR_AND_STORE(19);
10932 /* Fall through */
10933 case 1:
10934 DECR_AND_STORE(18);
10935 }
10936
10937 if (do_s1) {
10938 DECR_AND_STORE(17);
10939 }
10940 if (do_s0) {
10941 DECR_AND_STORE(16);
10942 }
10943
10944 switch (aregs) {
10945 case 0:
10946 case 4:
10947 case 8:
10948 case 12:
10949 case 14:
10950 astatic = 0;
10951 break;
10952 case 1:
10953 case 5:
10954 case 9:
10955 case 13:
10956 astatic = 1;
10957 break;
10958 case 2:
10959 case 6:
10960 case 10:
10961 astatic = 2;
10962 break;
10963 case 3:
10964 case 7:
10965 astatic = 3;
10966 break;
10967 case 11:
10968 astatic = 4;
10969 break;
10970 default:
10971 generate_exception(ctx, EXCP_RI);
10972 return;
10973 }
10974
10975 if (astatic > 0) {
10976 DECR_AND_STORE(7);
10977 if (astatic > 1) {
10978 DECR_AND_STORE(6);
10979 if (astatic > 2) {
10980 DECR_AND_STORE(5);
10981 if (astatic > 3) {
10982 DECR_AND_STORE(4);
10983 }
10984 }
10985 }
10986 }
10987 #undef DECR_AND_STORE
10988
10989 tcg_gen_movi_tl(t2, -framesize);
10990 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
10991 tcg_temp_free(t0);
10992 tcg_temp_free(t1);
10993 tcg_temp_free(t2);
10994 }
10995
10996 static void gen_mips16_restore (DisasContext *ctx,
10997 int xsregs, int aregs,
10998 int do_ra, int do_s0, int do_s1,
10999 int framesize)
11000 {
11001 int astatic;
11002 TCGv t0 = tcg_temp_new();
11003 TCGv t1 = tcg_temp_new();
11004 TCGv t2 = tcg_temp_new();
11005
11006 tcg_gen_movi_tl(t2, framesize);
11007 gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
11008
11009 #define DECR_AND_LOAD(reg) do { \
11010 tcg_gen_movi_tl(t2, -4); \
11011 gen_op_addr_add(ctx, t0, t0, t2); \
11012 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
11013 gen_store_gpr(t1, reg); \
11014 } while (0)
11015
11016 if (do_ra) {
11017 DECR_AND_LOAD(31);
11018 }
11019
11020 switch (xsregs) {
11021 case 7:
11022 DECR_AND_LOAD(30);
11023 /* Fall through */
11024 case 6:
11025 DECR_AND_LOAD(23);
11026 /* Fall through */
11027 case 5:
11028 DECR_AND_LOAD(22);
11029 /* Fall through */
11030 case 4:
11031 DECR_AND_LOAD(21);
11032 /* Fall through */
11033 case 3:
11034 DECR_AND_LOAD(20);
11035 /* Fall through */
11036 case 2:
11037 DECR_AND_LOAD(19);
11038 /* Fall through */
11039 case 1:
11040 DECR_AND_LOAD(18);
11041 }
11042
11043 if (do_s1) {
11044 DECR_AND_LOAD(17);
11045 }
11046 if (do_s0) {
11047 DECR_AND_LOAD(16);
11048 }
11049
11050 switch (aregs) {
11051 case 0:
11052 case 4:
11053 case 8:
11054 case 12:
11055 case 14:
11056 astatic = 0;
11057 break;
11058 case 1:
11059 case 5:
11060 case 9:
11061 case 13:
11062 astatic = 1;
11063 break;
11064 case 2:
11065 case 6:
11066 case 10:
11067 astatic = 2;
11068 break;
11069 case 3:
11070 case 7:
11071 astatic = 3;
11072 break;
11073 case 11:
11074 astatic = 4;
11075 break;
11076 default:
11077 generate_exception(ctx, EXCP_RI);
11078 return;
11079 }
11080
11081 if (astatic > 0) {
11082 DECR_AND_LOAD(7);
11083 if (astatic > 1) {
11084 DECR_AND_LOAD(6);
11085 if (astatic > 2) {
11086 DECR_AND_LOAD(5);
11087 if (astatic > 3) {
11088 DECR_AND_LOAD(4);
11089 }
11090 }
11091 }
11092 }
11093 #undef DECR_AND_LOAD
11094
11095 tcg_gen_movi_tl(t2, framesize);
11096 gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
11097 tcg_temp_free(t0);
11098 tcg_temp_free(t1);
11099 tcg_temp_free(t2);
11100 }
11101
11102 static void gen_addiupc (DisasContext *ctx, int rx, int imm,
11103 int is_64_bit, int extended)
11104 {
11105 TCGv t0;
11106
11107 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
11108 generate_exception(ctx, EXCP_RI);
11109 return;
11110 }
11111
11112 t0 = tcg_temp_new();
11113
11114 tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
11115 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
11116 if (!is_64_bit) {
11117 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
11118 }
11119
11120 tcg_temp_free(t0);
11121 }
11122
11123 #if defined(TARGET_MIPS64)
11124 static void decode_i64_mips16 (DisasContext *ctx,
11125 int ry, int funct, int16_t offset,
11126 int extended)
11127 {
11128 switch (funct) {
11129 case I64_LDSP:
11130 check_insn(ctx, ISA_MIPS3);
11131 check_mips_64(ctx);
11132 offset = extended ? offset : offset << 3;
11133 gen_ld(ctx, OPC_LD, ry, 29, offset);
11134 break;
11135 case I64_SDSP:
11136 check_insn(ctx, ISA_MIPS3);
11137 check_mips_64(ctx);
11138 offset = extended ? offset : offset << 3;
11139 gen_st(ctx, OPC_SD, ry, 29, offset);
11140 break;
11141 case I64_SDRASP:
11142 check_insn(ctx, ISA_MIPS3);
11143 check_mips_64(ctx);
11144 offset = extended ? offset : (ctx->opcode & 0xff) << 3;
11145 gen_st(ctx, OPC_SD, 31, 29, offset);
11146 break;
11147 case I64_DADJSP:
11148 check_insn(ctx, ISA_MIPS3);
11149 check_mips_64(ctx);
11150 offset = extended ? offset : ((int8_t)ctx->opcode) << 3;
11151 gen_arith_imm(ctx, OPC_DADDIU, 29, 29, offset);
11152 break;
11153 case I64_LDPC:
11154 check_insn(ctx, ISA_MIPS3);
11155 check_mips_64(ctx);
11156 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
11157 generate_exception(ctx, EXCP_RI);
11158 } else {
11159 offset = extended ? offset : offset << 3;
11160 gen_ld(ctx, OPC_LDPC, ry, 0, offset);
11161 }
11162 break;
11163 case I64_DADDIU5:
11164 check_insn(ctx, ISA_MIPS3);
11165 check_mips_64(ctx);
11166 offset = extended ? offset : ((int8_t)(offset << 3)) >> 3;
11167 gen_arith_imm(ctx, OPC_DADDIU, ry, ry, offset);
11168 break;
11169 case I64_DADDIUPC:
11170 check_insn(ctx, ISA_MIPS3);
11171 check_mips_64(ctx);
11172 offset = extended ? offset : offset << 2;
11173 gen_addiupc(ctx, ry, offset, 1, extended);
11174 break;
11175 case I64_DADDIUSP:
11176 check_insn(ctx, ISA_MIPS3);
11177 check_mips_64(ctx);
11178 offset = extended ? offset : offset << 2;
11179 gen_arith_imm(ctx, OPC_DADDIU, ry, 29, offset);
11180 break;
11181 }
11182 }
11183 #endif
11184
11185 static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
11186 {
11187 int extend = cpu_lduw_code(env, ctx->pc + 2);
11188 int op, rx, ry, funct, sa;
11189 int16_t imm, offset;
11190
11191 ctx->opcode = (ctx->opcode << 16) | extend;
11192 op = (ctx->opcode >> 11) & 0x1f;
11193 sa = (ctx->opcode >> 22) & 0x1f;
11194 funct = (ctx->opcode >> 8) & 0x7;
11195 rx = xlat((ctx->opcode >> 8) & 0x7);
11196 ry = xlat((ctx->opcode >> 5) & 0x7);
11197 offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
11198 | ((ctx->opcode >> 21) & 0x3f) << 5
11199 | (ctx->opcode & 0x1f));
11200
11201 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
11202 counterparts. */
11203 switch (op) {
11204 case M16_OPC_ADDIUSP:
11205 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
11206 break;
11207 case M16_OPC_ADDIUPC:
11208 gen_addiupc(ctx, rx, imm, 0, 1);
11209 break;
11210 case M16_OPC_B:
11211 gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1, 0);
11212 /* No delay slot, so just process as a normal instruction */
11213 break;
11214 case M16_OPC_BEQZ:
11215 gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1, 0);
11216 /* No delay slot, so just process as a normal instruction */
11217 break;
11218 case M16_OPC_BNEQZ:
11219 gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1, 0);
11220 /* No delay slot, so just process as a normal instruction */
11221 break;
11222 case M16_OPC_SHIFT:
11223 switch (ctx->opcode & 0x3) {
11224 case 0x0:
11225 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
11226 break;
11227 case 0x1:
11228 #if defined(TARGET_MIPS64)
11229 check_mips_64(ctx);
11230 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
11231 #else
11232 generate_exception(ctx, EXCP_RI);
11233 #endif
11234 break;
11235 case 0x2:
11236 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
11237 break;
11238 case 0x3:
11239 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
11240 break;
11241 }
11242 break;
11243 #if defined(TARGET_MIPS64)
11244 case M16_OPC_LD:
11245 check_insn(ctx, ISA_MIPS3);
11246 check_mips_64(ctx);
11247 gen_ld(ctx, OPC_LD, ry, rx, offset);
11248 break;
11249 #endif
11250 case M16_OPC_RRIA:
11251 imm = ctx->opcode & 0xf;
11252 imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
11253 imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
11254 imm = (int16_t) (imm << 1) >> 1;
11255 if ((ctx->opcode >> 4) & 0x1) {
11256 #if defined(TARGET_MIPS64)
11257 check_mips_64(ctx);
11258 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
11259 #else
11260 generate_exception(ctx, EXCP_RI);
11261 #endif
11262 } else {
11263 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
11264 }
11265 break;
11266 case M16_OPC_ADDIU8:
11267 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
11268 break;
11269 case M16_OPC_SLTI:
11270 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
11271 break;
11272 case M16_OPC_SLTIU:
11273 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
11274 break;
11275 case M16_OPC_I8:
11276 switch (funct) {
11277 case I8_BTEQZ:
11278 gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1, 0);
11279 break;
11280 case I8_BTNEZ:
11281 gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1, 0);
11282 break;
11283 case I8_SWRASP:
11284 gen_st(ctx, OPC_SW, 31, 29, imm);
11285 break;
11286 case I8_ADJSP:
11287 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
11288 break;
11289 case I8_SVRS:
11290 check_insn(ctx, ISA_MIPS32);
11291 {
11292 int xsregs = (ctx->opcode >> 24) & 0x7;
11293 int aregs = (ctx->opcode >> 16) & 0xf;
11294 int do_ra = (ctx->opcode >> 6) & 0x1;
11295 int do_s0 = (ctx->opcode >> 5) & 0x1;
11296 int do_s1 = (ctx->opcode >> 4) & 0x1;
11297 int framesize = (((ctx->opcode >> 20) & 0xf) << 4
11298 | (ctx->opcode & 0xf)) << 3;
11299
11300 if (ctx->opcode & (1 << 7)) {
11301 gen_mips16_save(ctx, xsregs, aregs,
11302 do_ra, do_s0, do_s1,
11303 framesize);
11304 } else {
11305 gen_mips16_restore(ctx, xsregs, aregs,
11306 do_ra, do_s0, do_s1,
11307 framesize);
11308 }
11309 }
11310 break;
11311 default:
11312 generate_exception(ctx, EXCP_RI);
11313 break;
11314 }
11315 break;
11316 case M16_OPC_LI:
11317 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
11318 break;
11319 case M16_OPC_CMPI:
11320 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
11321 break;
11322 #if defined(TARGET_MIPS64)
11323 case M16_OPC_SD:
11324 check_insn(ctx, ISA_MIPS3);
11325 check_mips_64(ctx);
11326 gen_st(ctx, OPC_SD, ry, rx, offset);
11327 break;
11328 #endif
11329 case M16_OPC_LB:
11330 gen_ld(ctx, OPC_LB, ry, rx, offset);
11331 break;
11332 case M16_OPC_LH:
11333 gen_ld(ctx, OPC_LH, ry, rx, offset);
11334 break;
11335 case M16_OPC_LWSP:
11336 gen_ld(ctx, OPC_LW, rx, 29, offset);
11337 break;
11338 case M16_OPC_LW:
11339 gen_ld(ctx, OPC_LW, ry, rx, offset);
11340 break;
11341 case M16_OPC_LBU:
11342 gen_ld(ctx, OPC_LBU, ry, rx, offset);
11343 break;
11344 case M16_OPC_LHU:
11345 gen_ld(ctx, OPC_LHU, ry, rx, offset);
11346 break;
11347 case M16_OPC_LWPC:
11348 gen_ld(ctx, OPC_LWPC, rx, 0, offset);
11349 break;
11350 #if defined(TARGET_MIPS64)
11351 case M16_OPC_LWU:
11352 check_insn(ctx, ISA_MIPS3);
11353 check_mips_64(ctx);
11354 gen_ld(ctx, OPC_LWU, ry, rx, offset);
11355 break;
11356 #endif
11357 case M16_OPC_SB:
11358 gen_st(ctx, OPC_SB, ry, rx, offset);
11359 break;
11360 case M16_OPC_SH:
11361 gen_st(ctx, OPC_SH, ry, rx, offset);
11362 break;
11363 case M16_OPC_SWSP:
11364 gen_st(ctx, OPC_SW, rx, 29, offset);
11365 break;
11366 case M16_OPC_SW:
11367 gen_st(ctx, OPC_SW, ry, rx, offset);
11368 break;
11369 #if defined(TARGET_MIPS64)
11370 case M16_OPC_I64:
11371 decode_i64_mips16(ctx, ry, funct, offset, 1);
11372 break;
11373 #endif
11374 default:
11375 generate_exception(ctx, EXCP_RI);
11376 break;
11377 }
11378
11379 return 4;
11380 }
11381
11382 static inline bool is_uhi(int sdbbp_code)
11383 {
11384 #ifdef CONFIG_USER_ONLY
11385 return false;
11386 #else
11387 return semihosting_enabled() && sdbbp_code == 1;
11388 #endif
11389 }
11390
11391 static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
11392 {
11393 int rx, ry;
11394 int sa;
11395 int op, cnvt_op, op1, offset;
11396 int funct;
11397 int n_bytes;
11398
11399 op = (ctx->opcode >> 11) & 0x1f;
11400 sa = (ctx->opcode >> 2) & 0x7;
11401 sa = sa == 0 ? 8 : sa;
11402 rx = xlat((ctx->opcode >> 8) & 0x7);
11403 cnvt_op = (ctx->opcode >> 5) & 0x7;
11404 ry = xlat((ctx->opcode >> 5) & 0x7);
11405 op1 = offset = ctx->opcode & 0x1f;
11406
11407 n_bytes = 2;
11408
11409 switch (op) {
11410 case M16_OPC_ADDIUSP:
11411 {
11412 int16_t imm = ((uint8_t) ctx->opcode) << 2;
11413
11414 gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
11415 }
11416 break;
11417 case M16_OPC_ADDIUPC:
11418 gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0);
11419 break;
11420 case M16_OPC_B:
11421 offset = (ctx->opcode & 0x7ff) << 1;
11422 offset = (int16_t)(offset << 4) >> 4;
11423 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset, 0);
11424 /* No delay slot, so just process as a normal instruction */
11425 break;
11426 case M16_OPC_JAL:
11427 offset = cpu_lduw_code(env, ctx->pc + 2);
11428 offset = (((ctx->opcode & 0x1f) << 21)
11429 | ((ctx->opcode >> 5) & 0x1f) << 16
11430 | offset) << 2;
11431 op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALX : OPC_JAL;
11432 gen_compute_branch(ctx, op, 4, rx, ry, offset, 2);
11433 n_bytes = 4;
11434 break;
11435 case M16_OPC_BEQZ:
11436 gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0,
11437 ((int8_t)ctx->opcode) << 1, 0);
11438 /* No delay slot, so just process as a normal instruction */
11439 break;
11440 case M16_OPC_BNEQZ:
11441 gen_compute_branch(ctx, OPC_BNE, 2, rx, 0,
11442 ((int8_t)ctx->opcode) << 1, 0);
11443 /* No delay slot, so just process as a normal instruction */
11444 break;
11445 case M16_OPC_SHIFT:
11446 switch (ctx->opcode & 0x3) {
11447 case 0x0:
11448 gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
11449 break;
11450 case 0x1:
11451 #if defined(TARGET_MIPS64)
11452 check_insn(ctx, ISA_MIPS3);
11453 check_mips_64(ctx);
11454 gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
11455 #else
11456 generate_exception(ctx, EXCP_RI);
11457 #endif
11458 break;
11459 case 0x2:
11460 gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
11461 break;
11462 case 0x3:
11463 gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
11464 break;
11465 }
11466 break;
11467 #if defined(TARGET_MIPS64)
11468 case M16_OPC_LD:
11469 check_insn(ctx, ISA_MIPS3);
11470 check_mips_64(ctx);
11471 gen_ld(ctx, OPC_LD, ry, rx, offset << 3);
11472 break;
11473 #endif
11474 case M16_OPC_RRIA:
11475 {
11476 int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4;
11477
11478 if ((ctx->opcode >> 4) & 1) {
11479 #if defined(TARGET_MIPS64)
11480 check_insn(ctx, ISA_MIPS3);
11481 check_mips_64(ctx);
11482 gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
11483 #else
11484 generate_exception(ctx, EXCP_RI);
11485 #endif
11486 } else {
11487 gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
11488 }
11489 }
11490 break;
11491 case M16_OPC_ADDIU8:
11492 {
11493 int16_t imm = (int8_t) ctx->opcode;
11494
11495 gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
11496 }
11497 break;
11498 case M16_OPC_SLTI:
11499 {
11500 int16_t imm = (uint8_t) ctx->opcode;
11501 gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
11502 }
11503 break;
11504 case M16_OPC_SLTIU:
11505 {
11506 int16_t imm = (uint8_t) ctx->opcode;
11507 gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
11508 }
11509 break;
11510 case M16_OPC_I8:
11511 {
11512 int reg32;
11513
11514 funct = (ctx->opcode >> 8) & 0x7;
11515 switch (funct) {
11516 case I8_BTEQZ:
11517 gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0,
11518 ((int8_t)ctx->opcode) << 1, 0);
11519 break;
11520 case I8_BTNEZ:
11521 gen_compute_branch(ctx, OPC_BNE, 2, 24, 0,
11522 ((int8_t)ctx->opcode) << 1, 0);
11523 break;
11524 case I8_SWRASP:
11525 gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2);
11526 break;
11527 case I8_ADJSP:
11528 gen_arith_imm(ctx, OPC_ADDIU, 29, 29,
11529 ((int8_t)ctx->opcode) << 3);
11530 break;
11531 case I8_SVRS:
11532 check_insn(ctx, ISA_MIPS32);
11533 {
11534 int do_ra = ctx->opcode & (1 << 6);
11535 int do_s0 = ctx->opcode & (1 << 5);
11536 int do_s1 = ctx->opcode & (1 << 4);
11537 int framesize = ctx->opcode & 0xf;
11538
11539 if (framesize == 0) {
11540 framesize = 128;
11541 } else {
11542 framesize = framesize << 3;
11543 }
11544
11545 if (ctx->opcode & (1 << 7)) {
11546 gen_mips16_save(ctx, 0, 0,
11547 do_ra, do_s0, do_s1, framesize);
11548 } else {
11549 gen_mips16_restore(ctx, 0, 0,
11550 do_ra, do_s0, do_s1, framesize);
11551 }
11552 }
11553 break;
11554 case I8_MOV32R:
11555 {
11556 int rz = xlat(ctx->opcode & 0x7);
11557
11558 reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
11559 ((ctx->opcode >> 5) & 0x7);
11560 gen_arith(ctx, OPC_ADDU, reg32, rz, 0);
11561 }
11562 break;
11563 case I8_MOVR32:
11564 reg32 = ctx->opcode & 0x1f;
11565 gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
11566 break;
11567 default:
11568 generate_exception(ctx, EXCP_RI);
11569 break;
11570 }
11571 }
11572 break;
11573 case M16_OPC_LI:
11574 {
11575 int16_t imm = (uint8_t) ctx->opcode;
11576
11577 gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
11578 }
11579 break;
11580 case M16_OPC_CMPI:
11581 {
11582 int16_t imm = (uint8_t) ctx->opcode;
11583 gen_logic_imm(ctx, OPC_XORI, 24, rx, imm);
11584 }
11585 break;
11586 #if defined(TARGET_MIPS64)
11587 case M16_OPC_SD:
11588 check_insn(ctx, ISA_MIPS3);
11589 check_mips_64(ctx);
11590 gen_st(ctx, OPC_SD, ry, rx, offset << 3);
11591 break;
11592 #endif
11593 case M16_OPC_LB:
11594 gen_ld(ctx, OPC_LB, ry, rx, offset);
11595 break;
11596 case M16_OPC_LH:
11597 gen_ld(ctx, OPC_LH, ry, rx, offset << 1);
11598 break;
11599 case M16_OPC_LWSP:
11600 gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
11601 break;
11602 case M16_OPC_LW:
11603 gen_ld(ctx, OPC_LW, ry, rx, offset << 2);
11604 break;
11605 case M16_OPC_LBU:
11606 gen_ld(ctx, OPC_LBU, ry, rx, offset);
11607 break;
11608 case M16_OPC_LHU:
11609 gen_ld(ctx, OPC_LHU, ry, rx, offset << 1);
11610 break;
11611 case M16_OPC_LWPC:
11612 gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
11613 break;
11614 #if defined (TARGET_MIPS64)
11615 case M16_OPC_LWU:
11616 check_insn(ctx, ISA_MIPS3);
11617 check_mips_64(ctx);
11618 gen_ld(ctx, OPC_LWU, ry, rx, offset << 2);
11619 break;
11620 #endif
11621 case M16_OPC_SB:
11622 gen_st(ctx, OPC_SB, ry, rx, offset);
11623 break;
11624 case M16_OPC_SH:
11625 gen_st(ctx, OPC_SH, ry, rx, offset << 1);
11626 break;
11627 case M16_OPC_SWSP:
11628 gen_st(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2);
11629 break;
11630 case M16_OPC_SW:
11631 gen_st(ctx, OPC_SW, ry, rx, offset << 2);
11632 break;
11633 case M16_OPC_RRR:
11634 {
11635 int rz = xlat((ctx->opcode >> 2) & 0x7);
11636 int mips32_op;
11637
11638 switch (ctx->opcode & 0x3) {
11639 case RRR_ADDU:
11640 mips32_op = OPC_ADDU;
11641 break;
11642 case RRR_SUBU:
11643 mips32_op = OPC_SUBU;
11644 break;
11645 #if defined(TARGET_MIPS64)
11646 case RRR_DADDU:
11647 mips32_op = OPC_DADDU;
11648 check_insn(ctx, ISA_MIPS3);
11649 check_mips_64(ctx);
11650 break;
11651 case RRR_DSUBU:
11652 mips32_op = OPC_DSUBU;
11653 check_insn(ctx, ISA_MIPS3);
11654 check_mips_64(ctx);
11655 break;
11656 #endif
11657 default:
11658 generate_exception(ctx, EXCP_RI);
11659 goto done;
11660 }
11661
11662 gen_arith(ctx, mips32_op, rz, rx, ry);
11663 done:
11664 ;
11665 }
11666 break;
11667 case M16_OPC_RR:
11668 switch (op1) {
11669 case RR_JR:
11670 {
11671 int nd = (ctx->opcode >> 7) & 0x1;
11672 int link = (ctx->opcode >> 6) & 0x1;
11673 int ra = (ctx->opcode >> 5) & 0x1;
11674
11675 if (nd) {
11676 check_insn(ctx, ISA_MIPS32);
11677 }
11678
11679 if (link) {
11680 op = OPC_JALR;
11681 } else {
11682 op = OPC_JR;
11683 }
11684
11685 gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0,
11686 (nd ? 0 : 2));
11687 }
11688 break;
11689 case RR_SDBBP:
11690 if (is_uhi(extract32(ctx->opcode, 5, 6))) {
11691 gen_helper_do_semihosting(cpu_env);
11692 } else {
11693 /* XXX: not clear which exception should be raised
11694 * when in debug mode...
11695 */
11696 check_insn(ctx, ISA_MIPS32);
11697 generate_exception(ctx, EXCP_DBp);
11698 }
11699 break;
11700 case RR_SLT:
11701 gen_slt(ctx, OPC_SLT, 24, rx, ry);
11702 break;
11703 case RR_SLTU:
11704 gen_slt(ctx, OPC_SLTU, 24, rx, ry);
11705 break;
11706 case RR_BREAK:
11707 generate_exception(ctx, EXCP_BREAK);
11708 break;
11709 case RR_SLLV:
11710 gen_shift(ctx, OPC_SLLV, ry, rx, ry);
11711 break;
11712 case RR_SRLV:
11713 gen_shift(ctx, OPC_SRLV, ry, rx, ry);
11714 break;
11715 case RR_SRAV:
11716 gen_shift(ctx, OPC_SRAV, ry, rx, ry);
11717 break;
11718 #if defined (TARGET_MIPS64)
11719 case RR_DSRL:
11720 check_insn(ctx, ISA_MIPS3);
11721 check_mips_64(ctx);
11722 gen_shift_imm(ctx, OPC_DSRL, ry, ry, sa);
11723 break;
11724 #endif
11725 case RR_CMP:
11726 gen_logic(ctx, OPC_XOR, 24, rx, ry);
11727 break;
11728 case RR_NEG:
11729 gen_arith(ctx, OPC_SUBU, rx, 0, ry);
11730 break;
11731 case RR_AND:
11732 gen_logic(ctx, OPC_AND, rx, rx, ry);
11733 break;
11734 case RR_OR:
11735 gen_logic(ctx, OPC_OR, rx, rx, ry);
11736 break;
11737 case RR_XOR:
11738 gen_logic(ctx, OPC_XOR, rx, rx, ry);
11739 break;
11740 case RR_NOT:
11741 gen_logic(ctx, OPC_NOR, rx, ry, 0);
11742 break;
11743 case RR_MFHI:
11744 gen_HILO(ctx, OPC_MFHI, 0, rx);
11745 break;
11746 case RR_CNVT:
11747 check_insn(ctx, ISA_MIPS32);
11748 switch (cnvt_op) {
11749 case RR_RY_CNVT_ZEB:
11750 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
11751 break;
11752 case RR_RY_CNVT_ZEH:
11753 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]);
11754 break;
11755 case RR_RY_CNVT_SEB:
11756 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]);
11757 break;
11758 case RR_RY_CNVT_SEH:
11759 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
11760 break;
11761 #if defined (TARGET_MIPS64)
11762 case RR_RY_CNVT_ZEW:
11763 check_insn(ctx, ISA_MIPS64);
11764 check_mips_64(ctx);
11765 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
11766 break;
11767 case RR_RY_CNVT_SEW:
11768 check_insn(ctx, ISA_MIPS64);
11769 check_mips_64(ctx);
11770 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
11771 break;
11772 #endif
11773 default:
11774 generate_exception(ctx, EXCP_RI);
11775 break;
11776 }
11777 break;
11778 case RR_MFLO:
11779 gen_HILO(ctx, OPC_MFLO, 0, rx);
11780 break;
11781 #if defined (TARGET_MIPS64)
11782 case RR_DSRA:
11783 check_insn(ctx, ISA_MIPS3);
11784 check_mips_64(ctx);
11785 gen_shift_imm(ctx, OPC_DSRA, ry, ry, sa);
11786 break;
11787 case RR_DSLLV:
11788 check_insn(ctx, ISA_MIPS3);
11789 check_mips_64(ctx);
11790 gen_shift(ctx, OPC_DSLLV, ry, rx, ry);
11791 break;
11792 case RR_DSRLV:
11793 check_insn(ctx, ISA_MIPS3);
11794 check_mips_64(ctx);
11795 gen_shift(ctx, OPC_DSRLV, ry, rx, ry);
11796 break;
11797 case RR_DSRAV:
11798 check_insn(ctx, ISA_MIPS3);
11799 check_mips_64(ctx);
11800 gen_shift(ctx, OPC_DSRAV, ry, rx, ry);
11801 break;
11802 #endif
11803 case RR_MULT:
11804 gen_muldiv(ctx, OPC_MULT, 0, rx, ry);
11805 break;
11806 case RR_MULTU:
11807 gen_muldiv(ctx, OPC_MULTU, 0, rx, ry);
11808 break;
11809 case RR_DIV:
11810 gen_muldiv(ctx, OPC_DIV, 0, rx, ry);
11811 break;
11812 case RR_DIVU:
11813 gen_muldiv(ctx, OPC_DIVU, 0, rx, ry);
11814 break;
11815 #if defined (TARGET_MIPS64)
11816 case RR_DMULT:
11817 check_insn(ctx, ISA_MIPS3);
11818 check_mips_64(ctx);
11819 gen_muldiv(ctx, OPC_DMULT, 0, rx, ry);
11820 break;
11821 case RR_DMULTU:
11822 check_insn(ctx, ISA_MIPS3);
11823 check_mips_64(ctx);
11824 gen_muldiv(ctx, OPC_DMULTU, 0, rx, ry);
11825 break;
11826 case RR_DDIV:
11827 check_insn(ctx, ISA_MIPS3);
11828 check_mips_64(ctx);
11829 gen_muldiv(ctx, OPC_DDIV, 0, rx, ry);
11830 break;
11831 case RR_DDIVU:
11832 check_insn(ctx, ISA_MIPS3);
11833 check_mips_64(ctx);
11834 gen_muldiv(ctx, OPC_DDIVU, 0, rx, ry);
11835 break;
11836 #endif
11837 default:
11838 generate_exception(ctx, EXCP_RI);
11839 break;
11840 }
11841 break;
11842 case M16_OPC_EXTEND:
11843 decode_extended_mips16_opc(env, ctx);
11844 n_bytes = 4;
11845 break;
11846 #if defined(TARGET_MIPS64)
11847 case M16_OPC_I64:
11848 funct = (ctx->opcode >> 8) & 0x7;
11849 decode_i64_mips16(ctx, ry, funct, offset, 0);
11850 break;
11851 #endif
11852 default:
11853 generate_exception(ctx, EXCP_RI);
11854 break;
11855 }
11856
11857 return n_bytes;
11858 }
11859
11860 /* microMIPS extension to MIPS32/MIPS64 */
11861
11862 /*
11863 * microMIPS32/microMIPS64 major opcodes
11864 *
11865 * 1. MIPS Architecture for Programmers Volume II-B:
11866 * The microMIPS32 Instruction Set (Revision 3.05)
11867 *
11868 * Table 6.2 microMIPS32 Encoding of Major Opcode Field
11869 *
11870 * 2. MIPS Architecture For Programmers Volume II-A:
11871 * The MIPS64 Instruction Set (Revision 3.51)
11872 */
11873
11874 enum {
11875 POOL32A = 0x00,
11876 POOL16A = 0x01,
11877 LBU16 = 0x02,
11878 MOVE16 = 0x03,
11879 ADDI32 = 0x04,
11880 R6_LUI = 0x04,
11881 AUI = 0x04,
11882 LBU32 = 0x05,
11883 SB32 = 0x06,
11884 LB32 = 0x07,
11885
11886 POOL32B = 0x08,
11887 POOL16B = 0x09,
11888 LHU16 = 0x0a,
11889 ANDI16 = 0x0b,
11890 ADDIU32 = 0x0c,
11891 LHU32 = 0x0d,
11892 SH32 = 0x0e,
11893 LH32 = 0x0f,
11894
11895 POOL32I = 0x10,
11896 POOL16C = 0x11,
11897 LWSP16 = 0x12,
11898 POOL16D = 0x13,
11899 ORI32 = 0x14,
11900 POOL32F = 0x15,
11901 POOL32S = 0x16, /* MIPS64 */
11902 DADDIU32 = 0x17, /* MIPS64 */
11903
11904 POOL32C = 0x18,
11905 LWGP16 = 0x19,
11906 LW16 = 0x1a,
11907 POOL16E = 0x1b,
11908 XORI32 = 0x1c,
11909 JALS32 = 0x1d,
11910 BOVC = 0x1d,
11911 BEQC = 0x1d,
11912 BEQZALC = 0x1d,
11913 ADDIUPC = 0x1e,
11914 PCREL = 0x1e,
11915 BNVC = 0x1f,
11916 BNEC = 0x1f,
11917 BNEZALC = 0x1f,
11918
11919 R6_BEQZC = 0x20,
11920 JIC = 0x20,
11921 POOL16F = 0x21,
11922 SB16 = 0x22,
11923 BEQZ16 = 0x23,
11924 BEQZC16 = 0x23,
11925 SLTI32 = 0x24,
11926 BEQ32 = 0x25,
11927 BC = 0x25,
11928 SWC132 = 0x26,
11929 LWC132 = 0x27,
11930
11931 /* 0x29 is reserved */
11932 RES_29 = 0x29,
11933 R6_BNEZC = 0x28,
11934 JIALC = 0x28,
11935 SH16 = 0x2a,
11936 BNEZ16 = 0x2b,
11937 BNEZC16 = 0x2b,
11938 SLTIU32 = 0x2c,
11939 BNE32 = 0x2d,
11940 BALC = 0x2d,
11941 SDC132 = 0x2e,
11942 LDC132 = 0x2f,
11943
11944 /* 0x31 is reserved */
11945 RES_31 = 0x31,
11946 BLEZALC = 0x30,
11947 BGEZALC = 0x30,
11948 BGEUC = 0x30,
11949 SWSP16 = 0x32,
11950 B16 = 0x33,
11951 BC16 = 0x33,
11952 ANDI32 = 0x34,
11953 J32 = 0x35,
11954 BGTZC = 0x35,
11955 BLTZC = 0x35,
11956 BLTC = 0x35,
11957 SD32 = 0x36, /* MIPS64 */
11958 LD32 = 0x37, /* MIPS64 */
11959
11960 /* 0x39 is reserved */
11961 RES_39 = 0x39,
11962 BGTZALC = 0x38,
11963 BLTZALC = 0x38,
11964 BLTUC = 0x38,
11965 SW16 = 0x3a,
11966 LI16 = 0x3b,
11967 JALX32 = 0x3c,
11968 JAL32 = 0x3d,
11969 BLEZC = 0x3d,
11970 BGEZC = 0x3d,
11971 BGEC = 0x3d,
11972 SW32 = 0x3e,
11973 LW32 = 0x3f
11974 };
11975
11976 /* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
11977 enum {
11978 ADDIUPC_00 = 0x00,
11979 ADDIUPC_07 = 0x07,
11980 AUIPC = 0x1e,
11981 ALUIPC = 0x1f,
11982 LWPC_08 = 0x08,
11983 LWPC_0F = 0x0F,
11984 };
11985
11986 /* POOL32A encoding of minor opcode field */
11987
11988 enum {
11989 /* These opcodes are distinguished only by bits 9..6; those bits are
11990 * what are recorded below. */
11991 SLL32 = 0x0,
11992 SRL32 = 0x1,
11993 SRA = 0x2,
11994 ROTR = 0x3,
11995 SELEQZ = 0x5,
11996 SELNEZ = 0x6,
11997
11998 SLLV = 0x0,
11999 SRLV = 0x1,
12000 SRAV = 0x2,
12001 ROTRV = 0x3,
12002 ADD = 0x4,
12003 ADDU32 = 0x5,
12004 SUB = 0x6,
12005 SUBU32 = 0x7,
12006 MUL = 0x8,
12007 AND = 0x9,
12008 OR32 = 0xa,
12009 NOR = 0xb,
12010 XOR32 = 0xc,
12011 SLT = 0xd,
12012 SLTU = 0xe,
12013
12014 MOVN = 0x0,
12015 R6_MUL = 0x0,
12016 MOVZ = 0x1,
12017 MUH = 0x1,
12018 MULU = 0x2,
12019 MUHU = 0x3,
12020 LWXS = 0x4,
12021 R6_DIV = 0x4,
12022 MOD = 0x5,
12023 R6_DIVU = 0x6,
12024 MODU = 0x7,
12025
12026 /* The following can be distinguished by their lower 6 bits. */
12027 INS = 0x0c,
12028 LSA = 0x0f,
12029 ALIGN = 0x1f,
12030 EXT = 0x2c,
12031 POOL32AXF = 0x3c
12032 };
12033
12034 /* POOL32AXF encoding of minor opcode field extension */
12035
12036 /*
12037 * 1. MIPS Architecture for Programmers Volume II-B:
12038 * The microMIPS32 Instruction Set (Revision 3.05)
12039 *
12040 * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
12041 *
12042 * 2. MIPS Architecture for Programmers VolumeIV-e:
12043 * The MIPS DSP Application-Specific Extension
12044 * to the microMIPS32 Architecture (Revision 2.34)
12045 *
12046 * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
12047 */
12048
12049 enum {
12050 /* bits 11..6 */
12051 TEQ = 0x00,
12052 TGE = 0x08,
12053 TGEU = 0x10,
12054 TLT = 0x20,
12055 TLTU = 0x28,
12056 TNE = 0x30,
12057
12058 MFC0 = 0x03,
12059 MTC0 = 0x0b,
12060
12061 /* begin of microMIPS32 DSP */
12062
12063 /* bits 13..12 for 0x01 */
12064 MFHI_ACC = 0x0,
12065 MFLO_ACC = 0x1,
12066 MTHI_ACC = 0x2,
12067 MTLO_ACC = 0x3,
12068
12069 /* bits 13..12 for 0x2a */
12070 MADD_ACC = 0x0,
12071 MADDU_ACC = 0x1,
12072 MSUB_ACC = 0x2,
12073 MSUBU_ACC = 0x3,
12074
12075 /* bits 13..12 for 0x32 */
12076 MULT_ACC = 0x0,
12077 MULTU_ACC = 0x1,
12078
12079 /* end of microMIPS32 DSP */
12080
12081 /* bits 15..12 for 0x2c */
12082 BITSWAP = 0x0,
12083 SEB = 0x2,
12084 SEH = 0x3,
12085 CLO = 0x4,
12086 CLZ = 0x5,
12087 RDHWR = 0x6,
12088 WSBH = 0x7,
12089 MULT = 0x8,
12090 MULTU = 0x9,
12091 DIV = 0xa,
12092 DIVU = 0xb,
12093 MADD = 0xc,
12094 MADDU = 0xd,
12095 MSUB = 0xe,
12096 MSUBU = 0xf,
12097
12098 /* bits 15..12 for 0x34 */
12099 MFC2 = 0x4,
12100 MTC2 = 0x5,
12101 MFHC2 = 0x8,
12102 MTHC2 = 0x9,
12103 CFC2 = 0xc,
12104 CTC2 = 0xd,
12105
12106 /* bits 15..12 for 0x3c */
12107 JALR = 0x0,
12108 JR = 0x0, /* alias */
12109 JALRC = 0x0,
12110 JRC = 0x0,
12111 JALR_HB = 0x1,
12112 JALRC_HB = 0x1,
12113 JALRS = 0x4,
12114 JALRS_HB = 0x5,
12115
12116 /* bits 15..12 for 0x05 */
12117 RDPGPR = 0xe,
12118 WRPGPR = 0xf,
12119
12120 /* bits 15..12 for 0x0d */
12121 TLBP = 0x0,
12122 TLBR = 0x1,
12123 TLBWI = 0x2,
12124 TLBWR = 0x3,
12125 TLBINV = 0x4,
12126 TLBINVF = 0x5,
12127 WAIT = 0x9,
12128 IRET = 0xd,
12129 DERET = 0xe,
12130 ERET = 0xf,
12131
12132 /* bits 15..12 for 0x15 */
12133 DMT = 0x0,
12134 DVPE = 0x1,
12135 EMT = 0x2,
12136 EVPE = 0x3,
12137
12138 /* bits 15..12 for 0x1d */
12139 DI = 0x4,
12140 EI = 0x5,
12141
12142 /* bits 15..12 for 0x2d */
12143 SYNC = 0x6,
12144 SYSCALL = 0x8,
12145 SDBBP = 0xd,
12146
12147 /* bits 15..12 for 0x35 */
12148 MFHI32 = 0x0,
12149 MFLO32 = 0x1,
12150 MTHI32 = 0x2,
12151 MTLO32 = 0x3,
12152 };
12153
12154 /* POOL32B encoding of minor opcode field (bits 15..12) */
12155
12156 enum {
12157 LWC2 = 0x0,
12158 LWP = 0x1,
12159 LDP = 0x4,
12160 LWM32 = 0x5,
12161 CACHE = 0x6,
12162 LDM = 0x7,
12163 SWC2 = 0x8,
12164 SWP = 0x9,
12165 SDP = 0xc,
12166 SWM32 = 0xd,
12167 SDM = 0xf
12168 };
12169
12170 /* POOL32C encoding of minor opcode field (bits 15..12) */
12171
12172 enum {
12173 LWL = 0x0,
12174 SWL = 0x8,
12175 LWR = 0x1,
12176 SWR = 0x9,
12177 PREF = 0x2,
12178 /* 0xa is reserved */
12179 LL = 0x3,
12180 SC = 0xb,
12181 LDL = 0x4,
12182 SDL = 0xc,
12183 LDR = 0x5,
12184 SDR = 0xd,
12185 /* 0x6 is reserved */
12186 LWU = 0xe,
12187 LLD = 0x7,
12188 SCD = 0xf
12189 };
12190
12191 /* POOL32F encoding of minor opcode field (bits 5..0) */
12192
12193 enum {
12194 /* These are the bit 7..6 values */
12195 ADD_FMT = 0x0,
12196
12197 SUB_FMT = 0x1,
12198
12199 MUL_FMT = 0x2,
12200
12201 DIV_FMT = 0x3,
12202
12203 /* These are the bit 8..6 values */
12204 MOVN_FMT = 0x0,
12205 RSQRT2_FMT = 0x0,
12206 MOVF_FMT = 0x0,
12207 RINT_FMT = 0x0,
12208 SELNEZ_FMT = 0x0,
12209
12210 MOVZ_FMT = 0x1,
12211 LWXC1 = 0x1,
12212 MOVT_FMT = 0x1,
12213 CLASS_FMT = 0x1,
12214 SELEQZ_FMT = 0x1,
12215
12216 PLL_PS = 0x2,
12217 SWXC1 = 0x2,
12218 SEL_FMT = 0x2,
12219
12220 PLU_PS = 0x3,
12221 LDXC1 = 0x3,
12222
12223 MOVN_FMT_04 = 0x4,
12224 PUL_PS = 0x4,
12225 SDXC1 = 0x4,
12226 RECIP2_FMT = 0x4,
12227
12228 MOVZ_FMT_05 = 0x05,
12229 PUU_PS = 0x5,
12230 LUXC1 = 0x5,
12231
12232 CVT_PS_S = 0x6,
12233 SUXC1 = 0x6,
12234 ADDR_PS = 0x6,
12235 PREFX = 0x6,
12236 MADDF_FMT = 0x6,
12237
12238 MULR_PS = 0x7,
12239 MSUBF_FMT = 0x7,
12240
12241 MADD_S = 0x01,
12242 MADD_D = 0x09,
12243 MADD_PS = 0x11,
12244 ALNV_PS = 0x19,
12245 MSUB_S = 0x21,
12246 MSUB_D = 0x29,
12247 MSUB_PS = 0x31,
12248
12249 NMADD_S = 0x02,
12250 NMADD_D = 0x0a,
12251 NMADD_PS = 0x12,
12252 NMSUB_S = 0x22,
12253 NMSUB_D = 0x2a,
12254 NMSUB_PS = 0x32,
12255
12256 MIN_FMT = 0x3,
12257 MAX_FMT = 0xb,
12258 MINA_FMT = 0x23,
12259 MAXA_FMT = 0x2b,
12260 POOL32FXF = 0x3b,
12261
12262 CABS_COND_FMT = 0x1c, /* MIPS3D */
12263 C_COND_FMT = 0x3c,
12264
12265 CMP_CONDN_S = 0x5,
12266 CMP_CONDN_D = 0x15
12267 };
12268
12269 /* POOL32Fxf encoding of minor opcode extension field */
12270
12271 enum {
12272 CVT_L = 0x04,
12273 RSQRT_FMT = 0x08,
12274 FLOOR_L = 0x0c,
12275 CVT_PW_PS = 0x1c,
12276 CVT_W = 0x24,
12277 SQRT_FMT = 0x28,
12278 FLOOR_W = 0x2c,
12279 CVT_PS_PW = 0x3c,
12280 CFC1 = 0x40,
12281 RECIP_FMT = 0x48,
12282 CEIL_L = 0x4c,
12283 CTC1 = 0x60,
12284 CEIL_W = 0x6c,
12285 MFC1 = 0x80,
12286 CVT_S_PL = 0x84,
12287 TRUNC_L = 0x8c,
12288 MTC1 = 0xa0,
12289 CVT_S_PU = 0xa4,
12290 TRUNC_W = 0xac,
12291 MFHC1 = 0xc0,
12292 ROUND_L = 0xcc,
12293 MTHC1 = 0xe0,
12294 ROUND_W = 0xec,
12295
12296 MOV_FMT = 0x01,
12297 MOVF = 0x05,
12298 ABS_FMT = 0x0d,
12299 RSQRT1_FMT = 0x1d,
12300 MOVT = 0x25,
12301 NEG_FMT = 0x2d,
12302 CVT_D = 0x4d,
12303 RECIP1_FMT = 0x5d,
12304 CVT_S = 0x6d
12305 };
12306
12307 /* POOL32I encoding of minor opcode field (bits 25..21) */
12308
12309 enum {
12310 BLTZ = 0x00,
12311 BLTZAL = 0x01,
12312 BGEZ = 0x02,
12313 BGEZAL = 0x03,
12314 BLEZ = 0x04,
12315 BNEZC = 0x05,
12316 BGTZ = 0x06,
12317 BEQZC = 0x07,
12318 TLTI = 0x08,
12319 BC1EQZC = 0x08,
12320 TGEI = 0x09,
12321 BC1NEZC = 0x09,
12322 TLTIU = 0x0a,
12323 BC2EQZC = 0x0a,
12324 TGEIU = 0x0b,
12325 BC2NEZC = 0x0a,
12326 TNEI = 0x0c,
12327 R6_SYNCI = 0x0c,
12328 LUI = 0x0d,
12329 TEQI = 0x0e,
12330 SYNCI = 0x10,
12331 BLTZALS = 0x11,
12332 BGEZALS = 0x13,
12333 BC2F = 0x14,
12334 BC2T = 0x15,
12335 BPOSGE64 = 0x1a,
12336 BPOSGE32 = 0x1b,
12337 /* These overlap and are distinguished by bit16 of the instruction */
12338 BC1F = 0x1c,
12339 BC1T = 0x1d,
12340 BC1ANY2F = 0x1c,
12341 BC1ANY2T = 0x1d,
12342 BC1ANY4F = 0x1e,
12343 BC1ANY4T = 0x1f
12344 };
12345
12346 /* POOL16A encoding of minor opcode field */
12347
12348 enum {
12349 ADDU16 = 0x0,
12350 SUBU16 = 0x1
12351 };
12352
12353 /* POOL16B encoding of minor opcode field */
12354
12355 enum {
12356 SLL16 = 0x0,
12357 SRL16 = 0x1
12358 };
12359
12360 /* POOL16C encoding of minor opcode field */
12361
12362 enum {
12363 NOT16 = 0x00,
12364 XOR16 = 0x04,
12365 AND16 = 0x08,
12366 OR16 = 0x0c,
12367 LWM16 = 0x10,
12368 SWM16 = 0x14,
12369 JR16 = 0x18,
12370 JRC16 = 0x1a,
12371 JALR16 = 0x1c,
12372 JALR16S = 0x1e,
12373 MFHI16 = 0x20,
12374 MFLO16 = 0x24,
12375 BREAK16 = 0x28,
12376 SDBBP16 = 0x2c,
12377 JRADDIUSP = 0x30
12378 };
12379
12380 /* R6 POOL16C encoding of minor opcode field (bits 0..5) */
12381
12382 enum {
12383 R6_NOT16 = 0x00,
12384 R6_AND16 = 0x01,
12385 R6_LWM16 = 0x02,
12386 R6_JRC16 = 0x03,
12387 MOVEP = 0x04,
12388 MOVEP_07 = 0x07,
12389 R6_XOR16 = 0x08,
12390 R6_OR16 = 0x09,
12391 R6_SWM16 = 0x0a,
12392 JALRC16 = 0x0b,
12393 MOVEP_0C = 0x0c,
12394 MOVEP_0F = 0x0f,
12395 JRCADDIUSP = 0x13,
12396 R6_BREAK16 = 0x1b,
12397 R6_SDBBP16 = 0x3b
12398 };
12399
12400 /* POOL16D encoding of minor opcode field */
12401
12402 enum {
12403 ADDIUS5 = 0x0,
12404 ADDIUSP = 0x1
12405 };
12406
12407 /* POOL16E encoding of minor opcode field */
12408
12409 enum {
12410 ADDIUR2 = 0x0,
12411 ADDIUR1SP = 0x1
12412 };
12413
12414 static int mmreg (int r)
12415 {
12416 static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
12417
12418 return map[r];
12419 }
12420
12421 /* Used for 16-bit store instructions. */
12422 static int mmreg2 (int r)
12423 {
12424 static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
12425
12426 return map[r];
12427 }
12428
12429 #define uMIPS_RD(op) ((op >> 7) & 0x7)
12430 #define uMIPS_RS(op) ((op >> 4) & 0x7)
12431 #define uMIPS_RS2(op) uMIPS_RS(op)
12432 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
12433 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
12434 #define uMIPS_RS5(op) (op & 0x1f)
12435
12436 /* Signed immediate */
12437 #define SIMM(op, start, width) \
12438 ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
12439 << (32-width)) \
12440 >> (32-width))
12441 /* Zero-extended immediate */
12442 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
12443
12444 static void gen_addiur1sp(DisasContext *ctx)
12445 {
12446 int rd = mmreg(uMIPS_RD(ctx->opcode));
12447
12448 gen_arith_imm(ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2);
12449 }
12450
12451 static void gen_addiur2(DisasContext *ctx)
12452 {
12453 static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
12454 int rd = mmreg(uMIPS_RD(ctx->opcode));
12455 int rs = mmreg(uMIPS_RS(ctx->opcode));
12456
12457 gen_arith_imm(ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]);
12458 }
12459
12460 static void gen_addiusp(DisasContext *ctx)
12461 {
12462 int encoded = ZIMM(ctx->opcode, 1, 9);
12463 int decoded;
12464
12465 if (encoded <= 1) {
12466 decoded = 256 + encoded;
12467 } else if (encoded <= 255) {
12468 decoded = encoded;
12469 } else if (encoded <= 509) {
12470 decoded = encoded - 512;
12471 } else {
12472 decoded = encoded - 768;
12473 }
12474
12475 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, decoded << 2);
12476 }
12477
12478 static void gen_addius5(DisasContext *ctx)
12479 {
12480 int imm = SIMM(ctx->opcode, 1, 4);
12481 int rd = (ctx->opcode >> 5) & 0x1f;
12482
12483 gen_arith_imm(ctx, OPC_ADDIU, rd, rd, imm);
12484 }
12485
12486 static void gen_andi16(DisasContext *ctx)
12487 {
12488 static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
12489 31, 32, 63, 64, 255, 32768, 65535 };
12490 int rd = mmreg(uMIPS_RD(ctx->opcode));
12491 int rs = mmreg(uMIPS_RS(ctx->opcode));
12492 int encoded = ZIMM(ctx->opcode, 0, 4);
12493
12494 gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]);
12495 }
12496
12497 static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
12498 int base, int16_t offset)
12499 {
12500 TCGv t0, t1;
12501 TCGv_i32 t2;
12502
12503 if (ctx->hflags & MIPS_HFLAG_BMASK) {
12504 generate_exception(ctx, EXCP_RI);
12505 return;
12506 }
12507
12508 t0 = tcg_temp_new();
12509
12510 gen_base_offset_addr(ctx, t0, base, offset);
12511
12512 t1 = tcg_const_tl(reglist);
12513 t2 = tcg_const_i32(ctx->mem_idx);
12514
12515 save_cpu_state(ctx, 1);
12516 switch (opc) {
12517 case LWM32:
12518 gen_helper_lwm(cpu_env, t0, t1, t2);
12519 break;
12520 case SWM32:
12521 gen_helper_swm(cpu_env, t0, t1, t2);
12522 break;
12523 #ifdef TARGET_MIPS64
12524 case LDM:
12525 gen_helper_ldm(cpu_env, t0, t1, t2);
12526 break;
12527 case SDM:
12528 gen_helper_sdm(cpu_env, t0, t1, t2);
12529 break;
12530 #endif
12531 }
12532 tcg_temp_free(t0);
12533 tcg_temp_free(t1);
12534 tcg_temp_free_i32(t2);
12535 }
12536
12537
12538 static void gen_pool16c_insn(DisasContext *ctx)
12539 {
12540 int rd = mmreg((ctx->opcode >> 3) & 0x7);
12541 int rs = mmreg(ctx->opcode & 0x7);
12542
12543 switch (((ctx->opcode) >> 4) & 0x3f) {
12544 case NOT16 + 0:
12545 case NOT16 + 1:
12546 case NOT16 + 2:
12547 case NOT16 + 3:
12548 gen_logic(ctx, OPC_NOR, rd, rs, 0);
12549 break;
12550 case XOR16 + 0:
12551 case XOR16 + 1:
12552 case XOR16 + 2:
12553 case XOR16 + 3:
12554 gen_logic(ctx, OPC_XOR, rd, rd, rs);
12555 break;
12556 case AND16 + 0:
12557 case AND16 + 1:
12558 case AND16 + 2:
12559 case AND16 + 3:
12560 gen_logic(ctx, OPC_AND, rd, rd, rs);
12561 break;
12562 case OR16 + 0:
12563 case OR16 + 1:
12564 case OR16 + 2:
12565 case OR16 + 3:
12566 gen_logic(ctx, OPC_OR, rd, rd, rs);
12567 break;
12568 case LWM16 + 0:
12569 case LWM16 + 1:
12570 case LWM16 + 2:
12571 case LWM16 + 3:
12572 {
12573 static const int lwm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
12574 int offset = ZIMM(ctx->opcode, 0, 4);
12575
12576 gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3],
12577 29, offset << 2);
12578 }
12579 break;
12580 case SWM16 + 0:
12581 case SWM16 + 1:
12582 case SWM16 + 2:
12583 case SWM16 + 3:
12584 {
12585 static const int swm_convert[] = { 0x11, 0x12, 0x13, 0x14 };
12586 int offset = ZIMM(ctx->opcode, 0, 4);
12587
12588 gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3],
12589 29, offset << 2);
12590 }
12591 break;
12592 case JR16 + 0:
12593 case JR16 + 1:
12594 {
12595 int reg = ctx->opcode & 0x1f;
12596
12597 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 4);
12598 }
12599 break;
12600 case JRC16 + 0:
12601 case JRC16 + 1:
12602 {
12603 int reg = ctx->opcode & 0x1f;
12604 gen_compute_branch(ctx, OPC_JR, 2, reg, 0, 0, 0);
12605 /* Let normal delay slot handling in our caller take us
12606 to the branch target. */
12607 }
12608 break;
12609 case JALR16 + 0:
12610 case JALR16 + 1:
12611 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4);
12612 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
12613 break;
12614 case JALR16S + 0:
12615 case JALR16S + 1:
12616 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2);
12617 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
12618 break;
12619 case MFHI16 + 0:
12620 case MFHI16 + 1:
12621 gen_HILO(ctx, OPC_MFHI, 0, uMIPS_RS5(ctx->opcode));
12622 break;
12623 case MFLO16 + 0:
12624 case MFLO16 + 1:
12625 gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode));
12626 break;
12627 case BREAK16:
12628 generate_exception(ctx, EXCP_BREAK);
12629 break;
12630 case SDBBP16:
12631 if (is_uhi(extract32(ctx->opcode, 0, 4))) {
12632 gen_helper_do_semihosting(cpu_env);
12633 } else {
12634 /* XXX: not clear which exception should be raised
12635 * when in debug mode...
12636 */
12637 check_insn(ctx, ISA_MIPS32);
12638 generate_exception(ctx, EXCP_DBp);
12639 }
12640 break;
12641 case JRADDIUSP + 0:
12642 case JRADDIUSP + 1:
12643 {
12644 int imm = ZIMM(ctx->opcode, 0, 5);
12645 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
12646 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
12647 /* Let normal delay slot handling in our caller take us
12648 to the branch target. */
12649 }
12650 break;
12651 default:
12652 generate_exception(ctx, EXCP_RI);
12653 break;
12654 }
12655 }
12656
12657 static inline void gen_movep(DisasContext *ctx, int enc_dest, int enc_rt,
12658 int enc_rs)
12659 {
12660 int rd, rs, re, rt;
12661 static const int rd_enc[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
12662 static const int re_enc[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
12663 static const int rs_rt_enc[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
12664 rd = rd_enc[enc_dest];
12665 re = re_enc[enc_dest];
12666 rs = rs_rt_enc[enc_rs];
12667 rt = rs_rt_enc[enc_rt];
12668 if (rs) {
12669 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
12670 } else {
12671 tcg_gen_movi_tl(cpu_gpr[rd], 0);
12672 }
12673 if (rt) {
12674 tcg_gen_mov_tl(cpu_gpr[re], cpu_gpr[rt]);
12675 } else {
12676 tcg_gen_movi_tl(cpu_gpr[re], 0);
12677 }
12678 }
12679
12680 static void gen_pool16c_r6_insn(DisasContext *ctx)
12681 {
12682 int rt = mmreg((ctx->opcode >> 7) & 0x7);
12683 int rs = mmreg((ctx->opcode >> 4) & 0x7);
12684
12685 switch (ctx->opcode & 0xf) {
12686 case R6_NOT16:
12687 gen_logic(ctx, OPC_NOR, rt, rs, 0);
12688 break;
12689 case R6_AND16:
12690 gen_logic(ctx, OPC_AND, rt, rt, rs);
12691 break;
12692 case R6_LWM16:
12693 {
12694 int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
12695 int offset = extract32(ctx->opcode, 4, 4);
12696 gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2);
12697 }
12698 break;
12699 case R6_JRC16: /* JRCADDIUSP */
12700 if ((ctx->opcode >> 4) & 1) {
12701 /* JRCADDIUSP */
12702 int imm = extract32(ctx->opcode, 5, 5);
12703 gen_compute_branch(ctx, OPC_JR, 2, 31, 0, 0, 0);
12704 gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
12705 } else {
12706 /* JRC16 */
12707 int rs = extract32(ctx->opcode, 5, 5);
12708 gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
12709 }
12710 break;
12711 case MOVEP ... MOVEP_07:
12712 case MOVEP_0C ... MOVEP_0F:
12713 {
12714 int enc_dest = uMIPS_RD(ctx->opcode);
12715 int enc_rt = uMIPS_RS2(ctx->opcode);
12716 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4);
12717 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
12718 }
12719 break;
12720 case R6_XOR16:
12721 gen_logic(ctx, OPC_XOR, rt, rt, rs);
12722 break;
12723 case R6_OR16:
12724 gen_logic(ctx, OPC_OR, rt, rt, rs);
12725 break;
12726 case R6_SWM16:
12727 {
12728 int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2);
12729 int offset = extract32(ctx->opcode, 4, 4);
12730 gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2);
12731 }
12732 break;
12733 case JALRC16: /* BREAK16, SDBBP16 */
12734 switch (ctx->opcode & 0x3f) {
12735 case JALRC16:
12736 case JALRC16 + 0x20:
12737 /* JALRC16 */
12738 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
12739 31, 0, 0);
12740 break;
12741 case R6_BREAK16:
12742 /* BREAK16 */
12743 generate_exception(ctx, EXCP_BREAK);
12744 break;
12745 case R6_SDBBP16:
12746 /* SDBBP16 */
12747 if (is_uhi(extract32(ctx->opcode, 6, 4))) {
12748 gen_helper_do_semihosting(cpu_env);
12749 } else {
12750 if (ctx->hflags & MIPS_HFLAG_SBRI) {
12751 generate_exception(ctx, EXCP_RI);
12752 } else {
12753 generate_exception(ctx, EXCP_DBp);
12754 }
12755 }
12756 break;
12757 }
12758 break;
12759 default:
12760 generate_exception(ctx, EXCP_RI);
12761 break;
12762 }
12763 }
12764
12765 static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
12766 {
12767 TCGv t0 = tcg_temp_new();
12768 TCGv t1 = tcg_temp_new();
12769
12770 gen_load_gpr(t0, base);
12771
12772 if (index != 0) {
12773 gen_load_gpr(t1, index);
12774 tcg_gen_shli_tl(t1, t1, 2);
12775 gen_op_addr_add(ctx, t0, t1, t0);
12776 }
12777
12778 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
12779 gen_store_gpr(t1, rd);
12780
12781 tcg_temp_free(t0);
12782 tcg_temp_free(t1);
12783 }
12784
12785 static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
12786 int base, int16_t offset)
12787 {
12788 TCGv t0, t1;
12789
12790 if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
12791 generate_exception(ctx, EXCP_RI);
12792 return;
12793 }
12794
12795 t0 = tcg_temp_new();
12796 t1 = tcg_temp_new();
12797
12798 gen_base_offset_addr(ctx, t0, base, offset);
12799
12800 switch (opc) {
12801 case LWP:
12802 if (rd == base) {
12803 generate_exception(ctx, EXCP_RI);
12804 return;
12805 }
12806 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
12807 gen_store_gpr(t1, rd);
12808 tcg_gen_movi_tl(t1, 4);
12809 gen_op_addr_add(ctx, t0, t0, t1);
12810 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
12811 gen_store_gpr(t1, rd+1);
12812 break;
12813 case SWP:
12814 gen_load_gpr(t1, rd);
12815 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12816 tcg_gen_movi_tl(t1, 4);
12817 gen_op_addr_add(ctx, t0, t0, t1);
12818 gen_load_gpr(t1, rd+1);
12819 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
12820 break;
12821 #ifdef TARGET_MIPS64
12822 case LDP:
12823 if (rd == base) {
12824 generate_exception(ctx, EXCP_RI);
12825 return;
12826 }
12827 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
12828 gen_store_gpr(t1, rd);
12829 tcg_gen_movi_tl(t1, 8);
12830 gen_op_addr_add(ctx, t0, t0, t1);
12831 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
12832 gen_store_gpr(t1, rd+1);
12833 break;
12834 case SDP:
12835 gen_load_gpr(t1, rd);
12836 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
12837 tcg_gen_movi_tl(t1, 8);
12838 gen_op_addr_add(ctx, t0, t0, t1);
12839 gen_load_gpr(t1, rd+1);
12840 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
12841 break;
12842 #endif
12843 }
12844 tcg_temp_free(t0);
12845 tcg_temp_free(t1);
12846 }
12847
12848 static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
12849 {
12850 int extension = (ctx->opcode >> 6) & 0x3f;
12851 int minor = (ctx->opcode >> 12) & 0xf;
12852 uint32_t mips32_op;
12853
12854 switch (extension) {
12855 case TEQ:
12856 mips32_op = OPC_TEQ;
12857 goto do_trap;
12858 case TGE:
12859 mips32_op = OPC_TGE;
12860 goto do_trap;
12861 case TGEU:
12862 mips32_op = OPC_TGEU;
12863 goto do_trap;
12864 case TLT:
12865 mips32_op = OPC_TLT;
12866 goto do_trap;
12867 case TLTU:
12868 mips32_op = OPC_TLTU;
12869 goto do_trap;
12870 case TNE:
12871 mips32_op = OPC_TNE;
12872 do_trap:
12873 gen_trap(ctx, mips32_op, rs, rt, -1);
12874 break;
12875 #ifndef CONFIG_USER_ONLY
12876 case MFC0:
12877 case MFC0 + 32:
12878 check_cp0_enabled(ctx);
12879 if (rt == 0) {
12880 /* Treat as NOP. */
12881 break;
12882 }
12883 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7);
12884 break;
12885 case MTC0:
12886 case MTC0 + 32:
12887 check_cp0_enabled(ctx);
12888 {
12889 TCGv t0 = tcg_temp_new();
12890
12891 gen_load_gpr(t0, rt);
12892 gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
12893 tcg_temp_free(t0);
12894 }
12895 break;
12896 #endif
12897 case 0x2a:
12898 switch (minor & 3) {
12899 case MADD_ACC:
12900 gen_muldiv(ctx, OPC_MADD, (ctx->opcode >> 14) & 3, rs, rt);
12901 break;
12902 case MADDU_ACC:
12903 gen_muldiv(ctx, OPC_MADDU, (ctx->opcode >> 14) & 3, rs, rt);
12904 break;
12905 case MSUB_ACC:
12906 gen_muldiv(ctx, OPC_MSUB, (ctx->opcode >> 14) & 3, rs, rt);
12907 break;
12908 case MSUBU_ACC:
12909 gen_muldiv(ctx, OPC_MSUBU, (ctx->opcode >> 14) & 3, rs, rt);
12910 break;
12911 default:
12912 goto pool32axf_invalid;
12913 }
12914 break;
12915 case 0x32:
12916 switch (minor & 3) {
12917 case MULT_ACC:
12918 gen_muldiv(ctx, OPC_MULT, (ctx->opcode >> 14) & 3, rs, rt);
12919 break;
12920 case MULTU_ACC:
12921 gen_muldiv(ctx, OPC_MULTU, (ctx->opcode >> 14) & 3, rs, rt);
12922 break;
12923 default:
12924 goto pool32axf_invalid;
12925 }
12926 break;
12927 case 0x2c:
12928 switch (minor) {
12929 case BITSWAP:
12930 check_insn(ctx, ISA_MIPS32R6);
12931 gen_bitswap(ctx, OPC_BITSWAP, rs, rt);
12932 break;
12933 case SEB:
12934 gen_bshfl(ctx, OPC_SEB, rs, rt);
12935 break;
12936 case SEH:
12937 gen_bshfl(ctx, OPC_SEH, rs, rt);
12938 break;
12939 case CLO:
12940 mips32_op = OPC_CLO;
12941 goto do_cl;
12942 case CLZ:
12943 mips32_op = OPC_CLZ;
12944 do_cl:
12945 check_insn(ctx, ISA_MIPS32);
12946 gen_cl(ctx, mips32_op, rt, rs);
12947 break;
12948 case RDHWR:
12949 gen_rdhwr(ctx, rt, rs);
12950 break;
12951 case WSBH:
12952 gen_bshfl(ctx, OPC_WSBH, rs, rt);
12953 break;
12954 case MULT:
12955 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12956 mips32_op = OPC_MULT;
12957 goto do_mul;
12958 case MULTU:
12959 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12960 mips32_op = OPC_MULTU;
12961 goto do_mul;
12962 case DIV:
12963 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12964 mips32_op = OPC_DIV;
12965 goto do_div;
12966 case DIVU:
12967 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12968 mips32_op = OPC_DIVU;
12969 goto do_div;
12970 do_div:
12971 check_insn(ctx, ISA_MIPS32);
12972 gen_muldiv(ctx, mips32_op, 0, rs, rt);
12973 break;
12974 case MADD:
12975 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12976 mips32_op = OPC_MADD;
12977 goto do_mul;
12978 case MADDU:
12979 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12980 mips32_op = OPC_MADDU;
12981 goto do_mul;
12982 case MSUB:
12983 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12984 mips32_op = OPC_MSUB;
12985 goto do_mul;
12986 case MSUBU:
12987 check_insn_opc_removed(ctx, ISA_MIPS32R6);
12988 mips32_op = OPC_MSUBU;
12989 do_mul:
12990 check_insn(ctx, ISA_MIPS32);
12991 gen_muldiv(ctx, mips32_op, 0, rs, rt);
12992 break;
12993 default:
12994 goto pool32axf_invalid;
12995 }
12996 break;
12997 case 0x34:
12998 switch (minor) {
12999 case MFC2:
13000 case MTC2:
13001 case MFHC2:
13002 case MTHC2:
13003 case CFC2:
13004 case CTC2:
13005 generate_exception_err(ctx, EXCP_CpU, 2);
13006 break;
13007 default:
13008 goto pool32axf_invalid;
13009 }
13010 break;
13011 case 0x3c:
13012 switch (minor) {
13013 case JALR: /* JALRC */
13014 case JALR_HB: /* JALRC_HB */
13015 if (ctx->insn_flags & ISA_MIPS32R6) {
13016 /* JALRC, JALRC_HB */
13017 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
13018 } else {
13019 /* JALR, JALR_HB */
13020 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4);
13021 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
13022 }
13023 break;
13024 case JALRS:
13025 case JALRS_HB:
13026 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13027 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
13028 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
13029 break;
13030 default:
13031 goto pool32axf_invalid;
13032 }
13033 break;
13034 case 0x05:
13035 switch (minor) {
13036 case RDPGPR:
13037 check_cp0_enabled(ctx);
13038 check_insn(ctx, ISA_MIPS32R2);
13039 gen_load_srsgpr(rs, rt);
13040 break;
13041 case WRPGPR:
13042 check_cp0_enabled(ctx);
13043 check_insn(ctx, ISA_MIPS32R2);
13044 gen_store_srsgpr(rs, rt);
13045 break;
13046 default:
13047 goto pool32axf_invalid;
13048 }
13049 break;
13050 #ifndef CONFIG_USER_ONLY
13051 case 0x0d:
13052 switch (minor) {
13053 case TLBP:
13054 mips32_op = OPC_TLBP;
13055 goto do_cp0;
13056 case TLBR:
13057 mips32_op = OPC_TLBR;
13058 goto do_cp0;
13059 case TLBWI:
13060 mips32_op = OPC_TLBWI;
13061 goto do_cp0;
13062 case TLBWR:
13063 mips32_op = OPC_TLBWR;
13064 goto do_cp0;
13065 case TLBINV:
13066 mips32_op = OPC_TLBINV;
13067 goto do_cp0;
13068 case TLBINVF:
13069 mips32_op = OPC_TLBINVF;
13070 goto do_cp0;
13071 case WAIT:
13072 mips32_op = OPC_WAIT;
13073 goto do_cp0;
13074 case DERET:
13075 mips32_op = OPC_DERET;
13076 goto do_cp0;
13077 case ERET:
13078 mips32_op = OPC_ERET;
13079 do_cp0:
13080 gen_cp0(env, ctx, mips32_op, rt, rs);
13081 break;
13082 default:
13083 goto pool32axf_invalid;
13084 }
13085 break;
13086 case 0x1d:
13087 switch (minor) {
13088 case DI:
13089 check_cp0_enabled(ctx);
13090 {
13091 TCGv t0 = tcg_temp_new();
13092
13093 save_cpu_state(ctx, 1);
13094 gen_helper_di(t0, cpu_env);
13095 gen_store_gpr(t0, rs);
13096 /* Stop translation as we may have switched the execution mode */
13097 ctx->bstate = BS_STOP;
13098 tcg_temp_free(t0);
13099 }
13100 break;
13101 case EI:
13102 check_cp0_enabled(ctx);
13103 {
13104 TCGv t0 = tcg_temp_new();
13105
13106 save_cpu_state(ctx, 1);
13107 gen_helper_ei(t0, cpu_env);
13108 gen_store_gpr(t0, rs);
13109 /* Stop translation as we may have switched the execution mode */
13110 ctx->bstate = BS_STOP;
13111 tcg_temp_free(t0);
13112 }
13113 break;
13114 default:
13115 goto pool32axf_invalid;
13116 }
13117 break;
13118 #endif
13119 case 0x2d:
13120 switch (minor) {
13121 case SYNC:
13122 /* NOP */
13123 break;
13124 case SYSCALL:
13125 generate_exception(ctx, EXCP_SYSCALL);
13126 ctx->bstate = BS_STOP;
13127 break;
13128 case SDBBP:
13129 if (is_uhi(extract32(ctx->opcode, 16, 10))) {
13130 gen_helper_do_semihosting(cpu_env);
13131 } else {
13132 check_insn(ctx, ISA_MIPS32);
13133 if (ctx->hflags & MIPS_HFLAG_SBRI) {
13134 generate_exception(ctx, EXCP_RI);
13135 } else {
13136 generate_exception(ctx, EXCP_DBp);
13137 }
13138 }
13139 break;
13140 default:
13141 goto pool32axf_invalid;
13142 }
13143 break;
13144 case 0x01:
13145 switch (minor & 3) {
13146 case MFHI_ACC:
13147 gen_HILO(ctx, OPC_MFHI, minor >> 2, rs);
13148 break;
13149 case MFLO_ACC:
13150 gen_HILO(ctx, OPC_MFLO, minor >> 2, rs);
13151 break;
13152 case MTHI_ACC:
13153 gen_HILO(ctx, OPC_MTHI, minor >> 2, rs);
13154 break;
13155 case MTLO_ACC:
13156 gen_HILO(ctx, OPC_MTLO, minor >> 2, rs);
13157 break;
13158 default:
13159 goto pool32axf_invalid;
13160 }
13161 break;
13162 case 0x35:
13163 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13164 switch (minor) {
13165 case MFHI32:
13166 gen_HILO(ctx, OPC_MFHI, 0, rs);
13167 break;
13168 case MFLO32:
13169 gen_HILO(ctx, OPC_MFLO, 0, rs);
13170 break;
13171 case MTHI32:
13172 gen_HILO(ctx, OPC_MTHI, 0, rs);
13173 break;
13174 case MTLO32:
13175 gen_HILO(ctx, OPC_MTLO, 0, rs);
13176 break;
13177 default:
13178 goto pool32axf_invalid;
13179 }
13180 break;
13181 default:
13182 pool32axf_invalid:
13183 MIPS_INVAL("pool32axf");
13184 generate_exception(ctx, EXCP_RI);
13185 break;
13186 }
13187 }
13188
13189 /* Values for microMIPS fmt field. Variable-width, depending on which
13190 formats the instruction supports. */
13191
13192 enum {
13193 FMT_SD_S = 0,
13194 FMT_SD_D = 1,
13195
13196 FMT_SDPS_S = 0,
13197 FMT_SDPS_D = 1,
13198 FMT_SDPS_PS = 2,
13199
13200 FMT_SWL_S = 0,
13201 FMT_SWL_W = 1,
13202 FMT_SWL_L = 2,
13203
13204 FMT_DWL_D = 0,
13205 FMT_DWL_W = 1,
13206 FMT_DWL_L = 2
13207 };
13208
13209 static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
13210 {
13211 int extension = (ctx->opcode >> 6) & 0x3ff;
13212 uint32_t mips32_op;
13213
13214 #define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
13215 #define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
13216 #define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
13217
13218 switch (extension) {
13219 case FLOAT_1BIT_FMT(CFC1, 0):
13220 mips32_op = OPC_CFC1;
13221 goto do_cp1;
13222 case FLOAT_1BIT_FMT(CTC1, 0):
13223 mips32_op = OPC_CTC1;
13224 goto do_cp1;
13225 case FLOAT_1BIT_FMT(MFC1, 0):
13226 mips32_op = OPC_MFC1;
13227 goto do_cp1;
13228 case FLOAT_1BIT_FMT(MTC1, 0):
13229 mips32_op = OPC_MTC1;
13230 goto do_cp1;
13231 case FLOAT_1BIT_FMT(MFHC1, 0):
13232 mips32_op = OPC_MFHC1;
13233 goto do_cp1;
13234 case FLOAT_1BIT_FMT(MTHC1, 0):
13235 mips32_op = OPC_MTHC1;
13236 do_cp1:
13237 gen_cp1(ctx, mips32_op, rt, rs);
13238 break;
13239
13240 /* Reciprocal square root */
13241 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_S):
13242 mips32_op = OPC_RSQRT_S;
13243 goto do_unaryfp;
13244 case FLOAT_1BIT_FMT(RSQRT_FMT, FMT_SD_D):
13245 mips32_op = OPC_RSQRT_D;
13246 goto do_unaryfp;
13247
13248 /* Square root */
13249 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_S):
13250 mips32_op = OPC_SQRT_S;
13251 goto do_unaryfp;
13252 case FLOAT_1BIT_FMT(SQRT_FMT, FMT_SD_D):
13253 mips32_op = OPC_SQRT_D;
13254 goto do_unaryfp;
13255
13256 /* Reciprocal */
13257 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_S):
13258 mips32_op = OPC_RECIP_S;
13259 goto do_unaryfp;
13260 case FLOAT_1BIT_FMT(RECIP_FMT, FMT_SD_D):
13261 mips32_op = OPC_RECIP_D;
13262 goto do_unaryfp;
13263
13264 /* Floor */
13265 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_S):
13266 mips32_op = OPC_FLOOR_L_S;
13267 goto do_unaryfp;
13268 case FLOAT_1BIT_FMT(FLOOR_L, FMT_SD_D):
13269 mips32_op = OPC_FLOOR_L_D;
13270 goto do_unaryfp;
13271 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_S):
13272 mips32_op = OPC_FLOOR_W_S;
13273 goto do_unaryfp;
13274 case FLOAT_1BIT_FMT(FLOOR_W, FMT_SD_D):
13275 mips32_op = OPC_FLOOR_W_D;
13276 goto do_unaryfp;
13277
13278 /* Ceiling */
13279 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_S):
13280 mips32_op = OPC_CEIL_L_S;
13281 goto do_unaryfp;
13282 case FLOAT_1BIT_FMT(CEIL_L, FMT_SD_D):
13283 mips32_op = OPC_CEIL_L_D;
13284 goto do_unaryfp;
13285 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_S):
13286 mips32_op = OPC_CEIL_W_S;
13287 goto do_unaryfp;
13288 case FLOAT_1BIT_FMT(CEIL_W, FMT_SD_D):
13289 mips32_op = OPC_CEIL_W_D;
13290 goto do_unaryfp;
13291
13292 /* Truncation */
13293 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_S):
13294 mips32_op = OPC_TRUNC_L_S;
13295 goto do_unaryfp;
13296 case FLOAT_1BIT_FMT(TRUNC_L, FMT_SD_D):
13297 mips32_op = OPC_TRUNC_L_D;
13298 goto do_unaryfp;
13299 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_S):
13300 mips32_op = OPC_TRUNC_W_S;
13301 goto do_unaryfp;
13302 case FLOAT_1BIT_FMT(TRUNC_W, FMT_SD_D):
13303 mips32_op = OPC_TRUNC_W_D;
13304 goto do_unaryfp;
13305
13306 /* Round */
13307 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_S):
13308 mips32_op = OPC_ROUND_L_S;
13309 goto do_unaryfp;
13310 case FLOAT_1BIT_FMT(ROUND_L, FMT_SD_D):
13311 mips32_op = OPC_ROUND_L_D;
13312 goto do_unaryfp;
13313 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_S):
13314 mips32_op = OPC_ROUND_W_S;
13315 goto do_unaryfp;
13316 case FLOAT_1BIT_FMT(ROUND_W, FMT_SD_D):
13317 mips32_op = OPC_ROUND_W_D;
13318 goto do_unaryfp;
13319
13320 /* Integer to floating-point conversion */
13321 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_S):
13322 mips32_op = OPC_CVT_L_S;
13323 goto do_unaryfp;
13324 case FLOAT_1BIT_FMT(CVT_L, FMT_SD_D):
13325 mips32_op = OPC_CVT_L_D;
13326 goto do_unaryfp;
13327 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_S):
13328 mips32_op = OPC_CVT_W_S;
13329 goto do_unaryfp;
13330 case FLOAT_1BIT_FMT(CVT_W, FMT_SD_D):
13331 mips32_op = OPC_CVT_W_D;
13332 goto do_unaryfp;
13333
13334 /* Paired-foo conversions */
13335 case FLOAT_1BIT_FMT(CVT_S_PL, 0):
13336 mips32_op = OPC_CVT_S_PL;
13337 goto do_unaryfp;
13338 case FLOAT_1BIT_FMT(CVT_S_PU, 0):
13339 mips32_op = OPC_CVT_S_PU;
13340 goto do_unaryfp;
13341 case FLOAT_1BIT_FMT(CVT_PW_PS, 0):
13342 mips32_op = OPC_CVT_PW_PS;
13343 goto do_unaryfp;
13344 case FLOAT_1BIT_FMT(CVT_PS_PW, 0):
13345 mips32_op = OPC_CVT_PS_PW;
13346 goto do_unaryfp;
13347
13348 /* Floating-point moves */
13349 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_S):
13350 mips32_op = OPC_MOV_S;
13351 goto do_unaryfp;
13352 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_D):
13353 mips32_op = OPC_MOV_D;
13354 goto do_unaryfp;
13355 case FLOAT_2BIT_FMT(MOV_FMT, FMT_SDPS_PS):
13356 mips32_op = OPC_MOV_PS;
13357 goto do_unaryfp;
13358
13359 /* Absolute value */
13360 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_S):
13361 mips32_op = OPC_ABS_S;
13362 goto do_unaryfp;
13363 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_D):
13364 mips32_op = OPC_ABS_D;
13365 goto do_unaryfp;
13366 case FLOAT_2BIT_FMT(ABS_FMT, FMT_SDPS_PS):
13367 mips32_op = OPC_ABS_PS;
13368 goto do_unaryfp;
13369
13370 /* Negation */
13371 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_S):
13372 mips32_op = OPC_NEG_S;
13373 goto do_unaryfp;
13374 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_D):
13375 mips32_op = OPC_NEG_D;
13376 goto do_unaryfp;
13377 case FLOAT_2BIT_FMT(NEG_FMT, FMT_SDPS_PS):
13378 mips32_op = OPC_NEG_PS;
13379 goto do_unaryfp;
13380
13381 /* Reciprocal square root step */
13382 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_S):
13383 mips32_op = OPC_RSQRT1_S;
13384 goto do_unaryfp;
13385 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_D):
13386 mips32_op = OPC_RSQRT1_D;
13387 goto do_unaryfp;
13388 case FLOAT_2BIT_FMT(RSQRT1_FMT, FMT_SDPS_PS):
13389 mips32_op = OPC_RSQRT1_PS;
13390 goto do_unaryfp;
13391
13392 /* Reciprocal step */
13393 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_S):
13394 mips32_op = OPC_RECIP1_S;
13395 goto do_unaryfp;
13396 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_D):
13397 mips32_op = OPC_RECIP1_S;
13398 goto do_unaryfp;
13399 case FLOAT_2BIT_FMT(RECIP1_FMT, FMT_SDPS_PS):
13400 mips32_op = OPC_RECIP1_PS;
13401 goto do_unaryfp;
13402
13403 /* Conversions from double */
13404 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_S):
13405 mips32_op = OPC_CVT_D_S;
13406 goto do_unaryfp;
13407 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_W):
13408 mips32_op = OPC_CVT_D_W;
13409 goto do_unaryfp;
13410 case FLOAT_2BIT_FMT(CVT_D, FMT_SWL_L):
13411 mips32_op = OPC_CVT_D_L;
13412 goto do_unaryfp;
13413
13414 /* Conversions from single */
13415 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_D):
13416 mips32_op = OPC_CVT_S_D;
13417 goto do_unaryfp;
13418 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_W):
13419 mips32_op = OPC_CVT_S_W;
13420 goto do_unaryfp;
13421 case FLOAT_2BIT_FMT(CVT_S, FMT_DWL_L):
13422 mips32_op = OPC_CVT_S_L;
13423 do_unaryfp:
13424 gen_farith(ctx, mips32_op, -1, rs, rt, 0);
13425 break;
13426
13427 /* Conditional moves on floating-point codes */
13428 case COND_FLOAT_MOV(MOVT, 0):
13429 case COND_FLOAT_MOV(MOVT, 1):
13430 case COND_FLOAT_MOV(MOVT, 2):
13431 case COND_FLOAT_MOV(MOVT, 3):
13432 case COND_FLOAT_MOV(MOVT, 4):
13433 case COND_FLOAT_MOV(MOVT, 5):
13434 case COND_FLOAT_MOV(MOVT, 6):
13435 case COND_FLOAT_MOV(MOVT, 7):
13436 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13437 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
13438 break;
13439 case COND_FLOAT_MOV(MOVF, 0):
13440 case COND_FLOAT_MOV(MOVF, 1):
13441 case COND_FLOAT_MOV(MOVF, 2):
13442 case COND_FLOAT_MOV(MOVF, 3):
13443 case COND_FLOAT_MOV(MOVF, 4):
13444 case COND_FLOAT_MOV(MOVF, 5):
13445 case COND_FLOAT_MOV(MOVF, 6):
13446 case COND_FLOAT_MOV(MOVF, 7):
13447 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13448 gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
13449 break;
13450 default:
13451 MIPS_INVAL("pool32fxf");
13452 generate_exception(ctx, EXCP_RI);
13453 break;
13454 }
13455 }
13456
13457 static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
13458 {
13459 int32_t offset;
13460 uint16_t insn;
13461 int rt, rs, rd, rr;
13462 int16_t imm;
13463 uint32_t op, minor, mips32_op;
13464 uint32_t cond, fmt, cc;
13465
13466 insn = cpu_lduw_code(env, ctx->pc + 2);
13467 ctx->opcode = (ctx->opcode << 16) | insn;
13468
13469 rt = (ctx->opcode >> 21) & 0x1f;
13470 rs = (ctx->opcode >> 16) & 0x1f;
13471 rd = (ctx->opcode >> 11) & 0x1f;
13472 rr = (ctx->opcode >> 6) & 0x1f;
13473 imm = (int16_t) ctx->opcode;
13474
13475 op = (ctx->opcode >> 26) & 0x3f;
13476 switch (op) {
13477 case POOL32A:
13478 minor = ctx->opcode & 0x3f;
13479 switch (minor) {
13480 case 0x00:
13481 minor = (ctx->opcode >> 6) & 0xf;
13482 switch (minor) {
13483 case SLL32:
13484 mips32_op = OPC_SLL;
13485 goto do_shifti;
13486 case SRA:
13487 mips32_op = OPC_SRA;
13488 goto do_shifti;
13489 case SRL32:
13490 mips32_op = OPC_SRL;
13491 goto do_shifti;
13492 case ROTR:
13493 mips32_op = OPC_ROTR;
13494 do_shifti:
13495 gen_shift_imm(ctx, mips32_op, rt, rs, rd);
13496 break;
13497 case SELEQZ:
13498 check_insn(ctx, ISA_MIPS32R6);
13499 gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt);
13500 break;
13501 case SELNEZ:
13502 check_insn(ctx, ISA_MIPS32R6);
13503 gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt);
13504 break;
13505 default:
13506 goto pool32a_invalid;
13507 }
13508 break;
13509 case 0x10:
13510 minor = (ctx->opcode >> 6) & 0xf;
13511 switch (minor) {
13512 /* Arithmetic */
13513 case ADD:
13514 mips32_op = OPC_ADD;
13515 goto do_arith;
13516 case ADDU32:
13517 mips32_op = OPC_ADDU;
13518 goto do_arith;
13519 case SUB:
13520 mips32_op = OPC_SUB;
13521 goto do_arith;
13522 case SUBU32:
13523 mips32_op = OPC_SUBU;
13524 goto do_arith;
13525 case MUL:
13526 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13527 mips32_op = OPC_MUL;
13528 do_arith:
13529 gen_arith(ctx, mips32_op, rd, rs, rt);
13530 break;
13531 /* Shifts */
13532 case SLLV:
13533 mips32_op = OPC_SLLV;
13534 goto do_shift;
13535 case SRLV:
13536 mips32_op = OPC_SRLV;
13537 goto do_shift;
13538 case SRAV:
13539 mips32_op = OPC_SRAV;
13540 goto do_shift;
13541 case ROTRV:
13542 mips32_op = OPC_ROTRV;
13543 do_shift:
13544 gen_shift(ctx, mips32_op, rd, rs, rt);
13545 break;
13546 /* Logical operations */
13547 case AND:
13548 mips32_op = OPC_AND;
13549 goto do_logic;
13550 case OR32:
13551 mips32_op = OPC_OR;
13552 goto do_logic;
13553 case NOR:
13554 mips32_op = OPC_NOR;
13555 goto do_logic;
13556 case XOR32:
13557 mips32_op = OPC_XOR;
13558 do_logic:
13559 gen_logic(ctx, mips32_op, rd, rs, rt);
13560 break;
13561 /* Set less than */
13562 case SLT:
13563 mips32_op = OPC_SLT;
13564 goto do_slt;
13565 case SLTU:
13566 mips32_op = OPC_SLTU;
13567 do_slt:
13568 gen_slt(ctx, mips32_op, rd, rs, rt);
13569 break;
13570 default:
13571 goto pool32a_invalid;
13572 }
13573 break;
13574 case 0x18:
13575 minor = (ctx->opcode >> 6) & 0xf;
13576 switch (minor) {
13577 /* Conditional moves */
13578 case MOVN: /* MUL */
13579 if (ctx->insn_flags & ISA_MIPS32R6) {
13580 /* MUL */
13581 gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
13582 } else {
13583 /* MOVN */
13584 gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
13585 }
13586 break;
13587 case MOVZ: /* MUH */
13588 if (ctx->insn_flags & ISA_MIPS32R6) {
13589 /* MUH */
13590 gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
13591 } else {
13592 /* MOVZ */
13593 gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
13594 }
13595 break;
13596 case MULU:
13597 check_insn(ctx, ISA_MIPS32R6);
13598 gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
13599 break;
13600 case MUHU:
13601 check_insn(ctx, ISA_MIPS32R6);
13602 gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
13603 break;
13604 case LWXS: /* DIV */
13605 if (ctx->insn_flags & ISA_MIPS32R6) {
13606 /* DIV */
13607 gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
13608 } else {
13609 /* LWXS */
13610 gen_ldxs(ctx, rs, rt, rd);
13611 }
13612 break;
13613 case MOD:
13614 check_insn(ctx, ISA_MIPS32R6);
13615 gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
13616 break;
13617 case R6_DIVU:
13618 check_insn(ctx, ISA_MIPS32R6);
13619 gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
13620 break;
13621 case MODU:
13622 check_insn(ctx, ISA_MIPS32R6);
13623 gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
13624 break;
13625 default:
13626 goto pool32a_invalid;
13627 }
13628 break;
13629 case INS:
13630 gen_bitops(ctx, OPC_INS, rt, rs, rr, rd);
13631 return;
13632 case LSA:
13633 check_insn(ctx, ISA_MIPS32R6);
13634 gen_lsa(ctx, OPC_LSA, rd, rs, rt,
13635 extract32(ctx->opcode, 9, 2));
13636 break;
13637 case ALIGN:
13638 check_insn(ctx, ISA_MIPS32R6);
13639 gen_align(ctx, OPC_ALIGN, rd, rs, rt,
13640 extract32(ctx->opcode, 9, 2));
13641 break;
13642 case EXT:
13643 gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
13644 return;
13645 case POOL32AXF:
13646 gen_pool32axf(env, ctx, rt, rs);
13647 break;
13648 case 0x07:
13649 generate_exception(ctx, EXCP_BREAK);
13650 break;
13651 default:
13652 pool32a_invalid:
13653 MIPS_INVAL("pool32a");
13654 generate_exception(ctx, EXCP_RI);
13655 break;
13656 }
13657 break;
13658 case POOL32B:
13659 minor = (ctx->opcode >> 12) & 0xf;
13660 switch (minor) {
13661 case CACHE:
13662 check_cp0_enabled(ctx);
13663 /* Treat as no-op. */
13664 break;
13665 case LWC2:
13666 case SWC2:
13667 /* COP2: Not implemented. */
13668 generate_exception_err(ctx, EXCP_CpU, 2);
13669 break;
13670 #ifdef TARGET_MIPS64
13671 case LDP:
13672 case SDP:
13673 check_insn(ctx, ISA_MIPS3);
13674 check_mips_64(ctx);
13675 /* Fallthrough */
13676 #endif
13677 case LWP:
13678 case SWP:
13679 gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
13680 break;
13681 #ifdef TARGET_MIPS64
13682 case LDM:
13683 case SDM:
13684 check_insn(ctx, ISA_MIPS3);
13685 check_mips_64(ctx);
13686 /* Fallthrough */
13687 #endif
13688 case LWM32:
13689 case SWM32:
13690 gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
13691 break;
13692 default:
13693 MIPS_INVAL("pool32b");
13694 generate_exception(ctx, EXCP_RI);
13695 break;
13696 }
13697 break;
13698 case POOL32F:
13699 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
13700 minor = ctx->opcode & 0x3f;
13701 check_cp1_enabled(ctx);
13702 switch (minor) {
13703 case ALNV_PS:
13704 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13705 mips32_op = OPC_ALNV_PS;
13706 goto do_madd;
13707 case MADD_S:
13708 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13709 mips32_op = OPC_MADD_S;
13710 goto do_madd;
13711 case MADD_D:
13712 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13713 mips32_op = OPC_MADD_D;
13714 goto do_madd;
13715 case MADD_PS:
13716 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13717 mips32_op = OPC_MADD_PS;
13718 goto do_madd;
13719 case MSUB_S:
13720 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13721 mips32_op = OPC_MSUB_S;
13722 goto do_madd;
13723 case MSUB_D:
13724 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13725 mips32_op = OPC_MSUB_D;
13726 goto do_madd;
13727 case MSUB_PS:
13728 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13729 mips32_op = OPC_MSUB_PS;
13730 goto do_madd;
13731 case NMADD_S:
13732 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13733 mips32_op = OPC_NMADD_S;
13734 goto do_madd;
13735 case NMADD_D:
13736 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13737 mips32_op = OPC_NMADD_D;
13738 goto do_madd;
13739 case NMADD_PS:
13740 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13741 mips32_op = OPC_NMADD_PS;
13742 goto do_madd;
13743 case NMSUB_S:
13744 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13745 mips32_op = OPC_NMSUB_S;
13746 goto do_madd;
13747 case NMSUB_D:
13748 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13749 mips32_op = OPC_NMSUB_D;
13750 goto do_madd;
13751 case NMSUB_PS:
13752 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13753 mips32_op = OPC_NMSUB_PS;
13754 do_madd:
13755 gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
13756 break;
13757 case CABS_COND_FMT:
13758 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13759 cond = (ctx->opcode >> 6) & 0xf;
13760 cc = (ctx->opcode >> 13) & 0x7;
13761 fmt = (ctx->opcode >> 10) & 0x3;
13762 switch (fmt) {
13763 case 0x0:
13764 gen_cmpabs_s(ctx, cond, rt, rs, cc);
13765 break;
13766 case 0x1:
13767 gen_cmpabs_d(ctx, cond, rt, rs, cc);
13768 break;
13769 case 0x2:
13770 gen_cmpabs_ps(ctx, cond, rt, rs, cc);
13771 break;
13772 default:
13773 goto pool32f_invalid;
13774 }
13775 break;
13776 case C_COND_FMT:
13777 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13778 cond = (ctx->opcode >> 6) & 0xf;
13779 cc = (ctx->opcode >> 13) & 0x7;
13780 fmt = (ctx->opcode >> 10) & 0x3;
13781 switch (fmt) {
13782 case 0x0:
13783 gen_cmp_s(ctx, cond, rt, rs, cc);
13784 break;
13785 case 0x1:
13786 gen_cmp_d(ctx, cond, rt, rs, cc);
13787 break;
13788 case 0x2:
13789 gen_cmp_ps(ctx, cond, rt, rs, cc);
13790 break;
13791 default:
13792 goto pool32f_invalid;
13793 }
13794 break;
13795 case CMP_CONDN_S:
13796 check_insn(ctx, ISA_MIPS32R6);
13797 gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
13798 break;
13799 case CMP_CONDN_D:
13800 check_insn(ctx, ISA_MIPS32R6);
13801 gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
13802 break;
13803 case POOL32FXF:
13804 gen_pool32fxf(ctx, rt, rs);
13805 break;
13806 case 0x00:
13807 /* PLL foo */
13808 switch ((ctx->opcode >> 6) & 0x7) {
13809 case PLL_PS:
13810 mips32_op = OPC_PLL_PS;
13811 goto do_ps;
13812 case PLU_PS:
13813 mips32_op = OPC_PLU_PS;
13814 goto do_ps;
13815 case PUL_PS:
13816 mips32_op = OPC_PUL_PS;
13817 goto do_ps;
13818 case PUU_PS:
13819 mips32_op = OPC_PUU_PS;
13820 goto do_ps;
13821 case CVT_PS_S:
13822 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13823 mips32_op = OPC_CVT_PS_S;
13824 do_ps:
13825 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
13826 break;
13827 default:
13828 goto pool32f_invalid;
13829 }
13830 break;
13831 case MIN_FMT:
13832 check_insn(ctx, ISA_MIPS32R6);
13833 switch ((ctx->opcode >> 9) & 0x3) {
13834 case FMT_SDPS_S:
13835 gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
13836 break;
13837 case FMT_SDPS_D:
13838 gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
13839 break;
13840 default:
13841 goto pool32f_invalid;
13842 }
13843 break;
13844 case 0x08:
13845 /* [LS][WDU]XC1 */
13846 switch ((ctx->opcode >> 6) & 0x7) {
13847 case LWXC1:
13848 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13849 mips32_op = OPC_LWXC1;
13850 goto do_ldst_cp1;
13851 case SWXC1:
13852 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13853 mips32_op = OPC_SWXC1;
13854 goto do_ldst_cp1;
13855 case LDXC1:
13856 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13857 mips32_op = OPC_LDXC1;
13858 goto do_ldst_cp1;
13859 case SDXC1:
13860 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13861 mips32_op = OPC_SDXC1;
13862 goto do_ldst_cp1;
13863 case LUXC1:
13864 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13865 mips32_op = OPC_LUXC1;
13866 goto do_ldst_cp1;
13867 case SUXC1:
13868 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13869 mips32_op = OPC_SUXC1;
13870 do_ldst_cp1:
13871 gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
13872 break;
13873 default:
13874 goto pool32f_invalid;
13875 }
13876 break;
13877 case MAX_FMT:
13878 check_insn(ctx, ISA_MIPS32R6);
13879 switch ((ctx->opcode >> 9) & 0x3) {
13880 case FMT_SDPS_S:
13881 gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
13882 break;
13883 case FMT_SDPS_D:
13884 gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
13885 break;
13886 default:
13887 goto pool32f_invalid;
13888 }
13889 break;
13890 case 0x18:
13891 /* 3D insns */
13892 check_insn_opc_removed(ctx, ISA_MIPS32R6);
13893 fmt = (ctx->opcode >> 9) & 0x3;
13894 switch ((ctx->opcode >> 6) & 0x7) {
13895 case RSQRT2_FMT:
13896 switch (fmt) {
13897 case FMT_SDPS_S:
13898 mips32_op = OPC_RSQRT2_S;
13899 goto do_3d;
13900 case FMT_SDPS_D:
13901 mips32_op = OPC_RSQRT2_D;
13902 goto do_3d;
13903 case FMT_SDPS_PS:
13904 mips32_op = OPC_RSQRT2_PS;
13905 goto do_3d;
13906 default:
13907 goto pool32f_invalid;
13908 }
13909 break;
13910 case RECIP2_FMT:
13911 switch (fmt) {
13912 case FMT_SDPS_S:
13913 mips32_op = OPC_RECIP2_S;
13914 goto do_3d;
13915 case FMT_SDPS_D:
13916 mips32_op = OPC_RECIP2_D;
13917 goto do_3d;
13918 case FMT_SDPS_PS:
13919 mips32_op = OPC_RECIP2_PS;
13920 goto do_3d;
13921 default:
13922 goto pool32f_invalid;
13923 }
13924 break;
13925 case ADDR_PS:
13926 mips32_op = OPC_ADDR_PS;
13927 goto do_3d;
13928 case MULR_PS:
13929 mips32_op = OPC_MULR_PS;
13930 do_3d:
13931 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
13932 break;
13933 default:
13934 goto pool32f_invalid;
13935 }
13936 break;
13937 case 0x20:
13938 /* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
13939 cc = (ctx->opcode >> 13) & 0x7;
13940 fmt = (ctx->opcode >> 9) & 0x3;
13941 switch ((ctx->opcode >> 6) & 0x7) {
13942 case MOVF_FMT: /* RINT_FMT */
13943 if (ctx->insn_flags & ISA_MIPS32R6) {
13944 /* RINT_FMT */
13945 switch (fmt) {
13946 case FMT_SDPS_S:
13947 gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
13948 break;
13949 case FMT_SDPS_D:
13950 gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
13951 break;
13952 default:
13953 goto pool32f_invalid;
13954 }
13955 } else {
13956 /* MOVF_FMT */
13957 switch (fmt) {
13958 case FMT_SDPS_S:
13959 gen_movcf_s(ctx, rs, rt, cc, 0);
13960 break;
13961 case FMT_SDPS_D:
13962 gen_movcf_d(ctx, rs, rt, cc, 0);
13963 break;
13964 case FMT_SDPS_PS:
13965 check_ps(ctx);
13966 gen_movcf_ps(ctx, rs, rt, cc, 0);
13967 break;
13968 default:
13969 goto pool32f_invalid;
13970 }
13971 }
13972 break;
13973 case MOVT_FMT: /* CLASS_FMT */
13974 if (ctx->insn_flags & ISA_MIPS32R6) {
13975 /* CLASS_FMT */
13976 switch (fmt) {
13977 case FMT_SDPS_S:
13978 gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
13979 break;
13980 case FMT_SDPS_D:
13981 gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
13982 break;
13983 default:
13984 goto pool32f_invalid;
13985 }
13986 } else {
13987 /* MOVT_FMT */
13988 switch (fmt) {
13989 case FMT_SDPS_S:
13990 gen_movcf_s(ctx, rs, rt, cc, 1);
13991 break;
13992 case FMT_SDPS_D:
13993 gen_movcf_d(ctx, rs, rt, cc, 1);
13994 break;
13995 case FMT_SDPS_PS:
13996 check_ps(ctx);
13997 gen_movcf_ps(ctx, rs, rt, cc, 1);
13998 break;
13999 default:
14000 goto pool32f_invalid;
14001 }
14002 }
14003 break;
14004 case PREFX:
14005 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14006 break;
14007 default:
14008 goto pool32f_invalid;
14009 }
14010 break;
14011 #define FINSN_3ARG_SDPS(prfx) \
14012 switch ((ctx->opcode >> 8) & 0x3) { \
14013 case FMT_SDPS_S: \
14014 mips32_op = OPC_##prfx##_S; \
14015 goto do_fpop; \
14016 case FMT_SDPS_D: \
14017 mips32_op = OPC_##prfx##_D; \
14018 goto do_fpop; \
14019 case FMT_SDPS_PS: \
14020 check_ps(ctx); \
14021 mips32_op = OPC_##prfx##_PS; \
14022 goto do_fpop; \
14023 default: \
14024 goto pool32f_invalid; \
14025 }
14026 case MINA_FMT:
14027 check_insn(ctx, ISA_MIPS32R6);
14028 switch ((ctx->opcode >> 9) & 0x3) {
14029 case FMT_SDPS_S:
14030 gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
14031 break;
14032 case FMT_SDPS_D:
14033 gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
14034 break;
14035 default:
14036 goto pool32f_invalid;
14037 }
14038 break;
14039 case MAXA_FMT:
14040 check_insn(ctx, ISA_MIPS32R6);
14041 switch ((ctx->opcode >> 9) & 0x3) {
14042 case FMT_SDPS_S:
14043 gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
14044 break;
14045 case FMT_SDPS_D:
14046 gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
14047 break;
14048 default:
14049 goto pool32f_invalid;
14050 }
14051 break;
14052 case 0x30:
14053 /* regular FP ops */
14054 switch ((ctx->opcode >> 6) & 0x3) {
14055 case ADD_FMT:
14056 FINSN_3ARG_SDPS(ADD);
14057 break;
14058 case SUB_FMT:
14059 FINSN_3ARG_SDPS(SUB);
14060 break;
14061 case MUL_FMT:
14062 FINSN_3ARG_SDPS(MUL);
14063 break;
14064 case DIV_FMT:
14065 fmt = (ctx->opcode >> 8) & 0x3;
14066 if (fmt == 1) {
14067 mips32_op = OPC_DIV_D;
14068 } else if (fmt == 0) {
14069 mips32_op = OPC_DIV_S;
14070 } else {
14071 goto pool32f_invalid;
14072 }
14073 goto do_fpop;
14074 default:
14075 goto pool32f_invalid;
14076 }
14077 break;
14078 case 0x38:
14079 /* cmovs */
14080 switch ((ctx->opcode >> 6) & 0x7) {
14081 case MOVN_FMT: /* SELNEZ_FMT */
14082 if (ctx->insn_flags & ISA_MIPS32R6) {
14083 /* SELNEZ_FMT */
14084 switch ((ctx->opcode >> 9) & 0x3) {
14085 case FMT_SDPS_S:
14086 gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
14087 break;
14088 case FMT_SDPS_D:
14089 gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
14090 break;
14091 default:
14092 goto pool32f_invalid;
14093 }
14094 } else {
14095 /* MOVN_FMT */
14096 FINSN_3ARG_SDPS(MOVN);
14097 }
14098 break;
14099 case MOVN_FMT_04:
14100 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14101 FINSN_3ARG_SDPS(MOVN);
14102 break;
14103 case MOVZ_FMT: /* SELEQZ_FMT */
14104 if (ctx->insn_flags & ISA_MIPS32R6) {
14105 /* SELEQZ_FMT */
14106 switch ((ctx->opcode >> 9) & 0x3) {
14107 case FMT_SDPS_S:
14108 gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
14109 break;
14110 case FMT_SDPS_D:
14111 gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
14112 break;
14113 default:
14114 goto pool32f_invalid;
14115 }
14116 } else {
14117 /* MOVZ_FMT */
14118 FINSN_3ARG_SDPS(MOVZ);
14119 }
14120 break;
14121 case MOVZ_FMT_05:
14122 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14123 FINSN_3ARG_SDPS(MOVZ);
14124 break;
14125 case SEL_FMT:
14126 check_insn(ctx, ISA_MIPS32R6);
14127 switch ((ctx->opcode >> 9) & 0x3) {
14128 case FMT_SDPS_S:
14129 gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
14130 break;
14131 case FMT_SDPS_D:
14132 gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
14133 break;
14134 default:
14135 goto pool32f_invalid;
14136 }
14137 break;
14138 case MADDF_FMT:
14139 check_insn(ctx, ISA_MIPS32R6);
14140 switch ((ctx->opcode >> 9) & 0x3) {
14141 case FMT_SDPS_S:
14142 mips32_op = OPC_MADDF_S;
14143 goto do_fpop;
14144 case FMT_SDPS_D:
14145 mips32_op = OPC_MADDF_D;
14146 goto do_fpop;
14147 default:
14148 goto pool32f_invalid;
14149 }
14150 break;
14151 case MSUBF_FMT:
14152 check_insn(ctx, ISA_MIPS32R6);
14153 switch ((ctx->opcode >> 9) & 0x3) {
14154 case FMT_SDPS_S:
14155 mips32_op = OPC_MSUBF_S;
14156 goto do_fpop;
14157 case FMT_SDPS_D:
14158 mips32_op = OPC_MSUBF_D;
14159 goto do_fpop;
14160 default:
14161 goto pool32f_invalid;
14162 }
14163 break;
14164 default:
14165 goto pool32f_invalid;
14166 }
14167 break;
14168 do_fpop:
14169 gen_farith(ctx, mips32_op, rt, rs, rd, 0);
14170 break;
14171 default:
14172 pool32f_invalid:
14173 MIPS_INVAL("pool32f");
14174 generate_exception(ctx, EXCP_RI);
14175 break;
14176 }
14177 } else {
14178 generate_exception_err(ctx, EXCP_CpU, 1);
14179 }
14180 break;
14181 case POOL32I:
14182 minor = (ctx->opcode >> 21) & 0x1f;
14183 switch (minor) {
14184 case BLTZ:
14185 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14186 gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
14187 break;
14188 case BLTZAL:
14189 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14190 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
14191 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14192 break;
14193 case BLTZALS:
14194 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14195 gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
14196 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14197 break;
14198 case BGEZ:
14199 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14200 gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
14201 break;
14202 case BGEZAL:
14203 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14204 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
14205 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14206 break;
14207 case BGEZALS:
14208 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14209 gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
14210 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14211 break;
14212 case BLEZ:
14213 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14214 gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
14215 break;
14216 case BGTZ:
14217 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14218 gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
14219 break;
14220
14221 /* Traps */
14222 case TLTI: /* BC1EQZC */
14223 if (ctx->insn_flags & ISA_MIPS32R6) {
14224 /* BC1EQZC */
14225 check_cp1_enabled(ctx);
14226 gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0);
14227 } else {
14228 /* TLTI */
14229 mips32_op = OPC_TLTI;
14230 goto do_trapi;
14231 }
14232 break;
14233 case TGEI: /* BC1NEZC */
14234 if (ctx->insn_flags & ISA_MIPS32R6) {
14235 /* BC1NEZC */
14236 check_cp1_enabled(ctx);
14237 gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0);
14238 } else {
14239 /* TGEI */
14240 mips32_op = OPC_TGEI;
14241 goto do_trapi;
14242 }
14243 break;
14244 case TLTIU:
14245 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14246 mips32_op = OPC_TLTIU;
14247 goto do_trapi;
14248 case TGEIU:
14249 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14250 mips32_op = OPC_TGEIU;
14251 goto do_trapi;
14252 case TNEI: /* SYNCI */
14253 if (ctx->insn_flags & ISA_MIPS32R6) {
14254 /* SYNCI */
14255 /* Break the TB to be able to sync copied instructions
14256 immediately */
14257 ctx->bstate = BS_STOP;
14258 } else {
14259 /* TNEI */
14260 mips32_op = OPC_TNEI;
14261 goto do_trapi;
14262 }
14263 break;
14264 case TEQI:
14265 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14266 mips32_op = OPC_TEQI;
14267 do_trapi:
14268 gen_trap(ctx, mips32_op, rs, -1, imm);
14269 break;
14270
14271 case BNEZC:
14272 case BEQZC:
14273 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14274 gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
14275 4, rs, 0, imm << 1, 0);
14276 /* Compact branches don't have a delay slot, so just let
14277 the normal delay slot handling take us to the branch
14278 target. */
14279 break;
14280 case LUI:
14281 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14282 gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
14283 break;
14284 case SYNCI:
14285 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14286 /* Break the TB to be able to sync copied instructions
14287 immediately */
14288 ctx->bstate = BS_STOP;
14289 break;
14290 case BC2F:
14291 case BC2T:
14292 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14293 /* COP2: Not implemented. */
14294 generate_exception_err(ctx, EXCP_CpU, 2);
14295 break;
14296 case BC1F:
14297 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14298 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
14299 goto do_cp1branch;
14300 case BC1T:
14301 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14302 mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
14303 goto do_cp1branch;
14304 case BC1ANY4F:
14305 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14306 mips32_op = OPC_BC1FANY4;
14307 goto do_cp1mips3d;
14308 case BC1ANY4T:
14309 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14310 mips32_op = OPC_BC1TANY4;
14311 do_cp1mips3d:
14312 check_cop1x(ctx);
14313 check_insn(ctx, ASE_MIPS3D);
14314 /* Fall through */
14315 do_cp1branch:
14316 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
14317 check_cp1_enabled(ctx);
14318 gen_compute_branch1(ctx, mips32_op,
14319 (ctx->opcode >> 18) & 0x7, imm << 1);
14320 } else {
14321 generate_exception_err(ctx, EXCP_CpU, 1);
14322 }
14323 break;
14324 case BPOSGE64:
14325 case BPOSGE32:
14326 /* MIPS DSP: not implemented */
14327 /* Fall through */
14328 default:
14329 MIPS_INVAL("pool32i");
14330 generate_exception(ctx, EXCP_RI);
14331 break;
14332 }
14333 break;
14334 case POOL32C:
14335 minor = (ctx->opcode >> 12) & 0xf;
14336 offset = sextract32(ctx->opcode, 0,
14337 (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
14338 switch (minor) {
14339 case LWL:
14340 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14341 mips32_op = OPC_LWL;
14342 goto do_ld_lr;
14343 case SWL:
14344 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14345 mips32_op = OPC_SWL;
14346 goto do_st_lr;
14347 case LWR:
14348 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14349 mips32_op = OPC_LWR;
14350 goto do_ld_lr;
14351 case SWR:
14352 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14353 mips32_op = OPC_SWR;
14354 goto do_st_lr;
14355 #if defined(TARGET_MIPS64)
14356 case LDL:
14357 check_insn(ctx, ISA_MIPS3);
14358 check_mips_64(ctx);
14359 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14360 mips32_op = OPC_LDL;
14361 goto do_ld_lr;
14362 case SDL:
14363 check_insn(ctx, ISA_MIPS3);
14364 check_mips_64(ctx);
14365 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14366 mips32_op = OPC_SDL;
14367 goto do_st_lr;
14368 case LDR:
14369 check_insn(ctx, ISA_MIPS3);
14370 check_mips_64(ctx);
14371 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14372 mips32_op = OPC_LDR;
14373 goto do_ld_lr;
14374 case SDR:
14375 check_insn(ctx, ISA_MIPS3);
14376 check_mips_64(ctx);
14377 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14378 mips32_op = OPC_SDR;
14379 goto do_st_lr;
14380 case LWU:
14381 check_insn(ctx, ISA_MIPS3);
14382 check_mips_64(ctx);
14383 mips32_op = OPC_LWU;
14384 goto do_ld_lr;
14385 case LLD:
14386 check_insn(ctx, ISA_MIPS3);
14387 check_mips_64(ctx);
14388 mips32_op = OPC_LLD;
14389 goto do_ld_lr;
14390 #endif
14391 case LL:
14392 mips32_op = OPC_LL;
14393 goto do_ld_lr;
14394 do_ld_lr:
14395 gen_ld(ctx, mips32_op, rt, rs, offset);
14396 break;
14397 do_st_lr:
14398 gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
14399 break;
14400 case SC:
14401 gen_st_cond(ctx, OPC_SC, rt, rs, offset);
14402 break;
14403 #if defined(TARGET_MIPS64)
14404 case SCD:
14405 check_insn(ctx, ISA_MIPS3);
14406 check_mips_64(ctx);
14407 gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
14408 break;
14409 #endif
14410 case PREF:
14411 /* Treat as no-op */
14412 if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
14413 /* hint codes 24-31 are reserved and signal RI */
14414 generate_exception(ctx, EXCP_RI);
14415 }
14416 break;
14417 default:
14418 MIPS_INVAL("pool32c");
14419 generate_exception(ctx, EXCP_RI);
14420 break;
14421 }
14422 break;
14423 case ADDI32: /* AUI, LUI */
14424 if (ctx->insn_flags & ISA_MIPS32R6) {
14425 /* AUI, LUI */
14426 gen_logic_imm(ctx, OPC_LUI, rt, rs, imm);
14427 } else {
14428 /* ADDI32 */
14429 mips32_op = OPC_ADDI;
14430 goto do_addi;
14431 }
14432 break;
14433 case ADDIU32:
14434 mips32_op = OPC_ADDIU;
14435 do_addi:
14436 gen_arith_imm(ctx, mips32_op, rt, rs, imm);
14437 break;
14438
14439 /* Logical operations */
14440 case ORI32:
14441 mips32_op = OPC_ORI;
14442 goto do_logici;
14443 case XORI32:
14444 mips32_op = OPC_XORI;
14445 goto do_logici;
14446 case ANDI32:
14447 mips32_op = OPC_ANDI;
14448 do_logici:
14449 gen_logic_imm(ctx, mips32_op, rt, rs, imm);
14450 break;
14451
14452 /* Set less than immediate */
14453 case SLTI32:
14454 mips32_op = OPC_SLTI;
14455 goto do_slti;
14456 case SLTIU32:
14457 mips32_op = OPC_SLTIU;
14458 do_slti:
14459 gen_slt_imm(ctx, mips32_op, rt, rs, imm);
14460 break;
14461 case JALX32:
14462 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14463 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
14464 gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
14465 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14466 break;
14467 case JALS32: /* BOVC, BEQC, BEQZALC */
14468 if (ctx->insn_flags & ISA_MIPS32R6) {
14469 if (rs >= rt) {
14470 /* BOVC */
14471 mips32_op = OPC_BOVC;
14472 } else if (rs < rt && rs == 0) {
14473 /* BEQZALC */
14474 mips32_op = OPC_BEQZALC;
14475 } else {
14476 /* BEQC */
14477 mips32_op = OPC_BEQC;
14478 }
14479 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14480 } else {
14481 /* JALS32 */
14482 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 1;
14483 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, offset, 2);
14484 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14485 }
14486 break;
14487 case BEQ32: /* BC */
14488 if (ctx->insn_flags & ISA_MIPS32R6) {
14489 /* BC */
14490 gen_compute_compact_branch(ctx, OPC_BC, 0, 0,
14491 sextract32(ctx->opcode << 1, 0, 27));
14492 } else {
14493 /* BEQ32 */
14494 gen_compute_branch(ctx, OPC_BEQ, 4, rt, rs, imm << 1, 4);
14495 }
14496 break;
14497 case BNE32: /* BALC */
14498 if (ctx->insn_flags & ISA_MIPS32R6) {
14499 /* BALC */
14500 gen_compute_compact_branch(ctx, OPC_BALC, 0, 0,
14501 sextract32(ctx->opcode << 1, 0, 27));
14502 } else {
14503 /* BNE32 */
14504 gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4);
14505 }
14506 break;
14507 case J32: /* BGTZC, BLTZC, BLTC */
14508 if (ctx->insn_flags & ISA_MIPS32R6) {
14509 if (rs == 0 && rt != 0) {
14510 /* BGTZC */
14511 mips32_op = OPC_BGTZC;
14512 } else if (rs != 0 && rt != 0 && rs == rt) {
14513 /* BLTZC */
14514 mips32_op = OPC_BLTZC;
14515 } else {
14516 /* BLTC */
14517 mips32_op = OPC_BLTC;
14518 }
14519 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14520 } else {
14521 /* J32 */
14522 gen_compute_branch(ctx, OPC_J, 4, rt, rs,
14523 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
14524 }
14525 break;
14526 case JAL32: /* BLEZC, BGEZC, BGEC */
14527 if (ctx->insn_flags & ISA_MIPS32R6) {
14528 if (rs == 0 && rt != 0) {
14529 /* BLEZC */
14530 mips32_op = OPC_BLEZC;
14531 } else if (rs != 0 && rt != 0 && rs == rt) {
14532 /* BGEZC */
14533 mips32_op = OPC_BGEZC;
14534 } else {
14535 /* BGEC */
14536 mips32_op = OPC_BGEC;
14537 }
14538 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14539 } else {
14540 /* JAL32 */
14541 gen_compute_branch(ctx, OPC_JAL, 4, rt, rs,
14542 (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
14543 ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
14544 }
14545 break;
14546 /* Floating point (COP1) */
14547 case LWC132:
14548 mips32_op = OPC_LWC1;
14549 goto do_cop1;
14550 case LDC132:
14551 mips32_op = OPC_LDC1;
14552 goto do_cop1;
14553 case SWC132:
14554 mips32_op = OPC_SWC1;
14555 goto do_cop1;
14556 case SDC132:
14557 mips32_op = OPC_SDC1;
14558 do_cop1:
14559 gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
14560 break;
14561 case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
14562 if (ctx->insn_flags & ISA_MIPS32R6) {
14563 /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
14564 switch ((ctx->opcode >> 16) & 0x1f) {
14565 case ADDIUPC_00 ... ADDIUPC_07:
14566 gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
14567 break;
14568 case AUIPC:
14569 gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
14570 break;
14571 case ALUIPC:
14572 gen_pcrel(ctx, OPC_ALUIPC, ctx->pc, rt);
14573 break;
14574 case LWPC_08 ... LWPC_0F:
14575 gen_pcrel(ctx, R6_OPC_LWPC, ctx->pc & ~0x3, rt);
14576 break;
14577 default:
14578 generate_exception(ctx, EXCP_RI);
14579 break;
14580 }
14581 } else {
14582 /* ADDIUPC */
14583 int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
14584 int offset = SIMM(ctx->opcode, 0, 23) << 2;
14585
14586 gen_addiupc(ctx, reg, offset, 0, 0);
14587 }
14588 break;
14589 case BNVC: /* BNEC, BNEZALC */
14590 check_insn(ctx, ISA_MIPS32R6);
14591 if (rs >= rt) {
14592 /* BNVC */
14593 mips32_op = OPC_BNVC;
14594 } else if (rs < rt && rs == 0) {
14595 /* BNEZALC */
14596 mips32_op = OPC_BNEZALC;
14597 } else {
14598 /* BNEC */
14599 mips32_op = OPC_BNEC;
14600 }
14601 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14602 break;
14603 case R6_BNEZC: /* JIALC */
14604 check_insn(ctx, ISA_MIPS32R6);
14605 if (rt != 0) {
14606 /* BNEZC */
14607 gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0,
14608 sextract32(ctx->opcode << 1, 0, 22));
14609 } else {
14610 /* JIALC */
14611 gen_compute_compact_branch(ctx, OPC_JIALC, 0, rs, imm);
14612 }
14613 break;
14614 case R6_BEQZC: /* JIC */
14615 check_insn(ctx, ISA_MIPS32R6);
14616 if (rt != 0) {
14617 /* BEQZC */
14618 gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0,
14619 sextract32(ctx->opcode << 1, 0, 22));
14620 } else {
14621 /* JIC */
14622 gen_compute_compact_branch(ctx, OPC_JIC, 0, rs, imm);
14623 }
14624 break;
14625 case BLEZALC: /* BGEZALC, BGEUC */
14626 check_insn(ctx, ISA_MIPS32R6);
14627 if (rs == 0 && rt != 0) {
14628 /* BLEZALC */
14629 mips32_op = OPC_BLEZALC;
14630 } else if (rs != 0 && rt != 0 && rs == rt) {
14631 /* BGEZALC */
14632 mips32_op = OPC_BGEZALC;
14633 } else {
14634 /* BGEUC */
14635 mips32_op = OPC_BGEUC;
14636 }
14637 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14638 break;
14639 case BGTZALC: /* BLTZALC, BLTUC */
14640 check_insn(ctx, ISA_MIPS32R6);
14641 if (rs == 0 && rt != 0) {
14642 /* BGTZALC */
14643 mips32_op = OPC_BGTZALC;
14644 } else if (rs != 0 && rt != 0 && rs == rt) {
14645 /* BLTZALC */
14646 mips32_op = OPC_BLTZALC;
14647 } else {
14648 /* BLTUC */
14649 mips32_op = OPC_BLTUC;
14650 }
14651 gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1);
14652 break;
14653 /* Loads and stores */
14654 case LB32:
14655 mips32_op = OPC_LB;
14656 goto do_ld;
14657 case LBU32:
14658 mips32_op = OPC_LBU;
14659 goto do_ld;
14660 case LH32:
14661 mips32_op = OPC_LH;
14662 goto do_ld;
14663 case LHU32:
14664 mips32_op = OPC_LHU;
14665 goto do_ld;
14666 case LW32:
14667 mips32_op = OPC_LW;
14668 goto do_ld;
14669 #ifdef TARGET_MIPS64
14670 case LD32:
14671 check_insn(ctx, ISA_MIPS3);
14672 check_mips_64(ctx);
14673 mips32_op = OPC_LD;
14674 goto do_ld;
14675 case SD32:
14676 check_insn(ctx, ISA_MIPS3);
14677 check_mips_64(ctx);
14678 mips32_op = OPC_SD;
14679 goto do_st;
14680 #endif
14681 case SB32:
14682 mips32_op = OPC_SB;
14683 goto do_st;
14684 case SH32:
14685 mips32_op = OPC_SH;
14686 goto do_st;
14687 case SW32:
14688 mips32_op = OPC_SW;
14689 goto do_st;
14690 do_ld:
14691 gen_ld(ctx, mips32_op, rt, rs, imm);
14692 break;
14693 do_st:
14694 gen_st(ctx, mips32_op, rt, rs, imm);
14695 break;
14696 default:
14697 generate_exception(ctx, EXCP_RI);
14698 break;
14699 }
14700 }
14701
14702 static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
14703 {
14704 uint32_t op;
14705
14706 /* make sure instructions are on a halfword boundary */
14707 if (ctx->pc & 0x1) {
14708 env->CP0_BadVAddr = ctx->pc;
14709 generate_exception(ctx, EXCP_AdEL);
14710 ctx->bstate = BS_STOP;
14711 return 2;
14712 }
14713
14714 op = (ctx->opcode >> 10) & 0x3f;
14715 /* Enforce properly-sized instructions in a delay slot */
14716 if (ctx->hflags & MIPS_HFLAG_BDS_STRICT) {
14717 switch (op & 0x7) { /* MSB-3..MSB-5 */
14718 case 0:
14719 /* POOL32A, POOL32B, POOL32I, POOL32C */
14720 case 4:
14721 /* ADDI32, ADDIU32, ORI32, XORI32, SLTI32, SLTIU32, ANDI32, JALX32 */
14722 case 5:
14723 /* LBU32, LHU32, POOL32F, JALS32, BEQ32, BNE32, J32, JAL32 */
14724 case 6:
14725 /* SB32, SH32, ADDIUPC, SWC132, SDC132, SW32 */
14726 case 7:
14727 /* LB32, LH32, LWC132, LDC132, LW32 */
14728 if (ctx->hflags & MIPS_HFLAG_BDS16) {
14729 generate_exception(ctx, EXCP_RI);
14730 /* Just stop translation; the user is confused. */
14731 ctx->bstate = BS_STOP;
14732 return 2;
14733 }
14734 break;
14735 case 1:
14736 /* POOL16A, POOL16B, POOL16C, LWGP16, POOL16F */
14737 case 2:
14738 /* LBU16, LHU16, LWSP16, LW16, SB16, SH16, SWSP16, SW16 */
14739 case 3:
14740 /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
14741 if (ctx->hflags & MIPS_HFLAG_BDS32) {
14742 generate_exception(ctx, EXCP_RI);
14743 /* Just stop translation; the user is confused. */
14744 ctx->bstate = BS_STOP;
14745 return 2;
14746 }
14747 break;
14748 }
14749 }
14750
14751 switch (op) {
14752 case POOL16A:
14753 {
14754 int rd = mmreg(uMIPS_RD(ctx->opcode));
14755 int rs1 = mmreg(uMIPS_RS1(ctx->opcode));
14756 int rs2 = mmreg(uMIPS_RS2(ctx->opcode));
14757 uint32_t opc = 0;
14758
14759 switch (ctx->opcode & 0x1) {
14760 case ADDU16:
14761 opc = OPC_ADDU;
14762 break;
14763 case SUBU16:
14764 opc = OPC_SUBU;
14765 break;
14766 }
14767 if (ctx->insn_flags & ISA_MIPS32R6) {
14768 /* In the Release 6 the register number location in
14769 * the instruction encoding has changed.
14770 */
14771 gen_arith(ctx, opc, rs1, rd, rs2);
14772 } else {
14773 gen_arith(ctx, opc, rd, rs1, rs2);
14774 }
14775 }
14776 break;
14777 case POOL16B:
14778 {
14779 int rd = mmreg(uMIPS_RD(ctx->opcode));
14780 int rs = mmreg(uMIPS_RS(ctx->opcode));
14781 int amount = (ctx->opcode >> 1) & 0x7;
14782 uint32_t opc = 0;
14783 amount = amount == 0 ? 8 : amount;
14784
14785 switch (ctx->opcode & 0x1) {
14786 case SLL16:
14787 opc = OPC_SLL;
14788 break;
14789 case SRL16:
14790 opc = OPC_SRL;
14791 break;
14792 }
14793
14794 gen_shift_imm(ctx, opc, rd, rs, amount);
14795 }
14796 break;
14797 case POOL16C:
14798 if (ctx->insn_flags & ISA_MIPS32R6) {
14799 gen_pool16c_r6_insn(ctx);
14800 } else {
14801 gen_pool16c_insn(ctx);
14802 }
14803 break;
14804 case LWGP16:
14805 {
14806 int rd = mmreg(uMIPS_RD(ctx->opcode));
14807 int rb = 28; /* GP */
14808 int16_t offset = SIMM(ctx->opcode, 0, 7) << 2;
14809
14810 gen_ld(ctx, OPC_LW, rd, rb, offset);
14811 }
14812 break;
14813 case POOL16F:
14814 check_insn_opc_removed(ctx, ISA_MIPS32R6);
14815 if (ctx->opcode & 1) {
14816 generate_exception(ctx, EXCP_RI);
14817 } else {
14818 /* MOVEP */
14819 int enc_dest = uMIPS_RD(ctx->opcode);
14820 int enc_rt = uMIPS_RS2(ctx->opcode);
14821 int enc_rs = uMIPS_RS1(ctx->opcode);
14822 gen_movep(ctx, enc_dest, enc_rt, enc_rs);
14823 }
14824 break;
14825 case LBU16:
14826 {
14827 int rd = mmreg(uMIPS_RD(ctx->opcode));
14828 int rb = mmreg(uMIPS_RS(ctx->opcode));
14829 int16_t offset = ZIMM(ctx->opcode, 0, 4);
14830 offset = (offset == 0xf ? -1 : offset);
14831
14832 gen_ld(ctx, OPC_LBU, rd, rb, offset);
14833 }
14834 break;
14835 case LHU16:
14836 {
14837 int rd = mmreg(uMIPS_RD(ctx->opcode));
14838 int rb = mmreg(uMIPS_RS(ctx->opcode));
14839 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
14840
14841 gen_ld(ctx, OPC_LHU, rd, rb, offset);
14842 }
14843 break;
14844 case LWSP16:
14845 {
14846 int rd = (ctx->opcode >> 5) & 0x1f;
14847 int rb = 29; /* SP */
14848 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
14849
14850 gen_ld(ctx, OPC_LW, rd, rb, offset);
14851 }
14852 break;
14853 case LW16:
14854 {
14855 int rd = mmreg(uMIPS_RD(ctx->opcode));
14856 int rb = mmreg(uMIPS_RS(ctx->opcode));
14857 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
14858
14859 gen_ld(ctx, OPC_LW, rd, rb, offset);
14860 }
14861 break;
14862 case SB16:
14863 {
14864 int rd = mmreg2(uMIPS_RD(ctx->opcode));
14865 int rb = mmreg(uMIPS_RS(ctx->opcode));
14866 int16_t offset = ZIMM(ctx->opcode, 0, 4);
14867
14868 gen_st(ctx, OPC_SB, rd, rb, offset);
14869 }
14870 break;
14871 case SH16:
14872 {
14873 int rd = mmreg2(uMIPS_RD(ctx->opcode));
14874 int rb = mmreg(uMIPS_RS(ctx->opcode));
14875 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 1;
14876
14877 gen_st(ctx, OPC_SH, rd, rb, offset);
14878 }
14879 break;
14880 case SWSP16:
14881 {
14882 int rd = (ctx->opcode >> 5) & 0x1f;
14883 int rb = 29; /* SP */
14884 int16_t offset = ZIMM(ctx->opcode, 0, 5) << 2;
14885
14886 gen_st(ctx, OPC_SW, rd, rb, offset);
14887 }
14888 break;
14889 case SW16:
14890 {
14891 int rd = mmreg2(uMIPS_RD(ctx->opcode));
14892 int rb = mmreg(uMIPS_RS(ctx->opcode));
14893 int16_t offset = ZIMM(ctx->opcode, 0, 4) << 2;
14894
14895 gen_st(ctx, OPC_SW, rd, rb, offset);
14896 }
14897 break;
14898 case MOVE16:
14899 {
14900 int rd = uMIPS_RD5(ctx->opcode);
14901 int rs = uMIPS_RS5(ctx->opcode);
14902
14903 gen_arith(ctx, OPC_ADDU, rd, rs, 0);
14904 }
14905 break;
14906 case ANDI16:
14907 gen_andi16(ctx);
14908 break;
14909 case POOL16D:
14910 switch (ctx->opcode & 0x1) {
14911 case ADDIUS5:
14912 gen_addius5(ctx);
14913 break;
14914 case ADDIUSP:
14915 gen_addiusp(ctx);
14916 break;
14917 }
14918 break;
14919 case POOL16E:
14920 switch (ctx->opcode & 0x1) {
14921 case ADDIUR2:
14922 gen_addiur2(ctx);
14923 break;
14924 case ADDIUR1SP:
14925 gen_addiur1sp(ctx);
14926 break;
14927 }
14928 break;
14929 case B16: /* BC16 */
14930 gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0,
14931 sextract32(ctx->opcode, 0, 10) << 1,
14932 (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
14933 break;
14934 case BNEZ16: /* BNEZC16 */
14935 case BEQZ16: /* BEQZC16 */
14936 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,
14937 mmreg(uMIPS_RD(ctx->opcode)),
14938 0, sextract32(ctx->opcode, 0, 7) << 1,
14939 (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4);
14940
14941 break;
14942 case LI16:
14943 {
14944 int reg = mmreg(uMIPS_RD(ctx->opcode));
14945 int imm = ZIMM(ctx->opcode, 0, 7);
14946
14947 imm = (imm == 0x7f ? -1 : imm);
14948 tcg_gen_movi_tl(cpu_gpr[reg], imm);
14949 }
14950 break;
14951 case RES_29:
14952 case RES_31:
14953 case RES_39:
14954 generate_exception(ctx, EXCP_RI);
14955 break;
14956 default:
14957 decode_micromips32_opc(env, ctx);
14958 return 4;
14959 }
14960
14961 return 2;
14962 }
14963
14964 /* SmartMIPS extension to MIPS32 */
14965
14966 #if defined(TARGET_MIPS64)
14967
14968 /* MDMX extension to MIPS64 */
14969
14970 #endif
14971
14972 /* MIPSDSP functions. */
14973 static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
14974 int rd, int base, int offset)
14975 {
14976 TCGv t0;
14977
14978 check_dsp(ctx);
14979 t0 = tcg_temp_new();
14980
14981 if (base == 0) {
14982 gen_load_gpr(t0, offset);
14983 } else if (offset == 0) {
14984 gen_load_gpr(t0, base);
14985 } else {
14986 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
14987 }
14988
14989 switch (opc) {
14990 case OPC_LBUX:
14991 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
14992 gen_store_gpr(t0, rd);
14993 break;
14994 case OPC_LHX:
14995 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
14996 gen_store_gpr(t0, rd);
14997 break;
14998 case OPC_LWX:
14999 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
15000 gen_store_gpr(t0, rd);
15001 break;
15002 #if defined(TARGET_MIPS64)
15003 case OPC_LDX:
15004 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
15005 gen_store_gpr(t0, rd);
15006 break;
15007 #endif
15008 }
15009 tcg_temp_free(t0);
15010 }
15011
15012 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
15013 int ret, int v1, int v2)
15014 {
15015 TCGv v1_t;
15016 TCGv v2_t;
15017
15018 if (ret == 0) {
15019 /* Treat as NOP. */
15020 return;
15021 }
15022
15023 v1_t = tcg_temp_new();
15024 v2_t = tcg_temp_new();
15025
15026 gen_load_gpr(v1_t, v1);
15027 gen_load_gpr(v2_t, v2);
15028
15029 switch (op1) {
15030 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
15031 case OPC_MULT_G_2E:
15032 check_dspr2(ctx);
15033 switch (op2) {
15034 case OPC_ADDUH_QB:
15035 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
15036 break;
15037 case OPC_ADDUH_R_QB:
15038 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
15039 break;
15040 case OPC_ADDQH_PH:
15041 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
15042 break;
15043 case OPC_ADDQH_R_PH:
15044 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
15045 break;
15046 case OPC_ADDQH_W:
15047 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
15048 break;
15049 case OPC_ADDQH_R_W:
15050 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
15051 break;
15052 case OPC_SUBUH_QB:
15053 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
15054 break;
15055 case OPC_SUBUH_R_QB:
15056 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
15057 break;
15058 case OPC_SUBQH_PH:
15059 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
15060 break;
15061 case OPC_SUBQH_R_PH:
15062 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
15063 break;
15064 case OPC_SUBQH_W:
15065 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
15066 break;
15067 case OPC_SUBQH_R_W:
15068 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
15069 break;
15070 }
15071 break;
15072 case OPC_ABSQ_S_PH_DSP:
15073 switch (op2) {
15074 case OPC_ABSQ_S_QB:
15075 check_dspr2(ctx);
15076 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
15077 break;
15078 case OPC_ABSQ_S_PH:
15079 check_dsp(ctx);
15080 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
15081 break;
15082 case OPC_ABSQ_S_W:
15083 check_dsp(ctx);
15084 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
15085 break;
15086 case OPC_PRECEQ_W_PHL:
15087 check_dsp(ctx);
15088 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000);
15089 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
15090 break;
15091 case OPC_PRECEQ_W_PHR:
15092 check_dsp(ctx);
15093 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF);
15094 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
15095 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
15096 break;
15097 case OPC_PRECEQU_PH_QBL:
15098 check_dsp(ctx);
15099 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
15100 break;
15101 case OPC_PRECEQU_PH_QBR:
15102 check_dsp(ctx);
15103 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
15104 break;
15105 case OPC_PRECEQU_PH_QBLA:
15106 check_dsp(ctx);
15107 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
15108 break;
15109 case OPC_PRECEQU_PH_QBRA:
15110 check_dsp(ctx);
15111 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
15112 break;
15113 case OPC_PRECEU_PH_QBL:
15114 check_dsp(ctx);
15115 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
15116 break;
15117 case OPC_PRECEU_PH_QBR:
15118 check_dsp(ctx);
15119 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
15120 break;
15121 case OPC_PRECEU_PH_QBLA:
15122 check_dsp(ctx);
15123 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
15124 break;
15125 case OPC_PRECEU_PH_QBRA:
15126 check_dsp(ctx);
15127 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
15128 break;
15129 }
15130 break;
15131 case OPC_ADDU_QB_DSP:
15132 switch (op2) {
15133 case OPC_ADDQ_PH:
15134 check_dsp(ctx);
15135 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15136 break;
15137 case OPC_ADDQ_S_PH:
15138 check_dsp(ctx);
15139 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15140 break;
15141 case OPC_ADDQ_S_W:
15142 check_dsp(ctx);
15143 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15144 break;
15145 case OPC_ADDU_QB:
15146 check_dsp(ctx);
15147 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15148 break;
15149 case OPC_ADDU_S_QB:
15150 check_dsp(ctx);
15151 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15152 break;
15153 case OPC_ADDU_PH:
15154 check_dspr2(ctx);
15155 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15156 break;
15157 case OPC_ADDU_S_PH:
15158 check_dspr2(ctx);
15159 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15160 break;
15161 case OPC_SUBQ_PH:
15162 check_dsp(ctx);
15163 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15164 break;
15165 case OPC_SUBQ_S_PH:
15166 check_dsp(ctx);
15167 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15168 break;
15169 case OPC_SUBQ_S_W:
15170 check_dsp(ctx);
15171 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15172 break;
15173 case OPC_SUBU_QB:
15174 check_dsp(ctx);
15175 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15176 break;
15177 case OPC_SUBU_S_QB:
15178 check_dsp(ctx);
15179 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15180 break;
15181 case OPC_SUBU_PH:
15182 check_dspr2(ctx);
15183 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15184 break;
15185 case OPC_SUBU_S_PH:
15186 check_dspr2(ctx);
15187 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15188 break;
15189 case OPC_ADDSC:
15190 check_dsp(ctx);
15191 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15192 break;
15193 case OPC_ADDWC:
15194 check_dsp(ctx);
15195 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15196 break;
15197 case OPC_MODSUB:
15198 check_dsp(ctx);
15199 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
15200 break;
15201 case OPC_RADDU_W_QB:
15202 check_dsp(ctx);
15203 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
15204 break;
15205 }
15206 break;
15207 case OPC_CMPU_EQ_QB_DSP:
15208 switch (op2) {
15209 case OPC_PRECR_QB_PH:
15210 check_dspr2(ctx);
15211 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
15212 break;
15213 case OPC_PRECRQ_QB_PH:
15214 check_dsp(ctx);
15215 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
15216 break;
15217 case OPC_PRECR_SRA_PH_W:
15218 check_dspr2(ctx);
15219 {
15220 TCGv_i32 sa_t = tcg_const_i32(v2);
15221 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
15222 cpu_gpr[ret]);
15223 tcg_temp_free_i32(sa_t);
15224 break;
15225 }
15226 case OPC_PRECR_SRA_R_PH_W:
15227 check_dspr2(ctx);
15228 {
15229 TCGv_i32 sa_t = tcg_const_i32(v2);
15230 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
15231 cpu_gpr[ret]);
15232 tcg_temp_free_i32(sa_t);
15233 break;
15234 }
15235 case OPC_PRECRQ_PH_W:
15236 check_dsp(ctx);
15237 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
15238 break;
15239 case OPC_PRECRQ_RS_PH_W:
15240 check_dsp(ctx);
15241 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15242 break;
15243 case OPC_PRECRQU_S_QB_PH:
15244 check_dsp(ctx);
15245 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15246 break;
15247 }
15248 break;
15249 #ifdef TARGET_MIPS64
15250 case OPC_ABSQ_S_QH_DSP:
15251 switch (op2) {
15252 case OPC_PRECEQ_L_PWL:
15253 check_dsp(ctx);
15254 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
15255 break;
15256 case OPC_PRECEQ_L_PWR:
15257 check_dsp(ctx);
15258 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32);
15259 break;
15260 case OPC_PRECEQ_PW_QHL:
15261 check_dsp(ctx);
15262 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
15263 break;
15264 case OPC_PRECEQ_PW_QHR:
15265 check_dsp(ctx);
15266 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
15267 break;
15268 case OPC_PRECEQ_PW_QHLA:
15269 check_dsp(ctx);
15270 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
15271 break;
15272 case OPC_PRECEQ_PW_QHRA:
15273 check_dsp(ctx);
15274 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
15275 break;
15276 case OPC_PRECEQU_QH_OBL:
15277 check_dsp(ctx);
15278 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
15279 break;
15280 case OPC_PRECEQU_QH_OBR:
15281 check_dsp(ctx);
15282 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
15283 break;
15284 case OPC_PRECEQU_QH_OBLA:
15285 check_dsp(ctx);
15286 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
15287 break;
15288 case OPC_PRECEQU_QH_OBRA:
15289 check_dsp(ctx);
15290 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
15291 break;
15292 case OPC_PRECEU_QH_OBL:
15293 check_dsp(ctx);
15294 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
15295 break;
15296 case OPC_PRECEU_QH_OBR:
15297 check_dsp(ctx);
15298 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
15299 break;
15300 case OPC_PRECEU_QH_OBLA:
15301 check_dsp(ctx);
15302 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
15303 break;
15304 case OPC_PRECEU_QH_OBRA:
15305 check_dsp(ctx);
15306 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
15307 break;
15308 case OPC_ABSQ_S_OB:
15309 check_dspr2(ctx);
15310 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
15311 break;
15312 case OPC_ABSQ_S_PW:
15313 check_dsp(ctx);
15314 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
15315 break;
15316 case OPC_ABSQ_S_QH:
15317 check_dsp(ctx);
15318 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
15319 break;
15320 }
15321 break;
15322 case OPC_ADDU_OB_DSP:
15323 switch (op2) {
15324 case OPC_RADDU_L_OB:
15325 check_dsp(ctx);
15326 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
15327 break;
15328 case OPC_SUBQ_PW:
15329 check_dsp(ctx);
15330 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15331 break;
15332 case OPC_SUBQ_S_PW:
15333 check_dsp(ctx);
15334 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15335 break;
15336 case OPC_SUBQ_QH:
15337 check_dsp(ctx);
15338 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15339 break;
15340 case OPC_SUBQ_S_QH:
15341 check_dsp(ctx);
15342 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15343 break;
15344 case OPC_SUBU_OB:
15345 check_dsp(ctx);
15346 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15347 break;
15348 case OPC_SUBU_S_OB:
15349 check_dsp(ctx);
15350 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15351 break;
15352 case OPC_SUBU_QH:
15353 check_dspr2(ctx);
15354 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15355 break;
15356 case OPC_SUBU_S_QH:
15357 check_dspr2(ctx);
15358 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15359 break;
15360 case OPC_SUBUH_OB:
15361 check_dspr2(ctx);
15362 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
15363 break;
15364 case OPC_SUBUH_R_OB:
15365 check_dspr2(ctx);
15366 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
15367 break;
15368 case OPC_ADDQ_PW:
15369 check_dsp(ctx);
15370 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15371 break;
15372 case OPC_ADDQ_S_PW:
15373 check_dsp(ctx);
15374 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15375 break;
15376 case OPC_ADDQ_QH:
15377 check_dsp(ctx);
15378 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15379 break;
15380 case OPC_ADDQ_S_QH:
15381 check_dsp(ctx);
15382 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15383 break;
15384 case OPC_ADDU_OB:
15385 check_dsp(ctx);
15386 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15387 break;
15388 case OPC_ADDU_S_OB:
15389 check_dsp(ctx);
15390 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15391 break;
15392 case OPC_ADDU_QH:
15393 check_dspr2(ctx);
15394 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15395 break;
15396 case OPC_ADDU_S_QH:
15397 check_dspr2(ctx);
15398 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15399 break;
15400 case OPC_ADDUH_OB:
15401 check_dspr2(ctx);
15402 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
15403 break;
15404 case OPC_ADDUH_R_OB:
15405 check_dspr2(ctx);
15406 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
15407 break;
15408 }
15409 break;
15410 case OPC_CMPU_EQ_OB_DSP:
15411 switch (op2) {
15412 case OPC_PRECR_OB_QH:
15413 check_dspr2(ctx);
15414 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
15415 break;
15416 case OPC_PRECR_SRA_QH_PW:
15417 check_dspr2(ctx);
15418 {
15419 TCGv_i32 ret_t = tcg_const_i32(ret);
15420 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
15421 tcg_temp_free_i32(ret_t);
15422 break;
15423 }
15424 case OPC_PRECR_SRA_R_QH_PW:
15425 check_dspr2(ctx);
15426 {
15427 TCGv_i32 sa_v = tcg_const_i32(ret);
15428 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
15429 tcg_temp_free_i32(sa_v);
15430 break;
15431 }
15432 case OPC_PRECRQ_OB_QH:
15433 check_dsp(ctx);
15434 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
15435 break;
15436 case OPC_PRECRQ_PW_L:
15437 check_dsp(ctx);
15438 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
15439 break;
15440 case OPC_PRECRQ_QH_PW:
15441 check_dsp(ctx);
15442 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
15443 break;
15444 case OPC_PRECRQ_RS_QH_PW:
15445 check_dsp(ctx);
15446 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15447 break;
15448 case OPC_PRECRQU_S_OB_QH:
15449 check_dsp(ctx);
15450 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15451 break;
15452 }
15453 break;
15454 #endif
15455 }
15456
15457 tcg_temp_free(v1_t);
15458 tcg_temp_free(v2_t);
15459 }
15460
15461 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
15462 int ret, int v1, int v2)
15463 {
15464 uint32_t op2;
15465 TCGv t0;
15466 TCGv v1_t;
15467 TCGv v2_t;
15468
15469 if (ret == 0) {
15470 /* Treat as NOP. */
15471 return;
15472 }
15473
15474 t0 = tcg_temp_new();
15475 v1_t = tcg_temp_new();
15476 v2_t = tcg_temp_new();
15477
15478 tcg_gen_movi_tl(t0, v1);
15479 gen_load_gpr(v1_t, v1);
15480 gen_load_gpr(v2_t, v2);
15481
15482 switch (opc) {
15483 case OPC_SHLL_QB_DSP:
15484 {
15485 op2 = MASK_SHLL_QB(ctx->opcode);
15486 switch (op2) {
15487 case OPC_SHLL_QB:
15488 check_dsp(ctx);
15489 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env);
15490 break;
15491 case OPC_SHLLV_QB:
15492 check_dsp(ctx);
15493 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15494 break;
15495 case OPC_SHLL_PH:
15496 check_dsp(ctx);
15497 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
15498 break;
15499 case OPC_SHLLV_PH:
15500 check_dsp(ctx);
15501 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15502 break;
15503 case OPC_SHLL_S_PH:
15504 check_dsp(ctx);
15505 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env);
15506 break;
15507 case OPC_SHLLV_S_PH:
15508 check_dsp(ctx);
15509 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15510 break;
15511 case OPC_SHLL_S_W:
15512 check_dsp(ctx);
15513 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env);
15514 break;
15515 case OPC_SHLLV_S_W:
15516 check_dsp(ctx);
15517 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15518 break;
15519 case OPC_SHRL_QB:
15520 check_dsp(ctx);
15521 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
15522 break;
15523 case OPC_SHRLV_QB:
15524 check_dsp(ctx);
15525 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
15526 break;
15527 case OPC_SHRL_PH:
15528 check_dspr2(ctx);
15529 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
15530 break;
15531 case OPC_SHRLV_PH:
15532 check_dspr2(ctx);
15533 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
15534 break;
15535 case OPC_SHRA_QB:
15536 check_dspr2(ctx);
15537 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
15538 break;
15539 case OPC_SHRA_R_QB:
15540 check_dspr2(ctx);
15541 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
15542 break;
15543 case OPC_SHRAV_QB:
15544 check_dspr2(ctx);
15545 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
15546 break;
15547 case OPC_SHRAV_R_QB:
15548 check_dspr2(ctx);
15549 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
15550 break;
15551 case OPC_SHRA_PH:
15552 check_dsp(ctx);
15553 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
15554 break;
15555 case OPC_SHRA_R_PH:
15556 check_dsp(ctx);
15557 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
15558 break;
15559 case OPC_SHRAV_PH:
15560 check_dsp(ctx);
15561 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
15562 break;
15563 case OPC_SHRAV_R_PH:
15564 check_dsp(ctx);
15565 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
15566 break;
15567 case OPC_SHRA_R_W:
15568 check_dsp(ctx);
15569 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
15570 break;
15571 case OPC_SHRAV_R_W:
15572 check_dsp(ctx);
15573 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
15574 break;
15575 default: /* Invalid */
15576 MIPS_INVAL("MASK SHLL.QB");
15577 generate_exception(ctx, EXCP_RI);
15578 break;
15579 }
15580 break;
15581 }
15582 #ifdef TARGET_MIPS64
15583 case OPC_SHLL_OB_DSP:
15584 op2 = MASK_SHLL_OB(ctx->opcode);
15585 switch (op2) {
15586 case OPC_SHLL_PW:
15587 check_dsp(ctx);
15588 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
15589 break;
15590 case OPC_SHLLV_PW:
15591 check_dsp(ctx);
15592 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15593 break;
15594 case OPC_SHLL_S_PW:
15595 check_dsp(ctx);
15596 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env);
15597 break;
15598 case OPC_SHLLV_S_PW:
15599 check_dsp(ctx);
15600 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15601 break;
15602 case OPC_SHLL_OB:
15603 check_dsp(ctx);
15604 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env);
15605 break;
15606 case OPC_SHLLV_OB:
15607 check_dsp(ctx);
15608 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15609 break;
15610 case OPC_SHLL_QH:
15611 check_dsp(ctx);
15612 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
15613 break;
15614 case OPC_SHLLV_QH:
15615 check_dsp(ctx);
15616 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15617 break;
15618 case OPC_SHLL_S_QH:
15619 check_dsp(ctx);
15620 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env);
15621 break;
15622 case OPC_SHLLV_S_QH:
15623 check_dsp(ctx);
15624 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
15625 break;
15626 case OPC_SHRA_OB:
15627 check_dspr2(ctx);
15628 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
15629 break;
15630 case OPC_SHRAV_OB:
15631 check_dspr2(ctx);
15632 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
15633 break;
15634 case OPC_SHRA_R_OB:
15635 check_dspr2(ctx);
15636 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
15637 break;
15638 case OPC_SHRAV_R_OB:
15639 check_dspr2(ctx);
15640 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
15641 break;
15642 case OPC_SHRA_PW:
15643 check_dsp(ctx);
15644 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
15645 break;
15646 case OPC_SHRAV_PW:
15647 check_dsp(ctx);
15648 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
15649 break;
15650 case OPC_SHRA_R_PW:
15651 check_dsp(ctx);
15652 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
15653 break;
15654 case OPC_SHRAV_R_PW:
15655 check_dsp(ctx);
15656 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
15657 break;
15658 case OPC_SHRA_QH:
15659 check_dsp(ctx);
15660 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
15661 break;
15662 case OPC_SHRAV_QH:
15663 check_dsp(ctx);
15664 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
15665 break;
15666 case OPC_SHRA_R_QH:
15667 check_dsp(ctx);
15668 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
15669 break;
15670 case OPC_SHRAV_R_QH:
15671 check_dsp(ctx);
15672 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
15673 break;
15674 case OPC_SHRL_OB:
15675 check_dsp(ctx);
15676 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
15677 break;
15678 case OPC_SHRLV_OB:
15679 check_dsp(ctx);
15680 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
15681 break;
15682 case OPC_SHRL_QH:
15683 check_dspr2(ctx);
15684 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
15685 break;
15686 case OPC_SHRLV_QH:
15687 check_dspr2(ctx);
15688 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
15689 break;
15690 default: /* Invalid */
15691 MIPS_INVAL("MASK SHLL.OB");
15692 generate_exception(ctx, EXCP_RI);
15693 break;
15694 }
15695 break;
15696 #endif
15697 }
15698
15699 tcg_temp_free(t0);
15700 tcg_temp_free(v1_t);
15701 tcg_temp_free(v2_t);
15702 }
15703
15704 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
15705 int ret, int v1, int v2, int check_ret)
15706 {
15707 TCGv_i32 t0;
15708 TCGv v1_t;
15709 TCGv v2_t;
15710
15711 if ((ret == 0) && (check_ret == 1)) {
15712 /* Treat as NOP. */
15713 return;
15714 }
15715
15716 t0 = tcg_temp_new_i32();
15717 v1_t = tcg_temp_new();
15718 v2_t = tcg_temp_new();
15719
15720 tcg_gen_movi_i32(t0, ret);
15721 gen_load_gpr(v1_t, v1);
15722 gen_load_gpr(v2_t, v2);
15723
15724 switch (op1) {
15725 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
15726 * the same mask and op1. */
15727 case OPC_MULT_G_2E:
15728 check_dspr2(ctx);
15729 switch (op2) {
15730 case OPC_MUL_PH:
15731 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15732 break;
15733 case OPC_MUL_S_PH:
15734 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15735 break;
15736 case OPC_MULQ_S_W:
15737 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15738 break;
15739 case OPC_MULQ_RS_W:
15740 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15741 break;
15742 }
15743 break;
15744 case OPC_DPA_W_PH_DSP:
15745 switch (op2) {
15746 case OPC_DPAU_H_QBL:
15747 check_dsp(ctx);
15748 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env);
15749 break;
15750 case OPC_DPAU_H_QBR:
15751 check_dsp(ctx);
15752 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env);
15753 break;
15754 case OPC_DPSU_H_QBL:
15755 check_dsp(ctx);
15756 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env);
15757 break;
15758 case OPC_DPSU_H_QBR:
15759 check_dsp(ctx);
15760 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
15761 break;
15762 case OPC_DPA_W_PH:
15763 check_dspr2(ctx);
15764 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
15765 break;
15766 case OPC_DPAX_W_PH:
15767 check_dspr2(ctx);
15768 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
15769 break;
15770 case OPC_DPAQ_S_W_PH:
15771 check_dsp(ctx);
15772 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
15773 break;
15774 case OPC_DPAQX_S_W_PH:
15775 check_dspr2(ctx);
15776 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
15777 break;
15778 case OPC_DPAQX_SA_W_PH:
15779 check_dspr2(ctx);
15780 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
15781 break;
15782 case OPC_DPS_W_PH:
15783 check_dspr2(ctx);
15784 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
15785 break;
15786 case OPC_DPSX_W_PH:
15787 check_dspr2(ctx);
15788 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
15789 break;
15790 case OPC_DPSQ_S_W_PH:
15791 check_dsp(ctx);
15792 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
15793 break;
15794 case OPC_DPSQX_S_W_PH:
15795 check_dspr2(ctx);
15796 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
15797 break;
15798 case OPC_DPSQX_SA_W_PH:
15799 check_dspr2(ctx);
15800 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
15801 break;
15802 case OPC_MULSAQ_S_W_PH:
15803 check_dsp(ctx);
15804 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
15805 break;
15806 case OPC_DPAQ_SA_L_W:
15807 check_dsp(ctx);
15808 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env);
15809 break;
15810 case OPC_DPSQ_SA_L_W:
15811 check_dsp(ctx);
15812 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env);
15813 break;
15814 case OPC_MAQ_S_W_PHL:
15815 check_dsp(ctx);
15816 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env);
15817 break;
15818 case OPC_MAQ_S_W_PHR:
15819 check_dsp(ctx);
15820 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env);
15821 break;
15822 case OPC_MAQ_SA_W_PHL:
15823 check_dsp(ctx);
15824 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env);
15825 break;
15826 case OPC_MAQ_SA_W_PHR:
15827 check_dsp(ctx);
15828 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
15829 break;
15830 case OPC_MULSA_W_PH:
15831 check_dspr2(ctx);
15832 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
15833 break;
15834 }
15835 break;
15836 #ifdef TARGET_MIPS64
15837 case OPC_DPAQ_W_QH_DSP:
15838 {
15839 int ac = ret & 0x03;
15840 tcg_gen_movi_i32(t0, ac);
15841
15842 switch (op2) {
15843 case OPC_DMADD:
15844 check_dsp(ctx);
15845 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env);
15846 break;
15847 case OPC_DMADDU:
15848 check_dsp(ctx);
15849 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env);
15850 break;
15851 case OPC_DMSUB:
15852 check_dsp(ctx);
15853 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env);
15854 break;
15855 case OPC_DMSUBU:
15856 check_dsp(ctx);
15857 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
15858 break;
15859 case OPC_DPA_W_QH:
15860 check_dspr2(ctx);
15861 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
15862 break;
15863 case OPC_DPAQ_S_W_QH:
15864 check_dsp(ctx);
15865 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
15866 break;
15867 case OPC_DPAQ_SA_L_PW:
15868 check_dsp(ctx);
15869 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
15870 break;
15871 case OPC_DPAU_H_OBL:
15872 check_dsp(ctx);
15873 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env);
15874 break;
15875 case OPC_DPAU_H_OBR:
15876 check_dsp(ctx);
15877 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
15878 break;
15879 case OPC_DPS_W_QH:
15880 check_dspr2(ctx);
15881 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
15882 break;
15883 case OPC_DPSQ_S_W_QH:
15884 check_dsp(ctx);
15885 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env);
15886 break;
15887 case OPC_DPSQ_SA_L_PW:
15888 check_dsp(ctx);
15889 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env);
15890 break;
15891 case OPC_DPSU_H_OBL:
15892 check_dsp(ctx);
15893 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env);
15894 break;
15895 case OPC_DPSU_H_OBR:
15896 check_dsp(ctx);
15897 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env);
15898 break;
15899 case OPC_MAQ_S_L_PWL:
15900 check_dsp(ctx);
15901 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env);
15902 break;
15903 case OPC_MAQ_S_L_PWR:
15904 check_dsp(ctx);
15905 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env);
15906 break;
15907 case OPC_MAQ_S_W_QHLL:
15908 check_dsp(ctx);
15909 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env);
15910 break;
15911 case OPC_MAQ_SA_W_QHLL:
15912 check_dsp(ctx);
15913 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env);
15914 break;
15915 case OPC_MAQ_S_W_QHLR:
15916 check_dsp(ctx);
15917 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env);
15918 break;
15919 case OPC_MAQ_SA_W_QHLR:
15920 check_dsp(ctx);
15921 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env);
15922 break;
15923 case OPC_MAQ_S_W_QHRL:
15924 check_dsp(ctx);
15925 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env);
15926 break;
15927 case OPC_MAQ_SA_W_QHRL:
15928 check_dsp(ctx);
15929 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env);
15930 break;
15931 case OPC_MAQ_S_W_QHRR:
15932 check_dsp(ctx);
15933 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env);
15934 break;
15935 case OPC_MAQ_SA_W_QHRR:
15936 check_dsp(ctx);
15937 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env);
15938 break;
15939 case OPC_MULSAQ_S_L_PW:
15940 check_dsp(ctx);
15941 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env);
15942 break;
15943 case OPC_MULSAQ_S_W_QH:
15944 check_dsp(ctx);
15945 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env);
15946 break;
15947 }
15948 }
15949 break;
15950 #endif
15951 case OPC_ADDU_QB_DSP:
15952 switch (op2) {
15953 case OPC_MULEU_S_PH_QBL:
15954 check_dsp(ctx);
15955 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15956 break;
15957 case OPC_MULEU_S_PH_QBR:
15958 check_dsp(ctx);
15959 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15960 break;
15961 case OPC_MULQ_RS_PH:
15962 check_dsp(ctx);
15963 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15964 break;
15965 case OPC_MULEQ_S_W_PHL:
15966 check_dsp(ctx);
15967 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15968 break;
15969 case OPC_MULEQ_S_W_PHR:
15970 check_dsp(ctx);
15971 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15972 break;
15973 case OPC_MULQ_S_PH:
15974 check_dspr2(ctx);
15975 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15976 break;
15977 }
15978 break;
15979 #ifdef TARGET_MIPS64
15980 case OPC_ADDU_OB_DSP:
15981 switch (op2) {
15982 case OPC_MULEQ_S_PW_QHL:
15983 check_dsp(ctx);
15984 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15985 break;
15986 case OPC_MULEQ_S_PW_QHR:
15987 check_dsp(ctx);
15988 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15989 break;
15990 case OPC_MULEU_S_QH_OBL:
15991 check_dsp(ctx);
15992 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15993 break;
15994 case OPC_MULEU_S_QH_OBR:
15995 check_dsp(ctx);
15996 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
15997 break;
15998 case OPC_MULQ_RS_QH:
15999 check_dsp(ctx);
16000 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16001 break;
16002 }
16003 break;
16004 #endif
16005 }
16006
16007 tcg_temp_free_i32(t0);
16008 tcg_temp_free(v1_t);
16009 tcg_temp_free(v2_t);
16010 }
16011
16012 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
16013 int ret, int val)
16014 {
16015 int16_t imm;
16016 TCGv t0;
16017 TCGv val_t;
16018
16019 if (ret == 0) {
16020 /* Treat as NOP. */
16021 return;
16022 }
16023
16024 t0 = tcg_temp_new();
16025 val_t = tcg_temp_new();
16026 gen_load_gpr(val_t, val);
16027
16028 switch (op1) {
16029 case OPC_ABSQ_S_PH_DSP:
16030 switch (op2) {
16031 case OPC_BITREV:
16032 check_dsp(ctx);
16033 gen_helper_bitrev(cpu_gpr[ret], val_t);
16034 break;
16035 case OPC_REPL_QB:
16036 check_dsp(ctx);
16037 {
16038 target_long result;
16039 imm = (ctx->opcode >> 16) & 0xFF;
16040 result = (uint32_t)imm << 24 |
16041 (uint32_t)imm << 16 |
16042 (uint32_t)imm << 8 |
16043 (uint32_t)imm;
16044 result = (int32_t)result;
16045 tcg_gen_movi_tl(cpu_gpr[ret], result);
16046 }
16047 break;
16048 case OPC_REPLV_QB:
16049 check_dsp(ctx);
16050 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
16051 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
16052 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16053 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16054 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16055 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
16056 break;
16057 case OPC_REPL_PH:
16058 check_dsp(ctx);
16059 {
16060 imm = (ctx->opcode >> 16) & 0x03FF;
16061 imm = (int16_t)(imm << 6) >> 6;
16062 tcg_gen_movi_tl(cpu_gpr[ret], \
16063 (target_long)((int32_t)imm << 16 | \
16064 (uint16_t)imm));
16065 }
16066 break;
16067 case OPC_REPLV_PH:
16068 check_dsp(ctx);
16069 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
16070 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16071 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16072 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
16073 break;
16074 }
16075 break;
16076 #ifdef TARGET_MIPS64
16077 case OPC_ABSQ_S_QH_DSP:
16078 switch (op2) {
16079 case OPC_REPL_OB:
16080 check_dsp(ctx);
16081 {
16082 target_long temp;
16083
16084 imm = (ctx->opcode >> 16) & 0xFF;
16085 temp = ((uint64_t)imm << 8) | (uint64_t)imm;
16086 temp = (temp << 16) | temp;
16087 temp = (temp << 32) | temp;
16088 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16089 break;
16090 }
16091 case OPC_REPL_PW:
16092 check_dsp(ctx);
16093 {
16094 target_long temp;
16095
16096 imm = (ctx->opcode >> 16) & 0x03FF;
16097 imm = (int16_t)(imm << 6) >> 6;
16098 temp = ((target_long)imm << 32) \
16099 | ((target_long)imm & 0xFFFFFFFF);
16100 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16101 break;
16102 }
16103 case OPC_REPL_QH:
16104 check_dsp(ctx);
16105 {
16106 target_long temp;
16107
16108 imm = (ctx->opcode >> 16) & 0x03FF;
16109 imm = (int16_t)(imm << 6) >> 6;
16110
16111 temp = ((uint64_t)(uint16_t)imm << 48) |
16112 ((uint64_t)(uint16_t)imm << 32) |
16113 ((uint64_t)(uint16_t)imm << 16) |
16114 (uint64_t)(uint16_t)imm;
16115 tcg_gen_movi_tl(cpu_gpr[ret], temp);
16116 break;
16117 }
16118 case OPC_REPLV_OB:
16119 check_dsp(ctx);
16120 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
16121 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
16122 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16123 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16124 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16125 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16126 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16127 break;
16128 case OPC_REPLV_PW:
16129 check_dsp(ctx);
16130 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
16131 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16132 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16133 break;
16134 case OPC_REPLV_QH:
16135 check_dsp(ctx);
16136 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
16137 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
16138 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16139 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
16140 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
16141 break;
16142 }
16143 break;
16144 #endif
16145 }
16146 tcg_temp_free(t0);
16147 tcg_temp_free(val_t);
16148 }
16149
16150 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
16151 uint32_t op1, uint32_t op2,
16152 int ret, int v1, int v2, int check_ret)
16153 {
16154 TCGv t1;
16155 TCGv v1_t;
16156 TCGv v2_t;
16157
16158 if ((ret == 0) && (check_ret == 1)) {
16159 /* Treat as NOP. */
16160 return;
16161 }
16162
16163 t1 = tcg_temp_new();
16164 v1_t = tcg_temp_new();
16165 v2_t = tcg_temp_new();
16166
16167 gen_load_gpr(v1_t, v1);
16168 gen_load_gpr(v2_t, v2);
16169
16170 switch (op1) {
16171 case OPC_CMPU_EQ_QB_DSP:
16172 switch (op2) {
16173 case OPC_CMPU_EQ_QB:
16174 check_dsp(ctx);
16175 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env);
16176 break;
16177 case OPC_CMPU_LT_QB:
16178 check_dsp(ctx);
16179 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env);
16180 break;
16181 case OPC_CMPU_LE_QB:
16182 check_dsp(ctx);
16183 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env);
16184 break;
16185 case OPC_CMPGU_EQ_QB:
16186 check_dsp(ctx);
16187 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
16188 break;
16189 case OPC_CMPGU_LT_QB:
16190 check_dsp(ctx);
16191 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
16192 break;
16193 case OPC_CMPGU_LE_QB:
16194 check_dsp(ctx);
16195 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
16196 break;
16197 case OPC_CMPGDU_EQ_QB:
16198 check_dspr2(ctx);
16199 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
16200 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16201 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16202 tcg_gen_shli_tl(t1, t1, 24);
16203 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16204 break;
16205 case OPC_CMPGDU_LT_QB:
16206 check_dspr2(ctx);
16207 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
16208 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16209 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16210 tcg_gen_shli_tl(t1, t1, 24);
16211 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16212 break;
16213 case OPC_CMPGDU_LE_QB:
16214 check_dspr2(ctx);
16215 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
16216 tcg_gen_mov_tl(cpu_gpr[ret], t1);
16217 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
16218 tcg_gen_shli_tl(t1, t1, 24);
16219 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
16220 break;
16221 case OPC_CMP_EQ_PH:
16222 check_dsp(ctx);
16223 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env);
16224 break;
16225 case OPC_CMP_LT_PH:
16226 check_dsp(ctx);
16227 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env);
16228 break;
16229 case OPC_CMP_LE_PH:
16230 check_dsp(ctx);
16231 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env);
16232 break;
16233 case OPC_PICK_QB:
16234 check_dsp(ctx);
16235 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16236 break;
16237 case OPC_PICK_PH:
16238 check_dsp(ctx);
16239 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16240 break;
16241 case OPC_PACKRL_PH:
16242 check_dsp(ctx);
16243 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
16244 break;
16245 }
16246 break;
16247 #ifdef TARGET_MIPS64
16248 case OPC_CMPU_EQ_OB_DSP:
16249 switch (op2) {
16250 case OPC_CMP_EQ_PW:
16251 check_dsp(ctx);
16252 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env);
16253 break;
16254 case OPC_CMP_LT_PW:
16255 check_dsp(ctx);
16256 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env);
16257 break;
16258 case OPC_CMP_LE_PW:
16259 check_dsp(ctx);
16260 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env);
16261 break;
16262 case OPC_CMP_EQ_QH:
16263 check_dsp(ctx);
16264 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env);
16265 break;
16266 case OPC_CMP_LT_QH:
16267 check_dsp(ctx);
16268 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env);
16269 break;
16270 case OPC_CMP_LE_QH:
16271 check_dsp(ctx);
16272 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
16273 break;
16274 case OPC_CMPGDU_EQ_OB:
16275 check_dspr2(ctx);
16276 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16277 break;
16278 case OPC_CMPGDU_LT_OB:
16279 check_dspr2(ctx);
16280 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16281 break;
16282 case OPC_CMPGDU_LE_OB:
16283 check_dspr2(ctx);
16284 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16285 break;
16286 case OPC_CMPGU_EQ_OB:
16287 check_dsp(ctx);
16288 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t);
16289 break;
16290 case OPC_CMPGU_LT_OB:
16291 check_dsp(ctx);
16292 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t);
16293 break;
16294 case OPC_CMPGU_LE_OB:
16295 check_dsp(ctx);
16296 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t);
16297 break;
16298 case OPC_CMPU_EQ_OB:
16299 check_dsp(ctx);
16300 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env);
16301 break;
16302 case OPC_CMPU_LT_OB:
16303 check_dsp(ctx);
16304 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env);
16305 break;
16306 case OPC_CMPU_LE_OB:
16307 check_dsp(ctx);
16308 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env);
16309 break;
16310 case OPC_PACKRL_PW:
16311 check_dsp(ctx);
16312 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t);
16313 break;
16314 case OPC_PICK_OB:
16315 check_dsp(ctx);
16316 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16317 break;
16318 case OPC_PICK_PW:
16319 check_dsp(ctx);
16320 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16321 break;
16322 case OPC_PICK_QH:
16323 check_dsp(ctx);
16324 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
16325 break;
16326 }
16327 break;
16328 #endif
16329 }
16330
16331 tcg_temp_free(t1);
16332 tcg_temp_free(v1_t);
16333 tcg_temp_free(v2_t);
16334 }
16335
16336 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
16337 uint32_t op1, int rt, int rs, int sa)
16338 {
16339 TCGv t0;
16340
16341 check_dspr2(ctx);
16342
16343 if (rt == 0) {
16344 /* Treat as NOP. */
16345 return;
16346 }
16347
16348 t0 = tcg_temp_new();
16349 gen_load_gpr(t0, rs);
16350
16351 switch (op1) {
16352 case OPC_APPEND_DSP:
16353 switch (MASK_APPEND(ctx->opcode)) {
16354 case OPC_APPEND:
16355 if (sa != 0) {
16356 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa);
16357 }
16358 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16359 break;
16360 case OPC_PREPEND:
16361 if (sa != 0) {
16362 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]);
16363 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
16364 tcg_gen_shli_tl(t0, t0, 32 - sa);
16365 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16366 }
16367 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16368 break;
16369 case OPC_BALIGN:
16370 sa &= 3;
16371 if (sa != 0 && sa != 2) {
16372 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
16373 tcg_gen_ext32u_tl(t0, t0);
16374 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa));
16375 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16376 }
16377 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
16378 break;
16379 default: /* Invalid */
16380 MIPS_INVAL("MASK APPEND");
16381 generate_exception(ctx, EXCP_RI);
16382 break;
16383 }
16384 break;
16385 #ifdef TARGET_MIPS64
16386 case OPC_DAPPEND_DSP:
16387 switch (MASK_DAPPEND(ctx->opcode)) {
16388 case OPC_DAPPEND:
16389 if (sa != 0) {
16390 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa);
16391 }
16392 break;
16393 case OPC_PREPENDD:
16394 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa);
16395 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa));
16396 tcg_gen_or_tl(cpu_gpr[rt], t0, t0);
16397 break;
16398 case OPC_PREPENDW:
16399 if (sa != 0) {
16400 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
16401 tcg_gen_shli_tl(t0, t0, 64 - sa);
16402 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16403 }
16404 break;
16405 case OPC_DBALIGN:
16406 sa &= 7;
16407 if (sa != 0 && sa != 2 && sa != 4) {
16408 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
16409 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
16410 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
16411 }
16412 break;
16413 default: /* Invalid */
16414 MIPS_INVAL("MASK DAPPEND");
16415 generate_exception(ctx, EXCP_RI);
16416 break;
16417 }
16418 break;
16419 #endif
16420 }
16421 tcg_temp_free(t0);
16422 }
16423
16424 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
16425 int ret, int v1, int v2, int check_ret)
16426
16427 {
16428 TCGv t0;
16429 TCGv t1;
16430 TCGv v1_t;
16431 TCGv v2_t;
16432 int16_t imm;
16433
16434 if ((ret == 0) && (check_ret == 1)) {
16435 /* Treat as NOP. */
16436 return;
16437 }
16438
16439 t0 = tcg_temp_new();
16440 t1 = tcg_temp_new();
16441 v1_t = tcg_temp_new();
16442 v2_t = tcg_temp_new();
16443
16444 gen_load_gpr(v1_t, v1);
16445 gen_load_gpr(v2_t, v2);
16446
16447 switch (op1) {
16448 case OPC_EXTR_W_DSP:
16449 check_dsp(ctx);
16450 switch (op2) {
16451 case OPC_EXTR_W:
16452 tcg_gen_movi_tl(t0, v2);
16453 tcg_gen_movi_tl(t1, v1);
16454 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env);
16455 break;
16456 case OPC_EXTR_R_W:
16457 tcg_gen_movi_tl(t0, v2);
16458 tcg_gen_movi_tl(t1, v1);
16459 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
16460 break;
16461 case OPC_EXTR_RS_W:
16462 tcg_gen_movi_tl(t0, v2);
16463 tcg_gen_movi_tl(t1, v1);
16464 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
16465 break;
16466 case OPC_EXTR_S_H:
16467 tcg_gen_movi_tl(t0, v2);
16468 tcg_gen_movi_tl(t1, v1);
16469 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16470 break;
16471 case OPC_EXTRV_S_H:
16472 tcg_gen_movi_tl(t0, v2);
16473 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
16474 break;
16475 case OPC_EXTRV_W:
16476 tcg_gen_movi_tl(t0, v2);
16477 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16478 break;
16479 case OPC_EXTRV_R_W:
16480 tcg_gen_movi_tl(t0, v2);
16481 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16482 break;
16483 case OPC_EXTRV_RS_W:
16484 tcg_gen_movi_tl(t0, v2);
16485 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16486 break;
16487 case OPC_EXTP:
16488 tcg_gen_movi_tl(t0, v2);
16489 tcg_gen_movi_tl(t1, v1);
16490 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env);
16491 break;
16492 case OPC_EXTPV:
16493 tcg_gen_movi_tl(t0, v2);
16494 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env);
16495 break;
16496 case OPC_EXTPDP:
16497 tcg_gen_movi_tl(t0, v2);
16498 tcg_gen_movi_tl(t1, v1);
16499 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env);
16500 break;
16501 case OPC_EXTPDPV:
16502 tcg_gen_movi_tl(t0, v2);
16503 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
16504 break;
16505 case OPC_SHILO:
16506 imm = (ctx->opcode >> 20) & 0x3F;
16507 tcg_gen_movi_tl(t0, ret);
16508 tcg_gen_movi_tl(t1, imm);
16509 gen_helper_shilo(t0, t1, cpu_env);
16510 break;
16511 case OPC_SHILOV:
16512 tcg_gen_movi_tl(t0, ret);
16513 gen_helper_shilo(t0, v1_t, cpu_env);
16514 break;
16515 case OPC_MTHLIP:
16516 tcg_gen_movi_tl(t0, ret);
16517 gen_helper_mthlip(t0, v1_t, cpu_env);
16518 break;
16519 case OPC_WRDSP:
16520 imm = (ctx->opcode >> 11) & 0x3FF;
16521 tcg_gen_movi_tl(t0, imm);
16522 gen_helper_wrdsp(v1_t, t0, cpu_env);
16523 break;
16524 case OPC_RDDSP:
16525 imm = (ctx->opcode >> 16) & 0x03FF;
16526 tcg_gen_movi_tl(t0, imm);
16527 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
16528 break;
16529 }
16530 break;
16531 #ifdef TARGET_MIPS64
16532 case OPC_DEXTR_W_DSP:
16533 check_dsp(ctx);
16534 switch (op2) {
16535 case OPC_DMTHLIP:
16536 tcg_gen_movi_tl(t0, ret);
16537 gen_helper_dmthlip(v1_t, t0, cpu_env);
16538 break;
16539 case OPC_DSHILO:
16540 {
16541 int shift = (ctx->opcode >> 19) & 0x7F;
16542 int ac = (ctx->opcode >> 11) & 0x03;
16543 tcg_gen_movi_tl(t0, shift);
16544 tcg_gen_movi_tl(t1, ac);
16545 gen_helper_dshilo(t0, t1, cpu_env);
16546 break;
16547 }
16548 case OPC_DSHILOV:
16549 {
16550 int ac = (ctx->opcode >> 11) & 0x03;
16551 tcg_gen_movi_tl(t0, ac);
16552 gen_helper_dshilo(v1_t, t0, cpu_env);
16553 break;
16554 }
16555 case OPC_DEXTP:
16556 tcg_gen_movi_tl(t0, v2);
16557 tcg_gen_movi_tl(t1, v1);
16558
16559 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env);
16560 break;
16561 case OPC_DEXTPV:
16562 tcg_gen_movi_tl(t0, v2);
16563 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env);
16564 break;
16565 case OPC_DEXTPDP:
16566 tcg_gen_movi_tl(t0, v2);
16567 tcg_gen_movi_tl(t1, v1);
16568 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env);
16569 break;
16570 case OPC_DEXTPDPV:
16571 tcg_gen_movi_tl(t0, v2);
16572 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env);
16573 break;
16574 case OPC_DEXTR_L:
16575 tcg_gen_movi_tl(t0, v2);
16576 tcg_gen_movi_tl(t1, v1);
16577 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env);
16578 break;
16579 case OPC_DEXTR_R_L:
16580 tcg_gen_movi_tl(t0, v2);
16581 tcg_gen_movi_tl(t1, v1);
16582 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env);
16583 break;
16584 case OPC_DEXTR_RS_L:
16585 tcg_gen_movi_tl(t0, v2);
16586 tcg_gen_movi_tl(t1, v1);
16587 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env);
16588 break;
16589 case OPC_DEXTR_W:
16590 tcg_gen_movi_tl(t0, v2);
16591 tcg_gen_movi_tl(t1, v1);
16592 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env);
16593 break;
16594 case OPC_DEXTR_R_W:
16595 tcg_gen_movi_tl(t0, v2);
16596 tcg_gen_movi_tl(t1, v1);
16597 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env);
16598 break;
16599 case OPC_DEXTR_RS_W:
16600 tcg_gen_movi_tl(t0, v2);
16601 tcg_gen_movi_tl(t1, v1);
16602 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env);
16603 break;
16604 case OPC_DEXTR_S_H:
16605 tcg_gen_movi_tl(t0, v2);
16606 tcg_gen_movi_tl(t1, v1);
16607 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16608 break;
16609 case OPC_DEXTRV_S_H:
16610 tcg_gen_movi_tl(t0, v2);
16611 tcg_gen_movi_tl(t1, v1);
16612 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
16613 break;
16614 case OPC_DEXTRV_L:
16615 tcg_gen_movi_tl(t0, v2);
16616 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16617 break;
16618 case OPC_DEXTRV_R_L:
16619 tcg_gen_movi_tl(t0, v2);
16620 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16621 break;
16622 case OPC_DEXTRV_RS_L:
16623 tcg_gen_movi_tl(t0, v2);
16624 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env);
16625 break;
16626 case OPC_DEXTRV_W:
16627 tcg_gen_movi_tl(t0, v2);
16628 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16629 break;
16630 case OPC_DEXTRV_R_W:
16631 tcg_gen_movi_tl(t0, v2);
16632 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16633 break;
16634 case OPC_DEXTRV_RS_W:
16635 tcg_gen_movi_tl(t0, v2);
16636 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env);
16637 break;
16638 }
16639 break;
16640 #endif
16641 }
16642
16643 tcg_temp_free(t0);
16644 tcg_temp_free(t1);
16645 tcg_temp_free(v1_t);
16646 tcg_temp_free(v2_t);
16647 }
16648
16649 /* End MIPSDSP functions. */
16650
16651 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
16652 {
16653 int rs, rt, rd, sa;
16654 uint32_t op1, op2;
16655
16656 rs = (ctx->opcode >> 21) & 0x1f;
16657 rt = (ctx->opcode >> 16) & 0x1f;
16658 rd = (ctx->opcode >> 11) & 0x1f;
16659 sa = (ctx->opcode >> 6) & 0x1f;
16660
16661 op1 = MASK_SPECIAL(ctx->opcode);
16662 switch (op1) {
16663 case OPC_LSA:
16664 gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
16665 break;
16666 case OPC_MULT ... OPC_DIVU:
16667 op2 = MASK_R6_MULDIV(ctx->opcode);
16668 switch (op2) {
16669 case R6_OPC_MUL:
16670 case R6_OPC_MUH:
16671 case R6_OPC_MULU:
16672 case R6_OPC_MUHU:
16673 case R6_OPC_DIV:
16674 case R6_OPC_MOD:
16675 case R6_OPC_DIVU:
16676 case R6_OPC_MODU:
16677 gen_r6_muldiv(ctx, op2, rd, rs, rt);
16678 break;
16679 default:
16680 MIPS_INVAL("special_r6 muldiv");
16681 generate_exception(ctx, EXCP_RI);
16682 break;
16683 }
16684 break;
16685 case OPC_SELEQZ:
16686 case OPC_SELNEZ:
16687 gen_cond_move(ctx, op1, rd, rs, rt);
16688 break;
16689 case R6_OPC_CLO:
16690 case R6_OPC_CLZ:
16691 if (rt == 0 && sa == 1) {
16692 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
16693 We need additionally to check other fields */
16694 gen_cl(ctx, op1, rd, rs);
16695 } else {
16696 generate_exception(ctx, EXCP_RI);
16697 }
16698 break;
16699 case R6_OPC_SDBBP:
16700 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
16701 gen_helper_do_semihosting(cpu_env);
16702 } else {
16703 if (ctx->hflags & MIPS_HFLAG_SBRI) {
16704 generate_exception(ctx, EXCP_RI);
16705 } else {
16706 generate_exception(ctx, EXCP_DBp);
16707 }
16708 }
16709 break;
16710 #if defined(TARGET_MIPS64)
16711 case OPC_DLSA:
16712 check_mips_64(ctx);
16713 gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
16714 break;
16715 case R6_OPC_DCLO:
16716 case R6_OPC_DCLZ:
16717 if (rt == 0 && sa == 1) {
16718 /* Major opcode and function field is shared with preR6 MFHI/MTHI.
16719 We need additionally to check other fields */
16720 check_mips_64(ctx);
16721 gen_cl(ctx, op1, rd, rs);
16722 } else {
16723 generate_exception(ctx, EXCP_RI);
16724 }
16725 break;
16726 case OPC_DMULT ... OPC_DDIVU:
16727 op2 = MASK_R6_MULDIV(ctx->opcode);
16728 switch (op2) {
16729 case R6_OPC_DMUL:
16730 case R6_OPC_DMUH:
16731 case R6_OPC_DMULU:
16732 case R6_OPC_DMUHU:
16733 case R6_OPC_DDIV:
16734 case R6_OPC_DMOD:
16735 case R6_OPC_DDIVU:
16736 case R6_OPC_DMODU:
16737 check_mips_64(ctx);
16738 gen_r6_muldiv(ctx, op2, rd, rs, rt);
16739 break;
16740 default:
16741 MIPS_INVAL("special_r6 muldiv");
16742 generate_exception(ctx, EXCP_RI);
16743 break;
16744 }
16745 break;
16746 #endif
16747 default: /* Invalid */
16748 MIPS_INVAL("special_r6");
16749 generate_exception(ctx, EXCP_RI);
16750 break;
16751 }
16752 }
16753
16754 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
16755 {
16756 int rs, rt, rd, sa;
16757 uint32_t op1;
16758
16759 rs = (ctx->opcode >> 21) & 0x1f;
16760 rt = (ctx->opcode >> 16) & 0x1f;
16761 rd = (ctx->opcode >> 11) & 0x1f;
16762 sa = (ctx->opcode >> 6) & 0x1f;
16763
16764 op1 = MASK_SPECIAL(ctx->opcode);
16765 switch (op1) {
16766 case OPC_MOVN: /* Conditional move */
16767 case OPC_MOVZ:
16768 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
16769 INSN_LOONGSON2E | INSN_LOONGSON2F);
16770 gen_cond_move(ctx, op1, rd, rs, rt);
16771 break;
16772 case OPC_MFHI: /* Move from HI/LO */
16773 case OPC_MFLO:
16774 gen_HILO(ctx, op1, rs & 3, rd);
16775 break;
16776 case OPC_MTHI:
16777 case OPC_MTLO: /* Move to HI/LO */
16778 gen_HILO(ctx, op1, rd & 3, rs);
16779 break;
16780 case OPC_MOVCI:
16781 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
16782 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
16783 check_cp1_enabled(ctx);
16784 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
16785 (ctx->opcode >> 16) & 1);
16786 } else {
16787 generate_exception_err(ctx, EXCP_CpU, 1);
16788 }
16789 break;
16790 case OPC_MULT:
16791 case OPC_MULTU:
16792 if (sa) {
16793 check_insn(ctx, INSN_VR54XX);
16794 op1 = MASK_MUL_VR54XX(ctx->opcode);
16795 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
16796 } else {
16797 gen_muldiv(ctx, op1, rd & 3, rs, rt);
16798 }
16799 break;
16800 case OPC_DIV:
16801 case OPC_DIVU:
16802 gen_muldiv(ctx, op1, 0, rs, rt);
16803 break;
16804 #if defined(TARGET_MIPS64)
16805 case OPC_DMULT ... OPC_DDIVU:
16806 check_insn(ctx, ISA_MIPS3);
16807 check_mips_64(ctx);
16808 gen_muldiv(ctx, op1, 0, rs, rt);
16809 break;
16810 #endif
16811 case OPC_JR:
16812 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
16813 break;
16814 case OPC_SPIM:
16815 #ifdef MIPS_STRICT_STANDARD
16816 MIPS_INVAL("SPIM");
16817 generate_exception(ctx, EXCP_RI);
16818 #else
16819 /* Implemented as RI exception for now. */
16820 MIPS_INVAL("spim (unofficial)");
16821 generate_exception(ctx, EXCP_RI);
16822 #endif
16823 break;
16824 default: /* Invalid */
16825 MIPS_INVAL("special_legacy");
16826 generate_exception(ctx, EXCP_RI);
16827 break;
16828 }
16829 }
16830
16831 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
16832 {
16833 int rs, rt, rd, sa;
16834 uint32_t op1;
16835
16836 rs = (ctx->opcode >> 21) & 0x1f;
16837 rt = (ctx->opcode >> 16) & 0x1f;
16838 rd = (ctx->opcode >> 11) & 0x1f;
16839 sa = (ctx->opcode >> 6) & 0x1f;
16840
16841 op1 = MASK_SPECIAL(ctx->opcode);
16842 switch (op1) {
16843 case OPC_SLL: /* Shift with immediate */
16844 if (sa == 5 && rd == 0 &&
16845 rs == 0 && rt == 0) { /* PAUSE */
16846 if ((ctx->insn_flags & ISA_MIPS32R6) &&
16847 (ctx->hflags & MIPS_HFLAG_BMASK)) {
16848 generate_exception(ctx, EXCP_RI);
16849 break;
16850 }
16851 }
16852 /* Fallthrough */
16853 case OPC_SRA:
16854 gen_shift_imm(ctx, op1, rd, rt, sa);
16855 break;
16856 case OPC_SRL:
16857 switch ((ctx->opcode >> 21) & 0x1f) {
16858 case 1:
16859 /* rotr is decoded as srl on non-R2 CPUs */
16860 if (ctx->insn_flags & ISA_MIPS32R2) {
16861 op1 = OPC_ROTR;
16862 }
16863 /* Fallthrough */
16864 case 0:
16865 gen_shift_imm(ctx, op1, rd, rt, sa);
16866 break;
16867 default:
16868 generate_exception(ctx, EXCP_RI);
16869 break;
16870 }
16871 break;
16872 case OPC_ADD ... OPC_SUBU:
16873 gen_arith(ctx, op1, rd, rs, rt);
16874 break;
16875 case OPC_SLLV: /* Shifts */
16876 case OPC_SRAV:
16877 gen_shift(ctx, op1, rd, rs, rt);
16878 break;
16879 case OPC_SRLV:
16880 switch ((ctx->opcode >> 6) & 0x1f) {
16881 case 1:
16882 /* rotrv is decoded as srlv on non-R2 CPUs */
16883 if (ctx->insn_flags & ISA_MIPS32R2) {
16884 op1 = OPC_ROTRV;
16885 }
16886 /* Fallthrough */
16887 case 0:
16888 gen_shift(ctx, op1, rd, rs, rt);
16889 break;
16890 default:
16891 generate_exception(ctx, EXCP_RI);
16892 break;
16893 }
16894 break;
16895 case OPC_SLT: /* Set on less than */
16896 case OPC_SLTU:
16897 gen_slt(ctx, op1, rd, rs, rt);
16898 break;
16899 case OPC_AND: /* Logic*/
16900 case OPC_OR:
16901 case OPC_NOR:
16902 case OPC_XOR:
16903 gen_logic(ctx, op1, rd, rs, rt);
16904 break;
16905 case OPC_JALR:
16906 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
16907 break;
16908 case OPC_TGE ... OPC_TEQ: /* Traps */
16909 case OPC_TNE:
16910 check_insn(ctx, ISA_MIPS2);
16911 gen_trap(ctx, op1, rs, rt, -1);
16912 break;
16913 case OPC_LSA: /* OPC_PMON */
16914 if ((ctx->insn_flags & ISA_MIPS32R6) ||
16915 (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
16916 decode_opc_special_r6(env, ctx);
16917 } else {
16918 /* Pmon entry point, also R4010 selsl */
16919 #ifdef MIPS_STRICT_STANDARD
16920 MIPS_INVAL("PMON / selsl");
16921 generate_exception(ctx, EXCP_RI);
16922 #else
16923 gen_helper_0e0i(pmon, sa);
16924 #endif
16925 }
16926 break;
16927 case OPC_SYSCALL:
16928 generate_exception(ctx, EXCP_SYSCALL);
16929 ctx->bstate = BS_STOP;
16930 break;
16931 case OPC_BREAK:
16932 generate_exception(ctx, EXCP_BREAK);
16933 break;
16934 case OPC_SYNC:
16935 check_insn(ctx, ISA_MIPS2);
16936 /* Treat as NOP. */
16937 break;
16938
16939 #if defined(TARGET_MIPS64)
16940 /* MIPS64 specific opcodes */
16941 case OPC_DSLL:
16942 case OPC_DSRA:
16943 case OPC_DSLL32:
16944 case OPC_DSRA32:
16945 check_insn(ctx, ISA_MIPS3);
16946 check_mips_64(ctx);
16947 gen_shift_imm(ctx, op1, rd, rt, sa);
16948 break;
16949 case OPC_DSRL:
16950 switch ((ctx->opcode >> 21) & 0x1f) {
16951 case 1:
16952 /* drotr is decoded as dsrl on non-R2 CPUs */
16953 if (ctx->insn_flags & ISA_MIPS32R2) {
16954 op1 = OPC_DROTR;
16955 }
16956 /* Fallthrough */
16957 case 0:
16958 check_insn(ctx, ISA_MIPS3);
16959 check_mips_64(ctx);
16960 gen_shift_imm(ctx, op1, rd, rt, sa);
16961 break;
16962 default:
16963 generate_exception(ctx, EXCP_RI);
16964 break;
16965 }
16966 break;
16967 case OPC_DSRL32:
16968 switch ((ctx->opcode >> 21) & 0x1f) {
16969 case 1:
16970 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
16971 if (ctx->insn_flags & ISA_MIPS32R2) {
16972 op1 = OPC_DROTR32;
16973 }
16974 /* Fallthrough */
16975 case 0:
16976 check_insn(ctx, ISA_MIPS3);
16977 check_mips_64(ctx);
16978 gen_shift_imm(ctx, op1, rd, rt, sa);
16979 break;
16980 default:
16981 generate_exception(ctx, EXCP_RI);
16982 break;
16983 }
16984 break;
16985 case OPC_DADD ... OPC_DSUBU:
16986 check_insn(ctx, ISA_MIPS3);
16987 check_mips_64(ctx);
16988 gen_arith(ctx, op1, rd, rs, rt);
16989 break;
16990 case OPC_DSLLV:
16991 case OPC_DSRAV:
16992 check_insn(ctx, ISA_MIPS3);
16993 check_mips_64(ctx);
16994 gen_shift(ctx, op1, rd, rs, rt);
16995 break;
16996 case OPC_DSRLV:
16997 switch ((ctx->opcode >> 6) & 0x1f) {
16998 case 1:
16999 /* drotrv is decoded as dsrlv on non-R2 CPUs */
17000 if (ctx->insn_flags & ISA_MIPS32R2) {
17001 op1 = OPC_DROTRV;
17002 }
17003 /* Fallthrough */
17004 case 0:
17005 check_insn(ctx, ISA_MIPS3);
17006 check_mips_64(ctx);
17007 gen_shift(ctx, op1, rd, rs, rt);
17008 break;
17009 default:
17010 generate_exception(ctx, EXCP_RI);
17011 break;
17012 }
17013 break;
17014 case OPC_DLSA:
17015 if ((ctx->insn_flags & ISA_MIPS32R6) ||
17016 (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
17017 decode_opc_special_r6(env, ctx);
17018 }
17019 break;
17020 #endif
17021 default:
17022 if (ctx->insn_flags & ISA_MIPS32R6) {
17023 decode_opc_special_r6(env, ctx);
17024 } else {
17025 decode_opc_special_legacy(env, ctx);
17026 }
17027 }
17028 }
17029
17030 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
17031 {
17032 int rs, rt, rd;
17033 uint32_t op1;
17034
17035 check_insn_opc_removed(ctx, ISA_MIPS32R6);
17036
17037 rs = (ctx->opcode >> 21) & 0x1f;
17038 rt = (ctx->opcode >> 16) & 0x1f;
17039 rd = (ctx->opcode >> 11) & 0x1f;
17040
17041 op1 = MASK_SPECIAL2(ctx->opcode);
17042 switch (op1) {
17043 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
17044 case OPC_MSUB ... OPC_MSUBU:
17045 check_insn(ctx, ISA_MIPS32);
17046 gen_muldiv(ctx, op1, rd & 3, rs, rt);
17047 break;
17048 case OPC_MUL:
17049 gen_arith(ctx, op1, rd, rs, rt);
17050 break;
17051 case OPC_DIV_G_2F:
17052 case OPC_DIVU_G_2F:
17053 case OPC_MULT_G_2F:
17054 case OPC_MULTU_G_2F:
17055 case OPC_MOD_G_2F:
17056 case OPC_MODU_G_2F:
17057 check_insn(ctx, INSN_LOONGSON2F);
17058 gen_loongson_integer(ctx, op1, rd, rs, rt);
17059 break;
17060 case OPC_CLO:
17061 case OPC_CLZ:
17062 check_insn(ctx, ISA_MIPS32);
17063 gen_cl(ctx, op1, rd, rs);
17064 break;
17065 case OPC_SDBBP:
17066 if (is_uhi(extract32(ctx->opcode, 6, 20))) {
17067 gen_helper_do_semihosting(cpu_env);
17068 } else {
17069 /* XXX: not clear which exception should be raised
17070 * when in debug mode...
17071 */
17072 check_insn(ctx, ISA_MIPS32);
17073 generate_exception(ctx, EXCP_DBp);
17074 }
17075 break;
17076 #if defined(TARGET_MIPS64)
17077 case OPC_DCLO:
17078 case OPC_DCLZ:
17079 check_insn(ctx, ISA_MIPS64);
17080 check_mips_64(ctx);
17081 gen_cl(ctx, op1, rd, rs);
17082 break;
17083 case OPC_DMULT_G_2F:
17084 case OPC_DMULTU_G_2F:
17085 case OPC_DDIV_G_2F:
17086 case OPC_DDIVU_G_2F:
17087 case OPC_DMOD_G_2F:
17088 case OPC_DMODU_G_2F:
17089 check_insn(ctx, INSN_LOONGSON2F);
17090 gen_loongson_integer(ctx, op1, rd, rs, rt);
17091 break;
17092 #endif
17093 default: /* Invalid */
17094 MIPS_INVAL("special2_legacy");
17095 generate_exception(ctx, EXCP_RI);
17096 break;
17097 }
17098 }
17099
17100 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
17101 {
17102 int rs, rt, rd, sa;
17103 uint32_t op1, op2;
17104 int16_t imm;
17105
17106 rs = (ctx->opcode >> 21) & 0x1f;
17107 rt = (ctx->opcode >> 16) & 0x1f;
17108 rd = (ctx->opcode >> 11) & 0x1f;
17109 sa = (ctx->opcode >> 6) & 0x1f;
17110 imm = (int16_t)ctx->opcode >> 7;
17111
17112 op1 = MASK_SPECIAL3(ctx->opcode);
17113 switch (op1) {
17114 case R6_OPC_PREF:
17115 if (rt >= 24) {
17116 /* hint codes 24-31 are reserved and signal RI */
17117 generate_exception(ctx, EXCP_RI);
17118 }
17119 /* Treat as NOP. */
17120 break;
17121 case R6_OPC_CACHE:
17122 /* Treat as NOP. */
17123 break;
17124 case R6_OPC_SC:
17125 gen_st_cond(ctx, op1, rt, rs, imm);
17126 break;
17127 case R6_OPC_LL:
17128 gen_ld(ctx, op1, rt, rs, imm);
17129 break;
17130 case OPC_BSHFL:
17131 {
17132 if (rd == 0) {
17133 /* Treat as NOP. */
17134 break;
17135 }
17136 op2 = MASK_BSHFL(ctx->opcode);
17137 switch (op2) {
17138 case OPC_ALIGN ... OPC_ALIGN_END:
17139 gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
17140 break;
17141 case OPC_BITSWAP:
17142 gen_bitswap(ctx, op2, rd, rt);
17143 break;
17144 }
17145 }
17146 break;
17147 #if defined(TARGET_MIPS64)
17148 case R6_OPC_SCD:
17149 gen_st_cond(ctx, op1, rt, rs, imm);
17150 break;
17151 case R6_OPC_LLD:
17152 gen_ld(ctx, op1, rt, rs, imm);
17153 break;
17154 case OPC_DBSHFL:
17155 check_mips_64(ctx);
17156 {
17157 if (rd == 0) {
17158 /* Treat as NOP. */
17159 break;
17160 }
17161 op2 = MASK_DBSHFL(ctx->opcode);
17162 switch (op2) {
17163 case OPC_DALIGN ... OPC_DALIGN_END:
17164 gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
17165 break;
17166 case OPC_DBITSWAP:
17167 gen_bitswap(ctx, op2, rd, rt);
17168 break;
17169 }
17170
17171 }
17172 break;
17173 #endif
17174 default: /* Invalid */
17175 MIPS_INVAL("special3_r6");
17176 generate_exception(ctx, EXCP_RI);
17177 break;
17178 }
17179 }
17180
17181 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
17182 {
17183 int rs, rt, rd;
17184 uint32_t op1, op2;
17185
17186 rs = (ctx->opcode >> 21) & 0x1f;
17187 rt = (ctx->opcode >> 16) & 0x1f;
17188 rd = (ctx->opcode >> 11) & 0x1f;
17189
17190 op1 = MASK_SPECIAL3(ctx->opcode);
17191 switch (op1) {
17192 case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
17193 case OPC_MOD_G_2E ... OPC_MODU_G_2E:
17194 case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
17195 /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
17196 * the same mask and op1. */
17197 if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
17198 op2 = MASK_ADDUH_QB(ctx->opcode);
17199 switch (op2) {
17200 case OPC_ADDUH_QB:
17201 case OPC_ADDUH_R_QB:
17202 case OPC_ADDQH_PH:
17203 case OPC_ADDQH_R_PH:
17204 case OPC_ADDQH_W:
17205 case OPC_ADDQH_R_W:
17206 case OPC_SUBUH_QB:
17207 case OPC_SUBUH_R_QB:
17208 case OPC_SUBQH_PH:
17209 case OPC_SUBQH_R_PH:
17210 case OPC_SUBQH_W:
17211 case OPC_SUBQH_R_W:
17212 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17213 break;
17214 case OPC_MUL_PH:
17215 case OPC_MUL_S_PH:
17216 case OPC_MULQ_S_W:
17217 case OPC_MULQ_RS_W:
17218 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17219 break;
17220 default:
17221 MIPS_INVAL("MASK ADDUH.QB");
17222 generate_exception(ctx, EXCP_RI);
17223 break;
17224 }
17225 } else if (ctx->insn_flags & INSN_LOONGSON2E) {
17226 gen_loongson_integer(ctx, op1, rd, rs, rt);
17227 } else {
17228 generate_exception(ctx, EXCP_RI);
17229 }
17230 break;
17231 case OPC_LX_DSP:
17232 op2 = MASK_LX(ctx->opcode);
17233 switch (op2) {
17234 #if defined(TARGET_MIPS64)
17235 case OPC_LDX:
17236 #endif
17237 case OPC_LBUX:
17238 case OPC_LHX:
17239 case OPC_LWX:
17240 gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
17241 break;
17242 default: /* Invalid */
17243 MIPS_INVAL("MASK LX");
17244 generate_exception(ctx, EXCP_RI);
17245 break;
17246 }
17247 break;
17248 case OPC_ABSQ_S_PH_DSP:
17249 op2 = MASK_ABSQ_S_PH(ctx->opcode);
17250 switch (op2) {
17251 case OPC_ABSQ_S_QB:
17252 case OPC_ABSQ_S_PH:
17253 case OPC_ABSQ_S_W:
17254 case OPC_PRECEQ_W_PHL:
17255 case OPC_PRECEQ_W_PHR:
17256 case OPC_PRECEQU_PH_QBL:
17257 case OPC_PRECEQU_PH_QBR:
17258 case OPC_PRECEQU_PH_QBLA:
17259 case OPC_PRECEQU_PH_QBRA:
17260 case OPC_PRECEU_PH_QBL:
17261 case OPC_PRECEU_PH_QBR:
17262 case OPC_PRECEU_PH_QBLA:
17263 case OPC_PRECEU_PH_QBRA:
17264 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17265 break;
17266 case OPC_BITREV:
17267 case OPC_REPL_QB:
17268 case OPC_REPLV_QB:
17269 case OPC_REPL_PH:
17270 case OPC_REPLV_PH:
17271 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
17272 break;
17273 default:
17274 MIPS_INVAL("MASK ABSQ_S.PH");
17275 generate_exception(ctx, EXCP_RI);
17276 break;
17277 }
17278 break;
17279 case OPC_ADDU_QB_DSP:
17280 op2 = MASK_ADDU_QB(ctx->opcode);
17281 switch (op2) {
17282 case OPC_ADDQ_PH:
17283 case OPC_ADDQ_S_PH:
17284 case OPC_ADDQ_S_W:
17285 case OPC_ADDU_QB:
17286 case OPC_ADDU_S_QB:
17287 case OPC_ADDU_PH:
17288 case OPC_ADDU_S_PH:
17289 case OPC_SUBQ_PH:
17290 case OPC_SUBQ_S_PH:
17291 case OPC_SUBQ_S_W:
17292 case OPC_SUBU_QB:
17293 case OPC_SUBU_S_QB:
17294 case OPC_SUBU_PH:
17295 case OPC_SUBU_S_PH:
17296 case OPC_ADDSC:
17297 case OPC_ADDWC:
17298 case OPC_MODSUB:
17299 case OPC_RADDU_W_QB:
17300 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17301 break;
17302 case OPC_MULEU_S_PH_QBL:
17303 case OPC_MULEU_S_PH_QBR:
17304 case OPC_MULQ_RS_PH:
17305 case OPC_MULEQ_S_W_PHL:
17306 case OPC_MULEQ_S_W_PHR:
17307 case OPC_MULQ_S_PH:
17308 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17309 break;
17310 default: /* Invalid */
17311 MIPS_INVAL("MASK ADDU.QB");
17312 generate_exception(ctx, EXCP_RI);
17313 break;
17314
17315 }
17316 break;
17317 case OPC_CMPU_EQ_QB_DSP:
17318 op2 = MASK_CMPU_EQ_QB(ctx->opcode);
17319 switch (op2) {
17320 case OPC_PRECR_SRA_PH_W:
17321 case OPC_PRECR_SRA_R_PH_W:
17322 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
17323 break;
17324 case OPC_PRECR_QB_PH:
17325 case OPC_PRECRQ_QB_PH:
17326 case OPC_PRECRQ_PH_W:
17327 case OPC_PRECRQ_RS_PH_W:
17328 case OPC_PRECRQU_S_QB_PH:
17329 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17330 break;
17331 case OPC_CMPU_EQ_QB:
17332 case OPC_CMPU_LT_QB:
17333 case OPC_CMPU_LE_QB:
17334 case OPC_CMP_EQ_PH:
17335 case OPC_CMP_LT_PH:
17336 case OPC_CMP_LE_PH:
17337 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
17338 break;
17339 case OPC_CMPGU_EQ_QB:
17340 case OPC_CMPGU_LT_QB:
17341 case OPC_CMPGU_LE_QB:
17342 case OPC_CMPGDU_EQ_QB:
17343 case OPC_CMPGDU_LT_QB:
17344 case OPC_CMPGDU_LE_QB:
17345 case OPC_PICK_QB:
17346 case OPC_PICK_PH:
17347 case OPC_PACKRL_PH:
17348 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
17349 break;
17350 default: /* Invalid */
17351 MIPS_INVAL("MASK CMPU.EQ.QB");
17352 generate_exception(ctx, EXCP_RI);
17353 break;
17354 }
17355 break;
17356 case OPC_SHLL_QB_DSP:
17357 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
17358 break;
17359 case OPC_DPA_W_PH_DSP:
17360 op2 = MASK_DPA_W_PH(ctx->opcode);
17361 switch (op2) {
17362 case OPC_DPAU_H_QBL:
17363 case OPC_DPAU_H_QBR:
17364 case OPC_DPSU_H_QBL:
17365 case OPC_DPSU_H_QBR:
17366 case OPC_DPA_W_PH:
17367 case OPC_DPAX_W_PH:
17368 case OPC_DPAQ_S_W_PH:
17369 case OPC_DPAQX_S_W_PH:
17370 case OPC_DPAQX_SA_W_PH:
17371 case OPC_DPS_W_PH:
17372 case OPC_DPSX_W_PH:
17373 case OPC_DPSQ_S_W_PH:
17374 case OPC_DPSQX_S_W_PH:
17375 case OPC_DPSQX_SA_W_PH:
17376 case OPC_MULSAQ_S_W_PH:
17377 case OPC_DPAQ_SA_L_W:
17378 case OPC_DPSQ_SA_L_W:
17379 case OPC_MAQ_S_W_PHL:
17380 case OPC_MAQ_S_W_PHR:
17381 case OPC_MAQ_SA_W_PHL:
17382 case OPC_MAQ_SA_W_PHR:
17383 case OPC_MULSA_W_PH:
17384 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17385 break;
17386 default: /* Invalid */
17387 MIPS_INVAL("MASK DPAW.PH");
17388 generate_exception(ctx, EXCP_RI);
17389 break;
17390 }
17391 break;
17392 case OPC_INSV_DSP:
17393 op2 = MASK_INSV(ctx->opcode);
17394 switch (op2) {
17395 case OPC_INSV:
17396 check_dsp(ctx);
17397 {
17398 TCGv t0, t1;
17399
17400 if (rt == 0) {
17401 break;
17402 }
17403
17404 t0 = tcg_temp_new();
17405 t1 = tcg_temp_new();
17406
17407 gen_load_gpr(t0, rt);
17408 gen_load_gpr(t1, rs);
17409
17410 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
17411
17412 tcg_temp_free(t0);
17413 tcg_temp_free(t1);
17414 break;
17415 }
17416 default: /* Invalid */
17417 MIPS_INVAL("MASK INSV");
17418 generate_exception(ctx, EXCP_RI);
17419 break;
17420 }
17421 break;
17422 case OPC_APPEND_DSP:
17423 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
17424 break;
17425 case OPC_EXTR_W_DSP:
17426 op2 = MASK_EXTR_W(ctx->opcode);
17427 switch (op2) {
17428 case OPC_EXTR_W:
17429 case OPC_EXTR_R_W:
17430 case OPC_EXTR_RS_W:
17431 case OPC_EXTR_S_H:
17432 case OPC_EXTRV_S_H:
17433 case OPC_EXTRV_W:
17434 case OPC_EXTRV_R_W:
17435 case OPC_EXTRV_RS_W:
17436 case OPC_EXTP:
17437 case OPC_EXTPV:
17438 case OPC_EXTPDP:
17439 case OPC_EXTPDPV:
17440 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
17441 break;
17442 case OPC_RDDSP:
17443 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1);
17444 break;
17445 case OPC_SHILO:
17446 case OPC_SHILOV:
17447 case OPC_MTHLIP:
17448 case OPC_WRDSP:
17449 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
17450 break;
17451 default: /* Invalid */
17452 MIPS_INVAL("MASK EXTR.W");
17453 generate_exception(ctx, EXCP_RI);
17454 break;
17455 }
17456 break;
17457 #if defined(TARGET_MIPS64)
17458 case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
17459 case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
17460 case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
17461 check_insn(ctx, INSN_LOONGSON2E);
17462 gen_loongson_integer(ctx, op1, rd, rs, rt);
17463 break;
17464 case OPC_ABSQ_S_QH_DSP:
17465 op2 = MASK_ABSQ_S_QH(ctx->opcode);
17466 switch (op2) {
17467 case OPC_PRECEQ_L_PWL:
17468 case OPC_PRECEQ_L_PWR:
17469 case OPC_PRECEQ_PW_QHL:
17470 case OPC_PRECEQ_PW_QHR:
17471 case OPC_PRECEQ_PW_QHLA:
17472 case OPC_PRECEQ_PW_QHRA:
17473 case OPC_PRECEQU_QH_OBL:
17474 case OPC_PRECEQU_QH_OBR:
17475 case OPC_PRECEQU_QH_OBLA:
17476 case OPC_PRECEQU_QH_OBRA:
17477 case OPC_PRECEU_QH_OBL:
17478 case OPC_PRECEU_QH_OBR:
17479 case OPC_PRECEU_QH_OBLA:
17480 case OPC_PRECEU_QH_OBRA:
17481 case OPC_ABSQ_S_OB:
17482 case OPC_ABSQ_S_PW:
17483 case OPC_ABSQ_S_QH:
17484 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17485 break;
17486 case OPC_REPL_OB:
17487 case OPC_REPL_PW:
17488 case OPC_REPL_QH:
17489 case OPC_REPLV_OB:
17490 case OPC_REPLV_PW:
17491 case OPC_REPLV_QH:
17492 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
17493 break;
17494 default: /* Invalid */
17495 MIPS_INVAL("MASK ABSQ_S.QH");
17496 generate_exception(ctx, EXCP_RI);
17497 break;
17498 }
17499 break;
17500 case OPC_ADDU_OB_DSP:
17501 op2 = MASK_ADDU_OB(ctx->opcode);
17502 switch (op2) {
17503 case OPC_RADDU_L_OB:
17504 case OPC_SUBQ_PW:
17505 case OPC_SUBQ_S_PW:
17506 case OPC_SUBQ_QH:
17507 case OPC_SUBQ_S_QH:
17508 case OPC_SUBU_OB:
17509 case OPC_SUBU_S_OB:
17510 case OPC_SUBU_QH:
17511 case OPC_SUBU_S_QH:
17512 case OPC_SUBUH_OB:
17513 case OPC_SUBUH_R_OB:
17514 case OPC_ADDQ_PW:
17515 case OPC_ADDQ_S_PW:
17516 case OPC_ADDQ_QH:
17517 case OPC_ADDQ_S_QH:
17518 case OPC_ADDU_OB:
17519 case OPC_ADDU_S_OB:
17520 case OPC_ADDU_QH:
17521 case OPC_ADDU_S_QH:
17522 case OPC_ADDUH_OB:
17523 case OPC_ADDUH_R_OB:
17524 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17525 break;
17526 case OPC_MULEQ_S_PW_QHL:
17527 case OPC_MULEQ_S_PW_QHR:
17528 case OPC_MULEU_S_QH_OBL:
17529 case OPC_MULEU_S_QH_OBR:
17530 case OPC_MULQ_RS_QH:
17531 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
17532 break;
17533 default: /* Invalid */
17534 MIPS_INVAL("MASK ADDU.OB");
17535 generate_exception(ctx, EXCP_RI);
17536 break;
17537 }
17538 break;
17539 case OPC_CMPU_EQ_OB_DSP:
17540 op2 = MASK_CMPU_EQ_OB(ctx->opcode);
17541 switch (op2) {
17542 case OPC_PRECR_SRA_QH_PW:
17543 case OPC_PRECR_SRA_R_QH_PW:
17544 /* Return value is rt. */
17545 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
17546 break;
17547 case OPC_PRECR_OB_QH:
17548 case OPC_PRECRQ_OB_QH:
17549 case OPC_PRECRQ_PW_L:
17550 case OPC_PRECRQ_QH_PW:
17551 case OPC_PRECRQ_RS_QH_PW:
17552 case OPC_PRECRQU_S_OB_QH:
17553 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
17554 break;
17555 case OPC_CMPU_EQ_OB:
17556 case OPC_CMPU_LT_OB:
17557 case OPC_CMPU_LE_OB:
17558 case OPC_CMP_EQ_QH:
17559 case OPC_CMP_LT_QH:
17560 case OPC_CMP_LE_QH:
17561 case OPC_CMP_EQ_PW:
17562 case OPC_CMP_LT_PW:
17563 case OPC_CMP_LE_PW:
17564 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
17565 break;
17566 case OPC_CMPGDU_EQ_OB:
17567 case OPC_CMPGDU_LT_OB:
17568 case OPC_CMPGDU_LE_OB:
17569 case OPC_CMPGU_EQ_OB:
17570 case OPC_CMPGU_LT_OB:
17571 case OPC_CMPGU_LE_OB:
17572 case OPC_PACKRL_PW:
17573 case OPC_PICK_OB:
17574 case OPC_PICK_PW:
17575 case OPC_PICK_QH:
17576 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
17577 break;
17578 default: /* Invalid */
17579 MIPS_INVAL("MASK CMPU_EQ.OB");
17580 generate_exception(ctx, EXCP_RI);
17581 break;
17582 }
17583 break;
17584 case OPC_DAPPEND_DSP:
17585 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
17586 break;
17587 case OPC_DEXTR_W_DSP:
17588 op2 = MASK_DEXTR_W(ctx->opcode);
17589 switch (op2) {
17590 case OPC_DEXTP:
17591 case OPC_DEXTPDP:
17592 case OPC_DEXTPDPV:
17593 case OPC_DEXTPV:
17594 case OPC_DEXTR_L:
17595 case OPC_DEXTR_R_L:
17596 case OPC_DEXTR_RS_L:
17597 case OPC_DEXTR_W:
17598 case OPC_DEXTR_R_W:
17599 case OPC_DEXTR_RS_W:
17600 case OPC_DEXTR_S_H:
17601 case OPC_DEXTRV_L:
17602 case OPC_DEXTRV_R_L:
17603 case OPC_DEXTRV_RS_L:
17604 case OPC_DEXTRV_S_H:
17605 case OPC_DEXTRV_W:
17606 case OPC_DEXTRV_R_W:
17607 case OPC_DEXTRV_RS_W:
17608 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
17609 break;
17610 case OPC_DMTHLIP:
17611 case OPC_DSHILO:
17612 case OPC_DSHILOV:
17613 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
17614 break;
17615 default: /* Invalid */
17616 MIPS_INVAL("MASK EXTR.W");
17617 generate_exception(ctx, EXCP_RI);
17618 break;
17619 }
17620 break;
17621 case OPC_DPAQ_W_QH_DSP:
17622 op2 = MASK_DPAQ_W_QH(ctx->opcode);
17623 switch (op2) {
17624 case OPC_DPAU_H_OBL:
17625 case OPC_DPAU_H_OBR:
17626 case OPC_DPSU_H_OBL:
17627 case OPC_DPSU_H_OBR:
17628 case OPC_DPA_W_QH:
17629 case OPC_DPAQ_S_W_QH:
17630 case OPC_DPS_W_QH:
17631 case OPC_DPSQ_S_W_QH:
17632 case OPC_MULSAQ_S_W_QH:
17633 case OPC_DPAQ_SA_L_PW:
17634 case OPC_DPSQ_SA_L_PW:
17635 case OPC_MULSAQ_S_L_PW:
17636 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17637 break;
17638 case OPC_MAQ_S_W_QHLL:
17639 case OPC_MAQ_S_W_QHLR:
17640 case OPC_MAQ_S_W_QHRL:
17641 case OPC_MAQ_S_W_QHRR:
17642 case OPC_MAQ_SA_W_QHLL:
17643 case OPC_MAQ_SA_W_QHLR:
17644 case OPC_MAQ_SA_W_QHRL:
17645 case OPC_MAQ_SA_W_QHRR:
17646 case OPC_MAQ_S_L_PWL:
17647 case OPC_MAQ_S_L_PWR:
17648 case OPC_DMADD:
17649 case OPC_DMADDU:
17650 case OPC_DMSUB:
17651 case OPC_DMSUBU:
17652 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
17653 break;
17654 default: /* Invalid */
17655 MIPS_INVAL("MASK DPAQ.W.QH");
17656 generate_exception(ctx, EXCP_RI);
17657 break;
17658 }
17659 break;
17660 case OPC_DINSV_DSP:
17661 op2 = MASK_INSV(ctx->opcode);
17662 switch (op2) {
17663 case OPC_DINSV:
17664 {
17665 TCGv t0, t1;
17666
17667 if (rt == 0) {
17668 break;
17669 }
17670 check_dsp(ctx);
17671
17672 t0 = tcg_temp_new();
17673 t1 = tcg_temp_new();
17674
17675 gen_load_gpr(t0, rt);
17676 gen_load_gpr(t1, rs);
17677
17678 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
17679
17680 tcg_temp_free(t0);
17681 tcg_temp_free(t1);
17682 break;
17683 }
17684 default: /* Invalid */
17685 MIPS_INVAL("MASK DINSV");
17686 generate_exception(ctx, EXCP_RI);
17687 break;
17688 }
17689 break;
17690 case OPC_SHLL_OB_DSP:
17691 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
17692 break;
17693 #endif
17694 default: /* Invalid */
17695 MIPS_INVAL("special3_legacy");
17696 generate_exception(ctx, EXCP_RI);
17697 break;
17698 }
17699 }
17700
17701 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
17702 {
17703 int rs, rt, rd, sa;
17704 uint32_t op1, op2;
17705
17706 rs = (ctx->opcode >> 21) & 0x1f;
17707 rt = (ctx->opcode >> 16) & 0x1f;
17708 rd = (ctx->opcode >> 11) & 0x1f;
17709 sa = (ctx->opcode >> 6) & 0x1f;
17710
17711 op1 = MASK_SPECIAL3(ctx->opcode);
17712 switch (op1) {
17713 case OPC_EXT:
17714 case OPC_INS:
17715 check_insn(ctx, ISA_MIPS32R2);
17716 gen_bitops(ctx, op1, rt, rs, sa, rd);
17717 break;
17718 case OPC_BSHFL:
17719 op2 = MASK_BSHFL(ctx->opcode);
17720 switch (op2) {
17721 case OPC_ALIGN ... OPC_ALIGN_END:
17722 case OPC_BITSWAP:
17723 check_insn(ctx, ISA_MIPS32R6);
17724 decode_opc_special3_r6(env, ctx);
17725 break;
17726 default:
17727 check_insn(ctx, ISA_MIPS32R2);
17728 gen_bshfl(ctx, op2, rt, rd);
17729 break;
17730 }
17731 break;
17732 #if defined(TARGET_MIPS64)
17733 case OPC_DEXTM ... OPC_DEXT:
17734 case OPC_DINSM ... OPC_DINS:
17735 check_insn(ctx, ISA_MIPS64R2);
17736 check_mips_64(ctx);
17737 gen_bitops(ctx, op1, rt, rs, sa, rd);
17738 break;
17739 case OPC_DBSHFL:
17740 op2 = MASK_DBSHFL(ctx->opcode);
17741 switch (op2) {
17742 case OPC_DALIGN ... OPC_DALIGN_END:
17743 case OPC_DBITSWAP:
17744 check_insn(ctx, ISA_MIPS32R6);
17745 decode_opc_special3_r6(env, ctx);
17746 break;
17747 default:
17748 check_insn(ctx, ISA_MIPS64R2);
17749 check_mips_64(ctx);
17750 op2 = MASK_DBSHFL(ctx->opcode);
17751 gen_bshfl(ctx, op2, rt, rd);
17752 break;
17753 }
17754 break;
17755 #endif
17756 case OPC_RDHWR:
17757 gen_rdhwr(ctx, rt, rd);
17758 break;
17759 case OPC_FORK:
17760 check_insn(ctx, ASE_MT);
17761 {
17762 TCGv t0 = tcg_temp_new();
17763 TCGv t1 = tcg_temp_new();
17764
17765 gen_load_gpr(t0, rt);
17766 gen_load_gpr(t1, rs);
17767 gen_helper_fork(t0, t1);
17768 tcg_temp_free(t0);
17769 tcg_temp_free(t1);
17770 }
17771 break;
17772 case OPC_YIELD:
17773 check_insn(ctx, ASE_MT);
17774 {
17775 TCGv t0 = tcg_temp_new();
17776
17777 save_cpu_state(ctx, 1);
17778 gen_load_gpr(t0, rs);
17779 gen_helper_yield(t0, cpu_env, t0);
17780 gen_store_gpr(t0, rd);
17781 tcg_temp_free(t0);
17782 }
17783 break;
17784 default:
17785 if (ctx->insn_flags & ISA_MIPS32R6) {
17786 decode_opc_special3_r6(env, ctx);
17787 } else {
17788 decode_opc_special3_legacy(env, ctx);
17789 }
17790 }
17791 }
17792
17793 /* MIPS SIMD Architecture (MSA) */
17794 static inline int check_msa_access(DisasContext *ctx)
17795 {
17796 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
17797 !(ctx->hflags & MIPS_HFLAG_F64))) {
17798 generate_exception(ctx, EXCP_RI);
17799 return 0;
17800 }
17801
17802 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
17803 if (ctx->insn_flags & ASE_MSA) {
17804 generate_exception(ctx, EXCP_MSADIS);
17805 return 0;
17806 } else {
17807 generate_exception(ctx, EXCP_RI);
17808 return 0;
17809 }
17810 }
17811 return 1;
17812 }
17813
17814 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
17815 {
17816 /* generates tcg ops to check if any element is 0 */
17817 /* Note this function only works with MSA_WRLEN = 128 */
17818 uint64_t eval_zero_or_big = 0;
17819 uint64_t eval_big = 0;
17820 TCGv_i64 t0 = tcg_temp_new_i64();
17821 TCGv_i64 t1 = tcg_temp_new_i64();
17822 switch (df) {
17823 case DF_BYTE:
17824 eval_zero_or_big = 0x0101010101010101ULL;
17825 eval_big = 0x8080808080808080ULL;
17826 break;
17827 case DF_HALF:
17828 eval_zero_or_big = 0x0001000100010001ULL;
17829 eval_big = 0x8000800080008000ULL;
17830 break;
17831 case DF_WORD:
17832 eval_zero_or_big = 0x0000000100000001ULL;
17833 eval_big = 0x8000000080000000ULL;
17834 break;
17835 case DF_DOUBLE:
17836 eval_zero_or_big = 0x0000000000000001ULL;
17837 eval_big = 0x8000000000000000ULL;
17838 break;
17839 }
17840 tcg_gen_subi_i64(t0, msa_wr_d[wt<<1], eval_zero_or_big);
17841 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt<<1]);
17842 tcg_gen_andi_i64(t0, t0, eval_big);
17843 tcg_gen_subi_i64(t1, msa_wr_d[(wt<<1)+1], eval_zero_or_big);
17844 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt<<1)+1]);
17845 tcg_gen_andi_i64(t1, t1, eval_big);
17846 tcg_gen_or_i64(t0, t0, t1);
17847 /* if all bits are zero then all elements are not zero */
17848 /* if some bit is non-zero then some element is zero */
17849 tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0);
17850 tcg_gen_trunc_i64_tl(tresult, t0);
17851 tcg_temp_free_i64(t0);
17852 tcg_temp_free_i64(t1);
17853 }
17854
17855 static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
17856 {
17857 uint8_t df = (ctx->opcode >> 21) & 0x3;
17858 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
17859 int64_t s16 = (int16_t)ctx->opcode;
17860
17861 check_msa_access(ctx);
17862
17863 if (ctx->insn_flags & ISA_MIPS32R6 && ctx->hflags & MIPS_HFLAG_BMASK) {
17864 generate_exception(ctx, EXCP_RI);
17865 return;
17866 }
17867 switch (op1) {
17868 case OPC_BZ_V:
17869 case OPC_BNZ_V:
17870 {
17871 TCGv_i64 t0 = tcg_temp_new_i64();
17872 tcg_gen_or_i64(t0, msa_wr_d[wt<<1], msa_wr_d[(wt<<1)+1]);
17873 tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
17874 TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
17875 tcg_gen_trunc_i64_tl(bcond, t0);
17876 tcg_temp_free_i64(t0);
17877 }
17878 break;
17879 case OPC_BZ_B:
17880 case OPC_BZ_H:
17881 case OPC_BZ_W:
17882 case OPC_BZ_D:
17883 gen_check_zero_element(bcond, df, wt);
17884 break;
17885 case OPC_BNZ_B:
17886 case OPC_BNZ_H:
17887 case OPC_BNZ_W:
17888 case OPC_BNZ_D:
17889 gen_check_zero_element(bcond, df, wt);
17890 tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
17891 break;
17892 }
17893
17894 ctx->btarget = ctx->pc + (s16 << 2) + 4;
17895
17896 ctx->hflags |= MIPS_HFLAG_BC;
17897 ctx->hflags |= MIPS_HFLAG_BDS32;
17898 }
17899
17900 static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
17901 {
17902 #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
17903 uint8_t i8 = (ctx->opcode >> 16) & 0xff;
17904 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
17905 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
17906
17907 TCGv_i32 twd = tcg_const_i32(wd);
17908 TCGv_i32 tws = tcg_const_i32(ws);
17909 TCGv_i32 ti8 = tcg_const_i32(i8);
17910
17911 switch (MASK_MSA_I8(ctx->opcode)) {
17912 case OPC_ANDI_B:
17913 gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
17914 break;
17915 case OPC_ORI_B:
17916 gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
17917 break;
17918 case OPC_NORI_B:
17919 gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
17920 break;
17921 case OPC_XORI_B:
17922 gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
17923 break;
17924 case OPC_BMNZI_B:
17925 gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
17926 break;
17927 case OPC_BMZI_B:
17928 gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
17929 break;
17930 case OPC_BSELI_B:
17931 gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
17932 break;
17933 case OPC_SHF_B:
17934 case OPC_SHF_H:
17935 case OPC_SHF_W:
17936 {
17937 uint8_t df = (ctx->opcode >> 24) & 0x3;
17938 if (df == DF_DOUBLE) {
17939 generate_exception(ctx, EXCP_RI);
17940 } else {
17941 TCGv_i32 tdf = tcg_const_i32(df);
17942 gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
17943 tcg_temp_free_i32(tdf);
17944 }
17945 }
17946 break;
17947 default:
17948 MIPS_INVAL("MSA instruction");
17949 generate_exception(ctx, EXCP_RI);
17950 break;
17951 }
17952
17953 tcg_temp_free_i32(twd);
17954 tcg_temp_free_i32(tws);
17955 tcg_temp_free_i32(ti8);
17956 }
17957
17958 static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
17959 {
17960 #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
17961 uint8_t df = (ctx->opcode >> 21) & 0x3;
17962 int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
17963 uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
17964 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
17965 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
17966
17967 TCGv_i32 tdf = tcg_const_i32(df);
17968 TCGv_i32 twd = tcg_const_i32(wd);
17969 TCGv_i32 tws = tcg_const_i32(ws);
17970 TCGv_i32 timm = tcg_temp_new_i32();
17971 tcg_gen_movi_i32(timm, u5);
17972
17973 switch (MASK_MSA_I5(ctx->opcode)) {
17974 case OPC_ADDVI_df:
17975 gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
17976 break;
17977 case OPC_SUBVI_df:
17978 gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
17979 break;
17980 case OPC_MAXI_S_df:
17981 tcg_gen_movi_i32(timm, s5);
17982 gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
17983 break;
17984 case OPC_MAXI_U_df:
17985 gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
17986 break;
17987 case OPC_MINI_S_df:
17988 tcg_gen_movi_i32(timm, s5);
17989 gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
17990 break;
17991 case OPC_MINI_U_df:
17992 gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
17993 break;
17994 case OPC_CEQI_df:
17995 tcg_gen_movi_i32(timm, s5);
17996 gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
17997 break;
17998 case OPC_CLTI_S_df:
17999 tcg_gen_movi_i32(timm, s5);
18000 gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
18001 break;
18002 case OPC_CLTI_U_df:
18003 gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
18004 break;
18005 case OPC_CLEI_S_df:
18006 tcg_gen_movi_i32(timm, s5);
18007 gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
18008 break;
18009 case OPC_CLEI_U_df:
18010 gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
18011 break;
18012 case OPC_LDI_df:
18013 {
18014 int32_t s10 = sextract32(ctx->opcode, 11, 10);
18015 tcg_gen_movi_i32(timm, s10);
18016 gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
18017 }
18018 break;
18019 default:
18020 MIPS_INVAL("MSA instruction");
18021 generate_exception(ctx, EXCP_RI);
18022 break;
18023 }
18024
18025 tcg_temp_free_i32(tdf);
18026 tcg_temp_free_i32(twd);
18027 tcg_temp_free_i32(tws);
18028 tcg_temp_free_i32(timm);
18029 }
18030
18031 static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
18032 {
18033 #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
18034 uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
18035 uint32_t df = 0, m = 0;
18036 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18037 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18038
18039 TCGv_i32 tdf;
18040 TCGv_i32 tm;
18041 TCGv_i32 twd;
18042 TCGv_i32 tws;
18043
18044 if ((dfm & 0x40) == 0x00) {
18045 m = dfm & 0x3f;
18046 df = DF_DOUBLE;
18047 } else if ((dfm & 0x60) == 0x40) {
18048 m = dfm & 0x1f;
18049 df = DF_WORD;
18050 } else if ((dfm & 0x70) == 0x60) {
18051 m = dfm & 0x0f;
18052 df = DF_HALF;
18053 } else if ((dfm & 0x78) == 0x70) {
18054 m = dfm & 0x7;
18055 df = DF_BYTE;
18056 } else {
18057 generate_exception(ctx, EXCP_RI);
18058 return;
18059 }
18060
18061 tdf = tcg_const_i32(df);
18062 tm = tcg_const_i32(m);
18063 twd = tcg_const_i32(wd);
18064 tws = tcg_const_i32(ws);
18065
18066 switch (MASK_MSA_BIT(ctx->opcode)) {
18067 case OPC_SLLI_df:
18068 gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm);
18069 break;
18070 case OPC_SRAI_df:
18071 gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm);
18072 break;
18073 case OPC_SRLI_df:
18074 gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm);
18075 break;
18076 case OPC_BCLRI_df:
18077 gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm);
18078 break;
18079 case OPC_BSETI_df:
18080 gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm);
18081 break;
18082 case OPC_BNEGI_df:
18083 gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm);
18084 break;
18085 case OPC_BINSLI_df:
18086 gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm);
18087 break;
18088 case OPC_BINSRI_df:
18089 gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm);
18090 break;
18091 case OPC_SAT_S_df:
18092 gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm);
18093 break;
18094 case OPC_SAT_U_df:
18095 gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm);
18096 break;
18097 case OPC_SRARI_df:
18098 gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm);
18099 break;
18100 case OPC_SRLRI_df:
18101 gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm);
18102 break;
18103 default:
18104 MIPS_INVAL("MSA instruction");
18105 generate_exception(ctx, EXCP_RI);
18106 break;
18107 }
18108
18109 tcg_temp_free_i32(tdf);
18110 tcg_temp_free_i32(tm);
18111 tcg_temp_free_i32(twd);
18112 tcg_temp_free_i32(tws);
18113 }
18114
18115 static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
18116 {
18117 #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
18118 uint8_t df = (ctx->opcode >> 21) & 0x3;
18119 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18120 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18121 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18122
18123 TCGv_i32 tdf = tcg_const_i32(df);
18124 TCGv_i32 twd = tcg_const_i32(wd);
18125 TCGv_i32 tws = tcg_const_i32(ws);
18126 TCGv_i32 twt = tcg_const_i32(wt);
18127
18128 switch (MASK_MSA_3R(ctx->opcode)) {
18129 case OPC_SLL_df:
18130 gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
18131 break;
18132 case OPC_ADDV_df:
18133 gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt);
18134 break;
18135 case OPC_CEQ_df:
18136 gen_helper_msa_ceq_df(cpu_env, tdf, twd, tws, twt);
18137 break;
18138 case OPC_ADD_A_df:
18139 gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt);
18140 break;
18141 case OPC_SUBS_S_df:
18142 gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
18143 break;
18144 case OPC_MULV_df:
18145 gen_helper_msa_mulv_df(cpu_env, tdf, twd, tws, twt);
18146 break;
18147 case OPC_SLD_df:
18148 gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
18149 break;
18150 case OPC_VSHF_df:
18151 gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
18152 break;
18153 case OPC_SRA_df:
18154 gen_helper_msa_sra_df(cpu_env, tdf, twd, tws, twt);
18155 break;
18156 case OPC_SUBV_df:
18157 gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
18158 break;
18159 case OPC_ADDS_A_df:
18160 gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt);
18161 break;
18162 case OPC_SUBS_U_df:
18163 gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
18164 break;
18165 case OPC_MADDV_df:
18166 gen_helper_msa_maddv_df(cpu_env, tdf, twd, tws, twt);
18167 break;
18168 case OPC_SPLAT_df:
18169 gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
18170 break;
18171 case OPC_SRAR_df:
18172 gen_helper_msa_srar_df(cpu_env, tdf, twd, tws, twt);
18173 break;
18174 case OPC_SRL_df:
18175 gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
18176 break;
18177 case OPC_MAX_S_df:
18178 gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt);
18179 break;
18180 case OPC_CLT_S_df:
18181 gen_helper_msa_clt_s_df(cpu_env, tdf, twd, tws, twt);
18182 break;
18183 case OPC_ADDS_S_df:
18184 gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
18185 break;
18186 case OPC_SUBSUS_U_df:
18187 gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
18188 break;
18189 case OPC_MSUBV_df:
18190 gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
18191 break;
18192 case OPC_PCKEV_df:
18193 gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt);
18194 break;
18195 case OPC_SRLR_df:
18196 gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
18197 break;
18198 case OPC_BCLR_df:
18199 gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt);
18200 break;
18201 case OPC_MAX_U_df:
18202 gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
18203 break;
18204 case OPC_CLT_U_df:
18205 gen_helper_msa_clt_u_df(cpu_env, tdf, twd, tws, twt);
18206 break;
18207 case OPC_ADDS_U_df:
18208 gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
18209 break;
18210 case OPC_SUBSUU_S_df:
18211 gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
18212 break;
18213 case OPC_PCKOD_df:
18214 gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
18215 break;
18216 case OPC_BSET_df:
18217 gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt);
18218 break;
18219 case OPC_MIN_S_df:
18220 gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
18221 break;
18222 case OPC_CLE_S_df:
18223 gen_helper_msa_cle_s_df(cpu_env, tdf, twd, tws, twt);
18224 break;
18225 case OPC_AVE_S_df:
18226 gen_helper_msa_ave_s_df(cpu_env, tdf, twd, tws, twt);
18227 break;
18228 case OPC_ASUB_S_df:
18229 gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
18230 break;
18231 case OPC_DIV_S_df:
18232 gen_helper_msa_div_s_df(cpu_env, tdf, twd, tws, twt);
18233 break;
18234 case OPC_ILVL_df:
18235 gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
18236 break;
18237 case OPC_BNEG_df:
18238 gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
18239 break;
18240 case OPC_MIN_U_df:
18241 gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
18242 break;
18243 case OPC_CLE_U_df:
18244 gen_helper_msa_cle_u_df(cpu_env, tdf, twd, tws, twt);
18245 break;
18246 case OPC_AVE_U_df:
18247 gen_helper_msa_ave_u_df(cpu_env, tdf, twd, tws, twt);
18248 break;
18249 case OPC_ASUB_U_df:
18250 gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
18251 break;
18252 case OPC_DIV_U_df:
18253 gen_helper_msa_div_u_df(cpu_env, tdf, twd, tws, twt);
18254 break;
18255 case OPC_ILVR_df:
18256 gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
18257 break;
18258 case OPC_BINSL_df:
18259 gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
18260 break;
18261 case OPC_MAX_A_df:
18262 gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
18263 break;
18264 case OPC_AVER_S_df:
18265 gen_helper_msa_aver_s_df(cpu_env, tdf, twd, tws, twt);
18266 break;
18267 case OPC_MOD_S_df:
18268 gen_helper_msa_mod_s_df(cpu_env, tdf, twd, tws, twt);
18269 break;
18270 case OPC_ILVEV_df:
18271 gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
18272 break;
18273 case OPC_BINSR_df:
18274 gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
18275 break;
18276 case OPC_MIN_A_df:
18277 gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
18278 break;
18279 case OPC_AVER_U_df:
18280 gen_helper_msa_aver_u_df(cpu_env, tdf, twd, tws, twt);
18281 break;
18282 case OPC_MOD_U_df:
18283 gen_helper_msa_mod_u_df(cpu_env, tdf, twd, tws, twt);
18284 break;
18285 case OPC_ILVOD_df:
18286 gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
18287 break;
18288
18289 case OPC_DOTP_S_df:
18290 case OPC_DOTP_U_df:
18291 case OPC_DPADD_S_df:
18292 case OPC_DPADD_U_df:
18293 case OPC_DPSUB_S_df:
18294 case OPC_HADD_S_df:
18295 case OPC_DPSUB_U_df:
18296 case OPC_HADD_U_df:
18297 case OPC_HSUB_S_df:
18298 case OPC_HSUB_U_df:
18299 if (df == DF_BYTE) {
18300 generate_exception(ctx, EXCP_RI);
18301 }
18302 switch (MASK_MSA_3R(ctx->opcode)) {
18303 case OPC_DOTP_S_df:
18304 gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
18305 break;
18306 case OPC_DOTP_U_df:
18307 gen_helper_msa_dotp_u_df(cpu_env, tdf, twd, tws, twt);
18308 break;
18309 case OPC_DPADD_S_df:
18310 gen_helper_msa_dpadd_s_df(cpu_env, tdf, twd, tws, twt);
18311 break;
18312 case OPC_DPADD_U_df:
18313 gen_helper_msa_dpadd_u_df(cpu_env, tdf, twd, tws, twt);
18314 break;
18315 case OPC_DPSUB_S_df:
18316 gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
18317 break;
18318 case OPC_HADD_S_df:
18319 gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt);
18320 break;
18321 case OPC_DPSUB_U_df:
18322 gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
18323 break;
18324 case OPC_HADD_U_df:
18325 gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt);
18326 break;
18327 case OPC_HSUB_S_df:
18328 gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt);
18329 break;
18330 case OPC_HSUB_U_df:
18331 gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt);
18332 break;
18333 }
18334 break;
18335 default:
18336 MIPS_INVAL("MSA instruction");
18337 generate_exception(ctx, EXCP_RI);
18338 break;
18339 }
18340 tcg_temp_free_i32(twd);
18341 tcg_temp_free_i32(tws);
18342 tcg_temp_free_i32(twt);
18343 tcg_temp_free_i32(tdf);
18344 }
18345
18346 static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
18347 {
18348 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
18349 uint8_t source = (ctx->opcode >> 11) & 0x1f;
18350 uint8_t dest = (ctx->opcode >> 6) & 0x1f;
18351 TCGv telm = tcg_temp_new();
18352 TCGv_i32 tsr = tcg_const_i32(source);
18353 TCGv_i32 tdt = tcg_const_i32(dest);
18354
18355 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
18356 case OPC_CTCMSA:
18357 gen_load_gpr(telm, source);
18358 gen_helper_msa_ctcmsa(cpu_env, telm, tdt);
18359 break;
18360 case OPC_CFCMSA:
18361 gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
18362 gen_store_gpr(telm, dest);
18363 break;
18364 case OPC_MOVE_V:
18365 gen_helper_msa_move_v(cpu_env, tdt, tsr);
18366 break;
18367 default:
18368 MIPS_INVAL("MSA instruction");
18369 generate_exception(ctx, EXCP_RI);
18370 break;
18371 }
18372
18373 tcg_temp_free(telm);
18374 tcg_temp_free_i32(tdt);
18375 tcg_temp_free_i32(tsr);
18376 }
18377
18378 static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
18379 uint32_t n)
18380 {
18381 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18382 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18383 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18384
18385 TCGv_i32 tws = tcg_const_i32(ws);
18386 TCGv_i32 twd = tcg_const_i32(wd);
18387 TCGv_i32 tn = tcg_const_i32(n);
18388 TCGv_i32 tdf = tcg_const_i32(df);
18389
18390 switch (MASK_MSA_ELM(ctx->opcode)) {
18391 case OPC_SLDI_df:
18392 gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
18393 break;
18394 case OPC_SPLATI_df:
18395 gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
18396 break;
18397 case OPC_INSVE_df:
18398 gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
18399 break;
18400 case OPC_COPY_S_df:
18401 case OPC_COPY_U_df:
18402 case OPC_INSERT_df:
18403 #if !defined(TARGET_MIPS64)
18404 /* Double format valid only for MIPS64 */
18405 if (df == DF_DOUBLE) {
18406 generate_exception(ctx, EXCP_RI);
18407 break;
18408 }
18409 #endif
18410 switch (MASK_MSA_ELM(ctx->opcode)) {
18411 case OPC_COPY_S_df:
18412 gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
18413 break;
18414 case OPC_COPY_U_df:
18415 gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
18416 break;
18417 case OPC_INSERT_df:
18418 gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
18419 break;
18420 }
18421 break;
18422 default:
18423 MIPS_INVAL("MSA instruction");
18424 generate_exception(ctx, EXCP_RI);
18425 }
18426 tcg_temp_free_i32(twd);
18427 tcg_temp_free_i32(tws);
18428 tcg_temp_free_i32(tn);
18429 tcg_temp_free_i32(tdf);
18430 }
18431
18432 static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
18433 {
18434 uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
18435 uint32_t df = 0, n = 0;
18436
18437 if ((dfn & 0x30) == 0x00) {
18438 n = dfn & 0x0f;
18439 df = DF_BYTE;
18440 } else if ((dfn & 0x38) == 0x20) {
18441 n = dfn & 0x07;
18442 df = DF_HALF;
18443 } else if ((dfn & 0x3c) == 0x30) {
18444 n = dfn & 0x03;
18445 df = DF_WORD;
18446 } else if ((dfn & 0x3e) == 0x38) {
18447 n = dfn & 0x01;
18448 df = DF_DOUBLE;
18449 } else if (dfn == 0x3E) {
18450 /* CTCMSA, CFCMSA, MOVE.V */
18451 gen_msa_elm_3e(env, ctx);
18452 return;
18453 } else {
18454 generate_exception(ctx, EXCP_RI);
18455 return;
18456 }
18457
18458 gen_msa_elm_df(env, ctx, df, n);
18459 }
18460
18461 static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
18462 {
18463 #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
18464 uint8_t df = (ctx->opcode >> 21) & 0x1;
18465 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18466 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18467 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18468
18469 TCGv_i32 twd = tcg_const_i32(wd);
18470 TCGv_i32 tws = tcg_const_i32(ws);
18471 TCGv_i32 twt = tcg_const_i32(wt);
18472 TCGv_i32 tdf = tcg_temp_new_i32();
18473
18474 /* adjust df value for floating-point instruction */
18475 tcg_gen_movi_i32(tdf, df + 2);
18476
18477 switch (MASK_MSA_3RF(ctx->opcode)) {
18478 case OPC_FCAF_df:
18479 gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt);
18480 break;
18481 case OPC_FADD_df:
18482 gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt);
18483 break;
18484 case OPC_FCUN_df:
18485 gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt);
18486 break;
18487 case OPC_FSUB_df:
18488 gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt);
18489 break;
18490 case OPC_FCOR_df:
18491 gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt);
18492 break;
18493 case OPC_FCEQ_df:
18494 gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt);
18495 break;
18496 case OPC_FMUL_df:
18497 gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt);
18498 break;
18499 case OPC_FCUNE_df:
18500 gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt);
18501 break;
18502 case OPC_FCUEQ_df:
18503 gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt);
18504 break;
18505 case OPC_FDIV_df:
18506 gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt);
18507 break;
18508 case OPC_FCNE_df:
18509 gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt);
18510 break;
18511 case OPC_FCLT_df:
18512 gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt);
18513 break;
18514 case OPC_FMADD_df:
18515 gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
18516 break;
18517 case OPC_MUL_Q_df:
18518 tcg_gen_movi_i32(tdf, df + 1);
18519 gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
18520 break;
18521 case OPC_FCULT_df:
18522 gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
18523 break;
18524 case OPC_FMSUB_df:
18525 gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
18526 break;
18527 case OPC_MADD_Q_df:
18528 tcg_gen_movi_i32(tdf, df + 1);
18529 gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
18530 break;
18531 case OPC_FCLE_df:
18532 gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
18533 break;
18534 case OPC_MSUB_Q_df:
18535 tcg_gen_movi_i32(tdf, df + 1);
18536 gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
18537 break;
18538 case OPC_FCULE_df:
18539 gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
18540 break;
18541 case OPC_FEXP2_df:
18542 gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt);
18543 break;
18544 case OPC_FSAF_df:
18545 gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt);
18546 break;
18547 case OPC_FEXDO_df:
18548 gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt);
18549 break;
18550 case OPC_FSUN_df:
18551 gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt);
18552 break;
18553 case OPC_FSOR_df:
18554 gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt);
18555 break;
18556 case OPC_FSEQ_df:
18557 gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt);
18558 break;
18559 case OPC_FTQ_df:
18560 gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt);
18561 break;
18562 case OPC_FSUNE_df:
18563 gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt);
18564 break;
18565 case OPC_FSUEQ_df:
18566 gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt);
18567 break;
18568 case OPC_FSNE_df:
18569 gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt);
18570 break;
18571 case OPC_FSLT_df:
18572 gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt);
18573 break;
18574 case OPC_FMIN_df:
18575 gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
18576 break;
18577 case OPC_MULR_Q_df:
18578 tcg_gen_movi_i32(tdf, df + 1);
18579 gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
18580 break;
18581 case OPC_FSULT_df:
18582 gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
18583 break;
18584 case OPC_FMIN_A_df:
18585 gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
18586 break;
18587 case OPC_MADDR_Q_df:
18588 tcg_gen_movi_i32(tdf, df + 1);
18589 gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
18590 break;
18591 case OPC_FSLE_df:
18592 gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
18593 break;
18594 case OPC_FMAX_df:
18595 gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
18596 break;
18597 case OPC_MSUBR_Q_df:
18598 tcg_gen_movi_i32(tdf, df + 1);
18599 gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
18600 break;
18601 case OPC_FSULE_df:
18602 gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
18603 break;
18604 case OPC_FMAX_A_df:
18605 gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt);
18606 break;
18607 default:
18608 MIPS_INVAL("MSA instruction");
18609 generate_exception(ctx, EXCP_RI);
18610 break;
18611 }
18612
18613 tcg_temp_free_i32(twd);
18614 tcg_temp_free_i32(tws);
18615 tcg_temp_free_i32(twt);
18616 tcg_temp_free_i32(tdf);
18617 }
18618
18619 static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
18620 {
18621 #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18622 (op & (0x7 << 18)))
18623 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18624 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18625 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18626 uint8_t df = (ctx->opcode >> 16) & 0x3;
18627 TCGv_i32 twd = tcg_const_i32(wd);
18628 TCGv_i32 tws = tcg_const_i32(ws);
18629 TCGv_i32 twt = tcg_const_i32(wt);
18630 TCGv_i32 tdf = tcg_const_i32(df);
18631
18632 switch (MASK_MSA_2R(ctx->opcode)) {
18633 case OPC_FILL_df:
18634 #if !defined(TARGET_MIPS64)
18635 /* Double format valid only for MIPS64 */
18636 if (df == DF_DOUBLE) {
18637 generate_exception(ctx, EXCP_RI);
18638 break;
18639 }
18640 #endif
18641 gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
18642 break;
18643 case OPC_PCNT_df:
18644 gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws);
18645 break;
18646 case OPC_NLOC_df:
18647 gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws);
18648 break;
18649 case OPC_NLZC_df:
18650 gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws);
18651 break;
18652 default:
18653 MIPS_INVAL("MSA instruction");
18654 generate_exception(ctx, EXCP_RI);
18655 break;
18656 }
18657
18658 tcg_temp_free_i32(twd);
18659 tcg_temp_free_i32(tws);
18660 tcg_temp_free_i32(twt);
18661 tcg_temp_free_i32(tdf);
18662 }
18663
18664 static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
18665 {
18666 #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
18667 (op & (0xf << 17)))
18668 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18669 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18670 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18671 uint8_t df = (ctx->opcode >> 16) & 0x1;
18672 TCGv_i32 twd = tcg_const_i32(wd);
18673 TCGv_i32 tws = tcg_const_i32(ws);
18674 TCGv_i32 twt = tcg_const_i32(wt);
18675 /* adjust df value for floating-point instruction */
18676 TCGv_i32 tdf = tcg_const_i32(df + 2);
18677
18678 switch (MASK_MSA_2RF(ctx->opcode)) {
18679 case OPC_FCLASS_df:
18680 gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws);
18681 break;
18682 case OPC_FTRUNC_S_df:
18683 gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws);
18684 break;
18685 case OPC_FTRUNC_U_df:
18686 gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws);
18687 break;
18688 case OPC_FSQRT_df:
18689 gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws);
18690 break;
18691 case OPC_FRSQRT_df:
18692 gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws);
18693 break;
18694 case OPC_FRCP_df:
18695 gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws);
18696 break;
18697 case OPC_FRINT_df:
18698 gen_helper_msa_frint_df(cpu_env, tdf, twd, tws);
18699 break;
18700 case OPC_FLOG2_df:
18701 gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws);
18702 break;
18703 case OPC_FEXUPL_df:
18704 gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws);
18705 break;
18706 case OPC_FEXUPR_df:
18707 gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws);
18708 break;
18709 case OPC_FFQL_df:
18710 gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws);
18711 break;
18712 case OPC_FFQR_df:
18713 gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws);
18714 break;
18715 case OPC_FTINT_S_df:
18716 gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws);
18717 break;
18718 case OPC_FTINT_U_df:
18719 gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws);
18720 break;
18721 case OPC_FFINT_S_df:
18722 gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws);
18723 break;
18724 case OPC_FFINT_U_df:
18725 gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws);
18726 break;
18727 }
18728
18729 tcg_temp_free_i32(twd);
18730 tcg_temp_free_i32(tws);
18731 tcg_temp_free_i32(twt);
18732 tcg_temp_free_i32(tdf);
18733 }
18734
18735 static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
18736 {
18737 #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
18738 uint8_t wt = (ctx->opcode >> 16) & 0x1f;
18739 uint8_t ws = (ctx->opcode >> 11) & 0x1f;
18740 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18741 TCGv_i32 twd = tcg_const_i32(wd);
18742 TCGv_i32 tws = tcg_const_i32(ws);
18743 TCGv_i32 twt = tcg_const_i32(wt);
18744
18745 switch (MASK_MSA_VEC(ctx->opcode)) {
18746 case OPC_AND_V:
18747 gen_helper_msa_and_v(cpu_env, twd, tws, twt);
18748 break;
18749 case OPC_OR_V:
18750 gen_helper_msa_or_v(cpu_env, twd, tws, twt);
18751 break;
18752 case OPC_NOR_V:
18753 gen_helper_msa_nor_v(cpu_env, twd, tws, twt);
18754 break;
18755 case OPC_XOR_V:
18756 gen_helper_msa_xor_v(cpu_env, twd, tws, twt);
18757 break;
18758 case OPC_BMNZ_V:
18759 gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt);
18760 break;
18761 case OPC_BMZ_V:
18762 gen_helper_msa_bmz_v(cpu_env, twd, tws, twt);
18763 break;
18764 case OPC_BSEL_V:
18765 gen_helper_msa_bsel_v(cpu_env, twd, tws, twt);
18766 break;
18767 default:
18768 MIPS_INVAL("MSA instruction");
18769 generate_exception(ctx, EXCP_RI);
18770 break;
18771 }
18772
18773 tcg_temp_free_i32(twd);
18774 tcg_temp_free_i32(tws);
18775 tcg_temp_free_i32(twt);
18776 }
18777
18778 static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
18779 {
18780 switch (MASK_MSA_VEC(ctx->opcode)) {
18781 case OPC_AND_V:
18782 case OPC_OR_V:
18783 case OPC_NOR_V:
18784 case OPC_XOR_V:
18785 case OPC_BMNZ_V:
18786 case OPC_BMZ_V:
18787 case OPC_BSEL_V:
18788 gen_msa_vec_v(env, ctx);
18789 break;
18790 case OPC_MSA_2R:
18791 gen_msa_2r(env, ctx);
18792 break;
18793 case OPC_MSA_2RF:
18794 gen_msa_2rf(env, ctx);
18795 break;
18796 default:
18797 MIPS_INVAL("MSA instruction");
18798 generate_exception(ctx, EXCP_RI);
18799 break;
18800 }
18801 }
18802
18803 static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
18804 {
18805 uint32_t opcode = ctx->opcode;
18806 check_insn(ctx, ASE_MSA);
18807 check_msa_access(ctx);
18808
18809 switch (MASK_MSA_MINOR(opcode)) {
18810 case OPC_MSA_I8_00:
18811 case OPC_MSA_I8_01:
18812 case OPC_MSA_I8_02:
18813 gen_msa_i8(env, ctx);
18814 break;
18815 case OPC_MSA_I5_06:
18816 case OPC_MSA_I5_07:
18817 gen_msa_i5(env, ctx);
18818 break;
18819 case OPC_MSA_BIT_09:
18820 case OPC_MSA_BIT_0A:
18821 gen_msa_bit(env, ctx);
18822 break;
18823 case OPC_MSA_3R_0D:
18824 case OPC_MSA_3R_0E:
18825 case OPC_MSA_3R_0F:
18826 case OPC_MSA_3R_10:
18827 case OPC_MSA_3R_11:
18828 case OPC_MSA_3R_12:
18829 case OPC_MSA_3R_13:
18830 case OPC_MSA_3R_14:
18831 case OPC_MSA_3R_15:
18832 gen_msa_3r(env, ctx);
18833 break;
18834 case OPC_MSA_ELM:
18835 gen_msa_elm(env, ctx);
18836 break;
18837 case OPC_MSA_3RF_1A:
18838 case OPC_MSA_3RF_1B:
18839 case OPC_MSA_3RF_1C:
18840 gen_msa_3rf(env, ctx);
18841 break;
18842 case OPC_MSA_VEC:
18843 gen_msa_vec(env, ctx);
18844 break;
18845 case OPC_LD_B:
18846 case OPC_LD_H:
18847 case OPC_LD_W:
18848 case OPC_LD_D:
18849 case OPC_ST_B:
18850 case OPC_ST_H:
18851 case OPC_ST_W:
18852 case OPC_ST_D:
18853 {
18854 int32_t s10 = sextract32(ctx->opcode, 16, 10);
18855 uint8_t rs = (ctx->opcode >> 11) & 0x1f;
18856 uint8_t wd = (ctx->opcode >> 6) & 0x1f;
18857 uint8_t df = (ctx->opcode >> 0) & 0x3;
18858
18859 TCGv_i32 twd = tcg_const_i32(wd);
18860 TCGv taddr = tcg_temp_new();
18861 gen_base_offset_addr(ctx, taddr, rs, s10 << df);
18862
18863 switch (MASK_MSA_MINOR(opcode)) {
18864 case OPC_LD_B:
18865 gen_helper_msa_ld_b(cpu_env, twd, taddr);
18866 break;
18867 case OPC_LD_H:
18868 gen_helper_msa_ld_h(cpu_env, twd, taddr);
18869 break;
18870 case OPC_LD_W:
18871 gen_helper_msa_ld_w(cpu_env, twd, taddr);
18872 break;
18873 case OPC_LD_D:
18874 gen_helper_msa_ld_d(cpu_env, twd, taddr);
18875 break;
18876 case OPC_ST_B:
18877 gen_helper_msa_st_b(cpu_env, twd, taddr);
18878 break;
18879 case OPC_ST_H:
18880 gen_helper_msa_st_h(cpu_env, twd, taddr);
18881 break;
18882 case OPC_ST_W:
18883 gen_helper_msa_st_w(cpu_env, twd, taddr);
18884 break;
18885 case OPC_ST_D:
18886 gen_helper_msa_st_d(cpu_env, twd, taddr);
18887 break;
18888 }
18889
18890 tcg_temp_free_i32(twd);
18891 tcg_temp_free(taddr);
18892 }
18893 break;
18894 default:
18895 MIPS_INVAL("MSA instruction");
18896 generate_exception(ctx, EXCP_RI);
18897 break;
18898 }
18899
18900 }
18901
18902 static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
18903 {
18904 int32_t offset;
18905 int rs, rt, rd, sa;
18906 uint32_t op, op1;
18907 int16_t imm;
18908
18909 /* make sure instructions are on a word boundary */
18910 if (ctx->pc & 0x3) {
18911 env->CP0_BadVAddr = ctx->pc;
18912 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
18913 ctx->bstate = BS_STOP;
18914 return;
18915 }
18916
18917 /* Handle blikely not taken case */
18918 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
18919 TCGLabel *l1 = gen_new_label();
18920
18921 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
18922 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
18923 gen_goto_tb(ctx, 1, ctx->pc + 4);
18924 gen_set_label(l1);
18925 }
18926
18927 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
18928 tcg_gen_debug_insn_start(ctx->pc);
18929 }
18930
18931 op = MASK_OP_MAJOR(ctx->opcode);
18932 rs = (ctx->opcode >> 21) & 0x1f;
18933 rt = (ctx->opcode >> 16) & 0x1f;
18934 rd = (ctx->opcode >> 11) & 0x1f;
18935 sa = (ctx->opcode >> 6) & 0x1f;
18936 imm = (int16_t)ctx->opcode;
18937 switch (op) {
18938 case OPC_SPECIAL:
18939 decode_opc_special(env, ctx);
18940 break;
18941 case OPC_SPECIAL2:
18942 decode_opc_special2_legacy(env, ctx);
18943 break;
18944 case OPC_SPECIAL3:
18945 decode_opc_special3(env, ctx);
18946 break;
18947 case OPC_REGIMM:
18948 op1 = MASK_REGIMM(ctx->opcode);
18949 switch (op1) {
18950 case OPC_BLTZL: /* REGIMM branches */
18951 case OPC_BGEZL:
18952 case OPC_BLTZALL:
18953 case OPC_BGEZALL:
18954 check_insn(ctx, ISA_MIPS2);
18955 check_insn_opc_removed(ctx, ISA_MIPS32R6);
18956 /* Fallthrough */
18957 case OPC_BLTZ:
18958 case OPC_BGEZ:
18959 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
18960 break;
18961 case OPC_BLTZAL:
18962 case OPC_BGEZAL:
18963 if (ctx->insn_flags & ISA_MIPS32R6) {
18964 if (rs == 0) {
18965 /* OPC_NAL, OPC_BAL */
18966 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
18967 } else {
18968 generate_exception(ctx, EXCP_RI);
18969 }
18970 } else {
18971 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
18972 }
18973 break;
18974 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
18975 case OPC_TNEI:
18976 check_insn(ctx, ISA_MIPS2);
18977 check_insn_opc_removed(ctx, ISA_MIPS32R6);
18978 gen_trap(ctx, op1, rs, -1, imm);
18979 break;
18980 case OPC_SYNCI:
18981 check_insn(ctx, ISA_MIPS32R2);
18982 /* Break the TB to be able to sync copied instructions
18983 immediately */
18984 ctx->bstate = BS_STOP;
18985 break;
18986 case OPC_BPOSGE32: /* MIPS DSP branch */
18987 #if defined(TARGET_MIPS64)
18988 case OPC_BPOSGE64:
18989 #endif
18990 check_dsp(ctx);
18991 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
18992 break;
18993 #if defined(TARGET_MIPS64)
18994 case OPC_DAHI:
18995 check_insn(ctx, ISA_MIPS32R6);
18996 check_mips_64(ctx);
18997 if (rs != 0) {
18998 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
18999 }
19000 break;
19001 case OPC_DATI:
19002 check_insn(ctx, ISA_MIPS32R6);
19003 check_mips_64(ctx);
19004 if (rs != 0) {
19005 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
19006 }
19007 break;
19008 #endif
19009 default: /* Invalid */
19010 MIPS_INVAL("regimm");
19011 generate_exception(ctx, EXCP_RI);
19012 break;
19013 }
19014 break;
19015 case OPC_CP0:
19016 check_cp0_enabled(ctx);
19017 op1 = MASK_CP0(ctx->opcode);
19018 switch (op1) {
19019 case OPC_MFC0:
19020 case OPC_MTC0:
19021 case OPC_MFTR:
19022 case OPC_MTTR:
19023 case OPC_MFHC0:
19024 case OPC_MTHC0:
19025 #if defined(TARGET_MIPS64)
19026 case OPC_DMFC0:
19027 case OPC_DMTC0:
19028 #endif
19029 #ifndef CONFIG_USER_ONLY
19030 gen_cp0(env, ctx, op1, rt, rd);
19031 #endif /* !CONFIG_USER_ONLY */
19032 break;
19033 case OPC_C0_FIRST ... OPC_C0_LAST:
19034 #ifndef CONFIG_USER_ONLY
19035 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
19036 #endif /* !CONFIG_USER_ONLY */
19037 break;
19038 case OPC_MFMC0:
19039 #ifndef CONFIG_USER_ONLY
19040 {
19041 uint32_t op2;
19042 TCGv t0 = tcg_temp_new();
19043
19044 op2 = MASK_MFMC0(ctx->opcode);
19045 switch (op2) {
19046 case OPC_DMT:
19047 check_insn(ctx, ASE_MT);
19048 gen_helper_dmt(t0);
19049 gen_store_gpr(t0, rt);
19050 break;
19051 case OPC_EMT:
19052 check_insn(ctx, ASE_MT);
19053 gen_helper_emt(t0);
19054 gen_store_gpr(t0, rt);
19055 break;
19056 case OPC_DVPE:
19057 check_insn(ctx, ASE_MT);
19058 gen_helper_dvpe(t0, cpu_env);
19059 gen_store_gpr(t0, rt);
19060 break;
19061 case OPC_EVPE:
19062 check_insn(ctx, ASE_MT);
19063 gen_helper_evpe(t0, cpu_env);
19064 gen_store_gpr(t0, rt);
19065 break;
19066 case OPC_DI:
19067 check_insn(ctx, ISA_MIPS32R2);
19068 save_cpu_state(ctx, 1);
19069 gen_helper_di(t0, cpu_env);
19070 gen_store_gpr(t0, rt);
19071 /* Stop translation as we may have switched
19072 the execution mode. */
19073 ctx->bstate = BS_STOP;
19074 break;
19075 case OPC_EI:
19076 check_insn(ctx, ISA_MIPS32R2);
19077 save_cpu_state(ctx, 1);
19078 gen_helper_ei(t0, cpu_env);
19079 gen_store_gpr(t0, rt);
19080 /* Stop translation as we may have switched
19081 the execution mode. */
19082 ctx->bstate = BS_STOP;
19083 break;
19084 default: /* Invalid */
19085 MIPS_INVAL("mfmc0");
19086 generate_exception(ctx, EXCP_RI);
19087 break;
19088 }
19089 tcg_temp_free(t0);
19090 }
19091 #endif /* !CONFIG_USER_ONLY */
19092 break;
19093 case OPC_RDPGPR:
19094 check_insn(ctx, ISA_MIPS32R2);
19095 gen_load_srsgpr(rt, rd);
19096 break;
19097 case OPC_WRPGPR:
19098 check_insn(ctx, ISA_MIPS32R2);
19099 gen_store_srsgpr(rt, rd);
19100 break;
19101 default:
19102 MIPS_INVAL("cp0");
19103 generate_exception(ctx, EXCP_RI);
19104 break;
19105 }
19106 break;
19107 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
19108 if (ctx->insn_flags & ISA_MIPS32R6) {
19109 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
19110 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19111 } else {
19112 /* OPC_ADDI */
19113 /* Arithmetic with immediate opcode */
19114 gen_arith_imm(ctx, op, rt, rs, imm);
19115 }
19116 break;
19117 case OPC_ADDIU:
19118 gen_arith_imm(ctx, op, rt, rs, imm);
19119 break;
19120 case OPC_SLTI: /* Set on less than with immediate opcode */
19121 case OPC_SLTIU:
19122 gen_slt_imm(ctx, op, rt, rs, imm);
19123 break;
19124 case OPC_ANDI: /* Arithmetic with immediate opcode */
19125 case OPC_LUI: /* OPC_AUI */
19126 case OPC_ORI:
19127 case OPC_XORI:
19128 gen_logic_imm(ctx, op, rt, rs, imm);
19129 break;
19130 case OPC_J ... OPC_JAL: /* Jump */
19131 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
19132 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
19133 break;
19134 /* Branch */
19135 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
19136 if (ctx->insn_flags & ISA_MIPS32R6) {
19137 if (rt == 0) {
19138 generate_exception(ctx, EXCP_RI);
19139 break;
19140 }
19141 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
19142 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19143 } else {
19144 /* OPC_BLEZL */
19145 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19146 }
19147 break;
19148 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
19149 if (ctx->insn_flags & ISA_MIPS32R6) {
19150 if (rt == 0) {
19151 generate_exception(ctx, EXCP_RI);
19152 break;
19153 }
19154 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
19155 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19156 } else {
19157 /* OPC_BGTZL */
19158 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19159 }
19160 break;
19161 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
19162 if (rt == 0) {
19163 /* OPC_BLEZ */
19164 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19165 } else {
19166 check_insn(ctx, ISA_MIPS32R6);
19167 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
19168 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19169 }
19170 break;
19171 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
19172 if (rt == 0) {
19173 /* OPC_BGTZ */
19174 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19175 } else {
19176 check_insn(ctx, ISA_MIPS32R6);
19177 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
19178 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19179 }
19180 break;
19181 case OPC_BEQL:
19182 case OPC_BNEL:
19183 check_insn(ctx, ISA_MIPS2);
19184 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19185 /* Fallthrough */
19186 case OPC_BEQ:
19187 case OPC_BNE:
19188 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
19189 break;
19190 case OPC_LL: /* Load and stores */
19191 check_insn(ctx, ISA_MIPS2);
19192 /* Fallthrough */
19193 case OPC_LWL:
19194 case OPC_LWR:
19195 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19196 /* Fallthrough */
19197 case OPC_LB ... OPC_LH:
19198 case OPC_LW ... OPC_LHU:
19199 gen_ld(ctx, op, rt, rs, imm);
19200 break;
19201 case OPC_SWL:
19202 case OPC_SWR:
19203 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19204 /* fall through */
19205 case OPC_SB ... OPC_SH:
19206 case OPC_SW:
19207 gen_st(ctx, op, rt, rs, imm);
19208 break;
19209 case OPC_SC:
19210 check_insn(ctx, ISA_MIPS2);
19211 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19212 gen_st_cond(ctx, op, rt, rs, imm);
19213 break;
19214 case OPC_CACHE:
19215 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19216 check_cp0_enabled(ctx);
19217 check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
19218 /* Treat as NOP. */
19219 break;
19220 case OPC_PREF:
19221 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19222 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
19223 /* Treat as NOP. */
19224 break;
19225
19226 /* Floating point (COP1). */
19227 case OPC_LWC1:
19228 case OPC_LDC1:
19229 case OPC_SWC1:
19230 case OPC_SDC1:
19231 gen_cop1_ldst(ctx, op, rt, rs, imm);
19232 break;
19233
19234 case OPC_CP1:
19235 op1 = MASK_CP1(ctx->opcode);
19236
19237 switch (op1) {
19238 case OPC_MFHC1:
19239 case OPC_MTHC1:
19240 check_cp1_enabled(ctx);
19241 check_insn(ctx, ISA_MIPS32R2);
19242 case OPC_MFC1:
19243 case OPC_CFC1:
19244 case OPC_MTC1:
19245 case OPC_CTC1:
19246 check_cp1_enabled(ctx);
19247 gen_cp1(ctx, op1, rt, rd);
19248 break;
19249 #if defined(TARGET_MIPS64)
19250 case OPC_DMFC1:
19251 case OPC_DMTC1:
19252 check_cp1_enabled(ctx);
19253 check_insn(ctx, ISA_MIPS3);
19254 check_mips_64(ctx);
19255 gen_cp1(ctx, op1, rt, rd);
19256 break;
19257 #endif
19258 case OPC_BC1EQZ: /* OPC_BC1ANY2 */
19259 check_cp1_enabled(ctx);
19260 if (ctx->insn_flags & ISA_MIPS32R6) {
19261 /* OPC_BC1EQZ */
19262 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
19263 rt, imm << 2, 4);
19264 } else {
19265 /* OPC_BC1ANY2 */
19266 check_cop1x(ctx);
19267 check_insn(ctx, ASE_MIPS3D);
19268 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
19269 (rt >> 2) & 0x7, imm << 2);
19270 }
19271 break;
19272 case OPC_BC1NEZ:
19273 check_cp1_enabled(ctx);
19274 check_insn(ctx, ISA_MIPS32R6);
19275 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
19276 rt, imm << 2, 4);
19277 break;
19278 case OPC_BC1ANY4:
19279 check_cp1_enabled(ctx);
19280 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19281 check_cop1x(ctx);
19282 check_insn(ctx, ASE_MIPS3D);
19283 /* fall through */
19284 case OPC_BC1:
19285 check_cp1_enabled(ctx);
19286 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19287 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
19288 (rt >> 2) & 0x7, imm << 2);
19289 break;
19290 case OPC_PS_FMT:
19291 check_ps(ctx);
19292 /* fall through */
19293 case OPC_S_FMT:
19294 case OPC_D_FMT:
19295 check_cp1_enabled(ctx);
19296 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
19297 (imm >> 8) & 0x7);
19298 break;
19299 case OPC_W_FMT:
19300 case OPC_L_FMT:
19301 {
19302 int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
19303 check_cp1_enabled(ctx);
19304 if (ctx->insn_flags & ISA_MIPS32R6) {
19305 switch (r6_op) {
19306 case R6_OPC_CMP_AF_S:
19307 case R6_OPC_CMP_UN_S:
19308 case R6_OPC_CMP_EQ_S:
19309 case R6_OPC_CMP_UEQ_S:
19310 case R6_OPC_CMP_LT_S:
19311 case R6_OPC_CMP_ULT_S:
19312 case R6_OPC_CMP_LE_S:
19313 case R6_OPC_CMP_ULE_S:
19314 case R6_OPC_CMP_SAF_S:
19315 case R6_OPC_CMP_SUN_S:
19316 case R6_OPC_CMP_SEQ_S:
19317 case R6_OPC_CMP_SEUQ_S:
19318 case R6_OPC_CMP_SLT_S:
19319 case R6_OPC_CMP_SULT_S:
19320 case R6_OPC_CMP_SLE_S:
19321 case R6_OPC_CMP_SULE_S:
19322 case R6_OPC_CMP_OR_S:
19323 case R6_OPC_CMP_UNE_S:
19324 case R6_OPC_CMP_NE_S:
19325 case R6_OPC_CMP_SOR_S:
19326 case R6_OPC_CMP_SUNE_S:
19327 case R6_OPC_CMP_SNE_S:
19328 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
19329 break;
19330 case R6_OPC_CMP_AF_D:
19331 case R6_OPC_CMP_UN_D:
19332 case R6_OPC_CMP_EQ_D:
19333 case R6_OPC_CMP_UEQ_D:
19334 case R6_OPC_CMP_LT_D:
19335 case R6_OPC_CMP_ULT_D:
19336 case R6_OPC_CMP_LE_D:
19337 case R6_OPC_CMP_ULE_D:
19338 case R6_OPC_CMP_SAF_D:
19339 case R6_OPC_CMP_SUN_D:
19340 case R6_OPC_CMP_SEQ_D:
19341 case R6_OPC_CMP_SEUQ_D:
19342 case R6_OPC_CMP_SLT_D:
19343 case R6_OPC_CMP_SULT_D:
19344 case R6_OPC_CMP_SLE_D:
19345 case R6_OPC_CMP_SULE_D:
19346 case R6_OPC_CMP_OR_D:
19347 case R6_OPC_CMP_UNE_D:
19348 case R6_OPC_CMP_NE_D:
19349 case R6_OPC_CMP_SOR_D:
19350 case R6_OPC_CMP_SUNE_D:
19351 case R6_OPC_CMP_SNE_D:
19352 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
19353 break;
19354 default:
19355 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
19356 rt, rd, sa, (imm >> 8) & 0x7);
19357
19358 break;
19359 }
19360 } else {
19361 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
19362 (imm >> 8) & 0x7);
19363 }
19364 break;
19365 }
19366 case OPC_BZ_V:
19367 case OPC_BNZ_V:
19368 case OPC_BZ_B:
19369 case OPC_BZ_H:
19370 case OPC_BZ_W:
19371 case OPC_BZ_D:
19372 case OPC_BNZ_B:
19373 case OPC_BNZ_H:
19374 case OPC_BNZ_W:
19375 case OPC_BNZ_D:
19376 check_insn(ctx, ASE_MSA);
19377 gen_msa_branch(env, ctx, op1);
19378 break;
19379 default:
19380 MIPS_INVAL("cp1");
19381 generate_exception(ctx, EXCP_RI);
19382 break;
19383 }
19384 break;
19385
19386 /* Compact branches [R6] and COP2 [non-R6] */
19387 case OPC_BC: /* OPC_LWC2 */
19388 case OPC_BALC: /* OPC_SWC2 */
19389 if (ctx->insn_flags & ISA_MIPS32R6) {
19390 /* OPC_BC, OPC_BALC */
19391 gen_compute_compact_branch(ctx, op, 0, 0,
19392 sextract32(ctx->opcode << 2, 0, 28));
19393 } else {
19394 /* OPC_LWC2, OPC_SWC2 */
19395 /* COP2: Not implemented. */
19396 generate_exception_err(ctx, EXCP_CpU, 2);
19397 }
19398 break;
19399 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
19400 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
19401 if (ctx->insn_flags & ISA_MIPS32R6) {
19402 if (rs != 0) {
19403 /* OPC_BEQZC, OPC_BNEZC */
19404 gen_compute_compact_branch(ctx, op, rs, 0,
19405 sextract32(ctx->opcode << 2, 0, 23));
19406 } else {
19407 /* OPC_JIC, OPC_JIALC */
19408 gen_compute_compact_branch(ctx, op, 0, rt, imm);
19409 }
19410 } else {
19411 /* OPC_LWC2, OPC_SWC2 */
19412 /* COP2: Not implemented. */
19413 generate_exception_err(ctx, EXCP_CpU, 2);
19414 }
19415 break;
19416 case OPC_CP2:
19417 check_insn(ctx, INSN_LOONGSON2F);
19418 /* Note that these instructions use different fields. */
19419 gen_loongson_multimedia(ctx, sa, rd, rt);
19420 break;
19421
19422 case OPC_CP3:
19423 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19424 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
19425 check_cp1_enabled(ctx);
19426 op1 = MASK_CP3(ctx->opcode);
19427 switch (op1) {
19428 case OPC_LUXC1:
19429 case OPC_SUXC1:
19430 check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
19431 /* Fallthrough */
19432 case OPC_LWXC1:
19433 case OPC_LDXC1:
19434 case OPC_SWXC1:
19435 case OPC_SDXC1:
19436 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19437 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
19438 break;
19439 case OPC_PREFX:
19440 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19441 /* Treat as NOP. */
19442 break;
19443 case OPC_ALNV_PS:
19444 check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
19445 /* Fallthrough */
19446 case OPC_MADD_S:
19447 case OPC_MADD_D:
19448 case OPC_MADD_PS:
19449 case OPC_MSUB_S:
19450 case OPC_MSUB_D:
19451 case OPC_MSUB_PS:
19452 case OPC_NMADD_S:
19453 case OPC_NMADD_D:
19454 case OPC_NMADD_PS:
19455 case OPC_NMSUB_S:
19456 case OPC_NMSUB_D:
19457 case OPC_NMSUB_PS:
19458 check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
19459 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
19460 break;
19461 default:
19462 MIPS_INVAL("cp3");
19463 generate_exception (ctx, EXCP_RI);
19464 break;
19465 }
19466 } else {
19467 generate_exception_err(ctx, EXCP_CpU, 1);
19468 }
19469 break;
19470
19471 #if defined(TARGET_MIPS64)
19472 /* MIPS64 opcodes */
19473 case OPC_LDL ... OPC_LDR:
19474 case OPC_LLD:
19475 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19476 /* fall through */
19477 case OPC_LWU:
19478 case OPC_LD:
19479 check_insn(ctx, ISA_MIPS3);
19480 check_mips_64(ctx);
19481 gen_ld(ctx, op, rt, rs, imm);
19482 break;
19483 case OPC_SDL ... OPC_SDR:
19484 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19485 /* fall through */
19486 case OPC_SD:
19487 check_insn(ctx, ISA_MIPS3);
19488 check_mips_64(ctx);
19489 gen_st(ctx, op, rt, rs, imm);
19490 break;
19491 case OPC_SCD:
19492 check_insn_opc_removed(ctx, ISA_MIPS32R6);
19493 check_insn(ctx, ISA_MIPS3);
19494 check_mips_64(ctx);
19495 gen_st_cond(ctx, op, rt, rs, imm);
19496 break;
19497 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
19498 if (ctx->insn_flags & ISA_MIPS32R6) {
19499 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
19500 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19501 } else {
19502 /* OPC_DADDI */
19503 check_insn(ctx, ISA_MIPS3);
19504 check_mips_64(ctx);
19505 gen_arith_imm(ctx, op, rt, rs, imm);
19506 }
19507 break;
19508 case OPC_DADDIU:
19509 check_insn(ctx, ISA_MIPS3);
19510 check_mips_64(ctx);
19511 gen_arith_imm(ctx, op, rt, rs, imm);
19512 break;
19513 #else
19514 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
19515 if (ctx->insn_flags & ISA_MIPS32R6) {
19516 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
19517 } else {
19518 MIPS_INVAL("major opcode");
19519 generate_exception(ctx, EXCP_RI);
19520 }
19521 break;
19522 #endif
19523 case OPC_DAUI: /* OPC_JALX */
19524 if (ctx->insn_flags & ISA_MIPS32R6) {
19525 #if defined(TARGET_MIPS64)
19526 /* OPC_DAUI */
19527 check_mips_64(ctx);
19528 if (rt != 0) {
19529 TCGv t0 = tcg_temp_new();
19530 gen_load_gpr(t0, rs);
19531 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
19532 tcg_temp_free(t0);
19533 }
19534 #else
19535 generate_exception(ctx, EXCP_RI);
19536 MIPS_INVAL("major opcode");
19537 #endif
19538 } else {
19539 /* OPC_JALX */
19540 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
19541 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
19542 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
19543 }
19544 break;
19545 case OPC_MSA: /* OPC_MDMX */
19546 /* MDMX: Not implemented. */
19547 gen_msa(env, ctx);
19548 break;
19549 case OPC_PCREL:
19550 check_insn(ctx, ISA_MIPS32R6);
19551 gen_pcrel(ctx, ctx->opcode, ctx->pc, rs);
19552 break;
19553 default: /* Invalid */
19554 MIPS_INVAL("major opcode");
19555 generate_exception(ctx, EXCP_RI);
19556 break;
19557 }
19558 }
19559
19560 static inline void
19561 gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
19562 bool search_pc)
19563 {
19564 CPUState *cs = CPU(cpu);
19565 CPUMIPSState *env = &cpu->env;
19566 DisasContext ctx;
19567 target_ulong pc_start;
19568 target_ulong next_page_start;
19569 CPUBreakpoint *bp;
19570 int j, lj = -1;
19571 int num_insns;
19572 int max_insns;
19573 int insn_bytes;
19574 int is_slot;
19575
19576 if (search_pc)
19577 qemu_log("search pc %d\n", search_pc);
19578
19579 pc_start = tb->pc;
19580 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
19581 ctx.pc = pc_start;
19582 ctx.saved_pc = -1;
19583 ctx.singlestep_enabled = cs->singlestep_enabled;
19584 ctx.insn_flags = env->insn_flags;
19585 ctx.CP0_Config1 = env->CP0_Config1;
19586 ctx.tb = tb;
19587 ctx.bstate = BS_NONE;
19588 ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
19589 ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
19590 ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
19591 ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
19592 ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
19593 ctx.PAMask = env->PAMask;
19594 ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
19595 ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
19596 /* Restore delay slot state from the tb context. */
19597 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
19598 ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
19599 ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
19600 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
19601 restore_cpu_state(env, &ctx);
19602 #ifdef CONFIG_USER_ONLY
19603 ctx.mem_idx = MIPS_HFLAG_UM;
19604 #else
19605 ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
19606 #endif
19607 ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
19608 MO_UNALN : MO_ALIGN;
19609 num_insns = 0;
19610 max_insns = tb->cflags & CF_COUNT_MASK;
19611 if (max_insns == 0)
19612 max_insns = CF_COUNT_MASK;
19613 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
19614 gen_tb_start(tb);
19615 while (ctx.bstate == BS_NONE) {
19616 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
19617 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
19618 if (bp->pc == ctx.pc) {
19619 save_cpu_state(&ctx, 1);
19620 ctx.bstate = BS_BRANCH;
19621 gen_helper_0e0i(raise_exception, EXCP_DEBUG);
19622 /* Include the breakpoint location or the tb won't
19623 * be flushed when it must be. */
19624 ctx.pc += 4;
19625 goto done_generating;
19626 }
19627 }
19628 }
19629
19630 if (search_pc) {
19631 j = tcg_op_buf_count();
19632 if (lj < j) {
19633 lj++;
19634 while (lj < j)
19635 tcg_ctx.gen_opc_instr_start[lj++] = 0;
19636 }
19637 tcg_ctx.gen_opc_pc[lj] = ctx.pc;
19638 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
19639 gen_opc_btarget[lj] = ctx.btarget;
19640 tcg_ctx.gen_opc_instr_start[lj] = 1;
19641 tcg_ctx.gen_opc_icount[lj] = num_insns;
19642 }
19643 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
19644 gen_io_start();
19645
19646 is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
19647 if (!(ctx.hflags & MIPS_HFLAG_M16)) {
19648 ctx.opcode = cpu_ldl_code(env, ctx.pc);
19649 insn_bytes = 4;
19650 decode_opc(env, &ctx);
19651 } else if (ctx.insn_flags & ASE_MICROMIPS) {
19652 ctx.opcode = cpu_lduw_code(env, ctx.pc);
19653 insn_bytes = decode_micromips_opc(env, &ctx);
19654 } else if (ctx.insn_flags & ASE_MIPS16) {
19655 ctx.opcode = cpu_lduw_code(env, ctx.pc);
19656 insn_bytes = decode_mips16_opc(env, &ctx);
19657 } else {
19658 generate_exception(&ctx, EXCP_RI);
19659 ctx.bstate = BS_STOP;
19660 break;
19661 }
19662
19663 if (ctx.hflags & MIPS_HFLAG_BMASK) {
19664 if (!(ctx.hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
19665 MIPS_HFLAG_FBNSLOT))) {
19666 /* force to generate branch as there is neither delay nor
19667 forbidden slot */
19668 is_slot = 1;
19669 }
19670 if ((ctx.hflags & MIPS_HFLAG_M16) &&
19671 (ctx.hflags & MIPS_HFLAG_FBNSLOT)) {
19672 /* Force to generate branch as microMIPS R6 doesn't restrict
19673 branches in the forbidden slot. */
19674 is_slot = 1;
19675 }
19676 }
19677 if (is_slot) {
19678 gen_branch(&ctx, insn_bytes);
19679 }
19680 ctx.pc += insn_bytes;
19681
19682 num_insns++;
19683
19684 /* Execute a branch and its delay slot as a single instruction.
19685 This is what GDB expects and is consistent with what the
19686 hardware does (e.g. if a delay slot instruction faults, the
19687 reported PC is the PC of the branch). */
19688 if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) {
19689 break;
19690 }
19691
19692 if (ctx.pc >= next_page_start) {
19693 break;
19694 }
19695
19696 if (tcg_op_buf_full()) {
19697 break;
19698 }
19699
19700 if (num_insns >= max_insns)
19701 break;
19702
19703 if (singlestep)
19704 break;
19705 }
19706 if (tb->cflags & CF_LAST_IO) {
19707 gen_io_end();
19708 }
19709 if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
19710 save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
19711 gen_helper_0e0i(raise_exception, EXCP_DEBUG);
19712 } else {
19713 switch (ctx.bstate) {
19714 case BS_STOP:
19715 gen_goto_tb(&ctx, 0, ctx.pc);
19716 break;
19717 case BS_NONE:
19718 save_cpu_state(&ctx, 0);
19719 gen_goto_tb(&ctx, 0, ctx.pc);
19720 break;
19721 case BS_EXCP:
19722 tcg_gen_exit_tb(0);
19723 break;
19724 case BS_BRANCH:
19725 default:
19726 break;
19727 }
19728 }
19729 done_generating:
19730 gen_tb_end(tb, num_insns);
19731
19732 if (search_pc) {
19733 j = tcg_op_buf_count();
19734 lj++;
19735 while (lj <= j)
19736 tcg_ctx.gen_opc_instr_start[lj++] = 0;
19737 } else {
19738 tb->size = ctx.pc - pc_start;
19739 tb->icount = num_insns;
19740 }
19741 #ifdef DEBUG_DISAS
19742 LOG_DISAS("\n");
19743 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
19744 qemu_log("IN: %s\n", lookup_symbol(pc_start));
19745 log_target_disas(cs, pc_start, ctx.pc - pc_start, 0);
19746 qemu_log("\n");
19747 }
19748 #endif
19749 }
19750
19751 void gen_intermediate_code (CPUMIPSState *env, struct TranslationBlock *tb)
19752 {
19753 gen_intermediate_code_internal(mips_env_get_cpu(env), tb, false);
19754 }
19755
19756 void gen_intermediate_code_pc (CPUMIPSState *env, struct TranslationBlock *tb)
19757 {
19758 gen_intermediate_code_internal(mips_env_get_cpu(env), tb, true);
19759 }
19760
19761 static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
19762 int flags)
19763 {
19764 int i;
19765 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
19766
19767 #define printfpr(fp) \
19768 do { \
19769 if (is_fpu64) \
19770 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
19771 " fd:%13g fs:%13g psu: %13g\n", \
19772 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
19773 (double)(fp)->fd, \
19774 (double)(fp)->fs[FP_ENDIAN_IDX], \
19775 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
19776 else { \
19777 fpr_t tmp; \
19778 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
19779 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
19780 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
19781 " fd:%13g fs:%13g psu:%13g\n", \
19782 tmp.w[FP_ENDIAN_IDX], tmp.d, \
19783 (double)tmp.fd, \
19784 (double)tmp.fs[FP_ENDIAN_IDX], \
19785 (double)tmp.fs[!FP_ENDIAN_IDX]); \
19786 } \
19787 } while(0)
19788
19789
19790 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
19791 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
19792 get_float_exception_flags(&env->active_fpu.fp_status));
19793 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
19794 fpu_fprintf(f, "%3s: ", fregnames[i]);
19795 printfpr(&env->active_fpu.fpr[i]);
19796 }
19797
19798 #undef printfpr
19799 }
19800
19801 void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
19802 int flags)
19803 {
19804 MIPSCPU *cpu = MIPS_CPU(cs);
19805 CPUMIPSState *env = &cpu->env;
19806 int i;
19807
19808 cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
19809 " LO=0x" TARGET_FMT_lx " ds %04x "
19810 TARGET_FMT_lx " " TARGET_FMT_ld "\n",
19811 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
19812 env->hflags, env->btarget, env->bcond);
19813 for (i = 0; i < 32; i++) {
19814 if ((i & 3) == 0)
19815 cpu_fprintf(f, "GPR%02d:", i);
19816 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
19817 if ((i & 3) == 3)
19818 cpu_fprintf(f, "\n");
19819 }
19820
19821 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
19822 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
19823 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
19824 PRIx64 "\n",
19825 env->CP0_Config0, env->CP0_Config1, env->lladdr);
19826 cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
19827 env->CP0_Config2, env->CP0_Config3);
19828 cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
19829 env->CP0_Config4, env->CP0_Config5);
19830 if (env->hflags & MIPS_HFLAG_FPU)
19831 fpu_dump_state(env, f, cpu_fprintf, flags);
19832 }
19833
19834 void mips_tcg_init(void)
19835 {
19836 int i;
19837 static int inited;
19838
19839 /* Initialize various static tables. */
19840 if (inited)
19841 return;
19842
19843 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
19844 TCGV_UNUSED(cpu_gpr[0]);
19845 for (i = 1; i < 32; i++)
19846 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
19847 offsetof(CPUMIPSState, active_tc.gpr[i]),
19848 regnames[i]);
19849
19850 for (i = 0; i < 32; i++) {
19851 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
19852 msa_wr_d[i * 2] =
19853 tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
19854 /* The scalar floating-point unit (FPU) registers are mapped on
19855 * the MSA vector registers. */
19856 fpu_f64[i] = msa_wr_d[i * 2];
19857 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
19858 msa_wr_d[i * 2 + 1] =
19859 tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
19860 }
19861
19862 cpu_PC = tcg_global_mem_new(TCG_AREG0,
19863 offsetof(CPUMIPSState, active_tc.PC), "PC");
19864 for (i = 0; i < MIPS_DSP_ACC; i++) {
19865 cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
19866 offsetof(CPUMIPSState, active_tc.HI[i]),
19867 regnames_HI[i]);
19868 cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
19869 offsetof(CPUMIPSState, active_tc.LO[i]),
19870 regnames_LO[i]);
19871 }
19872 cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
19873 offsetof(CPUMIPSState, active_tc.DSPControl),
19874 "DSPControl");
19875 bcond = tcg_global_mem_new(TCG_AREG0,
19876 offsetof(CPUMIPSState, bcond), "bcond");
19877 btarget = tcg_global_mem_new(TCG_AREG0,
19878 offsetof(CPUMIPSState, btarget), "btarget");
19879 hflags = tcg_global_mem_new_i32(TCG_AREG0,
19880 offsetof(CPUMIPSState, hflags), "hflags");
19881
19882 fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
19883 offsetof(CPUMIPSState, active_fpu.fcr0),
19884 "fcr0");
19885 fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
19886 offsetof(CPUMIPSState, active_fpu.fcr31),
19887 "fcr31");
19888
19889 inited = 1;
19890 }
19891
19892 #include "translate_init.c"
19893
19894 MIPSCPU *cpu_mips_init(const char *cpu_model)
19895 {
19896 MIPSCPU *cpu;
19897 CPUMIPSState *env;
19898 const mips_def_t *def;
19899
19900 def = cpu_mips_find_by_name(cpu_model);
19901 if (!def)
19902 return NULL;
19903 cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
19904 env = &cpu->env;
19905 env->cpu_model = def;
19906
19907 #ifndef CONFIG_USER_ONLY
19908 mmu_init(env, def);
19909 #endif
19910 fpu_init(env, def);
19911 mvp_init(env, def);
19912
19913 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
19914
19915 return cpu;
19916 }
19917
19918 void cpu_state_reset(CPUMIPSState *env)
19919 {
19920 MIPSCPU *cpu = mips_env_get_cpu(env);
19921 CPUState *cs = CPU(cpu);
19922
19923 /* Reset registers to their default values */
19924 env->CP0_PRid = env->cpu_model->CP0_PRid;
19925 env->CP0_Config0 = env->cpu_model->CP0_Config0;
19926 #ifdef TARGET_WORDS_BIGENDIAN
19927 env->CP0_Config0 |= (1 << CP0C0_BE);
19928 #endif
19929 env->CP0_Config1 = env->cpu_model->CP0_Config1;
19930 env->CP0_Config2 = env->cpu_model->CP0_Config2;
19931 env->CP0_Config3 = env->cpu_model->CP0_Config3;
19932 env->CP0_Config4 = env->cpu_model->CP0_Config4;
19933 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
19934 env->CP0_Config5 = env->cpu_model->CP0_Config5;
19935 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
19936 env->CP0_Config6 = env->cpu_model->CP0_Config6;
19937 env->CP0_Config7 = env->cpu_model->CP0_Config7;
19938 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
19939 << env->cpu_model->CP0_LLAddr_shift;
19940 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
19941 env->SYNCI_Step = env->cpu_model->SYNCI_Step;
19942 env->CCRes = env->cpu_model->CCRes;
19943 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
19944 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
19945 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
19946 env->current_tc = 0;
19947 env->SEGBITS = env->cpu_model->SEGBITS;
19948 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
19949 #if defined(TARGET_MIPS64)
19950 if (env->cpu_model->insn_flags & ISA_MIPS3) {
19951 env->SEGMask |= 3ULL << 62;
19952 }
19953 #endif
19954 env->PABITS = env->cpu_model->PABITS;
19955 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
19956 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
19957 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
19958 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
19959 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
19960 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
19961 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
19962 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
19963 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
19964 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
19965 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
19966 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
19967 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
19968 env->msair = env->cpu_model->MSAIR;
19969 env->insn_flags = env->cpu_model->insn_flags;
19970
19971 #if defined(CONFIG_USER_ONLY)
19972 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
19973 # ifdef TARGET_MIPS64
19974 /* Enable 64-bit register mode. */
19975 env->CP0_Status |= (1 << CP0St_PX);
19976 # endif
19977 # ifdef TARGET_ABI_MIPSN64
19978 /* Enable 64-bit address mode. */
19979 env->CP0_Status |= (1 << CP0St_UX);
19980 # endif
19981 /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
19982 hardware registers. */
19983 env->CP0_HWREna |= 0x0000000F;
19984 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
19985 env->CP0_Status |= (1 << CP0St_CU1);
19986 }
19987 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
19988 env->CP0_Status |= (1 << CP0St_MX);
19989 }
19990 # if defined(TARGET_MIPS64)
19991 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
19992 if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
19993 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
19994 env->CP0_Status |= (1 << CP0St_FR);
19995 }
19996 # endif
19997 #else
19998 if (env->hflags & MIPS_HFLAG_BMASK) {
19999 /* If the exception was raised from a delay slot,
20000 come back to the jump. */
20001 env->CP0_ErrorEPC = (env->active_tc.PC
20002 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
20003 } else {
20004 env->CP0_ErrorEPC = env->active_tc.PC;
20005 }
20006 env->active_tc.PC = (int32_t)0xBFC00000;
20007 env->CP0_Random = env->tlb->nb_tlb - 1;
20008 env->tlb->tlb_in_use = env->tlb->nb_tlb;
20009 env->CP0_Wired = 0;
20010 env->CP0_EBase = (cs->cpu_index & 0x3FF);
20011 if (kvm_enabled()) {
20012 env->CP0_EBase |= 0x40000000;
20013 } else {
20014 env->CP0_EBase |= 0x80000000;
20015 }
20016 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
20017 /* vectored interrupts not implemented, timer on int 7,
20018 no performance counters. */
20019 env->CP0_IntCtl = 0xe0000000;
20020 {
20021 int i;
20022
20023 for (i = 0; i < 7; i++) {
20024 env->CP0_WatchLo[i] = 0;
20025 env->CP0_WatchHi[i] = 0x80000000;
20026 }
20027 env->CP0_WatchLo[7] = 0;
20028 env->CP0_WatchHi[7] = 0;
20029 }
20030 /* Count register increments in debug mode, EJTAG version 1 */
20031 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
20032
20033 cpu_mips_store_count(env, 1);
20034
20035 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
20036 int i;
20037
20038 /* Only TC0 on VPE 0 starts as active. */
20039 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
20040 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
20041 env->tcs[i].CP0_TCHalt = 1;
20042 }
20043 env->active_tc.CP0_TCHalt = 1;
20044 cs->halted = 1;
20045
20046 if (cs->cpu_index == 0) {
20047 /* VPE0 starts up enabled. */
20048 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
20049 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
20050
20051 /* TC0 starts up unhalted. */
20052 cs->halted = 0;
20053 env->active_tc.CP0_TCHalt = 0;
20054 env->tcs[0].CP0_TCHalt = 0;
20055 /* With thread 0 active. */
20056 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
20057 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
20058 }
20059 }
20060 #endif
20061 if ((env->insn_flags & ISA_MIPS32R6) &&
20062 (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
20063 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
20064 env->CP0_Status |= (1 << CP0St_FR);
20065 }
20066
20067 /* MSA */
20068 if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
20069 msa_reset(env);
20070 }
20071
20072 compute_hflags(env);
20073 restore_rounding_mode(env);
20074 restore_flush_mode(env);
20075 restore_pamask(env);
20076 cs->exception_index = EXCP_NONE;
20077
20078 if (semihosting_get_argc()) {
20079 /* UHI interface can be used to obtain argc and argv */
20080 env->active_tc.gpr[4] = -1;
20081 }
20082 }
20083
20084 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
20085 {
20086 env->active_tc.PC = tcg_ctx.gen_opc_pc[pc_pos];
20087 env->hflags &= ~MIPS_HFLAG_BMASK;
20088 env->hflags |= gen_opc_hflags[pc_pos];
20089 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
20090 case MIPS_HFLAG_BR:
20091 break;
20092 case MIPS_HFLAG_BC:
20093 case MIPS_HFLAG_BL:
20094 case MIPS_HFLAG_B:
20095 env->btarget = gen_opc_btarget[pc_pos];
20096 break;
20097 }
20098 }
AR7 emulation for QEMU