2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "qemu/osdep.h"
31 #include "qemu-common.h"
33 #include "hw/boards.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/qdev-properties-system.h"
37 #include "hw/sysbus.h"
38 #include "migration/vmstate.h"
39 #include "strongarm.h"
40 #include "qemu/error-report.h"
41 #include "hw/arm/boot.h"
42 #include "chardev/char-fe.h"
43 #include "chardev/char-serial.h"
44 #include "sysemu/sysemu.h"
45 #include "hw/ssi/ssi.h"
46 #include "qapi/error.h"
47 #include "qemu/cutils.h"
49 #include "qom/object.h"
55 - Implement cp15, c14 ?
56 - Implement cp15, c15 !!! (idle used in L)
57 - Implement idle mode handling/DIM
58 - Implement sleep mode/Wake sources
59 - Implement reset control
60 - Implement memory control regs
62 - Maybe support MBGNT/MBREQ
67 - Enhance UART with modem signals
71 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
73 # define DPRINTF(format, ...) do { } while (0)
80 { 0x80010000, SA_PIC_UART1
},
81 { 0x80030000, SA_PIC_UART2
},
82 { 0x80050000, SA_PIC_UART3
},
86 /* Interrupt Controller */
88 #define TYPE_STRONGARM_PIC "strongarm_pic"
89 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPICState
, STRONGARM_PIC
)
91 struct StrongARMPICState
{
92 SysBusDevice parent_obj
;
111 #define SA_PIC_SRCS 32
114 static void strongarm_pic_update(void *opaque
)
116 StrongARMPICState
*s
= opaque
;
118 /* FIXME: reflect DIM */
119 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
120 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
123 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
125 StrongARMPICState
*s
= opaque
;
128 s
->pending
|= 1 << irq
;
130 s
->pending
&= ~(1 << irq
);
133 strongarm_pic_update(s
);
136 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
139 StrongARMPICState
*s
= opaque
;
143 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
149 return s
->int_idle
== 0;
151 return s
->pending
& s
->is_fiq
& s
->enabled
;
155 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
161 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
162 uint64_t value
, unsigned size
)
164 StrongARMPICState
*s
= opaque
;
174 s
->int_idle
= (value
& 1) ? 0 : ~0;
177 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
181 strongarm_pic_update(s
);
184 static const MemoryRegionOps strongarm_pic_ops
= {
185 .read
= strongarm_pic_mem_read
,
186 .write
= strongarm_pic_mem_write
,
187 .endianness
= DEVICE_NATIVE_ENDIAN
,
190 static void strongarm_pic_initfn(Object
*obj
)
192 DeviceState
*dev
= DEVICE(obj
);
193 StrongARMPICState
*s
= STRONGARM_PIC(obj
);
194 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
196 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
197 memory_region_init_io(&s
->iomem
, obj
, &strongarm_pic_ops
, s
,
199 sysbus_init_mmio(sbd
, &s
->iomem
);
200 sysbus_init_irq(sbd
, &s
->irq
);
201 sysbus_init_irq(sbd
, &s
->fiq
);
204 static int strongarm_pic_post_load(void *opaque
, int version_id
)
206 strongarm_pic_update(opaque
);
210 static VMStateDescription vmstate_strongarm_pic_regs
= {
211 .name
= "strongarm_pic",
213 .minimum_version_id
= 0,
214 .post_load
= strongarm_pic_post_load
,
215 .fields
= (VMStateField
[]) {
216 VMSTATE_UINT32(pending
, StrongARMPICState
),
217 VMSTATE_UINT32(enabled
, StrongARMPICState
),
218 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
219 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
220 VMSTATE_END_OF_LIST(),
224 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
226 DeviceClass
*dc
= DEVICE_CLASS(klass
);
228 dc
->desc
= "StrongARM PIC";
229 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
232 static const TypeInfo strongarm_pic_info
= {
233 .name
= TYPE_STRONGARM_PIC
,
234 .parent
= TYPE_SYS_BUS_DEVICE
,
235 .instance_size
= sizeof(StrongARMPICState
),
236 .instance_init
= strongarm_pic_initfn
,
237 .class_init
= strongarm_pic_class_init
,
240 /* Real-Time Clock */
241 #define RTAR 0x00 /* RTC Alarm register */
242 #define RCNR 0x04 /* RTC Counter register */
243 #define RTTR 0x08 /* RTC Timer Trim register */
244 #define RTSR 0x10 /* RTC Status register */
246 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
247 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
248 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
249 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
251 /* 16 LSB of RTTR are clockdiv for internal trim logic,
252 * trim delete isn't emulated, so
253 * f = 32 768 / (RTTR_trim + 1) */
255 #define TYPE_STRONGARM_RTC "strongarm-rtc"
256 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMRTCState
, STRONGARM_RTC
)
258 struct StrongARMRTCState
{
259 SysBusDevice parent_obj
;
267 QEMUTimer
*rtc_alarm
;
273 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
275 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
276 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
279 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
281 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
282 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
283 (1000 * ((s
->rttr
& 0xffff) + 1));
287 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
289 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
290 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
292 timer_del(s
->rtc_hz
);
295 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
296 timer_mod(s
->rtc_alarm
, s
->last_hz
+
297 (((s
->rtar
- s
->last_rcnr
) * 1000 *
298 ((s
->rttr
& 0xffff) + 1)) >> 15));
300 timer_del(s
->rtc_alarm
);
304 static inline void strongarm_rtc_alarm_tick(void *opaque
)
306 StrongARMRTCState
*s
= opaque
;
308 strongarm_rtc_timer_update(s
);
309 strongarm_rtc_int_update(s
);
312 static inline void strongarm_rtc_hz_tick(void *opaque
)
314 StrongARMRTCState
*s
= opaque
;
316 strongarm_rtc_timer_update(s
);
317 strongarm_rtc_int_update(s
);
320 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
323 StrongARMRTCState
*s
= opaque
;
333 return s
->last_rcnr
+
334 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
335 (1000 * ((s
->rttr
& 0xffff) + 1));
337 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
342 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
343 uint64_t value
, unsigned size
)
345 StrongARMRTCState
*s
= opaque
;
350 strongarm_rtc_hzupdate(s
);
352 strongarm_rtc_timer_update(s
);
357 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
358 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
360 if (s
->rtsr
!= old_rtsr
) {
361 strongarm_rtc_timer_update(s
);
364 strongarm_rtc_int_update(s
);
369 strongarm_rtc_timer_update(s
);
373 strongarm_rtc_hzupdate(s
);
374 s
->last_rcnr
= value
;
375 strongarm_rtc_timer_update(s
);
379 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
383 static const MemoryRegionOps strongarm_rtc_ops
= {
384 .read
= strongarm_rtc_read
,
385 .write
= strongarm_rtc_write
,
386 .endianness
= DEVICE_NATIVE_ENDIAN
,
389 static void strongarm_rtc_init(Object
*obj
)
391 StrongARMRTCState
*s
= STRONGARM_RTC(obj
);
392 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
398 qemu_get_timedate(&tm
, 0);
400 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
401 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
403 sysbus_init_irq(dev
, &s
->rtc_irq
);
404 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
406 memory_region_init_io(&s
->iomem
, obj
, &strongarm_rtc_ops
, s
,
408 sysbus_init_mmio(dev
, &s
->iomem
);
411 static void strongarm_rtc_realize(DeviceState
*dev
, Error
**errp
)
413 StrongARMRTCState
*s
= STRONGARM_RTC(dev
);
414 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
415 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
418 static int strongarm_rtc_pre_save(void *opaque
)
420 StrongARMRTCState
*s
= opaque
;
422 strongarm_rtc_hzupdate(s
);
427 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
429 StrongARMRTCState
*s
= opaque
;
431 strongarm_rtc_timer_update(s
);
432 strongarm_rtc_int_update(s
);
437 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
438 .name
= "strongarm-rtc",
440 .minimum_version_id
= 0,
441 .pre_save
= strongarm_rtc_pre_save
,
442 .post_load
= strongarm_rtc_post_load
,
443 .fields
= (VMStateField
[]) {
444 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
445 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
446 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
447 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
448 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
449 VMSTATE_END_OF_LIST(),
453 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
455 DeviceClass
*dc
= DEVICE_CLASS(klass
);
457 dc
->desc
= "StrongARM RTC Controller";
458 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
459 dc
->realize
= strongarm_rtc_realize
;
462 static const TypeInfo strongarm_rtc_sysbus_info
= {
463 .name
= TYPE_STRONGARM_RTC
,
464 .parent
= TYPE_SYS_BUS_DEVICE
,
465 .instance_size
= sizeof(StrongARMRTCState
),
466 .instance_init
= strongarm_rtc_init
,
467 .class_init
= strongarm_rtc_sysbus_class_init
,
480 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
481 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMGPIOInfo
, STRONGARM_GPIO
)
483 struct StrongARMGPIOInfo
{
486 qemu_irq handler
[28];
502 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
505 for (i
= 0; i
< 11; i
++) {
506 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
509 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
512 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
514 StrongARMGPIOInfo
*s
= opaque
;
520 s
->status
|= s
->rising
& mask
&
521 ~s
->ilevel
& ~s
->dir
;
524 s
->status
|= s
->falling
& mask
&
529 if (s
->status
& mask
) {
530 strongarm_gpio_irq_update(s
);
534 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
536 uint32_t level
, diff
;
539 level
= s
->olevel
& s
->dir
;
541 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
543 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
546 s
->prev_level
= level
;
549 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
552 StrongARMGPIOInfo
*s
= opaque
;
555 case GPDR
: /* GPIO Pin-Direction registers */
558 case GPSR
: /* GPIO Pin-Output Set registers */
559 qemu_log_mask(LOG_GUEST_ERROR
,
560 "strongarm GPIO: read from write only register GPSR\n");
563 case GPCR
: /* GPIO Pin-Output Clear registers */
564 qemu_log_mask(LOG_GUEST_ERROR
,
565 "strongarm GPIO: read from write only register GPCR\n");
568 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
571 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
574 case GAFR
: /* GPIO Alternate Function registers */
577 case GPLR
: /* GPIO Pin-Level registers */
578 return (s
->olevel
& s
->dir
) |
579 (s
->ilevel
& ~s
->dir
);
581 case GEDR
: /* GPIO Edge Detect Status registers */
585 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
591 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
592 uint64_t value
, unsigned size
)
594 StrongARMGPIOInfo
*s
= opaque
;
597 case GPDR
: /* GPIO Pin-Direction registers */
598 s
->dir
= value
& 0x0fffffff;
599 strongarm_gpio_handler_update(s
);
602 case GPSR
: /* GPIO Pin-Output Set registers */
603 s
->olevel
|= value
& 0x0fffffff;
604 strongarm_gpio_handler_update(s
);
607 case GPCR
: /* GPIO Pin-Output Clear registers */
609 strongarm_gpio_handler_update(s
);
612 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
616 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
620 case GAFR
: /* GPIO Alternate Function registers */
624 case GEDR
: /* GPIO Edge Detect Status registers */
626 strongarm_gpio_irq_update(s
);
630 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
634 static const MemoryRegionOps strongarm_gpio_ops
= {
635 .read
= strongarm_gpio_read
,
636 .write
= strongarm_gpio_write
,
637 .endianness
= DEVICE_NATIVE_ENDIAN
,
640 static DeviceState
*strongarm_gpio_init(hwaddr base
,
646 dev
= qdev_new(TYPE_STRONGARM_GPIO
);
647 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
649 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
650 for (i
= 0; i
< 12; i
++)
651 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
652 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
657 static void strongarm_gpio_initfn(Object
*obj
)
659 DeviceState
*dev
= DEVICE(obj
);
660 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(obj
);
661 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
664 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
665 qdev_init_gpio_out(dev
, s
->handler
, 28);
667 memory_region_init_io(&s
->iomem
, obj
, &strongarm_gpio_ops
, s
,
670 sysbus_init_mmio(sbd
, &s
->iomem
);
671 for (i
= 0; i
< 11; i
++) {
672 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
674 sysbus_init_irq(sbd
, &s
->irqX
);
677 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
678 .name
= "strongarm-gpio",
680 .minimum_version_id
= 0,
681 .fields
= (VMStateField
[]) {
682 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
683 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
684 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
685 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
686 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
687 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
688 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
689 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
690 VMSTATE_END_OF_LIST(),
694 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
696 DeviceClass
*dc
= DEVICE_CLASS(klass
);
698 dc
->desc
= "StrongARM GPIO controller";
699 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
702 static const TypeInfo strongarm_gpio_info
= {
703 .name
= TYPE_STRONGARM_GPIO
,
704 .parent
= TYPE_SYS_BUS_DEVICE
,
705 .instance_size
= sizeof(StrongARMGPIOInfo
),
706 .instance_init
= strongarm_gpio_initfn
,
707 .class_init
= strongarm_gpio_class_init
,
710 /* Peripheral Pin Controller */
717 #define TYPE_STRONGARM_PPC "strongarm-ppc"
718 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMPPCInfo
, STRONGARM_PPC
)
720 struct StrongARMPPCInfo
{
721 SysBusDevice parent_obj
;
724 qemu_irq handler
[28];
736 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
738 StrongARMPPCInfo
*s
= opaque
;
741 s
->ilevel
|= 1 << line
;
743 s
->ilevel
&= ~(1 << line
);
747 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
749 uint32_t level
, diff
;
752 level
= s
->olevel
& s
->dir
;
754 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
756 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
759 s
->prev_level
= level
;
762 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
765 StrongARMPPCInfo
*s
= opaque
;
768 case PPDR
: /* PPC Pin Direction registers */
769 return s
->dir
| ~0x3fffff;
771 case PPSR
: /* PPC Pin State registers */
772 return (s
->olevel
& s
->dir
) |
773 (s
->ilevel
& ~s
->dir
) |
777 return s
->ppar
| ~0x41000;
783 return s
->ppfr
| ~0x7f001;
786 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
792 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
793 uint64_t value
, unsigned size
)
795 StrongARMPPCInfo
*s
= opaque
;
798 case PPDR
: /* PPC Pin Direction registers */
799 s
->dir
= value
& 0x3fffff;
800 strongarm_ppc_handler_update(s
);
803 case PPSR
: /* PPC Pin State registers */
804 s
->olevel
= value
& s
->dir
& 0x3fffff;
805 strongarm_ppc_handler_update(s
);
809 s
->ppar
= value
& 0x41000;
813 s
->psdr
= value
& 0x3fffff;
817 s
->ppfr
= value
& 0x7f001;
821 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
825 static const MemoryRegionOps strongarm_ppc_ops
= {
826 .read
= strongarm_ppc_read
,
827 .write
= strongarm_ppc_write
,
828 .endianness
= DEVICE_NATIVE_ENDIAN
,
831 static void strongarm_ppc_init(Object
*obj
)
833 DeviceState
*dev
= DEVICE(obj
);
834 StrongARMPPCInfo
*s
= STRONGARM_PPC(obj
);
835 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
837 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
838 qdev_init_gpio_out(dev
, s
->handler
, 22);
840 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ppc_ops
, s
,
843 sysbus_init_mmio(sbd
, &s
->iomem
);
846 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
847 .name
= "strongarm-ppc",
849 .minimum_version_id
= 0,
850 .fields
= (VMStateField
[]) {
851 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
852 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
853 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
854 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
855 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
856 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
857 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
858 VMSTATE_END_OF_LIST(),
862 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
864 DeviceClass
*dc
= DEVICE_CLASS(klass
);
866 dc
->desc
= "StrongARM PPC controller";
867 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
870 static const TypeInfo strongarm_ppc_info
= {
871 .name
= TYPE_STRONGARM_PPC
,
872 .parent
= TYPE_SYS_BUS_DEVICE
,
873 .instance_size
= sizeof(StrongARMPPCInfo
),
874 .instance_init
= strongarm_ppc_init
,
875 .class_init
= strongarm_ppc_class_init
,
887 #define UTCR0_PE (1 << 0) /* Parity enable */
888 #define UTCR0_OES (1 << 1) /* Even parity */
889 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
890 #define UTCR0_DSS (1 << 3) /* 8-bit data */
892 #define UTCR3_RXE (1 << 0) /* Rx enable */
893 #define UTCR3_TXE (1 << 1) /* Tx enable */
894 #define UTCR3_BRK (1 << 2) /* Force Break */
895 #define UTCR3_RIE (1 << 3) /* Rx int enable */
896 #define UTCR3_TIE (1 << 4) /* Tx int enable */
897 #define UTCR3_LBM (1 << 5) /* Loopback */
899 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
900 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
901 #define UTSR0_RID (1 << 2) /* Receiver Idle */
902 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
903 #define UTSR0_REB (1 << 4) /* Receiver end break */
904 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
906 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
907 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
908 #define UTSR1_PRE (1 << 3) /* Parity error */
909 #define UTSR1_FRE (1 << 4) /* Frame error */
910 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
912 #define RX_FIFO_PRE (1 << 8)
913 #define RX_FIFO_FRE (1 << 9)
914 #define RX_FIFO_ROR (1 << 10)
916 #define TYPE_STRONGARM_UART "strongarm-uart"
917 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMUARTState
, STRONGARM_UART
)
919 struct StrongARMUARTState
{
920 SysBusDevice parent_obj
;
935 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
939 uint64_t char_transmit_time
; /* time to transmit a char in nanoseconds */
941 QEMUTimer
*rx_timeout_timer
;
945 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
949 if (s
->tx_len
!= 8) {
953 if (s
->rx_len
!= 0) {
954 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
957 if (ent
& RX_FIFO_PRE
) {
958 s
->utsr1
|= UTSR1_PRE
;
960 if (ent
& RX_FIFO_FRE
) {
961 s
->utsr1
|= UTSR1_FRE
;
963 if (ent
& RX_FIFO_ROR
) {
964 s
->utsr1
|= UTSR1_ROR
;
971 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
973 uint16_t utsr0
= s
->utsr0
&
974 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
977 if ((s
->utcr3
& UTCR3_TXE
) &&
978 (s
->utcr3
& UTCR3_TIE
) &&
983 if ((s
->utcr3
& UTCR3_RXE
) &&
984 (s
->utcr3
& UTCR3_RIE
) &&
989 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
990 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
996 qemu_set_irq(s
->irq
, utsr0
);
999 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
1001 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
1002 QEMUSerialSetParams ssp
;
1006 if (s
->utcr0
& UTCR0_PE
) {
1009 if (s
->utcr0
& UTCR0_OES
) {
1017 if (s
->utcr0
& UTCR0_SBS
) {
1023 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1024 frame_size
+= data_bits
+ stop_bits
;
1025 speed
= 3686400 / 16 / (s
->brd
+ 1);
1027 ssp
.parity
= parity
;
1028 ssp
.data_bits
= data_bits
;
1029 ssp
.stop_bits
= stop_bits
;
1030 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
1031 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1033 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1034 speed
, parity
, data_bits
, stop_bits
);
1037 static void strongarm_uart_rx_to(void *opaque
)
1039 StrongARMUARTState
*s
= opaque
;
1042 s
->utsr0
|= UTSR0_RID
;
1043 strongarm_uart_update_int_status(s
);
1047 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1049 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1054 if (s
->wait_break_end
) {
1055 s
->utsr0
|= UTSR0_REB
;
1056 s
->wait_break_end
= false;
1059 if (s
->rx_len
< 12) {
1060 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1063 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1066 static int strongarm_uart_can_receive(void *opaque
)
1068 StrongARMUARTState
*s
= opaque
;
1070 if (s
->rx_len
== 12) {
1073 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1074 if (s
->rx_len
< 8) {
1075 return 8 - s
->rx_len
;
1080 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1082 StrongARMUARTState
*s
= opaque
;
1085 for (i
= 0; i
< size
; i
++) {
1086 strongarm_uart_rx_push(s
, buf
[i
]);
1089 /* call the timeout receive callback in 3 char transmit time */
1090 timer_mod(s
->rx_timeout_timer
,
1091 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1093 strongarm_uart_update_status(s
);
1094 strongarm_uart_update_int_status(s
);
1097 static void strongarm_uart_event(void *opaque
, QEMUChrEvent event
)
1099 StrongARMUARTState
*s
= opaque
;
1100 if (event
== CHR_EVENT_BREAK
) {
1101 s
->utsr0
|= UTSR0_RBB
;
1102 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1103 s
->wait_break_end
= true;
1104 strongarm_uart_update_status(s
);
1105 strongarm_uart_update_int_status(s
);
1109 static void strongarm_uart_tx(void *opaque
)
1111 StrongARMUARTState
*s
= opaque
;
1112 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1114 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1115 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1116 } else if (qemu_chr_fe_backend_connected(&s
->chr
)) {
1117 /* XXX this blocks entire thread. Rewrite to use
1118 * qemu_chr_fe_write and background I/O callbacks */
1119 qemu_chr_fe_write_all(&s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1122 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1125 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1127 strongarm_uart_update_status(s
);
1128 strongarm_uart_update_int_status(s
);
1131 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1134 StrongARMUARTState
*s
= opaque
;
1145 return s
->brd
& 0xff;
1151 if (s
->rx_len
!= 0) {
1152 ret
= s
->rx_fifo
[s
->rx_start
];
1153 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1155 strongarm_uart_update_status(s
);
1156 strongarm_uart_update_int_status(s
);
1168 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1173 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1174 uint64_t value
, unsigned size
)
1176 StrongARMUARTState
*s
= opaque
;
1180 s
->utcr0
= value
& 0x7f;
1181 strongarm_uart_update_parameters(s
);
1185 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1186 strongarm_uart_update_parameters(s
);
1190 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1191 strongarm_uart_update_parameters(s
);
1195 s
->utcr3
= value
& 0x3f;
1196 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1199 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1202 strongarm_uart_update_status(s
);
1203 strongarm_uart_update_int_status(s
);
1207 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1208 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1210 strongarm_uart_update_status(s
);
1211 strongarm_uart_update_int_status(s
);
1212 if (s
->tx_len
== 1) {
1213 strongarm_uart_tx(s
);
1219 s
->utsr0
= s
->utsr0
& ~(value
&
1220 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1221 strongarm_uart_update_int_status(s
);
1225 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1229 static const MemoryRegionOps strongarm_uart_ops
= {
1230 .read
= strongarm_uart_read
,
1231 .write
= strongarm_uart_write
,
1232 .endianness
= DEVICE_NATIVE_ENDIAN
,
1235 static void strongarm_uart_init(Object
*obj
)
1237 StrongARMUARTState
*s
= STRONGARM_UART(obj
);
1238 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1240 memory_region_init_io(&s
->iomem
, obj
, &strongarm_uart_ops
, s
,
1242 sysbus_init_mmio(dev
, &s
->iomem
);
1243 sysbus_init_irq(dev
, &s
->irq
);
1246 static void strongarm_uart_realize(DeviceState
*dev
, Error
**errp
)
1248 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1250 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
1251 strongarm_uart_rx_to
,
1253 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1254 qemu_chr_fe_set_handlers(&s
->chr
,
1255 strongarm_uart_can_receive
,
1256 strongarm_uart_receive
,
1257 strongarm_uart_event
,
1258 NULL
, s
, NULL
, true);
1261 static void strongarm_uart_reset(DeviceState
*dev
)
1263 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1265 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1266 s
->brd
= 23; /* 9600 */
1267 /* enable send & recv - this actually violates spec */
1268 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1270 s
->rx_len
= s
->tx_len
= 0;
1272 strongarm_uart_update_parameters(s
);
1273 strongarm_uart_update_status(s
);
1274 strongarm_uart_update_int_status(s
);
1277 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1279 StrongARMUARTState
*s
= opaque
;
1281 strongarm_uart_update_parameters(s
);
1282 strongarm_uart_update_status(s
);
1283 strongarm_uart_update_int_status(s
);
1285 /* tx and restart timer */
1287 strongarm_uart_tx(s
);
1290 /* restart rx timeout timer */
1292 timer_mod(s
->rx_timeout_timer
,
1293 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1299 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1300 .name
= "strongarm-uart",
1302 .minimum_version_id
= 0,
1303 .post_load
= strongarm_uart_post_load
,
1304 .fields
= (VMStateField
[]) {
1305 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1306 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1307 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1308 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1309 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1310 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1311 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1312 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1313 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1314 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1315 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1316 VMSTATE_END_OF_LIST(),
1320 static Property strongarm_uart_properties
[] = {
1321 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1322 DEFINE_PROP_END_OF_LIST(),
1325 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1327 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1329 dc
->desc
= "StrongARM UART controller";
1330 dc
->reset
= strongarm_uart_reset
;
1331 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1332 device_class_set_props(dc
, strongarm_uart_properties
);
1333 dc
->realize
= strongarm_uart_realize
;
1336 static const TypeInfo strongarm_uart_info
= {
1337 .name
= TYPE_STRONGARM_UART
,
1338 .parent
= TYPE_SYS_BUS_DEVICE
,
1339 .instance_size
= sizeof(StrongARMUARTState
),
1340 .instance_init
= strongarm_uart_init
,
1341 .class_init
= strongarm_uart_class_init
,
1344 /* Synchronous Serial Ports */
1346 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1347 OBJECT_DECLARE_SIMPLE_TYPE(StrongARMSSPState
, STRONGARM_SSP
)
1349 struct StrongARMSSPState
{
1350 SysBusDevice parent_obj
;
1359 uint16_t rx_fifo
[8];
1364 #define SSCR0 0x60 /* SSP Control register 0 */
1365 #define SSCR1 0x64 /* SSP Control register 1 */
1366 #define SSDR 0x6c /* SSP Data register */
1367 #define SSSR 0x74 /* SSP Status register */
1369 /* Bitfields for above registers */
1370 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1371 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1372 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1373 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1374 #define SSCR0_SSE (1 << 7)
1375 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1376 #define SSCR1_RIE (1 << 0)
1377 #define SSCR1_TIE (1 << 1)
1378 #define SSCR1_LBM (1 << 2)
1379 #define SSSR_TNF (1 << 2)
1380 #define SSSR_RNE (1 << 3)
1381 #define SSSR_TFS (1 << 5)
1382 #define SSSR_RFS (1 << 6)
1383 #define SSSR_ROR (1 << 7)
1384 #define SSSR_RW 0x0080
1386 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1390 level
|= (s
->sssr
& SSSR_ROR
);
1391 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1392 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1393 qemu_set_irq(s
->irq
, level
);
1396 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1398 s
->sssr
&= ~SSSR_TFS
;
1399 s
->sssr
&= ~SSSR_TNF
;
1400 if (s
->sscr
[0] & SSCR0_SSE
) {
1401 if (s
->rx_level
>= 4) {
1402 s
->sssr
|= SSSR_RFS
;
1404 s
->sssr
&= ~SSSR_RFS
;
1407 s
->sssr
|= SSSR_RNE
;
1409 s
->sssr
&= ~SSSR_RNE
;
1411 /* TX FIFO is never filled, so it is always in underrun
1412 condition if SSP is enabled */
1413 s
->sssr
|= SSSR_TFS
;
1414 s
->sssr
|= SSSR_TNF
;
1417 strongarm_ssp_int_update(s
);
1420 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1423 StrongARMSSPState
*s
= opaque
;
1434 if (~s
->sscr
[0] & SSCR0_SSE
) {
1437 if (s
->rx_level
< 1) {
1438 printf("%s: SSP Rx Underrun\n", __func__
);
1442 retval
= s
->rx_fifo
[s
->rx_start
++];
1444 strongarm_ssp_fifo_update(s
);
1447 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1453 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1454 uint64_t value
, unsigned size
)
1456 StrongARMSSPState
*s
= opaque
;
1460 s
->sscr
[0] = value
& 0xffbf;
1461 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1462 printf("%s: Wrong data size: %i bits\n", __func__
,
1463 (int)SSCR0_DSS(value
));
1465 if (!(value
& SSCR0_SSE
)) {
1469 strongarm_ssp_fifo_update(s
);
1473 s
->sscr
[1] = value
& 0x2f;
1474 if (value
& SSCR1_LBM
) {
1475 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1477 strongarm_ssp_fifo_update(s
);
1481 s
->sssr
&= ~(value
& SSSR_RW
);
1482 strongarm_ssp_int_update(s
);
1486 if (SSCR0_UWIRE(s
->sscr
[0])) {
1489 /* Note how 32bits overflow does no harm here */
1490 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1492 /* Data goes from here to the Tx FIFO and is shifted out from
1493 * there directly to the slave, no need to buffer it.
1495 if (s
->sscr
[0] & SSCR0_SSE
) {
1497 if (s
->sscr
[1] & SSCR1_LBM
) {
1500 readval
= ssi_transfer(s
->bus
, value
);
1503 if (s
->rx_level
< 0x08) {
1504 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1506 s
->sssr
|= SSSR_ROR
;
1509 strongarm_ssp_fifo_update(s
);
1513 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1518 static const MemoryRegionOps strongarm_ssp_ops
= {
1519 .read
= strongarm_ssp_read
,
1520 .write
= strongarm_ssp_write
,
1521 .endianness
= DEVICE_NATIVE_ENDIAN
,
1524 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1526 StrongARMSSPState
*s
= opaque
;
1528 strongarm_ssp_fifo_update(s
);
1533 static void strongarm_ssp_init(Object
*obj
)
1535 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1536 DeviceState
*dev
= DEVICE(sbd
);
1537 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1539 sysbus_init_irq(sbd
, &s
->irq
);
1541 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ssp_ops
, s
,
1543 sysbus_init_mmio(sbd
, &s
->iomem
);
1545 s
->bus
= ssi_create_bus(dev
, "ssi");
1548 static void strongarm_ssp_reset(DeviceState
*dev
)
1550 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1552 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1557 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1558 .name
= "strongarm-ssp",
1560 .minimum_version_id
= 0,
1561 .post_load
= strongarm_ssp_post_load
,
1562 .fields
= (VMStateField
[]) {
1563 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1564 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1565 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1566 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1567 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1568 VMSTATE_END_OF_LIST(),
1572 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1574 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1576 dc
->desc
= "StrongARM SSP controller";
1577 dc
->reset
= strongarm_ssp_reset
;
1578 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1581 static const TypeInfo strongarm_ssp_info
= {
1582 .name
= TYPE_STRONGARM_SSP
,
1583 .parent
= TYPE_SYS_BUS_DEVICE
,
1584 .instance_size
= sizeof(StrongARMSSPState
),
1585 .instance_init
= strongarm_ssp_init
,
1586 .class_init
= strongarm_ssp_class_init
,
1589 /* Main CPU functions */
1590 StrongARMState
*sa1110_init(const char *cpu_type
)
1595 s
= g_new0(StrongARMState
, 1);
1597 if (strncmp(cpu_type
, "sa1110", 6)) {
1598 error_report("Machine requires a SA1110 processor.");
1602 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
1604 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1605 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1606 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1609 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1610 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1611 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1612 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1613 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1616 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1617 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1619 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1621 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1623 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1624 DeviceState
*dev
= qdev_new(TYPE_STRONGARM_UART
);
1625 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
1626 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1627 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1628 sa_serial
[i
].io_base
);
1629 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1630 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1633 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1634 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1635 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1640 static void strongarm_register_types(void)
1642 type_register_static(&strongarm_pic_info
);
1643 type_register_static(&strongarm_rtc_sysbus_info
);
1644 type_register_static(&strongarm_gpio_info
);
1645 type_register_static(&strongarm_ppc_info
);
1646 type_register_static(&strongarm_uart_info
);
1647 type_register_static(&strongarm_ssp_info
);
1650 type_init(strongarm_register_types
)